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authorRamakrishna Pallala <ramakrishna.pallala@intel.com>2012-03-20 17:33:16 -0400
committerAnton Vorontsov <anton.vorontsov@linaro.org>2012-03-26 12:41:29 -0400
commit5cdd4d7fa5424f2018193a0c2af3bef9036c973e (patch)
treeb265281c6e2483fa068b9d6f4338d85b292dfa93 /drivers/power
parentd6f0b00c0a5f21a54b7f44838f3c3bf73d37b920 (diff)
max17042_battery: Clean up interrupt handling
Max17042 driver has dummy hardIRQ function which does nothing but waking the threaded handler. This patch removes the hardIRQ function and also modifies the interrupt type to falling edge. While we are there, change the macros to comply with the Data sheet. Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com> Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
Diffstat (limited to 'drivers/power')
-rw-r--r--drivers/power/max17042_battery.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/power/max17042_battery.c b/drivers/power/max17042_battery.c
index d576912b1219..04620c2cb388 100644
--- a/drivers/power/max17042_battery.c
+++ b/drivers/power/max17042_battery.c
@@ -47,8 +47,8 @@
47 47
48/* Interrupt mask bits */ 48/* Interrupt mask bits */
49#define CONFIG_ALRT_BIT_ENBL (1 << 2) 49#define CONFIG_ALRT_BIT_ENBL (1 << 2)
50#define STATUS_INTR_SOC_BIT (1 << 14) 50#define STATUS_INTR_SOCMIN_BIT (1 << 10)
51#define STATUS_INTR_LOW_SOC_BIT (1 << 10) 51#define STATUS_INTR_SOCMAX_BIT (1 << 14)
52 52
53#define VFSOC0_LOCK 0x0000 53#define VFSOC0_LOCK 0x0000
54#define VFSOC0_UNLOCK 0x0080 54#define VFSOC0_UNLOCK 0x0080
@@ -569,19 +569,14 @@ static void max17042_set_soc_threshold(struct max17042_chip *chip, u16 off)
569 max17042_write_reg(chip->client, MAX17042_SALRT_Th, soc_tr); 569 max17042_write_reg(chip->client, MAX17042_SALRT_Th, soc_tr);
570} 570}
571 571
572static irqreturn_t max17042_intr_handler(int id, void *dev)
573{
574 return IRQ_WAKE_THREAD;
575}
576
577static irqreturn_t max17042_thread_handler(int id, void *dev) 572static irqreturn_t max17042_thread_handler(int id, void *dev)
578{ 573{
579 struct max17042_chip *chip = dev; 574 struct max17042_chip *chip = dev;
580 u16 val; 575 u16 val;
581 576
582 val = max17042_read_reg(chip->client, MAX17042_STATUS); 577 val = max17042_read_reg(chip->client, MAX17042_STATUS);
583 if ((val & STATUS_INTR_SOC_BIT) || 578 if ((val & STATUS_INTR_SOCMIN_BIT) ||
584 (val & STATUS_INTR_LOW_SOC_BIT)) { 579 (val & STATUS_INTR_SOCMAX_BIT)) {
585 dev_info(&chip->client->dev, "SOC threshold INTR\n"); 580 dev_info(&chip->client->dev, "SOC threshold INTR\n");
586 max17042_set_soc_threshold(chip, 1); 581 max17042_set_soc_threshold(chip, 1);
587 } 582 }
@@ -689,9 +684,10 @@ static int __devinit max17042_probe(struct i2c_client *client,
689 } 684 }
690 685
691 if (client->irq) { 686 if (client->irq) {
692 ret = request_threaded_irq(client->irq, max17042_intr_handler, 687 ret = request_threaded_irq(client->irq, NULL,
693 max17042_thread_handler, 688 max17042_thread_handler,
694 0, chip->battery.name, chip); 689 IRQF_TRIGGER_FALLING,
690 chip->battery.name, chip);
695 if (!ret) { 691 if (!ret) {
696 reg = max17042_read_reg(client, MAX17042_CONFIG); 692 reg = max17042_read_reg(client, MAX17042_CONFIG);
697 reg |= CONFIG_ALRT_BIT_ENBL; 693 reg |= CONFIG_ALRT_BIT_ENBL;