pinctrl: rockchip: handle first half of rk3188-bank0 correctly

The first half of pinbank 0 only has one muxing function (as gpios) and
does not have a special mux-register.

Therefore ensure that no other mux function can be selected and also do not
write to a non-existent register.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 2ac194370b73..96c60d230c13 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -350,6 +350,20 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
         u8 bit;
         u32 data;
 
+        /*
+         * The first 16 pins of rk3188_bank0 are always gpios and do not have
+         * a mux register at all.
+         */
+        if (bank->bank_type == RK3188_BANK0 && pin < 16) {
+                if (mux != RK_FUNC_GPIO) {
+                        dev_err(info->dev,
+                                "pin %d only supports a gpio mux\n", pin);
+                        return -ENOTSUPP;
+                } else {
+                        return 0;
+                }
+        }
+
         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
                                                 bank->bank_num, pin, mux);