diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-03 19:44:15 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-03 19:44:15 -0400 |
commit | 154d6f18a48e00dec2dc84a96914fe1a24669577 (patch) | |
tree | 7b92ac64a00eb173af396752f3bfc72c9eba615c /drivers/pinctrl | |
parent | 76ca7d1cca761bb9712dfcad9a27d70b520874ae (diff) | |
parent | b22978fc33dec72e5f8e17f90eb63ea9137aafd5 (diff) |
Merge tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull bulk of gpio updates from Linus Walleij:
"A pretty big chunk of changes this time, but it has all been on
rotation in linux-next and had some testing. Of course there will be
some amount of fixes on top...
- Merged in a branch of irqchip changes from Thomas Gleixner: we need
to have new callbacks from the irqchip to determine if the GPIO
line will be eligible for IRQs, and this callback must be able to
say "no". After some thinking I got the branch from tglx and have
switched all current users over to use this.
- Based on tglx patches, we have added some generic irqchip helpers
in the gpiolib core. These will help centralize code when GPIO
drivers have simple chained/cascaded IRQs. Drivers will still
define their irqchip vtables, but the gpiolib core will take care
of irqdomain set-up, mapping from local offsets to Linux irqs, and
reserve resources by marking the GPIO lines for IRQs.
- Initially the PL061 and Nomadik GPIO/pin control drivers have been
switched over to use the new gpiochip-to-irqchip infrastructure
with more drivers expected for the next kernel cycle. The
factoring of just two drivers still makes it worth it so it is
already a win.
- A new driver for the Synopsys DesignWare APB GPIO block.
- Modify the DaVinci GPIO driver to be reusable also for the new TI
Keystone architecture.
- A new driver for the LSI ZEVIO SoCs.
- Delete the obsolte tnetv107x driver.
- Some incremental work on GPIO descriptors: have
gpiod_direction_output() use a logical level, respecting assertion
polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw()
for the case where you want to set that very value. Add
gpiochip_get_desc() to fetch a GPIO descriptor from a specific
offset on a certain chip inside driver code.
- Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid
of gpio_to_desc().
- The ACPI GPIO event handling code has been reworked after
encountering an actual real life implementation.
- Support for ACPI GPIO operation regions.
- Generic GPIO chips can now be assigned labels/names from platform
data.
- We now clamp values returned from GPIO drivers to the boolean [0,1]
range.
- Some improved documentation on how to use the polarity flag was
added.
- a large slew of incremental driver updates and non-critical fixes.
Some targeted for stable"
* tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits)
gpio: rcar: Add helper variable dev = &pdev->dev
gpio-lynxpoint: force gpio_get() to return "1" and "0" only
gpio: unmap gpio irqs properly
pch_gpio: set value before enabling output direction
gpio: moxart: Actually set output state in moxart_gpio_direction_output()
gpio: moxart: Avoid forward declaration
gpio: mxs: Allow for recursive enable_irq_wake() call
gpio: samsung: Add missing "break" statement
gpio: twl4030: Remove redundant assignment
gpio: dwapb: correct gpio-cells in binding document
gpio: iop: fix devm_ioremap_resource() return value checking
pinctrl: coh901: convert driver to use gpiolib irqchip
pinctrl: nomadik: convert driver to use gpiolib irqchip
gpio: pl061: convert driver to use gpiolib irqchip
gpio: add IRQ chip helpers in gpiolib
pinctrl: nomadik: factor in platform data container
pinctrl: nomadik: rename secondary to latent
gpio: Driver for SYSCON-based GPIOs
gpio: generic: Use platform_device_id->driver_data field for driver flags
pinctrl: coh901: move irq line locking to resource callbacks
...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/Kconfig | 4 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-adi2.c | 1 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-baytrail.c | 14 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-coh901.c | 186 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-msm.c | 11 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-nomadik.c | 159 | ||||
-rw-r--r-- | drivers/pinctrl/sirf/pinctrl-sirf.c | 14 |
7 files changed, 126 insertions, 263 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 06cee0189f3e..e49324032611 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig | |||
@@ -235,6 +235,9 @@ config PINCTRL_NOMADIK | |||
235 | depends on ARCH_U8500 || ARCH_NOMADIK | 235 | depends on ARCH_U8500 || ARCH_NOMADIK |
236 | select PINMUX | 236 | select PINMUX |
237 | select PINCONF | 237 | select PINCONF |
238 | select GPIOLIB | ||
239 | select OF_GPIO | ||
240 | select GPIOLIB_IRQCHIP | ||
238 | 241 | ||
239 | config PINCTRL_STN8815 | 242 | config PINCTRL_STN8815 |
240 | bool "STN8815 pin controller driver" | 243 | bool "STN8815 pin controller driver" |
@@ -321,6 +324,7 @@ config PINCTRL_U300 | |||
321 | config PINCTRL_COH901 | 324 | config PINCTRL_COH901 |
322 | bool "ST-Ericsson U300 COH 901 335/571 GPIO" | 325 | bool "ST-Ericsson U300 COH 901 335/571 GPIO" |
323 | depends on GPIOLIB && ARCH_U300 && PINCTRL_U300 | 326 | depends on GPIOLIB && ARCH_U300 && PINCTRL_U300 |
327 | select GPIOLIB_IRQCHIP | ||
324 | help | 328 | help |
325 | Say yes here to support GPIO interface on ST-Ericsson U300. | 329 | Say yes here to support GPIO interface on ST-Ericsson U300. |
326 | The names of the two IP block variants supported are | 330 | The names of the two IP block variants supported are |
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 200ea1e72d40..0cc0eec83396 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c | |||
@@ -337,6 +337,7 @@ static unsigned int adi_gpio_irq_startup(struct irq_data *d) | |||
337 | 337 | ||
338 | if (!port) { | 338 | if (!port) { |
339 | pr_err("GPIO IRQ %d :Not exist\n", d->irq); | 339 | pr_err("GPIO IRQ %d :Not exist\n", d->irq); |
340 | /* FIXME: negative return code will be ignored */ | ||
340 | return -ENODEV; | 341 | return -ENODEV; |
341 | } | 342 | } |
342 | 343 | ||
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c index bf2b3f655469..6e8301f77187 100644 --- a/drivers/pinctrl/pinctrl-baytrail.c +++ b/drivers/pinctrl/pinctrl-baytrail.c | |||
@@ -407,23 +407,23 @@ static void byt_irq_mask(struct irq_data *d) | |||
407 | { | 407 | { |
408 | } | 408 | } |
409 | 409 | ||
410 | static unsigned int byt_irq_startup(struct irq_data *d) | 410 | static int byt_irq_reqres(struct irq_data *d) |
411 | { | 411 | { |
412 | struct byt_gpio *vg = irq_data_get_irq_chip_data(d); | 412 | struct byt_gpio *vg = irq_data_get_irq_chip_data(d); |
413 | 413 | ||
414 | if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) | 414 | if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) { |
415 | dev_err(vg->chip.dev, | 415 | dev_err(vg->chip.dev, |
416 | "unable to lock HW IRQ %lu for IRQ\n", | 416 | "unable to lock HW IRQ %lu for IRQ\n", |
417 | irqd_to_hwirq(d)); | 417 | irqd_to_hwirq(d)); |
418 | byt_irq_unmask(d); | 418 | return -EINVAL; |
419 | } | ||
419 | return 0; | 420 | return 0; |
420 | } | 421 | } |
421 | 422 | ||
422 | static void byt_irq_shutdown(struct irq_data *d) | 423 | static void byt_irq_relres(struct irq_data *d) |
423 | { | 424 | { |
424 | struct byt_gpio *vg = irq_data_get_irq_chip_data(d); | 425 | struct byt_gpio *vg = irq_data_get_irq_chip_data(d); |
425 | 426 | ||
426 | byt_irq_mask(d); | ||
427 | gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d)); | 427 | gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d)); |
428 | } | 428 | } |
429 | 429 | ||
@@ -432,8 +432,8 @@ static struct irq_chip byt_irqchip = { | |||
432 | .irq_mask = byt_irq_mask, | 432 | .irq_mask = byt_irq_mask, |
433 | .irq_unmask = byt_irq_unmask, | 433 | .irq_unmask = byt_irq_unmask, |
434 | .irq_set_type = byt_irq_type, | 434 | .irq_set_type = byt_irq_type, |
435 | .irq_startup = byt_irq_startup, | 435 | .irq_request_resources = byt_irq_reqres, |
436 | .irq_shutdown = byt_irq_shutdown, | 436 | .irq_release_resources = byt_irq_relres, |
437 | }; | 437 | }; |
438 | 438 | ||
439 | static void byt_gpio_irq_init_hw(struct byt_gpio *vg) | 439 | static void byt_gpio_irq_init_hw(struct byt_gpio *vg) |
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 162ac0d73739..d182fdd2e715 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c | |||
@@ -8,17 +8,14 @@ | |||
8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> | 8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
9 | */ | 9 | */ |
10 | #include <linux/module.h> | 10 | #include <linux/module.h> |
11 | #include <linux/irq.h> | ||
12 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
13 | #include <linux/delay.h> | 12 | #include <linux/delay.h> |
14 | #include <linux/errno.h> | 13 | #include <linux/errno.h> |
15 | #include <linux/io.h> | 14 | #include <linux/io.h> |
16 | #include <linux/irqdomain.h> | ||
17 | #include <linux/clk.h> | 15 | #include <linux/clk.h> |
18 | #include <linux/err.h> | 16 | #include <linux/err.h> |
19 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
20 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
21 | #include <linux/list.h> | ||
22 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
23 | #include <linux/pinctrl/consumer.h> | 20 | #include <linux/pinctrl/consumer.h> |
24 | #include <linux/pinctrl/pinconf-generic.h> | 21 | #include <linux/pinctrl/pinconf-generic.h> |
@@ -61,9 +58,17 @@ | |||
61 | #define U300_GPIO_PINS_PER_PORT 8 | 58 | #define U300_GPIO_PINS_PER_PORT 8 |
62 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) | 59 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) |
63 | 60 | ||
61 | struct u300_gpio_port { | ||
62 | struct u300_gpio *gpio; | ||
63 | char name[8]; | ||
64 | int irq; | ||
65 | int number; | ||
66 | u8 toggle_edge_mode; | ||
67 | }; | ||
68 | |||
64 | struct u300_gpio { | 69 | struct u300_gpio { |
65 | struct gpio_chip chip; | 70 | struct gpio_chip chip; |
66 | struct list_head port_list; | 71 | struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; |
67 | struct clk *clk; | 72 | struct clk *clk; |
68 | void __iomem *base; | 73 | void __iomem *base; |
69 | struct device *dev; | 74 | struct device *dev; |
@@ -78,16 +83,6 @@ struct u300_gpio { | |||
78 | u32 iev; | 83 | u32 iev; |
79 | }; | 84 | }; |
80 | 85 | ||
81 | struct u300_gpio_port { | ||
82 | struct list_head node; | ||
83 | struct u300_gpio *gpio; | ||
84 | char name[8]; | ||
85 | struct irq_domain *domain; | ||
86 | int irq; | ||
87 | int number; | ||
88 | u8 toggle_edge_mode; | ||
89 | }; | ||
90 | |||
91 | /* | 86 | /* |
92 | * Macro to expand to read a specific register found in the "gpio" | 87 | * Macro to expand to read a specific register found in the "gpio" |
93 | * struct. It requires the struct u300_gpio *gpio variable to exist in | 88 | * struct. It requires the struct u300_gpio *gpio variable to exist in |
@@ -308,39 +303,6 @@ static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |||
308 | return 0; | 303 | return 0; |
309 | } | 304 | } |
310 | 305 | ||
311 | static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | ||
312 | { | ||
313 | struct u300_gpio *gpio = to_u300_gpio(chip); | ||
314 | int portno = offset >> 3; | ||
315 | struct u300_gpio_port *port = NULL; | ||
316 | struct list_head *p; | ||
317 | int retirq; | ||
318 | bool found = false; | ||
319 | |||
320 | list_for_each(p, &gpio->port_list) { | ||
321 | port = list_entry(p, struct u300_gpio_port, node); | ||
322 | if (port->number == portno) { | ||
323 | found = true; | ||
324 | break; | ||
325 | } | ||
326 | } | ||
327 | if (!found) { | ||
328 | dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n", | ||
329 | offset); | ||
330 | return -EINVAL; | ||
331 | } | ||
332 | |||
333 | /* | ||
334 | * The local hwirqs on the port are the lower three bits, there | ||
335 | * are exactly 8 IRQs per port since they are 8-bit | ||
336 | */ | ||
337 | retirq = irq_find_mapping(port->domain, (offset & 0x7)); | ||
338 | |||
339 | dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n", | ||
340 | offset, retirq, port->number); | ||
341 | return retirq; | ||
342 | } | ||
343 | |||
344 | /* Returning -EINVAL means "supported but not available" */ | 306 | /* Returning -EINVAL means "supported but not available" */ |
345 | int u300_gpio_config_get(struct gpio_chip *chip, | 307 | int u300_gpio_config_get(struct gpio_chip *chip, |
346 | unsigned offset, | 308 | unsigned offset, |
@@ -461,7 +423,6 @@ static struct gpio_chip u300_gpio_chip = { | |||
461 | .set = u300_gpio_set, | 423 | .set = u300_gpio_set, |
462 | .direction_input = u300_gpio_direction_input, | 424 | .direction_input = u300_gpio_direction_input, |
463 | .direction_output = u300_gpio_direction_output, | 425 | .direction_output = u300_gpio_direction_output, |
464 | .to_irq = u300_gpio_to_irq, | ||
465 | }; | 426 | }; |
466 | 427 | ||
467 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) | 428 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) |
@@ -485,9 +446,10 @@ static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) | |||
485 | 446 | ||
486 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) | 447 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
487 | { | 448 | { |
488 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); | 449 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
489 | struct u300_gpio *gpio = port->gpio; | 450 | struct u300_gpio *gpio = to_u300_gpio(chip); |
490 | int offset = (port->number << 3) + d->hwirq; | 451 | struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; |
452 | int offset = d->hwirq; | ||
491 | u32 val; | 453 | u32 val; |
492 | 454 | ||
493 | if ((trigger & IRQF_TRIGGER_RISING) && | 455 | if ((trigger & IRQF_TRIGGER_RISING) && |
@@ -521,18 +483,15 @@ static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) | |||
521 | 483 | ||
522 | static void u300_gpio_irq_enable(struct irq_data *d) | 484 | static void u300_gpio_irq_enable(struct irq_data *d) |
523 | { | 485 | { |
524 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); | 486 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
525 | struct u300_gpio *gpio = port->gpio; | 487 | struct u300_gpio *gpio = to_u300_gpio(chip); |
526 | int offset = (port->number << 3) + d->hwirq; | 488 | struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; |
489 | int offset = d->hwirq; | ||
527 | u32 val; | 490 | u32 val; |
528 | unsigned long flags; | 491 | unsigned long flags; |
529 | 492 | ||
530 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", | 493 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", |
531 | d->hwirq, port->name, offset); | 494 | d->hwirq, port->name, offset); |
532 | if (gpio_lock_as_irq(&gpio->chip, d->hwirq)) | ||
533 | dev_err(gpio->dev, | ||
534 | "unable to lock HW IRQ %lu for IRQ\n", | ||
535 | d->hwirq); | ||
536 | local_irq_save(flags); | 495 | local_irq_save(flags); |
537 | val = readl(U300_PIN_REG(offset, ien)); | 496 | val = readl(U300_PIN_REG(offset, ien)); |
538 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | 497 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); |
@@ -541,9 +500,9 @@ static void u300_gpio_irq_enable(struct irq_data *d) | |||
541 | 500 | ||
542 | static void u300_gpio_irq_disable(struct irq_data *d) | 501 | static void u300_gpio_irq_disable(struct irq_data *d) |
543 | { | 502 | { |
544 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); | 503 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
545 | struct u300_gpio *gpio = port->gpio; | 504 | struct u300_gpio *gpio = to_u300_gpio(chip); |
546 | int offset = (port->number << 3) + d->hwirq; | 505 | int offset = d->hwirq; |
547 | u32 val; | 506 | u32 val; |
548 | unsigned long flags; | 507 | unsigned long flags; |
549 | 508 | ||
@@ -551,7 +510,6 @@ static void u300_gpio_irq_disable(struct irq_data *d) | |||
551 | val = readl(U300_PIN_REG(offset, ien)); | 510 | val = readl(U300_PIN_REG(offset, ien)); |
552 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | 511 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); |
553 | local_irq_restore(flags); | 512 | local_irq_restore(flags); |
554 | gpio_unlock_as_irq(&gpio->chip, d->hwirq); | ||
555 | } | 513 | } |
556 | 514 | ||
557 | static struct irq_chip u300_gpio_irqchip = { | 515 | static struct irq_chip u300_gpio_irqchip = { |
@@ -559,17 +517,19 @@ static struct irq_chip u300_gpio_irqchip = { | |||
559 | .irq_enable = u300_gpio_irq_enable, | 517 | .irq_enable = u300_gpio_irq_enable, |
560 | .irq_disable = u300_gpio_irq_disable, | 518 | .irq_disable = u300_gpio_irq_disable, |
561 | .irq_set_type = u300_gpio_irq_type, | 519 | .irq_set_type = u300_gpio_irq_type, |
562 | |||
563 | }; | 520 | }; |
564 | 521 | ||
565 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 522 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
566 | { | 523 | { |
567 | struct u300_gpio_port *port = irq_get_handler_data(irq); | 524 | struct irq_chip *parent_chip = irq_get_chip(irq); |
568 | struct u300_gpio *gpio = port->gpio; | 525 | struct gpio_chip *chip = irq_get_handler_data(irq); |
526 | struct u300_gpio *gpio = to_u300_gpio(chip); | ||
527 | struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; | ||
569 | int pinoffset = port->number << 3; /* get the right stride */ | 528 | int pinoffset = port->number << 3; /* get the right stride */ |
570 | unsigned long val; | 529 | unsigned long val; |
571 | 530 | ||
572 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 531 | chained_irq_enter(parent_chip, desc); |
532 | |||
573 | /* Read event register */ | 533 | /* Read event register */ |
574 | val = readl(U300_PIN_REG(pinoffset, iev)); | 534 | val = readl(U300_PIN_REG(pinoffset, iev)); |
575 | /* Mask relevant bits */ | 535 | /* Mask relevant bits */ |
@@ -582,8 +542,8 @@ static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
582 | int irqoffset; | 542 | int irqoffset; |
583 | 543 | ||
584 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { | 544 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { |
585 | int pin_irq = irq_find_mapping(port->domain, irqoffset); | ||
586 | int offset = pinoffset + irqoffset; | 545 | int offset = pinoffset + irqoffset; |
546 | int pin_irq = irq_find_mapping(chip->irqdomain, offset); | ||
587 | 547 | ||
588 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", | 548 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", |
589 | pin_irq, offset); | 549 | pin_irq, offset); |
@@ -597,7 +557,7 @@ static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
597 | } | 557 | } |
598 | } | 558 | } |
599 | 559 | ||
600 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | 560 | chained_irq_exit(parent_chip, desc); |
601 | } | 561 | } |
602 | 562 | ||
603 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, | 563 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
@@ -648,20 +608,6 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) | |||
648 | } | 608 | } |
649 | } | 609 | } |
650 | 610 | ||
651 | static inline void u300_gpio_free_ports(struct u300_gpio *gpio) | ||
652 | { | ||
653 | struct u300_gpio_port *port; | ||
654 | struct list_head *p, *n; | ||
655 | |||
656 | list_for_each_safe(p, n, &gpio->port_list) { | ||
657 | port = list_entry(p, struct u300_gpio_port, node); | ||
658 | list_del(&port->node); | ||
659 | if (port->domain) | ||
660 | irq_domain_remove(port->domain); | ||
661 | kfree(port); | ||
662 | } | ||
663 | } | ||
664 | |||
665 | /* | 611 | /* |
666 | * Here we map a GPIO in the local gpio_chip pin space to a pin in | 612 | * Here we map a GPIO in the local gpio_chip pin space to a pin in |
667 | * the local pinctrl pin space. The pin controller used is | 613 | * the local pinctrl pin space. The pin controller used is |
@@ -752,17 +698,28 @@ static int __init u300_gpio_probe(struct platform_device *pdev) | |||
752 | gpio->base + U300_GPIO_CR); | 698 | gpio->base + U300_GPIO_CR); |
753 | u300_gpio_init_coh901571(gpio); | 699 | u300_gpio_init_coh901571(gpio); |
754 | 700 | ||
701 | #ifdef CONFIG_OF_GPIO | ||
702 | gpio->chip.of_node = pdev->dev.of_node; | ||
703 | #endif | ||
704 | err = gpiochip_add(&gpio->chip); | ||
705 | if (err) { | ||
706 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); | ||
707 | goto err_no_chip; | ||
708 | } | ||
709 | |||
710 | err = gpiochip_irqchip_add(&gpio->chip, | ||
711 | &u300_gpio_irqchip, | ||
712 | 0, | ||
713 | handle_simple_irq, | ||
714 | IRQ_TYPE_EDGE_FALLING); | ||
715 | if (err) { | ||
716 | dev_err(gpio->dev, "no GPIO irqchip\n"); | ||
717 | goto err_no_irqchip; | ||
718 | } | ||
719 | |||
755 | /* Add each port with its IRQ separately */ | 720 | /* Add each port with its IRQ separately */ |
756 | INIT_LIST_HEAD(&gpio->port_list); | ||
757 | for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { | 721 | for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { |
758 | struct u300_gpio_port *port = | 722 | struct u300_gpio_port *port = &gpio->ports[portno]; |
759 | kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); | ||
760 | |||
761 | if (!port) { | ||
762 | dev_err(gpio->dev, "out of memory\n"); | ||
763 | err = -ENOMEM; | ||
764 | goto err_no_port; | ||
765 | } | ||
766 | 723 | ||
767 | snprintf(port->name, 8, "gpio%d", portno); | 724 | snprintf(port->name, 8, "gpio%d", portno); |
768 | port->number = portno; | 725 | port->number = portno; |
@@ -770,50 +727,16 @@ static int __init u300_gpio_probe(struct platform_device *pdev) | |||
770 | 727 | ||
771 | port->irq = platform_get_irq(pdev, portno); | 728 | port->irq = platform_get_irq(pdev, portno); |
772 | 729 | ||
773 | dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, | 730 | gpiochip_set_chained_irqchip(&gpio->chip, |
774 | port->name); | 731 | &u300_gpio_irqchip, |
775 | 732 | port->irq, | |
776 | port->domain = irq_domain_add_linear(pdev->dev.of_node, | 733 | u300_gpio_irq_handler); |
777 | U300_GPIO_PINS_PER_PORT, | ||
778 | &irq_domain_simple_ops, | ||
779 | port); | ||
780 | if (!port->domain) { | ||
781 | err = -ENOMEM; | ||
782 | goto err_no_domain; | ||
783 | } | ||
784 | |||
785 | irq_set_chained_handler(port->irq, u300_gpio_irq_handler); | ||
786 | irq_set_handler_data(port->irq, port); | ||
787 | |||
788 | /* For each GPIO pin set the unique IRQ handler */ | ||
789 | for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) { | ||
790 | int irqno = irq_create_mapping(port->domain, i); | ||
791 | |||
792 | dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n", | ||
793 | gpio->chip.base + (port->number << 3) + i, | ||
794 | port->name, irqno); | ||
795 | irq_set_chip_and_handler(irqno, &u300_gpio_irqchip, | ||
796 | handle_simple_irq); | ||
797 | set_irq_flags(irqno, IRQF_VALID); | ||
798 | irq_set_chip_data(irqno, port); | ||
799 | } | ||
800 | 734 | ||
801 | /* Turns off irq force (test register) for this port */ | 735 | /* Turns off irq force (test register) for this port */ |
802 | writel(0x0, gpio->base + portno * gpio->stride + ifr); | 736 | writel(0x0, gpio->base + portno * gpio->stride + ifr); |
803 | |||
804 | list_add_tail(&port->node, &gpio->port_list); | ||
805 | } | 737 | } |
806 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); | 738 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
807 | 739 | ||
808 | #ifdef CONFIG_OF_GPIO | ||
809 | gpio->chip.of_node = pdev->dev.of_node; | ||
810 | #endif | ||
811 | err = gpiochip_add(&gpio->chip); | ||
812 | if (err) { | ||
813 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); | ||
814 | goto err_no_chip; | ||
815 | } | ||
816 | |||
817 | /* | 740 | /* |
818 | * Add pinctrl pin ranges, the pin controller must be registered | 741 | * Add pinctrl pin ranges, the pin controller must be registered |
819 | * at this point | 742 | * at this point |
@@ -832,12 +755,10 @@ static int __init u300_gpio_probe(struct platform_device *pdev) | |||
832 | return 0; | 755 | return 0; |
833 | 756 | ||
834 | err_no_range: | 757 | err_no_range: |
758 | err_no_irqchip: | ||
835 | if (gpiochip_remove(&gpio->chip)) | 759 | if (gpiochip_remove(&gpio->chip)) |
836 | dev_err(&pdev->dev, "failed to remove gpio chip\n"); | 760 | dev_err(&pdev->dev, "failed to remove gpio chip\n"); |
837 | err_no_chip: | 761 | err_no_chip: |
838 | err_no_domain: | ||
839 | err_no_port: | ||
840 | u300_gpio_free_ports(gpio); | ||
841 | clk_disable_unprepare(gpio->clk); | 762 | clk_disable_unprepare(gpio->clk); |
842 | dev_err(&pdev->dev, "module ERROR:%d\n", err); | 763 | dev_err(&pdev->dev, "module ERROR:%d\n", err); |
843 | return err; | 764 | return err; |
@@ -856,7 +777,6 @@ static int __exit u300_gpio_remove(struct platform_device *pdev) | |||
856 | dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); | 777 | dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); |
857 | return err; | 778 | return err; |
858 | } | 779 | } |
859 | u300_gpio_free_ports(gpio); | ||
860 | clk_disable_unprepare(gpio->clk); | 780 | clk_disable_unprepare(gpio->clk); |
861 | return 0; | 781 | return 0; |
862 | } | 782 | } |
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c index 343f421c7696..38d579b47f31 100644 --- a/drivers/pinctrl/pinctrl-msm.c +++ b/drivers/pinctrl/pinctrl-msm.c | |||
@@ -785,23 +785,22 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |||
785 | return 0; | 785 | return 0; |
786 | } | 786 | } |
787 | 787 | ||
788 | static unsigned int msm_gpio_irq_startup(struct irq_data *d) | 788 | static int msm_gpio_irq_reqres(struct irq_data *d) |
789 | { | 789 | { |
790 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); | 790 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); |
791 | 791 | ||
792 | if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) { | 792 | if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) { |
793 | dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n", | 793 | dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n", |
794 | d->hwirq); | 794 | d->hwirq); |
795 | return -EINVAL; | ||
795 | } | 796 | } |
796 | msm_gpio_irq_unmask(d); | ||
797 | return 0; | 797 | return 0; |
798 | } | 798 | } |
799 | 799 | ||
800 | static void msm_gpio_irq_shutdown(struct irq_data *d) | 800 | static void msm_gpio_irq_relres(struct irq_data *d) |
801 | { | 801 | { |
802 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); | 802 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); |
803 | 803 | ||
804 | msm_gpio_irq_mask(d); | ||
805 | gpio_unlock_as_irq(&pctrl->chip, d->hwirq); | 804 | gpio_unlock_as_irq(&pctrl->chip, d->hwirq); |
806 | } | 805 | } |
807 | 806 | ||
@@ -812,8 +811,8 @@ static struct irq_chip msm_gpio_irq_chip = { | |||
812 | .irq_ack = msm_gpio_irq_ack, | 811 | .irq_ack = msm_gpio_irq_ack, |
813 | .irq_set_type = msm_gpio_irq_set_type, | 812 | .irq_set_type = msm_gpio_irq_set_type, |
814 | .irq_set_wake = msm_gpio_irq_set_wake, | 813 | .irq_set_wake = msm_gpio_irq_set_wake, |
815 | .irq_startup = msm_gpio_irq_startup, | 814 | .irq_request_resources = msm_gpio_irq_reqres, |
816 | .irq_shutdown = msm_gpio_irq_shutdown, | 815 | .irq_release_resources = msm_gpio_irq_relres, |
817 | }; | 816 | }; |
818 | 817 | ||
819 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 818 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index cec7762cf335..208341fd57d2 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c | |||
@@ -21,9 +21,6 @@ | |||
21 | #include <linux/gpio.h> | 21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | 22 | #include <linux/spinlock.h> |
23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
24 | #include <linux/irq.h> | ||
25 | #include <linux/irqdomain.h> | ||
26 | #include <linux/irqchip/chained_irq.h> | ||
27 | #include <linux/slab.h> | 24 | #include <linux/slab.h> |
28 | #include <linux/of_device.h> | 25 | #include <linux/of_device.h> |
29 | #include <linux/of_address.h> | 26 | #include <linux/of_address.h> |
@@ -246,28 +243,14 @@ enum nmk_gpio_slpm { | |||
246 | NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, | 243 | NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, |
247 | }; | 244 | }; |
248 | 245 | ||
249 | /* | ||
250 | * Platform data to register a block: only the initial gpio/irq number. | ||
251 | */ | ||
252 | struct nmk_gpio_platform_data { | ||
253 | char *name; | ||
254 | int first_gpio; | ||
255 | int first_irq; | ||
256 | int num_gpio; | ||
257 | u32 (*get_secondary_status)(unsigned int bank); | ||
258 | void (*set_ioforce)(bool enable); | ||
259 | bool supports_sleepmode; | ||
260 | }; | ||
261 | |||
262 | struct nmk_gpio_chip { | 246 | struct nmk_gpio_chip { |
263 | struct gpio_chip chip; | 247 | struct gpio_chip chip; |
264 | struct irq_domain *domain; | ||
265 | void __iomem *addr; | 248 | void __iomem *addr; |
266 | struct clk *clk; | 249 | struct clk *clk; |
267 | unsigned int bank; | 250 | unsigned int bank; |
268 | unsigned int parent_irq; | 251 | unsigned int parent_irq; |
269 | int secondary_parent_irq; | 252 | int latent_parent_irq; |
270 | u32 (*get_secondary_status)(unsigned int bank); | 253 | u32 (*get_latent_status)(unsigned int bank); |
271 | void (*set_ioforce)(bool enable); | 254 | void (*set_ioforce)(bool enable); |
272 | spinlock_t lock; | 255 | spinlock_t lock; |
273 | bool sleepmode; | 256 | bool sleepmode; |
@@ -432,7 +415,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |||
432 | u32 falling = nmk_chip->fimsc & BIT(offset); | 415 | u32 falling = nmk_chip->fimsc & BIT(offset); |
433 | u32 rising = nmk_chip->rimsc & BIT(offset); | 416 | u32 rising = nmk_chip->rimsc & BIT(offset); |
434 | int gpio = nmk_chip->chip.base + offset; | 417 | int gpio = nmk_chip->chip.base + offset; |
435 | int irq = irq_find_mapping(nmk_chip->domain, offset); | 418 | int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); |
436 | struct irq_data *d = irq_get_irq_data(irq); | 419 | struct irq_data *d = irq_get_irq_data(irq); |
437 | 420 | ||
438 | if (!rising && !falling) | 421 | if (!rising && !falling) |
@@ -660,11 +643,8 @@ static inline int nmk_gpio_get_bitmask(int gpio) | |||
660 | 643 | ||
661 | static void nmk_gpio_irq_ack(struct irq_data *d) | 644 | static void nmk_gpio_irq_ack(struct irq_data *d) |
662 | { | 645 | { |
663 | struct nmk_gpio_chip *nmk_chip; | 646 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
664 | 647 | struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
665 | nmk_chip = irq_data_get_irq_chip_data(d); | ||
666 | if (!nmk_chip) | ||
667 | return; | ||
668 | 648 | ||
669 | clk_enable(nmk_chip->clk); | 649 | clk_enable(nmk_chip->clk); |
670 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); | 650 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
@@ -848,10 +828,6 @@ static unsigned int nmk_gpio_irq_startup(struct irq_data *d) | |||
848 | { | 828 | { |
849 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | 829 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); |
850 | 830 | ||
851 | if (gpio_lock_as_irq(&nmk_chip->chip, d->hwirq)) | ||
852 | dev_err(nmk_chip->chip.dev, | ||
853 | "unable to lock HW IRQ %lu for IRQ\n", | ||
854 | d->hwirq); | ||
855 | clk_enable(nmk_chip->clk); | 831 | clk_enable(nmk_chip->clk); |
856 | nmk_gpio_irq_unmask(d); | 832 | nmk_gpio_irq_unmask(d); |
857 | return 0; | 833 | return 0; |
@@ -863,7 +839,6 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d) | |||
863 | 839 | ||
864 | nmk_gpio_irq_mask(d); | 840 | nmk_gpio_irq_mask(d); |
865 | clk_disable(nmk_chip->clk); | 841 | clk_disable(nmk_chip->clk); |
866 | gpio_unlock_as_irq(&nmk_chip->chip, d->hwirq); | ||
867 | } | 842 | } |
868 | 843 | ||
869 | static struct irq_chip nmk_gpio_irq_chip = { | 844 | static struct irq_chip nmk_gpio_irq_chip = { |
@@ -881,16 +856,15 @@ static struct irq_chip nmk_gpio_irq_chip = { | |||
881 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | 856 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
882 | u32 status) | 857 | u32 status) |
883 | { | 858 | { |
884 | struct nmk_gpio_chip *nmk_chip; | ||
885 | struct irq_chip *host_chip = irq_get_chip(irq); | 859 | struct irq_chip *host_chip = irq_get_chip(irq); |
860 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); | ||
886 | 861 | ||
887 | chained_irq_enter(host_chip, desc); | 862 | chained_irq_enter(host_chip, desc); |
888 | 863 | ||
889 | nmk_chip = irq_get_handler_data(irq); | ||
890 | while (status) { | 864 | while (status) { |
891 | int bit = __ffs(status); | 865 | int bit = __ffs(status); |
892 | 866 | ||
893 | generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); | 867 | generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); |
894 | status &= ~BIT(bit); | 868 | status &= ~BIT(bit); |
895 | } | 869 | } |
896 | 870 | ||
@@ -899,9 +873,11 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
899 | 873 | ||
900 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 874 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
901 | { | 875 | { |
902 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); | 876 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
877 | struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | ||
903 | u32 status; | 878 | u32 status; |
904 | 879 | ||
880 | pr_err("PLONK IRQ %d\n", irq); | ||
905 | clk_enable(nmk_chip->clk); | 881 | clk_enable(nmk_chip->clk); |
906 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | 882 | status = readl(nmk_chip->addr + NMK_GPIO_IS); |
907 | clk_disable(nmk_chip->clk); | 883 | clk_disable(nmk_chip->clk); |
@@ -909,29 +885,16 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
909 | __nmk_gpio_irq_handler(irq, desc, status); | 885 | __nmk_gpio_irq_handler(irq, desc, status); |
910 | } | 886 | } |
911 | 887 | ||
912 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | 888 | static void nmk_gpio_latent_irq_handler(unsigned int irq, |
913 | struct irq_desc *desc) | 889 | struct irq_desc *desc) |
914 | { | 890 | { |
915 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); | 891 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
916 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); | 892 | struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); |
893 | u32 status = nmk_chip->get_latent_status(nmk_chip->bank); | ||
917 | 894 | ||
918 | __nmk_gpio_irq_handler(irq, desc, status); | 895 | __nmk_gpio_irq_handler(irq, desc, status); |
919 | } | 896 | } |
920 | 897 | ||
921 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) | ||
922 | { | ||
923 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); | ||
924 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | ||
925 | |||
926 | if (nmk_chip->secondary_parent_irq >= 0) { | ||
927 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, | ||
928 | nmk_gpio_secondary_irq_handler); | ||
929 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); | ||
930 | } | ||
931 | |||
932 | return 0; | ||
933 | } | ||
934 | |||
935 | /* I/O Functions */ | 898 | /* I/O Functions */ |
936 | 899 | ||
937 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | 900 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) |
@@ -1010,14 +973,6 @@ static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, | |||
1010 | return 0; | 973 | return 0; |
1011 | } | 974 | } |
1012 | 975 | ||
1013 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | ||
1014 | { | ||
1015 | struct nmk_gpio_chip *nmk_chip = | ||
1016 | container_of(chip, struct nmk_gpio_chip, chip); | ||
1017 | |||
1018 | return irq_create_mapping(nmk_chip->domain, offset); | ||
1019 | } | ||
1020 | |||
1021 | #ifdef CONFIG_DEBUG_FS | 976 | #ifdef CONFIG_DEBUG_FS |
1022 | 977 | ||
1023 | #include <linux/seq_file.h> | 978 | #include <linux/seq_file.h> |
@@ -1116,7 +1071,6 @@ static struct gpio_chip nmk_gpio_template = { | |||
1116 | .get = nmk_gpio_get_input, | 1071 | .get = nmk_gpio_get_input, |
1117 | .direction_output = nmk_gpio_make_output, | 1072 | .direction_output = nmk_gpio_make_output, |
1118 | .set = nmk_gpio_set_output, | 1073 | .set = nmk_gpio_set_output, |
1119 | .to_irq = nmk_gpio_to_irq, | ||
1120 | .dbg_show = nmk_gpio_dbg_show, | 1074 | .dbg_show = nmk_gpio_dbg_show, |
1121 | .can_sleep = false, | 1075 | .can_sleep = false, |
1122 | }; | 1076 | }; |
@@ -1217,62 +1171,35 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |||
1217 | } | 1171 | } |
1218 | } | 1172 | } |
1219 | 1173 | ||
1220 | static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, | ||
1221 | irq_hw_number_t hwirq) | ||
1222 | { | ||
1223 | struct nmk_gpio_chip *nmk_chip = d->host_data; | ||
1224 | |||
1225 | if (!nmk_chip) | ||
1226 | return -EINVAL; | ||
1227 | |||
1228 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | ||
1229 | set_irq_flags(irq, IRQF_VALID); | ||
1230 | irq_set_chip_data(irq, nmk_chip); | ||
1231 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | ||
1232 | |||
1233 | return 0; | ||
1234 | } | ||
1235 | |||
1236 | static const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | ||
1237 | .map = nmk_gpio_irq_map, | ||
1238 | .xlate = irq_domain_xlate_twocell, | ||
1239 | }; | ||
1240 | |||
1241 | static int nmk_gpio_probe(struct platform_device *dev) | 1174 | static int nmk_gpio_probe(struct platform_device *dev) |
1242 | { | 1175 | { |
1243 | struct nmk_gpio_platform_data *pdata; | ||
1244 | struct device_node *np = dev->dev.of_node; | 1176 | struct device_node *np = dev->dev.of_node; |
1245 | struct nmk_gpio_chip *nmk_chip; | 1177 | struct nmk_gpio_chip *nmk_chip; |
1246 | struct gpio_chip *chip; | 1178 | struct gpio_chip *chip; |
1247 | struct resource *res; | 1179 | struct resource *res; |
1248 | struct clk *clk; | 1180 | struct clk *clk; |
1249 | int secondary_irq; | 1181 | int latent_irq; |
1182 | bool supports_sleepmode; | ||
1250 | void __iomem *base; | 1183 | void __iomem *base; |
1251 | int irq; | 1184 | int irq; |
1252 | int ret; | 1185 | int ret; |
1253 | 1186 | ||
1254 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); | ||
1255 | if (!pdata) | ||
1256 | return -ENOMEM; | ||
1257 | |||
1258 | if (of_get_property(np, "st,supports-sleepmode", NULL)) | 1187 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
1259 | pdata->supports_sleepmode = true; | 1188 | supports_sleepmode = true; |
1189 | else | ||
1190 | supports_sleepmode = false; | ||
1260 | 1191 | ||
1261 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | 1192 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { |
1262 | dev_err(&dev->dev, "gpio-bank property not found\n"); | 1193 | dev_err(&dev->dev, "gpio-bank property not found\n"); |
1263 | return -EINVAL; | 1194 | return -EINVAL; |
1264 | } | 1195 | } |
1265 | 1196 | ||
1266 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | ||
1267 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | ||
1268 | |||
1269 | irq = platform_get_irq(dev, 0); | 1197 | irq = platform_get_irq(dev, 0); |
1270 | if (irq < 0) | 1198 | if (irq < 0) |
1271 | return irq; | 1199 | return irq; |
1272 | 1200 | ||
1273 | secondary_irq = platform_get_irq(dev, 1); | 1201 | /* It's OK for this IRQ not to be present */ |
1274 | if (secondary_irq >= 0 && !pdata->get_secondary_status) | 1202 | latent_irq = platform_get_irq(dev, 1); |
1275 | return -EINVAL; | ||
1276 | 1203 | ||
1277 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | 1204 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
1278 | base = devm_ioremap_resource(&dev->dev, res); | 1205 | base = devm_ioremap_resource(&dev->dev, res); |
@@ -1297,16 +1224,14 @@ static int nmk_gpio_probe(struct platform_device *dev) | |||
1297 | nmk_chip->addr = base; | 1224 | nmk_chip->addr = base; |
1298 | nmk_chip->chip = nmk_gpio_template; | 1225 | nmk_chip->chip = nmk_gpio_template; |
1299 | nmk_chip->parent_irq = irq; | 1226 | nmk_chip->parent_irq = irq; |
1300 | nmk_chip->secondary_parent_irq = secondary_irq; | 1227 | nmk_chip->latent_parent_irq = latent_irq; |
1301 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | 1228 | nmk_chip->sleepmode = supports_sleepmode; |
1302 | nmk_chip->set_ioforce = pdata->set_ioforce; | ||
1303 | nmk_chip->sleepmode = pdata->supports_sleepmode; | ||
1304 | spin_lock_init(&nmk_chip->lock); | 1229 | spin_lock_init(&nmk_chip->lock); |
1305 | 1230 | ||
1306 | chip = &nmk_chip->chip; | 1231 | chip = &nmk_chip->chip; |
1307 | chip->base = pdata->first_gpio; | 1232 | chip->base = dev->id * NMK_GPIO_PER_CHIP; |
1308 | chip->ngpio = pdata->num_gpio; | 1233 | chip->ngpio = NMK_GPIO_PER_CHIP; |
1309 | chip->label = pdata->name ?: dev_name(&dev->dev); | 1234 | chip->label = dev_name(&dev->dev); |
1310 | chip->dev = &dev->dev; | 1235 | chip->dev = &dev->dev; |
1311 | chip->owner = THIS_MODULE; | 1236 | chip->owner = THIS_MODULE; |
1312 | 1237 | ||
@@ -1325,17 +1250,31 @@ static int nmk_gpio_probe(struct platform_device *dev) | |||
1325 | 1250 | ||
1326 | platform_set_drvdata(dev, nmk_chip); | 1251 | platform_set_drvdata(dev, nmk_chip); |
1327 | 1252 | ||
1328 | nmk_chip->domain = irq_domain_add_simple(np, | 1253 | /* |
1329 | NMK_GPIO_PER_CHIP, 0, | 1254 | * Let the generic code handle this edge IRQ, the the chained |
1330 | &nmk_gpio_irq_simple_ops, nmk_chip); | 1255 | * handler will perform the actual work of handling the parent |
1331 | if (!nmk_chip->domain) { | 1256 | * interrupt. |
1332 | dev_err(&dev->dev, "failed to create irqdomain\n"); | 1257 | */ |
1333 | /* Just do this, no matter if it fails */ | 1258 | ret = gpiochip_irqchip_add(&nmk_chip->chip, |
1259 | &nmk_gpio_irq_chip, | ||
1260 | 0, | ||
1261 | handle_edge_irq, | ||
1262 | IRQ_TYPE_EDGE_FALLING); | ||
1263 | if (ret) { | ||
1264 | dev_err(&dev->dev, "could not add irqchip\n"); | ||
1334 | ret = gpiochip_remove(&nmk_chip->chip); | 1265 | ret = gpiochip_remove(&nmk_chip->chip); |
1335 | return -ENOSYS; | 1266 | return -ENODEV; |
1336 | } | 1267 | } |
1337 | 1268 | /* Then register the chain on the parent IRQ */ | |
1338 | nmk_gpio_init_irq(nmk_chip); | 1269 | gpiochip_set_chained_irqchip(&nmk_chip->chip, |
1270 | &nmk_gpio_irq_chip, | ||
1271 | nmk_chip->parent_irq, | ||
1272 | nmk_gpio_irq_handler); | ||
1273 | if (nmk_chip->latent_parent_irq > 0) | ||
1274 | gpiochip_set_chained_irqchip(&nmk_chip->chip, | ||
1275 | &nmk_gpio_irq_chip, | ||
1276 | nmk_chip->latent_parent_irq, | ||
1277 | nmk_gpio_latent_irq_handler); | ||
1339 | 1278 | ||
1340 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); | 1279 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1341 | 1280 | ||
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 5f3adb87c1ef..76502aab2cb1 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c | |||
@@ -595,23 +595,23 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) | |||
595 | return 0; | 595 | return 0; |
596 | } | 596 | } |
597 | 597 | ||
598 | static unsigned int sirfsoc_gpio_irq_startup(struct irq_data *d) | 598 | static int sirfsoc_gpio_irq_reqres(struct irq_data *d) |
599 | { | 599 | { |
600 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | 600 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
601 | 601 | ||
602 | if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE)) | 602 | if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE)) { |
603 | dev_err(bank->chip.gc.dev, | 603 | dev_err(bank->chip.gc.dev, |
604 | "unable to lock HW IRQ %lu for IRQ\n", | 604 | "unable to lock HW IRQ %lu for IRQ\n", |
605 | d->hwirq); | 605 | d->hwirq); |
606 | sirfsoc_gpio_irq_unmask(d); | 606 | return -EINVAL; |
607 | } | ||
607 | return 0; | 608 | return 0; |
608 | } | 609 | } |
609 | 610 | ||
610 | static void sirfsoc_gpio_irq_shutdown(struct irq_data *d) | 611 | static void sirfsoc_gpio_irq_relres(struct irq_data *d) |
611 | { | 612 | { |
612 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | 613 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
613 | 614 | ||
614 | sirfsoc_gpio_irq_mask(d); | ||
615 | gpio_unlock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); | 615 | gpio_unlock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); |
616 | } | 616 | } |
617 | 617 | ||
@@ -621,8 +621,8 @@ static struct irq_chip sirfsoc_irq_chip = { | |||
621 | .irq_mask = sirfsoc_gpio_irq_mask, | 621 | .irq_mask = sirfsoc_gpio_irq_mask, |
622 | .irq_unmask = sirfsoc_gpio_irq_unmask, | 622 | .irq_unmask = sirfsoc_gpio_irq_unmask, |
623 | .irq_set_type = sirfsoc_gpio_irq_type, | 623 | .irq_set_type = sirfsoc_gpio_irq_type, |
624 | .irq_startup = sirfsoc_gpio_irq_startup, | 624 | .irq_request_resources = sirfsoc_gpio_irq_reqres, |
625 | .irq_shutdown = sirfsoc_gpio_irq_shutdown, | 625 | .irq_release_resources = sirfsoc_gpio_irq_relres, |
626 | }; | 626 | }; |
627 | 627 | ||
628 | static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | 628 | static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) |