aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2014-01-04 00:09:51 -0500
committerOlof Johansson <olof@lixom.net>2014-01-04 00:09:51 -0500
commit11b35a352521b740944455b45dbee190e9c893a4 (patch)
treeaa5bc9a24cb6290aaed5476990f0e5a05442ff38 /drivers/pinctrl
parent5631e7f4e29b1ebf3d856614c0b5876463857da6 (diff)
parentb652896b02df3dfde3a68957cce01f2aa4585842 (diff)
Merge tag 'renesas-dt3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman: Third Round of Renesas ARM Based SoC DT Updates for v3.14 * r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCSs - Add SSI, QSPI and MSIOF clocks in device tree r8a7791 (R-Car M2) based Koelsch and r8a7790 (R-Car H2) based Lager boards - Remove reference DTS - Specify external clock frequency in DT - Sync non-reference DTS with referene DTS - Add clocks to DTS * r8a7740 (R-Mobile A1) based Armadillo board - Add gpio-keys device - Add PWM backlight enable GPIO - Add PWM backlight power supply * r8a73a0 (SH-Mobile AG5), r8a7740 (R-Mobile A1) and r8a73a4 (SH-Mobile APE6) SoCs - Specify PFC interrupts in DT * tag 'renesas-dt3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (72 commits) ARM: shmobile: r8a7791: Add SSI clocks in device tree ARM: shmobile: r8a7790: Add SSI clocks in device tree ARM: shmobile: r8a7791: Add QSPI module clock in device tree ARM: shmobile: r8a7790: Add QSPI module clock in device tree ARM: shmobile: r8a7791: Add MSIOF clocks in device tree ARM: shmobile: r8a7790: Add MSIOF clocks in device tree ARM: shmobile: Remove Koelsch reference DTS ARM: shmobile: Remove Lager reference DTS ARM: shmobile: koelsch: Specify external clock frequency in DT ARM: shmobile: lager: Specify external clock frequency in DT ARM: shmobile: Sync Koelsch DTS with Koelsch reference DTS ARM: shmobile: Sync Lager DTS with Lager reference DTS ARM: shmobile: r8a7791: Add clocks ARM: shmobile: r8a7790: Reference clocks ARM: shmobile: r8a7790: Add clocks ARM: shmobile: armadillo: dts: Add gpio-keys device ARM: shmobile: sh73a0: Specify PFC interrupts in DT ARM: shmobile: r8a7740: Specify PFC interrupts in DT ARM: shmobile: r8a73a4: Specify PFC interrupts in DT ARM: shmobile: armadillo: dts: Add PWM backlight enable GPIO ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig28
-rw-r--r--drivers/pinctrl/Makefile3
-rw-r--r--drivers/pinctrl/pinconf.c20
-rw-r--r--drivers/pinctrl/pinctrl-at91.c9
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c30
-rw-r--r--drivers/pinctrl/pinctrl-imx1-core.c7
-rw-r--r--drivers/pinctrl/pinctrl-imx25.c351
-rw-r--r--drivers/pinctrl/pinctrl-msm.c1028
-rw-r--r--drivers/pinctrl/pinctrl-msm.h122
-rw-r--r--drivers/pinctrl/pinctrl-msm8x74.c636
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c6
-rw-r--r--drivers/pinctrl/sh-pfc/core.c76
-rw-r--r--drivers/pinctrl/sh-pfc/core.h4
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c24
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c15
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c13
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c748
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c57
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c13
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c64
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h7
21 files changed, 3051 insertions, 210 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 33f9dc1f14fd..30fcb897eb99 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -116,15 +116,22 @@ config PINCTRL_IMX1_CORE
116 116
117config PINCTRL_IMX27 117config PINCTRL_IMX27
118 bool "IMX27 pinctrl driver" 118 bool "IMX27 pinctrl driver"
119 depends on OF
120 depends on SOC_IMX27 119 depends on SOC_IMX27
121 select PINCTRL_IMX1_CORE 120 select PINCTRL_IMX1_CORE
122 help 121 help
123 Say Y here to enable the imx27 pinctrl driver 122 Say Y here to enable the imx27 pinctrl driver
124 123
124
125config PINCTRL_IMX25
126 bool "IMX25 pinctrl driver"
127 depends on OF
128 depends on SOC_IMX25
129 select PINCTRL_IMX
130 help
131 Say Y here to enable the imx25 pinctrl driver
132
125config PINCTRL_IMX35 133config PINCTRL_IMX35
126 bool "IMX35 pinctrl driver" 134 bool "IMX35 pinctrl driver"
127 depends on OF
128 depends on SOC_IMX35 135 depends on SOC_IMX35
129 select PINCTRL_IMX 136 select PINCTRL_IMX
130 help 137 help
@@ -132,7 +139,6 @@ config PINCTRL_IMX35
132 139
133config PINCTRL_IMX50 140config PINCTRL_IMX50
134 bool "IMX50 pinctrl driver" 141 bool "IMX50 pinctrl driver"
135 depends on OF
136 depends on SOC_IMX50 142 depends on SOC_IMX50
137 select PINCTRL_IMX 143 select PINCTRL_IMX
138 help 144 help
@@ -140,7 +146,6 @@ config PINCTRL_IMX50
140 146
141config PINCTRL_IMX51 147config PINCTRL_IMX51
142 bool "IMX51 pinctrl driver" 148 bool "IMX51 pinctrl driver"
143 depends on OF
144 depends on SOC_IMX51 149 depends on SOC_IMX51
145 select PINCTRL_IMX 150 select PINCTRL_IMX
146 help 151 help
@@ -148,7 +153,6 @@ config PINCTRL_IMX51
148 153
149config PINCTRL_IMX53 154config PINCTRL_IMX53
150 bool "IMX53 pinctrl driver" 155 bool "IMX53 pinctrl driver"
151 depends on OF
152 depends on SOC_IMX53 156 depends on SOC_IMX53
153 select PINCTRL_IMX 157 select PINCTRL_IMX
154 help 158 help
@@ -156,7 +160,6 @@ config PINCTRL_IMX53
156 160
157config PINCTRL_IMX6Q 161config PINCTRL_IMX6Q
158 bool "IMX6Q/DL pinctrl driver" 162 bool "IMX6Q/DL pinctrl driver"
159 depends on OF
160 depends on SOC_IMX6Q 163 depends on SOC_IMX6Q
161 select PINCTRL_IMX 164 select PINCTRL_IMX
162 help 165 help
@@ -164,7 +167,6 @@ config PINCTRL_IMX6Q
164 167
165config PINCTRL_IMX6SL 168config PINCTRL_IMX6SL
166 bool "IMX6SL pinctrl driver" 169 bool "IMX6SL pinctrl driver"
167 depends on OF
168 depends on SOC_IMX6SL 170 depends on SOC_IMX6SL
169 select PINCTRL_IMX 171 select PINCTRL_IMX
170 help 172 help
@@ -172,7 +174,6 @@ config PINCTRL_IMX6SL
172 174
173config PINCTRL_VF610 175config PINCTRL_VF610
174 bool "Freescale Vybrid VF610 pinctrl driver" 176 bool "Freescale Vybrid VF610 pinctrl driver"
175 depends on OF
176 depends on SOC_VF610 177 depends on SOC_VF610
177 select PINCTRL_IMX 178 select PINCTRL_IMX
178 help 179 help
@@ -202,6 +203,17 @@ config PINCTRL_IMX28
202 bool 203 bool
203 select PINCTRL_MXS 204 select PINCTRL_MXS
204 205
206config PINCTRL_MSM
207 bool
208 select PINMUX
209 select PINCONF
210 select GENERIC_PINCONF
211
212config PINCTRL_MSM8X74
213 bool "Qualcomm 8x74 pin controller driver"
214 depends on OF && OF_IRQ
215 select PINCTRL_MSM
216
205config PINCTRL_NOMADIK 217config PINCTRL_NOMADIK
206 bool "Nomadik pin controller driver" 218 bool "Nomadik pin controller driver"
207 depends on ARCH_U8500 || ARCH_NOMADIK 219 depends on ARCH_U8500 || ARCH_NOMADIK
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 4f7be2921aa5..5d91e4b448d4 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -34,7 +34,10 @@ obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
34obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 34obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
35obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 35obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
36obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 36obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
37obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
37obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 38obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
39obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
40obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
38obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o 41obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
39obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o 42obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
40obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 43obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index b8fcc38c0d11..4187fe58794d 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,12 +28,6 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
28{ 28{
29 const struct pinconf_ops *ops = pctldev->desc->confops; 29 const struct pinconf_ops *ops = pctldev->desc->confops;
30 30
31 /* We must be able to read out pin status */
32 if (!ops->pin_config_get && !ops->pin_config_group_get) {
33 dev_err(pctldev->dev,
34 "pinconf must be able to read out pin status\n");
35 return -EINVAL;
36 }
37 /* We have to be able to config the pins in SOME way */ 31 /* We have to be able to config the pins in SOME way */
38 if (!ops->pin_config_set && !ops->pin_config_group_set) { 32 if (!ops->pin_config_set && !ops->pin_config_group_set) {
39 dev_err(pctldev->dev, 33 dev_err(pctldev->dev,
@@ -67,9 +61,9 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
67 const struct pinconf_ops *ops = pctldev->desc->confops; 61 const struct pinconf_ops *ops = pctldev->desc->confops;
68 62
69 if (!ops || !ops->pin_config_get) { 63 if (!ops || !ops->pin_config_get) {
70 dev_err(pctldev->dev, "cannot get pin configuration, missing " 64 dev_dbg(pctldev->dev, "cannot get pin configuration, missing "
71 "pin_config_get() function in driver\n"); 65 "pin_config_get() function in driver\n");
72 return -EINVAL; 66 return -ENOTSUPP;
73 } 67 }
74 68
75 return ops->pin_config_get(pctldev, pin, config); 69 return ops->pin_config_get(pctldev, pin, config);
@@ -93,10 +87,10 @@ int pin_config_group_get(const char *dev_name, const char *pin_group,
93 ops = pctldev->desc->confops; 87 ops = pctldev->desc->confops;
94 88
95 if (!ops || !ops->pin_config_group_get) { 89 if (!ops || !ops->pin_config_group_get) {
96 dev_err(pctldev->dev, "cannot get configuration for pin " 90 dev_dbg(pctldev->dev, "cannot get configuration for pin "
97 "group, missing group config get function in " 91 "group, missing group config get function in "
98 "driver\n"); 92 "driver\n");
99 ret = -EINVAL; 93 ret = -ENOTSUPP;
100 goto unlock; 94 goto unlock;
101 } 95 }
102 96
@@ -305,9 +299,6 @@ static int pinconf_pins_show(struct seq_file *s, void *what)
305 const struct pinconf_ops *ops = pctldev->desc->confops; 299 const struct pinconf_ops *ops = pctldev->desc->confops;
306 unsigned i, pin; 300 unsigned i, pin;
307 301
308 if (!ops || !ops->pin_config_get)
309 return 0;
310
311 seq_puts(s, "Pin config settings per pin\n"); 302 seq_puts(s, "Pin config settings per pin\n");
312 seq_puts(s, "Format: pin (name): configs\n"); 303 seq_puts(s, "Format: pin (name): configs\n");
313 304
@@ -356,9 +347,6 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
356 unsigned ngroups = pctlops->get_groups_count(pctldev); 347 unsigned ngroups = pctlops->get_groups_count(pctldev);
357 unsigned selector = 0; 348 unsigned selector = 0;
358 349
359 if (!ops || !ops->pin_config_group_get)
360 return 0;
361
362 seq_puts(s, "Pin config settings per pin group\n"); 350 seq_puts(s, "Pin config settings per pin group\n");
363 seq_puts(s, "Format: group (name): configs\n"); 351 seq_puts(s, "Format: group (name): configs\n");
364 352
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index a7549c4c83b4..b0b78f3468ae 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -118,7 +118,7 @@ struct at91_pin_group {
118}; 118};
119 119
120/** 120/**
121 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group 121 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
122 * on new IP with support for periph C and D the way to mux in 122 * on new IP with support for periph C and D the way to mux in
123 * periph A and B has changed 123 * periph A and B has changed
124 * So provide the right call back 124 * So provide the right call back
@@ -722,7 +722,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
722 unsigned pin; 722 unsigned pin;
723 int div; 723 int div;
724 724
725 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); 725 *config = 0;
726 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
726 pio = pin_to_controller(info, pin_to_bank(pin_id)); 727 pio = pin_to_controller(info, pin_to_bank(pin_id));
727 pin = pin_id % MAX_NB_GPIO_PER_BANK; 728 pin = pin_id % MAX_NB_GPIO_PER_BANK;
728 729
@@ -1396,7 +1397,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1396 chained_irq_enter(chip, desc); 1397 chained_irq_enter(chip, desc);
1397 for (;;) { 1398 for (;;) {
1398 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1399 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1399 * When there none are pending, we're finished unless we need 1400 * When there are none pending, we're finished unless we need
1400 * to process multiple banks (like ID_PIOCDE on sam9263). 1401 * to process multiple banks (like ID_PIOCDE on sam9263).
1401 */ 1402 */
1402 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1403 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
@@ -1505,7 +1506,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1505 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1506 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1506 1507
1507 /* The top level handler handles one bank of GPIOs, except 1508 /* The top level handler handles one bank of GPIOs, except
1508 * on some SoC it can handles up to three... 1509 * on some SoC it can handle up to three...
1509 * We only set up the handler for the first of the list. 1510 * We only set up the handler for the first of the list.
1510 */ 1511 */
1511 if (prev && prev->next == at91_gpio) 1512 if (prev && prev->next == at91_gpio)
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index 2832576d8b12..5888066d80c2 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -286,13 +286,19 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
286 spin_lock_irqsave(&vg->lock, flags); 286 spin_lock_irqsave(&vg->lock, flags);
287 287
288 for (i = 0; i < vg->chip.ngpio; i++) { 288 for (i = 0; i < vg->chip.ngpio; i++) {
289 const char *label;
289 offs = vg->range->pins[i] * 16; 290 offs = vg->range->pins[i] * 16;
290 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 291 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
291 val = readl(vg->reg_base + offs + BYT_VAL_REG); 292 val = readl(vg->reg_base + offs + BYT_VAL_REG);
292 293
294 label = gpiochip_is_requested(chip, i);
295 if (!label)
296 label = "Unrequested";
297
293 seq_printf(s, 298 seq_printf(s,
294 " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n", 299 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
295 i, 300 i,
301 label,
296 val & BYT_INPUT_EN ? " " : "in", 302 val & BYT_INPUT_EN ? " " : "in",
297 val & BYT_OUTPUT_EN ? " " : "out", 303 val & BYT_OUTPUT_EN ? " " : "out",
298 val & BYT_LEVEL ? "hi" : "lo", 304 val & BYT_LEVEL ? "hi" : "lo",
@@ -366,11 +372,33 @@ static void byt_irq_mask(struct irq_data *d)
366{ 372{
367} 373}
368 374
375static unsigned int byt_irq_startup(struct irq_data *d)
376{
377 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
378
379 if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d)))
380 dev_err(vg->chip.dev,
381 "unable to lock HW IRQ %lu for IRQ\n",
382 irqd_to_hwirq(d));
383 byt_irq_unmask(d);
384 return 0;
385}
386
387static void byt_irq_shutdown(struct irq_data *d)
388{
389 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
390
391 byt_irq_mask(d);
392 gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
393}
394
369static struct irq_chip byt_irqchip = { 395static struct irq_chip byt_irqchip = {
370 .name = "BYT-GPIO", 396 .name = "BYT-GPIO",
371 .irq_mask = byt_irq_mask, 397 .irq_mask = byt_irq_mask,
372 .irq_unmask = byt_irq_unmask, 398 .irq_unmask = byt_irq_unmask,
373 .irq_set_type = byt_irq_type, 399 .irq_set_type = byt_irq_type,
400 .irq_startup = byt_irq_startup,
401 .irq_shutdown = byt_irq_shutdown,
374}; 402};
375 403
376static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 404static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
index f77914ac081a..17aecde1b51d 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -638,6 +638,13 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev,
638 return -EINVAL; 638 return -EINVAL;
639 } 639 }
640 640
641 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
642 if (ret) {
643 pinctrl_unregister(ipctl->pctl);
644 dev_err(&pdev->dev, "Failed to populate subdevices\n");
645 return ret;
646 }
647
641 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 648 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
642 649
643 return 0; 650 return 0;
diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/pinctrl-imx25.c
new file mode 100644
index 000000000000..1aae1b61c4dc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx25.c
@@ -0,0 +1,351 @@
1/*
2 * imx25 pinctrl driver.
3 *
4 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
5 *
6 * This driver was mostly copied from the imx51 pinctrl driver which has:
7 *
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Copyright (C) 2012 Linaro, Inc.
10 *
11 * Author: Denis Carikli <denis@eukrea.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as published
15 * by the Free Software Foundation.
16 */
17
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pinctrl/pinctrl.h>
25
26#include "pinctrl-imx.h"
27
28enum imx25_pads {
29 MX25_PAD_RESERVE0 = 1,
30 MX25_PAD_RESERVE1 = 2,
31 MX25_PAD_A10 = 3,
32 MX25_PAD_A13 = 4,
33 MX25_PAD_A14 = 5,
34 MX25_PAD_A15 = 6,
35 MX25_PAD_A16 = 7,
36 MX25_PAD_A17 = 8,
37 MX25_PAD_A18 = 9,
38 MX25_PAD_A19 = 10,
39 MX25_PAD_A20 = 11,
40 MX25_PAD_A21 = 12,
41 MX25_PAD_A22 = 13,
42 MX25_PAD_A23 = 14,
43 MX25_PAD_A24 = 15,
44 MX25_PAD_A25 = 16,
45 MX25_PAD_EB0 = 17,
46 MX25_PAD_EB1 = 18,
47 MX25_PAD_OE = 19,
48 MX25_PAD_CS0 = 20,
49 MX25_PAD_CS1 = 21,
50 MX25_PAD_CS4 = 22,
51 MX25_PAD_CS5 = 23,
52 MX25_PAD_NF_CE0 = 24,
53 MX25_PAD_ECB = 25,
54 MX25_PAD_LBA = 26,
55 MX25_PAD_BCLK = 27,
56 MX25_PAD_RW = 28,
57 MX25_PAD_NFWE_B = 29,
58 MX25_PAD_NFRE_B = 30,
59 MX25_PAD_NFALE = 31,
60 MX25_PAD_NFCLE = 32,
61 MX25_PAD_NFWP_B = 33,
62 MX25_PAD_NFRB = 34,
63 MX25_PAD_D15 = 35,
64 MX25_PAD_D14 = 36,
65 MX25_PAD_D13 = 37,
66 MX25_PAD_D12 = 38,
67 MX25_PAD_D11 = 39,
68 MX25_PAD_D10 = 40,
69 MX25_PAD_D9 = 41,
70 MX25_PAD_D8 = 42,
71 MX25_PAD_D7 = 43,
72 MX25_PAD_D6 = 44,
73 MX25_PAD_D5 = 45,
74 MX25_PAD_D4 = 46,
75 MX25_PAD_D3 = 47,
76 MX25_PAD_D2 = 48,
77 MX25_PAD_D1 = 49,
78 MX25_PAD_D0 = 50,
79 MX25_PAD_LD0 = 51,
80 MX25_PAD_LD1 = 52,
81 MX25_PAD_LD2 = 53,
82 MX25_PAD_LD3 = 54,
83 MX25_PAD_LD4 = 55,
84 MX25_PAD_LD5 = 56,
85 MX25_PAD_LD6 = 57,
86 MX25_PAD_LD7 = 58,
87 MX25_PAD_LD8 = 59,
88 MX25_PAD_LD9 = 60,
89 MX25_PAD_LD10 = 61,
90 MX25_PAD_LD11 = 62,
91 MX25_PAD_LD12 = 63,
92 MX25_PAD_LD13 = 64,
93 MX25_PAD_LD14 = 65,
94 MX25_PAD_LD15 = 66,
95 MX25_PAD_HSYNC = 67,
96 MX25_PAD_VSYNC = 68,
97 MX25_PAD_LSCLK = 69,
98 MX25_PAD_OE_ACD = 70,
99 MX25_PAD_CONTRAST = 71,
100 MX25_PAD_PWM = 72,
101 MX25_PAD_CSI_D2 = 73,
102 MX25_PAD_CSI_D3 = 74,
103 MX25_PAD_CSI_D4 = 75,
104 MX25_PAD_CSI_D5 = 76,
105 MX25_PAD_CSI_D6 = 77,
106 MX25_PAD_CSI_D7 = 78,
107 MX25_PAD_CSI_D8 = 79,
108 MX25_PAD_CSI_D9 = 80,
109 MX25_PAD_CSI_MCLK = 81,
110 MX25_PAD_CSI_VSYNC = 82,
111 MX25_PAD_CSI_HSYNC = 83,
112 MX25_PAD_CSI_PIXCLK = 84,
113 MX25_PAD_I2C1_CLK = 85,
114 MX25_PAD_I2C1_DAT = 86,
115 MX25_PAD_CSPI1_MOSI = 87,
116 MX25_PAD_CSPI1_MISO = 88,
117 MX25_PAD_CSPI1_SS0 = 89,
118 MX25_PAD_CSPI1_SS1 = 90,
119 MX25_PAD_CSPI1_SCLK = 91,
120 MX25_PAD_CSPI1_RDY = 92,
121 MX25_PAD_UART1_RXD = 93,
122 MX25_PAD_UART1_TXD = 94,
123 MX25_PAD_UART1_RTS = 95,
124 MX25_PAD_UART1_CTS = 96,
125 MX25_PAD_UART2_RXD = 97,
126 MX25_PAD_UART2_TXD = 98,
127 MX25_PAD_UART2_RTS = 99,
128 MX25_PAD_UART2_CTS = 100,
129 MX25_PAD_SD1_CMD = 101,
130 MX25_PAD_SD1_CLK = 102,
131 MX25_PAD_SD1_DATA0 = 103,
132 MX25_PAD_SD1_DATA1 = 104,
133 MX25_PAD_SD1_DATA2 = 105,
134 MX25_PAD_SD1_DATA3 = 106,
135 MX25_PAD_KPP_ROW0 = 107,
136 MX25_PAD_KPP_ROW1 = 108,
137 MX25_PAD_KPP_ROW2 = 109,
138 MX25_PAD_KPP_ROW3 = 110,
139 MX25_PAD_KPP_COL0 = 111,
140 MX25_PAD_KPP_COL1 = 112,
141 MX25_PAD_KPP_COL2 = 113,
142 MX25_PAD_KPP_COL3 = 114,
143 MX25_PAD_FEC_MDC = 115,
144 MX25_PAD_FEC_MDIO = 116,
145 MX25_PAD_FEC_TDATA0 = 117,
146 MX25_PAD_FEC_TDATA1 = 118,
147 MX25_PAD_FEC_TX_EN = 119,
148 MX25_PAD_FEC_RDATA0 = 120,
149 MX25_PAD_FEC_RDATA1 = 121,
150 MX25_PAD_FEC_RX_DV = 122,
151 MX25_PAD_FEC_TX_CLK = 123,
152 MX25_PAD_RTCK = 124,
153 MX25_PAD_DE_B = 125,
154 MX25_PAD_GPIO_A = 126,
155 MX25_PAD_GPIO_B = 127,
156 MX25_PAD_GPIO_C = 128,
157 MX25_PAD_GPIO_D = 129,
158 MX25_PAD_GPIO_E = 130,
159 MX25_PAD_GPIO_F = 131,
160 MX25_PAD_EXT_ARMCLK = 132,
161 MX25_PAD_UPLL_BYPCLK = 133,
162 MX25_PAD_VSTBY_REQ = 134,
163 MX25_PAD_VSTBY_ACK = 135,
164 MX25_PAD_POWER_FAIL = 136,
165 MX25_PAD_CLKO = 137,
166 MX25_PAD_BOOT_MODE0 = 138,
167 MX25_PAD_BOOT_MODE1 = 139,
168};
169
170/* Pad names for the pinmux subsystem */
171static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
172 IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
173 IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
174 IMX_PINCTRL_PIN(MX25_PAD_A10),
175 IMX_PINCTRL_PIN(MX25_PAD_A13),
176 IMX_PINCTRL_PIN(MX25_PAD_A14),
177 IMX_PINCTRL_PIN(MX25_PAD_A15),
178 IMX_PINCTRL_PIN(MX25_PAD_A16),
179 IMX_PINCTRL_PIN(MX25_PAD_A17),
180 IMX_PINCTRL_PIN(MX25_PAD_A18),
181 IMX_PINCTRL_PIN(MX25_PAD_A19),
182 IMX_PINCTRL_PIN(MX25_PAD_A20),
183 IMX_PINCTRL_PIN(MX25_PAD_A21),
184 IMX_PINCTRL_PIN(MX25_PAD_A22),
185 IMX_PINCTRL_PIN(MX25_PAD_A23),
186 IMX_PINCTRL_PIN(MX25_PAD_A24),
187 IMX_PINCTRL_PIN(MX25_PAD_A25),
188 IMX_PINCTRL_PIN(MX25_PAD_EB0),
189 IMX_PINCTRL_PIN(MX25_PAD_EB1),
190 IMX_PINCTRL_PIN(MX25_PAD_OE),
191 IMX_PINCTRL_PIN(MX25_PAD_CS0),
192 IMX_PINCTRL_PIN(MX25_PAD_CS1),
193 IMX_PINCTRL_PIN(MX25_PAD_CS4),
194 IMX_PINCTRL_PIN(MX25_PAD_CS5),
195 IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
196 IMX_PINCTRL_PIN(MX25_PAD_ECB),
197 IMX_PINCTRL_PIN(MX25_PAD_LBA),
198 IMX_PINCTRL_PIN(MX25_PAD_BCLK),
199 IMX_PINCTRL_PIN(MX25_PAD_RW),
200 IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
201 IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
202 IMX_PINCTRL_PIN(MX25_PAD_NFALE),
203 IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
204 IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
205 IMX_PINCTRL_PIN(MX25_PAD_NFRB),
206 IMX_PINCTRL_PIN(MX25_PAD_D15),
207 IMX_PINCTRL_PIN(MX25_PAD_D14),
208 IMX_PINCTRL_PIN(MX25_PAD_D13),
209 IMX_PINCTRL_PIN(MX25_PAD_D12),
210 IMX_PINCTRL_PIN(MX25_PAD_D11),
211 IMX_PINCTRL_PIN(MX25_PAD_D10),
212 IMX_PINCTRL_PIN(MX25_PAD_D9),
213 IMX_PINCTRL_PIN(MX25_PAD_D8),
214 IMX_PINCTRL_PIN(MX25_PAD_D7),
215 IMX_PINCTRL_PIN(MX25_PAD_D6),
216 IMX_PINCTRL_PIN(MX25_PAD_D5),
217 IMX_PINCTRL_PIN(MX25_PAD_D4),
218 IMX_PINCTRL_PIN(MX25_PAD_D3),
219 IMX_PINCTRL_PIN(MX25_PAD_D2),
220 IMX_PINCTRL_PIN(MX25_PAD_D1),
221 IMX_PINCTRL_PIN(MX25_PAD_D0),
222 IMX_PINCTRL_PIN(MX25_PAD_LD0),
223 IMX_PINCTRL_PIN(MX25_PAD_LD1),
224 IMX_PINCTRL_PIN(MX25_PAD_LD2),
225 IMX_PINCTRL_PIN(MX25_PAD_LD3),
226 IMX_PINCTRL_PIN(MX25_PAD_LD4),
227 IMX_PINCTRL_PIN(MX25_PAD_LD5),
228 IMX_PINCTRL_PIN(MX25_PAD_LD6),
229 IMX_PINCTRL_PIN(MX25_PAD_LD7),
230 IMX_PINCTRL_PIN(MX25_PAD_LD8),
231 IMX_PINCTRL_PIN(MX25_PAD_LD9),
232 IMX_PINCTRL_PIN(MX25_PAD_LD10),
233 IMX_PINCTRL_PIN(MX25_PAD_LD11),
234 IMX_PINCTRL_PIN(MX25_PAD_LD12),
235 IMX_PINCTRL_PIN(MX25_PAD_LD13),
236 IMX_PINCTRL_PIN(MX25_PAD_LD14),
237 IMX_PINCTRL_PIN(MX25_PAD_LD15),
238 IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
239 IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
240 IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
241 IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
242 IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
243 IMX_PINCTRL_PIN(MX25_PAD_PWM),
244 IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
245 IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
246 IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
247 IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
248 IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
249 IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
250 IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
251 IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
252 IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
253 IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
254 IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
255 IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
256 IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
257 IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
258 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
259 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
260 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
261 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
262 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
263 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
264 IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
265 IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
266 IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
267 IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
268 IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
269 IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
270 IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
271 IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
272 IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
273 IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
274 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
275 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
276 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
277 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
278 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
279 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
280 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
281 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
282 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
283 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
284 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
285 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
286 IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
287 IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
288 IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
289 IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
290 IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
291 IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
292 IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
293 IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
294 IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
295 IMX_PINCTRL_PIN(MX25_PAD_RTCK),
296 IMX_PINCTRL_PIN(MX25_PAD_DE_B),
297 IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
298 IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
299 IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
300 IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
301 IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
302 IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
303 IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
304 IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
305 IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
306 IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
307 IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
308 IMX_PINCTRL_PIN(MX25_PAD_CLKO),
309 IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
310 IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
311};
312
313static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
314 .pins = imx25_pinctrl_pads,
315 .npins = ARRAY_SIZE(imx25_pinctrl_pads),
316};
317
318static struct of_device_id imx25_pinctrl_of_match[] = {
319 { .compatible = "fsl,imx25-iomuxc", },
320 { /* sentinel */ }
321};
322
323static int imx25_pinctrl_probe(struct platform_device *pdev)
324{
325 return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
326}
327
328static struct platform_driver imx25_pinctrl_driver = {
329 .driver = {
330 .name = "imx25-pinctrl",
331 .owner = THIS_MODULE,
332 .of_match_table = of_match_ptr(imx25_pinctrl_of_match),
333 },
334 .probe = imx25_pinctrl_probe,
335 .remove = imx_pinctrl_remove,
336};
337
338static int __init imx25_pinctrl_init(void)
339{
340 return platform_driver_register(&imx25_pinctrl_driver);
341}
342arch_initcall(imx25_pinctrl_init);
343
344static void __exit imx25_pinctrl_exit(void)
345{
346 platform_driver_unregister(&imx25_pinctrl_driver);
347}
348module_exit(imx25_pinctrl_exit);
349MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
350MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
351MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
new file mode 100644
index 000000000000..28b90aba708d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-msm.c
@@ -0,0 +1,1028 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/slab.h>
27#include <linux/gpio.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/irqchip/chained_irq.h>
31#include <linux/of_irq.h>
32#include <linux/spinlock.h>
33
34#include "core.h"
35#include "pinconf.h"
36#include "pinctrl-msm.h"
37#include "pinctrl-utils.h"
38
39/**
40 * struct msm_pinctrl - state for a pinctrl-msm device
41 * @dev: device handle.
42 * @pctrl: pinctrl handle.
43 * @domain: irqdomain handle.
44 * @chip: gpiochip handle.
45 * @irq: parent irq for the TLMM irq_chip.
46 * @lock: Spinlock to protect register resources as well
47 * as msm_pinctrl data structures.
48 * @enabled_irqs: Bitmap of currently enabled irqs.
49 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
50 * detection.
51 * @wake_irqs: Bitmap of irqs with requested as wakeup source.
52 * @soc; Reference to soc_data of platform specific data.
53 * @regs: Base address for the TLMM register map.
54 */
55struct msm_pinctrl {
56 struct device *dev;
57 struct pinctrl_dev *pctrl;
58 struct irq_domain *domain;
59 struct gpio_chip chip;
60 unsigned irq;
61
62 spinlock_t lock;
63
64 unsigned long *enabled_irqs;
65 unsigned long *dual_edge_irqs;
66 unsigned long *wake_irqs;
67
68 const struct msm_pinctrl_soc_data *soc;
69 void __iomem *regs;
70};
71
72static int msm_get_groups_count(struct pinctrl_dev *pctldev)
73{
74 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
75
76 return pctrl->soc->ngroups;
77}
78
79static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
80 unsigned group)
81{
82 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
83
84 return pctrl->soc->groups[group].name;
85}
86
87static int msm_get_group_pins(struct pinctrl_dev *pctldev,
88 unsigned group,
89 const unsigned **pins,
90 unsigned *num_pins)
91{
92 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
93
94 *pins = pctrl->soc->groups[group].pins;
95 *num_pins = pctrl->soc->groups[group].npins;
96 return 0;
97}
98
99static struct pinctrl_ops msm_pinctrl_ops = {
100 .get_groups_count = msm_get_groups_count,
101 .get_group_name = msm_get_group_name,
102 .get_group_pins = msm_get_group_pins,
103 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
104 .dt_free_map = pinctrl_utils_dt_free_map,
105};
106
107static int msm_get_functions_count(struct pinctrl_dev *pctldev)
108{
109 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
110
111 return pctrl->soc->nfunctions;
112}
113
114static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
115 unsigned function)
116{
117 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
118
119 return pctrl->soc->functions[function].name;
120}
121
122static int msm_get_function_groups(struct pinctrl_dev *pctldev,
123 unsigned function,
124 const char * const **groups,
125 unsigned * const num_groups)
126{
127 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
128
129 *groups = pctrl->soc->functions[function].groups;
130 *num_groups = pctrl->soc->functions[function].ngroups;
131 return 0;
132}
133
134static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
135 unsigned function,
136 unsigned group)
137{
138 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
139 const struct msm_pingroup *g;
140 unsigned long flags;
141 u32 val;
142 int i;
143
144 g = &pctrl->soc->groups[group];
145
146 if (WARN_ON(g->mux_bit < 0))
147 return -EINVAL;
148
149 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
150 if (g->funcs[i] == function)
151 break;
152 }
153
154 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
155 return -EINVAL;
156
157 spin_lock_irqsave(&pctrl->lock, flags);
158
159 val = readl(pctrl->regs + g->ctl_reg);
160 val &= ~(0x7 << g->mux_bit);
161 val |= i << g->mux_bit;
162 writel(val, pctrl->regs + g->ctl_reg);
163
164 spin_unlock_irqrestore(&pctrl->lock, flags);
165
166 return 0;
167}
168
169static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
170 unsigned function,
171 unsigned group)
172{
173 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
174 const struct msm_pingroup *g;
175 unsigned long flags;
176 u32 val;
177
178 g = &pctrl->soc->groups[group];
179
180 if (WARN_ON(g->mux_bit < 0))
181 return;
182
183 spin_lock_irqsave(&pctrl->lock, flags);
184
185 /* Clear the mux bits to select gpio mode */
186 val = readl(pctrl->regs + g->ctl_reg);
187 val &= ~(0x7 << g->mux_bit);
188 writel(val, pctrl->regs + g->ctl_reg);
189
190 spin_unlock_irqrestore(&pctrl->lock, flags);
191}
192
193static struct pinmux_ops msm_pinmux_ops = {
194 .get_functions_count = msm_get_functions_count,
195 .get_function_name = msm_get_function_name,
196 .get_function_groups = msm_get_function_groups,
197 .enable = msm_pinmux_enable,
198 .disable = msm_pinmux_disable,
199};
200
201static int msm_config_reg(struct msm_pinctrl *pctrl,
202 const struct msm_pingroup *g,
203 unsigned param,
204 unsigned *reg,
205 unsigned *mask,
206 unsigned *bit)
207{
208 switch (param) {
209 case PIN_CONFIG_BIAS_DISABLE:
210 *reg = g->ctl_reg;
211 *bit = g->pull_bit;
212 *mask = 3;
213 break;
214 case PIN_CONFIG_BIAS_PULL_DOWN:
215 *reg = g->ctl_reg;
216 *bit = g->pull_bit;
217 *mask = 3;
218 break;
219 case PIN_CONFIG_BIAS_PULL_UP:
220 *reg = g->ctl_reg;
221 *bit = g->pull_bit;
222 *mask = 3;
223 break;
224 case PIN_CONFIG_DRIVE_STRENGTH:
225 *reg = g->ctl_reg;
226 *bit = g->drv_bit;
227 *mask = 7;
228 break;
229 default:
230 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
231 return -ENOTSUPP;
232 }
233
234 if (*reg < 0) {
235 dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
236 param, g->name);
237 return -ENOTSUPP;
238 }
239
240 return 0;
241}
242
243static int msm_config_get(struct pinctrl_dev *pctldev,
244 unsigned int pin,
245 unsigned long *config)
246{
247 dev_err(pctldev->dev, "pin_config_set op not supported\n");
248 return -ENOTSUPP;
249}
250
251static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
252 unsigned long *configs, unsigned num_configs)
253{
254 dev_err(pctldev->dev, "pin_config_set op not supported\n");
255 return -ENOTSUPP;
256}
257
258#define MSM_NO_PULL 0
259#define MSM_PULL_DOWN 1
260#define MSM_PULL_UP 3
261
262static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
263static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 };
264
265static int msm_config_group_get(struct pinctrl_dev *pctldev,
266 unsigned int group,
267 unsigned long *config)
268{
269 const struct msm_pingroup *g;
270 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
271 unsigned param = pinconf_to_config_param(*config);
272 unsigned mask;
273 unsigned arg;
274 unsigned bit;
275 unsigned reg;
276 int ret;
277 u32 val;
278
279 g = &pctrl->soc->groups[group];
280
281 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
282 if (ret < 0)
283 return ret;
284
285 val = readl(pctrl->regs + reg);
286 arg = (val >> bit) & mask;
287
288 /* Convert register value to pinconf value */
289 switch (param) {
290 case PIN_CONFIG_BIAS_DISABLE:
291 arg = arg == MSM_NO_PULL;
292 break;
293 case PIN_CONFIG_BIAS_PULL_DOWN:
294 arg = arg == MSM_PULL_DOWN;
295 break;
296 case PIN_CONFIG_BIAS_PULL_UP:
297 arg = arg == MSM_PULL_UP;
298 break;
299 case PIN_CONFIG_DRIVE_STRENGTH:
300 arg = msm_regval_to_drive[arg];
301 break;
302 default:
303 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
304 param);
305 return -EINVAL;
306 }
307
308 *config = pinconf_to_config_packed(param, arg);
309
310 return 0;
311}
312
313static int msm_config_group_set(struct pinctrl_dev *pctldev,
314 unsigned group,
315 unsigned long *configs,
316 unsigned num_configs)
317{
318 const struct msm_pingroup *g;
319 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
320 unsigned long flags;
321 unsigned param;
322 unsigned mask;
323 unsigned arg;
324 unsigned bit;
325 unsigned reg;
326 int ret;
327 u32 val;
328 int i;
329
330 g = &pctrl->soc->groups[group];
331
332 for (i = 0; i < num_configs; i++) {
333 param = pinconf_to_config_param(configs[i]);
334 arg = pinconf_to_config_argument(configs[i]);
335
336 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
337 if (ret < 0)
338 return ret;
339
340 /* Convert pinconf values to register values */
341 switch (param) {
342 case PIN_CONFIG_BIAS_DISABLE:
343 arg = MSM_NO_PULL;
344 break;
345 case PIN_CONFIG_BIAS_PULL_DOWN:
346 arg = MSM_PULL_DOWN;
347 break;
348 case PIN_CONFIG_BIAS_PULL_UP:
349 arg = MSM_PULL_UP;
350 break;
351 case PIN_CONFIG_DRIVE_STRENGTH:
352 /* Check for invalid values */
353 if (arg > ARRAY_SIZE(msm_drive_to_regval))
354 arg = -1;
355 else
356 arg = msm_drive_to_regval[arg];
357 break;
358 default:
359 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
360 param);
361 return -EINVAL;
362 }
363
364 /* Range-check user-supplied value */
365 if (arg & ~mask) {
366 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
367 return -EINVAL;
368 }
369
370 spin_lock_irqsave(&pctrl->lock, flags);
371 val = readl(pctrl->regs + reg);
372 val &= ~(mask << bit);
373 val |= arg << bit;
374 writel(val, pctrl->regs + reg);
375 spin_unlock_irqrestore(&pctrl->lock, flags);
376 }
377
378 return 0;
379}
380
381static struct pinconf_ops msm_pinconf_ops = {
382 .pin_config_get = msm_config_get,
383 .pin_config_set = msm_config_set,
384 .pin_config_group_get = msm_config_group_get,
385 .pin_config_group_set = msm_config_group_set,
386};
387
388static struct pinctrl_desc msm_pinctrl_desc = {
389 .pctlops = &msm_pinctrl_ops,
390 .pmxops = &msm_pinmux_ops,
391 .confops = &msm_pinconf_ops,
392 .owner = THIS_MODULE,
393};
394
395static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
396{
397 const struct msm_pingroup *g;
398 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
399 unsigned long flags;
400 u32 val;
401
402 if (WARN_ON(offset >= pctrl->soc->ngroups))
403 return -EINVAL;
404
405 g = &pctrl->soc->groups[offset];
406
407 if (WARN_ON(g->oe_bit < 0))
408 return -EINVAL;
409
410 spin_lock_irqsave(&pctrl->lock, flags);
411
412 val = readl(pctrl->regs + g->ctl_reg);
413 val &= ~BIT(g->oe_bit);
414 writel(val, pctrl->regs + g->ctl_reg);
415
416 spin_unlock_irqrestore(&pctrl->lock, flags);
417
418 return 0;
419}
420
421static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
422{
423 const struct msm_pingroup *g;
424 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
425 unsigned long flags;
426 u32 val;
427
428 if (WARN_ON(offset >= pctrl->soc->ngroups))
429 return -EINVAL;
430
431 g = &pctrl->soc->groups[offset];
432
433 if (WARN_ON(g->oe_bit < 0))
434 return -EINVAL;
435
436 spin_lock_irqsave(&pctrl->lock, flags);
437
438 writel(value ? BIT(g->out_bit) : 0, pctrl->regs + g->io_reg);
439
440 val = readl(pctrl->regs + g->ctl_reg);
441 val |= BIT(g->oe_bit);
442 writel(val, pctrl->regs + g->ctl_reg);
443
444 spin_unlock_irqrestore(&pctrl->lock, flags);
445
446 return 0;
447}
448
449static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
450{
451 const struct msm_pingroup *g;
452 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
453 u32 val;
454
455 if (WARN_ON(offset >= pctrl->soc->ngroups))
456 return -EINVAL;
457
458 g = &pctrl->soc->groups[offset];
459
460 val = readl(pctrl->regs + g->io_reg);
461 return !!(val & BIT(g->in_bit));
462}
463
464static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
465{
466 const struct msm_pingroup *g;
467 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
468 unsigned long flags;
469 u32 val;
470
471 if (WARN_ON(offset >= pctrl->soc->ngroups))
472 return;
473
474 g = &pctrl->soc->groups[offset];
475
476 spin_lock_irqsave(&pctrl->lock, flags);
477
478 val = readl(pctrl->regs + g->io_reg);
479 val |= BIT(g->out_bit);
480 writel(val, pctrl->regs + g->io_reg);
481
482 spin_unlock_irqrestore(&pctrl->lock, flags);
483}
484
485static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
486{
487 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
488
489 return irq_find_mapping(pctrl->domain, offset);
490}
491
492static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
493{
494 int gpio = chip->base + offset;
495 return pinctrl_request_gpio(gpio);
496}
497
498static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
499{
500 int gpio = chip->base + offset;
501 return pinctrl_free_gpio(gpio);
502}
503
504#ifdef CONFIG_DEBUG_FS
505#include <linux/seq_file.h>
506
507static void msm_gpio_dbg_show_one(struct seq_file *s,
508 struct pinctrl_dev *pctldev,
509 struct gpio_chip *chip,
510 unsigned offset,
511 unsigned gpio)
512{
513 const struct msm_pingroup *g;
514 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
515 unsigned func;
516 int is_out;
517 int drive;
518 int pull;
519 u32 ctl_reg;
520
521 const char *pulls[] = {
522 "no pull",
523 "pull down",
524 "keeper",
525 "pull up"
526 };
527
528 g = &pctrl->soc->groups[offset];
529 ctl_reg = readl(pctrl->regs + g->ctl_reg);
530
531 is_out = !!(ctl_reg & BIT(g->oe_bit));
532 func = (ctl_reg >> g->mux_bit) & 7;
533 drive = (ctl_reg >> g->drv_bit) & 7;
534 pull = (ctl_reg >> g->pull_bit) & 3;
535
536 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
537 seq_printf(s, " %dmA", msm_regval_to_drive[drive]);
538 seq_printf(s, " %s", pulls[pull]);
539}
540
541static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
542{
543 unsigned gpio = chip->base;
544 unsigned i;
545
546 for (i = 0; i < chip->ngpio; i++, gpio++) {
547 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
548 seq_printf(s, "\n");
549 }
550}
551
552#else
553#define msm_gpio_dbg_show NULL
554#endif
555
556static struct gpio_chip msm_gpio_template = {
557 .direction_input = msm_gpio_direction_input,
558 .direction_output = msm_gpio_direction_output,
559 .get = msm_gpio_get,
560 .set = msm_gpio_set,
561 .to_irq = msm_gpio_to_irq,
562 .request = msm_gpio_request,
563 .free = msm_gpio_free,
564 .dbg_show = msm_gpio_dbg_show,
565};
566
567/* For dual-edge interrupts in software, since some hardware has no
568 * such support:
569 *
570 * At appropriate moments, this function may be called to flip the polarity
571 * settings of both-edge irq lines to try and catch the next edge.
572 *
573 * The attempt is considered successful if:
574 * - the status bit goes high, indicating that an edge was caught, or
575 * - the input value of the gpio doesn't change during the attempt.
576 * If the value changes twice during the process, that would cause the first
577 * test to fail but would force the second, as two opposite
578 * transitions would cause a detection no matter the polarity setting.
579 *
580 * The do-loop tries to sledge-hammer closed the timing hole between
581 * the initial value-read and the polarity-write - if the line value changes
582 * during that window, an interrupt is lost, the new polarity setting is
583 * incorrect, and the first success test will fail, causing a retry.
584 *
585 * Algorithm comes from Google's msmgpio driver.
586 */
587static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
588 const struct msm_pingroup *g,
589 struct irq_data *d)
590{
591 int loop_limit = 100;
592 unsigned val, val2, intstat;
593 unsigned pol;
594
595 do {
596 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
597
598 pol = readl(pctrl->regs + g->intr_cfg_reg);
599 pol ^= BIT(g->intr_polarity_bit);
600 writel(pol, pctrl->regs + g->intr_cfg_reg);
601
602 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
603 intstat = readl(pctrl->regs + g->intr_status_reg);
604 if (intstat || (val == val2))
605 return;
606 } while (loop_limit-- > 0);
607 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
608 val, val2);
609}
610
611static void msm_gpio_irq_mask(struct irq_data *d)
612{
613 const struct msm_pingroup *g;
614 struct msm_pinctrl *pctrl;
615 unsigned long flags;
616 u32 val;
617
618 pctrl = irq_data_get_irq_chip_data(d);
619 if (!pctrl)
620 return;
621
622 if (WARN_ON(d->hwirq >= pctrl->soc->ngroups))
623 return;
624
625 g = &pctrl->soc->groups[d->hwirq];
626
627 spin_lock_irqsave(&pctrl->lock, flags);
628
629 val = readl(pctrl->regs + g->intr_cfg_reg);
630 val &= ~BIT(g->intr_enable_bit);
631 writel(val, pctrl->regs + g->intr_cfg_reg);
632
633 clear_bit(d->hwirq, pctrl->enabled_irqs);
634
635 spin_unlock_irqrestore(&pctrl->lock, flags);
636}
637
638static void msm_gpio_irq_unmask(struct irq_data *d)
639{
640 const struct msm_pingroup *g;
641 struct msm_pinctrl *pctrl;
642 unsigned long flags;
643 u32 val;
644
645 pctrl = irq_data_get_irq_chip_data(d);
646 if (!pctrl)
647 return;
648
649 if (WARN_ON(d->hwirq >= pctrl->soc->ngroups))
650 return;
651
652 g = &pctrl->soc->groups[d->hwirq];
653
654 spin_lock_irqsave(&pctrl->lock, flags);
655
656 val = readl(pctrl->regs + g->intr_status_reg);
657 val &= ~BIT(g->intr_status_bit);
658 writel(val, pctrl->regs + g->intr_status_reg);
659
660 val = readl(pctrl->regs + g->intr_cfg_reg);
661 val |= BIT(g->intr_enable_bit);
662 writel(val, pctrl->regs + g->intr_cfg_reg);
663
664 set_bit(d->hwirq, pctrl->enabled_irqs);
665
666 spin_unlock_irqrestore(&pctrl->lock, flags);
667}
668
669static void msm_gpio_irq_ack(struct irq_data *d)
670{
671 const struct msm_pingroup *g;
672 struct msm_pinctrl *pctrl;
673 unsigned long flags;
674 u32 val;
675
676 pctrl = irq_data_get_irq_chip_data(d);
677 if (!pctrl)
678 return;
679
680 if (WARN_ON(d->hwirq >= pctrl->soc->ngroups))
681 return;
682
683 g = &pctrl->soc->groups[d->hwirq];
684
685 spin_lock_irqsave(&pctrl->lock, flags);
686
687 val = readl(pctrl->regs + g->intr_status_reg);
688 val &= ~BIT(g->intr_status_bit);
689 writel(val, pctrl->regs + g->intr_status_reg);
690
691 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
692 msm_gpio_update_dual_edge_pos(pctrl, g, d);
693
694 spin_unlock_irqrestore(&pctrl->lock, flags);
695}
696
697#define INTR_TARGET_PROC_APPS 4
698
699static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
700{
701 const struct msm_pingroup *g;
702 struct msm_pinctrl *pctrl;
703 unsigned long flags;
704 u32 val;
705
706 pctrl = irq_data_get_irq_chip_data(d);
707 if (!pctrl)
708 return -EINVAL;
709
710 if (WARN_ON(d->hwirq >= pctrl->soc->ngroups))
711 return -EINVAL;
712
713 g = &pctrl->soc->groups[d->hwirq];
714
715 spin_lock_irqsave(&pctrl->lock, flags);
716
717 /*
718 * For hw without possibility of detecting both edges
719 */
720 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
721 set_bit(d->hwirq, pctrl->dual_edge_irqs);
722 else
723 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
724
725 /* Route interrupts to application cpu */
726 val = readl(pctrl->regs + g->intr_target_reg);
727 val &= ~(7 << g->intr_target_bit);
728 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
729 writel(val, pctrl->regs + g->intr_target_reg);
730
731 /* Update configuration for gpio.
732 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
733 * internal circuitry of TLMM, toggling the RAW_STATUS
734 * could cause the INTR_STATUS to be set for EDGE interrupts.
735 */
736 val = readl(pctrl->regs + g->intr_cfg_reg);
737 val |= BIT(g->intr_raw_status_bit);
738 if (g->intr_detection_width == 2) {
739 val &= ~(3 << g->intr_detection_bit);
740 val &= ~(1 << g->intr_polarity_bit);
741 switch (type) {
742 case IRQ_TYPE_EDGE_RISING:
743 val |= 1 << g->intr_detection_bit;
744 val |= BIT(g->intr_polarity_bit);
745 break;
746 case IRQ_TYPE_EDGE_FALLING:
747 val |= 2 << g->intr_detection_bit;
748 val |= BIT(g->intr_polarity_bit);
749 break;
750 case IRQ_TYPE_EDGE_BOTH:
751 val |= 3 << g->intr_detection_bit;
752 val |= BIT(g->intr_polarity_bit);
753 break;
754 case IRQ_TYPE_LEVEL_LOW:
755 break;
756 case IRQ_TYPE_LEVEL_HIGH:
757 val |= BIT(g->intr_polarity_bit);
758 break;
759 }
760 } else if (g->intr_detection_width == 1) {
761 val &= ~(1 << g->intr_detection_bit);
762 val &= ~(1 << g->intr_polarity_bit);
763 switch (type) {
764 case IRQ_TYPE_EDGE_RISING:
765 val |= BIT(g->intr_detection_bit);
766 val |= BIT(g->intr_polarity_bit);
767 break;
768 case IRQ_TYPE_EDGE_FALLING:
769 val |= BIT(g->intr_detection_bit);
770 break;
771 case IRQ_TYPE_EDGE_BOTH:
772 val |= BIT(g->intr_detection_bit);
773 break;
774 case IRQ_TYPE_LEVEL_LOW:
775 break;
776 case IRQ_TYPE_LEVEL_HIGH:
777 val |= BIT(g->intr_polarity_bit);
778 break;
779 }
780 } else {
781 BUG();
782 }
783 writel(val, pctrl->regs + g->intr_cfg_reg);
784
785 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
786 msm_gpio_update_dual_edge_pos(pctrl, g, d);
787
788 spin_unlock_irqrestore(&pctrl->lock, flags);
789
790 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
791 __irq_set_handler_locked(d->irq, handle_level_irq);
792 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
793 __irq_set_handler_locked(d->irq, handle_edge_irq);
794
795 return 0;
796}
797
798static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
799{
800 struct msm_pinctrl *pctrl;
801 unsigned long flags;
802 unsigned ngpio;
803
804 pctrl = irq_data_get_irq_chip_data(d);
805 if (!pctrl)
806 return -EINVAL;
807
808 ngpio = pctrl->chip.ngpio;
809
810 spin_lock_irqsave(&pctrl->lock, flags);
811
812 if (on) {
813 if (bitmap_empty(pctrl->wake_irqs, ngpio))
814 enable_irq_wake(pctrl->irq);
815 set_bit(d->hwirq, pctrl->wake_irqs);
816 } else {
817 clear_bit(d->hwirq, pctrl->wake_irqs);
818 if (bitmap_empty(pctrl->wake_irqs, ngpio))
819 disable_irq_wake(pctrl->irq);
820 }
821
822 spin_unlock_irqrestore(&pctrl->lock, flags);
823
824 return 0;
825}
826
827static unsigned int msm_gpio_irq_startup(struct irq_data *d)
828{
829 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
830
831 if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
832 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
833 d->hwirq);
834 }
835 msm_gpio_irq_unmask(d);
836 return 0;
837}
838
839static void msm_gpio_irq_shutdown(struct irq_data *d)
840{
841 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
842
843 msm_gpio_irq_mask(d);
844 gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
845}
846
847static struct irq_chip msm_gpio_irq_chip = {
848 .name = "msmgpio",
849 .irq_mask = msm_gpio_irq_mask,
850 .irq_unmask = msm_gpio_irq_unmask,
851 .irq_ack = msm_gpio_irq_ack,
852 .irq_set_type = msm_gpio_irq_set_type,
853 .irq_set_wake = msm_gpio_irq_set_wake,
854 .irq_startup = msm_gpio_irq_startup,
855 .irq_shutdown = msm_gpio_irq_shutdown,
856};
857
858static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
859{
860 const struct msm_pingroup *g;
861 struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
862 struct irq_chip *chip = irq_get_chip(irq);
863 int irq_pin;
864 int handled = 0;
865 u32 val;
866 int i;
867
868 chained_irq_enter(chip, desc);
869
870 /*
871 * Each pin have it's own IRQ status register, so use
872 * enabled_irq bitmap to limit the number of reads.
873 */
874 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
875 g = &pctrl->soc->groups[i];
876 val = readl(pctrl->regs + g->intr_status_reg);
877 if (val & BIT(g->intr_status_bit)) {
878 irq_pin = irq_find_mapping(pctrl->domain, i);
879 generic_handle_irq(irq_pin);
880 handled++;
881 }
882 }
883
884 /* No interrutps where flagged */
885 if (handled == 0)
886 handle_bad_irq(irq, desc);
887
888 chained_irq_exit(chip, desc);
889}
890
891static int msm_gpio_init(struct msm_pinctrl *pctrl)
892{
893 struct gpio_chip *chip;
894 int irq;
895 int ret;
896 int i;
897 int r;
898
899 chip = &pctrl->chip;
900 chip->base = 0;
901 chip->ngpio = pctrl->soc->ngpios;
902 chip->label = dev_name(pctrl->dev);
903 chip->dev = pctrl->dev;
904 chip->owner = THIS_MODULE;
905 chip->of_node = pctrl->dev->of_node;
906
907 pctrl->enabled_irqs = devm_kzalloc(pctrl->dev,
908 sizeof(unsigned long) * BITS_TO_LONGS(chip->ngpio),
909 GFP_KERNEL);
910 if (!pctrl->enabled_irqs) {
911 dev_err(pctrl->dev, "Failed to allocate enabled_irqs bitmap\n");
912 return -ENOMEM;
913 }
914
915 pctrl->dual_edge_irqs = devm_kzalloc(pctrl->dev,
916 sizeof(unsigned long) * BITS_TO_LONGS(chip->ngpio),
917 GFP_KERNEL);
918 if (!pctrl->dual_edge_irqs) {
919 dev_err(pctrl->dev, "Failed to allocate dual_edge_irqs bitmap\n");
920 return -ENOMEM;
921 }
922
923 pctrl->wake_irqs = devm_kzalloc(pctrl->dev,
924 sizeof(unsigned long) * BITS_TO_LONGS(chip->ngpio),
925 GFP_KERNEL);
926 if (!pctrl->wake_irqs) {
927 dev_err(pctrl->dev, "Failed to allocate wake_irqs bitmap\n");
928 return -ENOMEM;
929 }
930
931 ret = gpiochip_add(&pctrl->chip);
932 if (ret) {
933 dev_err(pctrl->dev, "Failed register gpiochip\n");
934 return ret;
935 }
936
937 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
938 if (ret) {
939 dev_err(pctrl->dev, "Failed to add pin range\n");
940 return ret;
941 }
942
943 pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
944 &irq_domain_simple_ops, NULL);
945 if (!pctrl->domain) {
946 dev_err(pctrl->dev, "Failed to register irq domain\n");
947 r = gpiochip_remove(&pctrl->chip);
948 return -ENOSYS;
949 }
950
951 for (i = 0; i < chip->ngpio; i++) {
952 irq = irq_create_mapping(pctrl->domain, i);
953 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
954 irq_set_chip_data(irq, pctrl);
955 }
956
957 irq_set_handler_data(pctrl->irq, pctrl);
958 irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
959
960 return 0;
961}
962
963int msm_pinctrl_probe(struct platform_device *pdev,
964 const struct msm_pinctrl_soc_data *soc_data)
965{
966 struct msm_pinctrl *pctrl;
967 struct resource *res;
968 int ret;
969
970 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
971 if (!pctrl) {
972 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
973 return -ENOMEM;
974 }
975 pctrl->dev = &pdev->dev;
976 pctrl->soc = soc_data;
977 pctrl->chip = msm_gpio_template;
978
979 spin_lock_init(&pctrl->lock);
980
981 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
983 if (IS_ERR(pctrl->regs))
984 return PTR_ERR(pctrl->regs);
985
986 pctrl->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
987 if (pctrl->irq < 0) {
988 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
989 return pctrl->irq;
990 }
991
992 msm_pinctrl_desc.name = dev_name(&pdev->dev);
993 msm_pinctrl_desc.pins = pctrl->soc->pins;
994 msm_pinctrl_desc.npins = pctrl->soc->npins;
995 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
996 if (!pctrl->pctrl) {
997 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
998 return -ENODEV;
999 }
1000
1001 ret = msm_gpio_init(pctrl);
1002 if (ret) {
1003 pinctrl_unregister(pctrl->pctrl);
1004 return ret;
1005 }
1006
1007 platform_set_drvdata(pdev, pctrl);
1008
1009 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1010
1011 return 0;
1012}
1013EXPORT_SYMBOL(msm_pinctrl_probe);
1014
1015int msm_pinctrl_remove(struct platform_device *pdev)
1016{
1017 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1018 int ret;
1019
1020 irq_set_chained_handler(pctrl->irq, NULL);
1021 irq_domain_remove(pctrl->domain);
1022 ret = gpiochip_remove(&pctrl->chip);
1023 pinctrl_unregister(pctrl->pctrl);
1024
1025 return 0;
1026}
1027EXPORT_SYMBOL(msm_pinctrl_remove);
1028
diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h
new file mode 100644
index 000000000000..206e782e2daa
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-msm.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __PINCTRL_MSM_H__
14#define __PINCTRL_MSM_H__
15
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/machine.h>
20
21/**
22 * struct msm_function - a pinmux function
23 * @name: Name of the pinmux function.
24 * @groups: List of pingroups for this function.
25 * @ngroups: Number of entries in @groups.
26 */
27struct msm_function {
28 const char *name;
29 const char * const *groups;
30 unsigned ngroups;
31};
32
33/**
34 * struct msm_pingroup - Qualcomm pingroup definition
35 * @name: Name of the pingroup.
36 * @pins: A list of pins assigned to this pingroup.
37 * @npins: Number of entries in @pins.
38 * @funcs: A list of pinmux functions that can be selected for
39 * this group. The index of the selected function is used
40 * for programming the function selector.
41 * Entries should be indices into the groups list of the
42 * struct msm_pinctrl_soc_data.
43 * @ctl_reg: Offset of the register holding control bits for this group.
44 * @io_reg: Offset of the register holding input/output bits for this group.
45 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
46 * @intr_status_reg: Offset of the register holding the status bits for this group.
47 * @intr_target_reg: Offset of the register specifying routing of the interrupts
48 * from this group.
49 * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
50 * @pull_bit: Offset in @ctl_reg for the bias configuration.
51 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
52 * @oe_bit: Offset in @ctl_reg for controlling output enable.
53 * @in_bit: Offset in @io_reg for the input bit value.
54 * @out_bit: Offset in @io_reg for the output bit value.
55 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
56 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
57 * status.
58 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
59 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
60 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
61 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
62 * @intr_detection_width: Number of bits used for specifying interrupt type,
63 * Should be 2 for SoCs that can detect both edges in hardware,
64 * otherwise 1.
65 */
66struct msm_pingroup {
67 const char *name;
68 const unsigned *pins;
69 unsigned npins;
70
71 unsigned funcs[8];
72
73 s16 ctl_reg;
74 s16 io_reg;
75 s16 intr_cfg_reg;
76 s16 intr_status_reg;
77 s16 intr_target_reg;
78
79 unsigned mux_bit:5;
80
81 unsigned pull_bit:5;
82 unsigned drv_bit:5;
83
84 unsigned oe_bit:5;
85 unsigned in_bit:5;
86 unsigned out_bit:5;
87
88 unsigned intr_enable_bit:5;
89 unsigned intr_status_bit:5;
90
91 unsigned intr_target_bit:5;
92 unsigned intr_raw_status_bit:5;
93 unsigned intr_polarity_bit:5;
94 unsigned intr_detection_bit:5;
95 unsigned intr_detection_width:5;
96};
97
98/**
99 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
100 * @pins: An array describing all pins the pin controller affects.
101 * @npins: The number of entries in @pins.
102 * @functions: An array describing all mux functions the SoC supports.
103 * @nfunctions: The number of entries in @functions.
104 * @groups: An array describing all pin groups the pin SoC supports.
105 * @ngroups: The numbmer of entries in @groups.
106 * @ngpio: The number of pingroups the driver should expose as GPIOs.
107 */
108struct msm_pinctrl_soc_data {
109 const struct pinctrl_pin_desc *pins;
110 unsigned npins;
111 const struct msm_function *functions;
112 unsigned nfunctions;
113 const struct msm_pingroup *groups;
114 unsigned ngroups;
115 unsigned ngpios;
116};
117
118int msm_pinctrl_probe(struct platform_device *pdev,
119 const struct msm_pinctrl_soc_data *soc_data);
120int msm_pinctrl_remove(struct platform_device *pdev);
121
122#endif
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c
new file mode 100644
index 000000000000..762552bc53b9
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-msm8x74.c
@@ -0,0 +1,636 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc msm8x74_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169
170 PINCTRL_PIN(146, "SDC1_CLK"),
171 PINCTRL_PIN(147, "SDC1_CMD"),
172 PINCTRL_PIN(148, "SDC1_DATA"),
173 PINCTRL_PIN(149, "SDC2_CLK"),
174 PINCTRL_PIN(150, "SDC2_CMD"),
175 PINCTRL_PIN(151, "SDC2_DATA"),
176};
177
178#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
179DECLARE_MSM_GPIO_PINS(0);
180DECLARE_MSM_GPIO_PINS(1);
181DECLARE_MSM_GPIO_PINS(2);
182DECLARE_MSM_GPIO_PINS(3);
183DECLARE_MSM_GPIO_PINS(4);
184DECLARE_MSM_GPIO_PINS(5);
185DECLARE_MSM_GPIO_PINS(6);
186DECLARE_MSM_GPIO_PINS(7);
187DECLARE_MSM_GPIO_PINS(8);
188DECLARE_MSM_GPIO_PINS(9);
189DECLARE_MSM_GPIO_PINS(10);
190DECLARE_MSM_GPIO_PINS(11);
191DECLARE_MSM_GPIO_PINS(12);
192DECLARE_MSM_GPIO_PINS(13);
193DECLARE_MSM_GPIO_PINS(14);
194DECLARE_MSM_GPIO_PINS(15);
195DECLARE_MSM_GPIO_PINS(16);
196DECLARE_MSM_GPIO_PINS(17);
197DECLARE_MSM_GPIO_PINS(18);
198DECLARE_MSM_GPIO_PINS(19);
199DECLARE_MSM_GPIO_PINS(20);
200DECLARE_MSM_GPIO_PINS(21);
201DECLARE_MSM_GPIO_PINS(22);
202DECLARE_MSM_GPIO_PINS(23);
203DECLARE_MSM_GPIO_PINS(24);
204DECLARE_MSM_GPIO_PINS(25);
205DECLARE_MSM_GPIO_PINS(26);
206DECLARE_MSM_GPIO_PINS(27);
207DECLARE_MSM_GPIO_PINS(28);
208DECLARE_MSM_GPIO_PINS(29);
209DECLARE_MSM_GPIO_PINS(30);
210DECLARE_MSM_GPIO_PINS(31);
211DECLARE_MSM_GPIO_PINS(32);
212DECLARE_MSM_GPIO_PINS(33);
213DECLARE_MSM_GPIO_PINS(34);
214DECLARE_MSM_GPIO_PINS(35);
215DECLARE_MSM_GPIO_PINS(36);
216DECLARE_MSM_GPIO_PINS(37);
217DECLARE_MSM_GPIO_PINS(38);
218DECLARE_MSM_GPIO_PINS(39);
219DECLARE_MSM_GPIO_PINS(40);
220DECLARE_MSM_GPIO_PINS(41);
221DECLARE_MSM_GPIO_PINS(42);
222DECLARE_MSM_GPIO_PINS(43);
223DECLARE_MSM_GPIO_PINS(44);
224DECLARE_MSM_GPIO_PINS(45);
225DECLARE_MSM_GPIO_PINS(46);
226DECLARE_MSM_GPIO_PINS(47);
227DECLARE_MSM_GPIO_PINS(48);
228DECLARE_MSM_GPIO_PINS(49);
229DECLARE_MSM_GPIO_PINS(50);
230DECLARE_MSM_GPIO_PINS(51);
231DECLARE_MSM_GPIO_PINS(52);
232DECLARE_MSM_GPIO_PINS(53);
233DECLARE_MSM_GPIO_PINS(54);
234DECLARE_MSM_GPIO_PINS(55);
235DECLARE_MSM_GPIO_PINS(56);
236DECLARE_MSM_GPIO_PINS(57);
237DECLARE_MSM_GPIO_PINS(58);
238DECLARE_MSM_GPIO_PINS(59);
239DECLARE_MSM_GPIO_PINS(60);
240DECLARE_MSM_GPIO_PINS(61);
241DECLARE_MSM_GPIO_PINS(62);
242DECLARE_MSM_GPIO_PINS(63);
243DECLARE_MSM_GPIO_PINS(64);
244DECLARE_MSM_GPIO_PINS(65);
245DECLARE_MSM_GPIO_PINS(66);
246DECLARE_MSM_GPIO_PINS(67);
247DECLARE_MSM_GPIO_PINS(68);
248DECLARE_MSM_GPIO_PINS(69);
249DECLARE_MSM_GPIO_PINS(70);
250DECLARE_MSM_GPIO_PINS(71);
251DECLARE_MSM_GPIO_PINS(72);
252DECLARE_MSM_GPIO_PINS(73);
253DECLARE_MSM_GPIO_PINS(74);
254DECLARE_MSM_GPIO_PINS(75);
255DECLARE_MSM_GPIO_PINS(76);
256DECLARE_MSM_GPIO_PINS(77);
257DECLARE_MSM_GPIO_PINS(78);
258DECLARE_MSM_GPIO_PINS(79);
259DECLARE_MSM_GPIO_PINS(80);
260DECLARE_MSM_GPIO_PINS(81);
261DECLARE_MSM_GPIO_PINS(82);
262DECLARE_MSM_GPIO_PINS(83);
263DECLARE_MSM_GPIO_PINS(84);
264DECLARE_MSM_GPIO_PINS(85);
265DECLARE_MSM_GPIO_PINS(86);
266DECLARE_MSM_GPIO_PINS(87);
267DECLARE_MSM_GPIO_PINS(88);
268DECLARE_MSM_GPIO_PINS(89);
269DECLARE_MSM_GPIO_PINS(90);
270DECLARE_MSM_GPIO_PINS(91);
271DECLARE_MSM_GPIO_PINS(92);
272DECLARE_MSM_GPIO_PINS(93);
273DECLARE_MSM_GPIO_PINS(94);
274DECLARE_MSM_GPIO_PINS(95);
275DECLARE_MSM_GPIO_PINS(96);
276DECLARE_MSM_GPIO_PINS(97);
277DECLARE_MSM_GPIO_PINS(98);
278DECLARE_MSM_GPIO_PINS(99);
279DECLARE_MSM_GPIO_PINS(100);
280DECLARE_MSM_GPIO_PINS(101);
281DECLARE_MSM_GPIO_PINS(102);
282DECLARE_MSM_GPIO_PINS(103);
283DECLARE_MSM_GPIO_PINS(104);
284DECLARE_MSM_GPIO_PINS(105);
285DECLARE_MSM_GPIO_PINS(106);
286DECLARE_MSM_GPIO_PINS(107);
287DECLARE_MSM_GPIO_PINS(108);
288DECLARE_MSM_GPIO_PINS(109);
289DECLARE_MSM_GPIO_PINS(110);
290DECLARE_MSM_GPIO_PINS(111);
291DECLARE_MSM_GPIO_PINS(112);
292DECLARE_MSM_GPIO_PINS(113);
293DECLARE_MSM_GPIO_PINS(114);
294DECLARE_MSM_GPIO_PINS(115);
295DECLARE_MSM_GPIO_PINS(116);
296DECLARE_MSM_GPIO_PINS(117);
297DECLARE_MSM_GPIO_PINS(118);
298DECLARE_MSM_GPIO_PINS(119);
299DECLARE_MSM_GPIO_PINS(120);
300DECLARE_MSM_GPIO_PINS(121);
301DECLARE_MSM_GPIO_PINS(122);
302DECLARE_MSM_GPIO_PINS(123);
303DECLARE_MSM_GPIO_PINS(124);
304DECLARE_MSM_GPIO_PINS(125);
305DECLARE_MSM_GPIO_PINS(126);
306DECLARE_MSM_GPIO_PINS(127);
307DECLARE_MSM_GPIO_PINS(128);
308DECLARE_MSM_GPIO_PINS(129);
309DECLARE_MSM_GPIO_PINS(130);
310DECLARE_MSM_GPIO_PINS(131);
311DECLARE_MSM_GPIO_PINS(132);
312DECLARE_MSM_GPIO_PINS(133);
313DECLARE_MSM_GPIO_PINS(134);
314DECLARE_MSM_GPIO_PINS(135);
315DECLARE_MSM_GPIO_PINS(136);
316DECLARE_MSM_GPIO_PINS(137);
317DECLARE_MSM_GPIO_PINS(138);
318DECLARE_MSM_GPIO_PINS(139);
319DECLARE_MSM_GPIO_PINS(140);
320DECLARE_MSM_GPIO_PINS(141);
321DECLARE_MSM_GPIO_PINS(142);
322DECLARE_MSM_GPIO_PINS(143);
323DECLARE_MSM_GPIO_PINS(144);
324DECLARE_MSM_GPIO_PINS(145);
325
326static const unsigned int sdc1_clk_pins[] = { 146 };
327static const unsigned int sdc1_cmd_pins[] = { 147 };
328static const unsigned int sdc1_data_pins[] = { 148 };
329static const unsigned int sdc2_clk_pins[] = { 149 };
330static const unsigned int sdc2_cmd_pins[] = { 150 };
331static const unsigned int sdc2_data_pins[] = { 151 };
332
333#define FUNCTION(fname) \
334 [MSM_MUX_##fname] = { \
335 .name = #fname, \
336 .groups = fname##_groups, \
337 .ngroups = ARRAY_SIZE(fname##_groups), \
338 }
339
340#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
341 { \
342 .name = "gpio" #id, \
343 .pins = gpio##id##_pins, \
344 .npins = ARRAY_SIZE(gpio##id##_pins), \
345 .funcs = { \
346 MSM_MUX_NA, /* gpio mode */ \
347 MSM_MUX_##f1, \
348 MSM_MUX_##f2, \
349 MSM_MUX_##f3, \
350 MSM_MUX_##f4, \
351 MSM_MUX_##f5, \
352 MSM_MUX_##f6, \
353 MSM_MUX_##f7 \
354 }, \
355 .ctl_reg = 0x1000 + 0x10 * id , \
356 .io_reg = 0x1004 + 0x10 * id, \
357 .intr_cfg_reg = 0x1008 + 0x10 * id, \
358 .intr_status_reg = 0x100c + 0x10 * id, \
359 .intr_target_reg = 0x1008 + 0x10 * id, \
360 .mux_bit = 2, \
361 .pull_bit = 0, \
362 .drv_bit = 6, \
363 .oe_bit = 9, \
364 .in_bit = 0, \
365 .out_bit = 1, \
366 .intr_enable_bit = 0, \
367 .intr_status_bit = 0, \
368 .intr_target_bit = 5, \
369 .intr_raw_status_bit = 4, \
370 .intr_polarity_bit = 1, \
371 .intr_detection_bit = 2, \
372 .intr_detection_width = 2, \
373 }
374
375#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
376 { \
377 .name = #pg_name, \
378 .pins = pg_name##_pins, \
379 .npins = ARRAY_SIZE(pg_name##_pins), \
380 .ctl_reg = ctl, \
381 .io_reg = 0, \
382 .intr_cfg_reg = 0, \
383 .intr_status_reg = 0, \
384 .intr_target_reg = 0, \
385 .mux_bit = -1, \
386 .pull_bit = pull, \
387 .drv_bit = drv, \
388 .oe_bit = -1, \
389 .in_bit = -1, \
390 .out_bit = -1, \
391 .intr_enable_bit = -1, \
392 .intr_status_bit = -1, \
393 .intr_target_bit = -1, \
394 .intr_raw_status_bit = -1, \
395 .intr_polarity_bit = -1, \
396 .intr_detection_bit = -1, \
397 .intr_detection_width = -1, \
398 }
399
400/*
401 * TODO: Add the rest of the possible functions and fill out
402 * the pingroup table below.
403 */
404enum msm8x74_functions {
405 MSM_MUX_blsp_i2c2,
406 MSM_MUX_blsp_i2c6,
407 MSM_MUX_blsp_i2c11,
408 MSM_MUX_blsp_spi1,
409 MSM_MUX_blsp_uart2,
410 MSM_MUX_blsp_uart8,
411 MSM_MUX_slimbus,
412 MSM_MUX_NA,
413};
414
415static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
416static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
417static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
418static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" };
419static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" };
420static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" };
421static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
422
423static const struct msm_function msm8x74_functions[] = {
424 FUNCTION(blsp_i2c2),
425 FUNCTION(blsp_i2c6),
426 FUNCTION(blsp_i2c11),
427 FUNCTION(blsp_spi1),
428 FUNCTION(blsp_uart2),
429 FUNCTION(blsp_uart8),
430 FUNCTION(slimbus),
431};
432
433static const struct msm_pingroup msm8x74_groups[] = {
434 PINGROUP(0, blsp_spi1, NA, NA, NA, NA, NA, NA),
435 PINGROUP(1, blsp_spi1, NA, NA, NA, NA, NA, NA),
436 PINGROUP(2, blsp_spi1, NA, NA, NA, NA, NA, NA),
437 PINGROUP(3, blsp_spi1, NA, NA, NA, NA, NA, NA),
438 PINGROUP(4, NA, blsp_uart2, NA, NA, NA, NA, NA),
439 PINGROUP(5, NA, blsp_uart2, NA, NA, NA, NA, NA),
440 PINGROUP(6, NA, NA, blsp_i2c2, NA, NA, NA, NA),
441 PINGROUP(7, NA, NA, blsp_i2c2, NA, NA, NA, NA),
442 PINGROUP(8, NA, NA, NA, NA, NA, NA, NA),
443 PINGROUP(9, NA, NA, NA, NA, NA, NA, NA),
444 PINGROUP(10, NA, NA, NA, NA, NA, NA, NA),
445 PINGROUP(11, NA, NA, NA, NA, NA, NA, NA),
446 PINGROUP(12, NA, NA, NA, NA, NA, NA, NA),
447 PINGROUP(13, NA, NA, NA, NA, NA, NA, NA),
448 PINGROUP(14, NA, NA, NA, NA, NA, NA, NA),
449 PINGROUP(15, NA, NA, NA, NA, NA, NA, NA),
450 PINGROUP(16, NA, NA, NA, NA, NA, NA, NA),
451 PINGROUP(17, NA, NA, NA, NA, NA, NA, NA),
452 PINGROUP(18, NA, NA, NA, NA, NA, NA, NA),
453 PINGROUP(19, NA, NA, NA, NA, NA, NA, NA),
454 PINGROUP(20, NA, NA, NA, NA, NA, NA, NA),
455 PINGROUP(21, NA, NA, NA, NA, NA, NA, NA),
456 PINGROUP(22, NA, NA, NA, NA, NA, NA, NA),
457 PINGROUP(23, NA, NA, NA, NA, NA, NA, NA),
458 PINGROUP(24, NA, NA, NA, NA, NA, NA, NA),
459 PINGROUP(25, NA, NA, NA, NA, NA, NA, NA),
460 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA),
461 PINGROUP(27, NA, NA, NA, NA, NA, NA, NA),
462 PINGROUP(28, NA, NA, NA, NA, NA, NA, NA),
463 PINGROUP(29, NA, NA, blsp_i2c6, NA, NA, NA, NA),
464 PINGROUP(30, NA, NA, blsp_i2c6, NA, NA, NA, NA),
465 PINGROUP(31, NA, NA, NA, NA, NA, NA, NA),
466 PINGROUP(32, NA, NA, NA, NA, NA, NA, NA),
467 PINGROUP(33, NA, NA, NA, NA, NA, NA, NA),
468 PINGROUP(34, NA, NA, NA, NA, NA, NA, NA),
469 PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
470 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
471 PINGROUP(37, NA, NA, NA, NA, NA, NA, NA),
472 PINGROUP(38, NA, NA, NA, NA, NA, NA, NA),
473 PINGROUP(39, NA, NA, NA, NA, NA, NA, NA),
474 PINGROUP(40, NA, NA, NA, NA, NA, NA, NA),
475 PINGROUP(41, NA, NA, NA, NA, NA, NA, NA),
476 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA),
477 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA),
478 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA),
479 PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA),
480 PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA),
481 PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
482 PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
483 PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
484 PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
485 PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
486 PINGROUP(52, NA, NA, NA, NA, NA, NA, NA),
487 PINGROUP(53, NA, NA, NA, NA, NA, NA, NA),
488 PINGROUP(54, NA, NA, NA, NA, NA, NA, NA),
489 PINGROUP(55, NA, NA, NA, NA, NA, NA, NA),
490 PINGROUP(56, NA, NA, NA, NA, NA, NA, NA),
491 PINGROUP(57, NA, NA, NA, NA, NA, NA, NA),
492 PINGROUP(58, NA, NA, NA, NA, NA, NA, NA),
493 PINGROUP(59, NA, NA, NA, NA, NA, NA, NA),
494 PINGROUP(60, NA, NA, NA, NA, NA, NA, NA),
495 PINGROUP(61, NA, NA, NA, NA, NA, NA, NA),
496 PINGROUP(62, NA, NA, NA, NA, NA, NA, NA),
497 PINGROUP(63, NA, NA, NA, NA, NA, NA, NA),
498 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA),
499 PINGROUP(65, NA, NA, NA, NA, NA, NA, NA),
500 PINGROUP(66, NA, NA, NA, NA, NA, NA, NA),
501 PINGROUP(67, NA, NA, NA, NA, NA, NA, NA),
502 PINGROUP(68, NA, NA, NA, NA, NA, NA, NA),
503 PINGROUP(69, NA, NA, NA, NA, NA, NA, NA),
504 PINGROUP(70, slimbus, NA, NA, NA, NA, NA, NA),
505 PINGROUP(71, slimbus, NA, NA, NA, NA, NA, NA),
506 PINGROUP(72, NA, NA, NA, NA, NA, NA, NA),
507 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
508 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
509 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA),
510 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA),
511 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA),
512 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA),
513 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA),
514 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA),
515 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA),
516 PINGROUP(82, NA, NA, NA, NA, NA, NA, NA),
517 PINGROUP(83, NA, NA, blsp_i2c11, NA, NA, NA, NA),
518 PINGROUP(84, NA, NA, blsp_i2c11, NA, NA, NA, NA),
519 PINGROUP(85, NA, NA, NA, NA, NA, NA, NA),
520 PINGROUP(86, NA, NA, NA, NA, NA, NA, NA),
521 PINGROUP(87, NA, NA, NA, NA, NA, NA, NA),
522 PINGROUP(88, NA, NA, NA, NA, NA, NA, NA),
523 PINGROUP(89, NA, NA, NA, NA, NA, NA, NA),
524 PINGROUP(90, NA, NA, NA, NA, NA, NA, NA),
525 PINGROUP(91, NA, NA, NA, NA, NA, NA, NA),
526 PINGROUP(92, NA, NA, NA, NA, NA, NA, NA),
527 PINGROUP(93, NA, NA, NA, NA, NA, NA, NA),
528 PINGROUP(94, NA, NA, NA, NA, NA, NA, NA),
529 PINGROUP(95, NA, NA, NA, NA, NA, NA, NA),
530 PINGROUP(96, NA, NA, NA, NA, NA, NA, NA),
531 PINGROUP(97, NA, NA, NA, NA, NA, NA, NA),
532 PINGROUP(98, NA, NA, NA, NA, NA, NA, NA),
533 PINGROUP(99, NA, NA, NA, NA, NA, NA, NA),
534 PINGROUP(100, NA, NA, NA, NA, NA, NA, NA),
535 PINGROUP(101, NA, NA, NA, NA, NA, NA, NA),
536 PINGROUP(102, NA, NA, NA, NA, NA, NA, NA),
537 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
538 PINGROUP(104, NA, NA, NA, NA, NA, NA, NA),
539 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
540 PINGROUP(106, NA, NA, NA, NA, NA, NA, NA),
541 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
543 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
544 PINGROUP(110, NA, NA, NA, NA, NA, NA, NA),
545 PINGROUP(111, NA, NA, NA, NA, NA, NA, NA),
546 PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
547 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
548 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
549 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
550 PINGROUP(116, NA, NA, NA, NA, NA, NA, NA),
551 PINGROUP(117, NA, NA, NA, NA, NA, NA, NA),
552 PINGROUP(118, NA, NA, NA, NA, NA, NA, NA),
553 PINGROUP(119, NA, NA, NA, NA, NA, NA, NA),
554 PINGROUP(120, NA, NA, NA, NA, NA, NA, NA),
555 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
556 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
557 PINGROUP(123, NA, NA, NA, NA, NA, NA, NA),
558 PINGROUP(124, NA, NA, NA, NA, NA, NA, NA),
559 PINGROUP(125, NA, NA, NA, NA, NA, NA, NA),
560 PINGROUP(126, NA, NA, NA, NA, NA, NA, NA),
561 PINGROUP(127, NA, NA, NA, NA, NA, NA, NA),
562 PINGROUP(128, NA, NA, NA, NA, NA, NA, NA),
563 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA),
564 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA),
565 PINGROUP(131, NA, NA, NA, NA, NA, NA, NA),
566 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA),
567 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA),
568 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA),
569 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA),
570 PINGROUP(136, NA, NA, NA, NA, NA, NA, NA),
571 PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
572 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
573 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
574 PINGROUP(140, NA, NA, NA, NA, NA, NA, NA),
575 PINGROUP(141, NA, NA, NA, NA, NA, NA, NA),
576 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
577 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
578 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
579 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
580 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
581 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
582 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
583 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
584 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
585 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
586};
587
588#define NUM_GPIO_PINGROUPS 146
589
590static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
591 .pins = msm8x74_pins,
592 .npins = ARRAY_SIZE(msm8x74_pins),
593 .functions = msm8x74_functions,
594 .nfunctions = ARRAY_SIZE(msm8x74_functions),
595 .groups = msm8x74_groups,
596 .ngroups = ARRAY_SIZE(msm8x74_groups),
597 .ngpios = NUM_GPIO_PINGROUPS,
598};
599
600static int msm8x74_pinctrl_probe(struct platform_device *pdev)
601{
602 return msm_pinctrl_probe(pdev, &msm8x74_pinctrl);
603}
604
605static struct of_device_id msm8x74_pinctrl_of_match[] = {
606 { .compatible = "qcom,msm8x74-pinctrl", },
607 { },
608};
609
610static struct platform_driver msm8x74_pinctrl_driver = {
611 .driver = {
612 .name = "msm8x74-pinctrl",
613 .owner = THIS_MODULE,
614 .of_match_table = msm8x74_pinctrl_of_match,
615 },
616 .probe = msm8x74_pinctrl_probe,
617 .remove = msm_pinctrl_remove,
618};
619
620static int __init msm8x74_pinctrl_init(void)
621{
622 return platform_driver_register(&msm8x74_pinctrl_driver);
623}
624arch_initcall(msm8x74_pinctrl_init);
625
626static void __exit msm8x74_pinctrl_exit(void)
627{
628 platform_driver_unregister(&msm8x74_pinctrl_driver);
629}
630module_exit(msm8x74_pinctrl_exit);
631
632MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
633MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");
634MODULE_LICENSE("GPL v2");
635MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
636
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 983662e846a4..6559e1436768 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1060,14 +1060,14 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
1060 (mode < 0) ? "unknown" : modes[mode], 1060 (mode < 0) ? "unknown" : modes[mode],
1061 pull ? "pull" : "none"); 1061 pull ? "pull" : "none");
1062 1062
1063 if (label && !is_out) { 1063 if (!is_out) {
1064 int irq = gpio_to_irq(gpio); 1064 int irq = gpio_to_irq(gpio);
1065 struct irq_desc *desc = irq_to_desc(irq); 1065 struct irq_desc *desc = irq_to_desc(irq);
1066 1066
1067 /* This races with request_irq(), set_irq_type(), 1067 /* This races with request_irq(), set_irq_type(),
1068 * and set_irq_wake() ... but those are "rare". 1068 * and set_irq_wake() ... but those are "rare".
1069 */ 1069 */
1070 if (irq >= 0 && desc->action) { 1070 if (irq > 0 && desc && desc->action) {
1071 char *trigger; 1071 char *trigger;
1072 u32 bitmask = nmk_gpio_get_bitmask(gpio); 1072 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1073 1073
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index d77ece5217f0..b9b464d0578c 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -26,29 +26,67 @@
26 26
27#include "core.h" 27#include "core.h"
28 28
29static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) 29static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
30{ 31{
32 unsigned int num_windows = 0;
33 unsigned int num_irqs = 0;
34 struct sh_pfc_window *windows;
35 unsigned int *irqs = NULL;
31 struct resource *res; 36 struct resource *res;
32 int k; 37 unsigned int i;
38
39 /* Count the MEM and IRQ resources. */
40 for (i = 0; i < pdev->num_resources; ++i) {
41 switch (resource_type(&pdev->resource[i])) {
42 case IORESOURCE_MEM:
43 num_windows++;
44 break;
45
46 case IORESOURCE_IRQ:
47 num_irqs++;
48 break;
49 }
50 }
33 51
34 if (pdev->num_resources == 0) 52 if (num_windows == 0)
35 return -EINVAL; 53 return -EINVAL;
36 54
37 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * 55 /* Allocate memory windows and IRQs arrays. */
38 sizeof(*pfc->window), GFP_NOWAIT); 56 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
39 if (!pfc->window) 57 GFP_KERNEL);
58 if (windows == NULL)
40 return -ENOMEM; 59 return -ENOMEM;
41 60
42 pfc->num_windows = pdev->num_resources; 61 pfc->num_windows = num_windows;
62 pfc->windows = windows;
43 63
44 for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { 64 if (num_irqs) {
45 WARN_ON(resource_type(res) != IORESOURCE_MEM); 65 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
46 pfc->window[k].phys = res->start; 66 GFP_KERNEL);
47 pfc->window[k].size = resource_size(res); 67 if (irqs == NULL)
48 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
49 resource_size(res));
50 if (!pfc->window[k].virt)
51 return -ENOMEM; 68 return -ENOMEM;
69
70 pfc->num_irqs = num_irqs;
71 pfc->irqs = irqs;
72 }
73
74 /* Fill them. */
75 for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
76 switch (resource_type(res)) {
77 case IORESOURCE_MEM:
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
82 return -ENOMEM;
83 windows++;
84 break;
85
86 case IORESOURCE_IRQ:
87 *irqs++ = res->start;
88 break;
89 }
52 } 90 }
53 91
54 return 0; 92 return 0;
@@ -62,7 +100,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
62 100
63 /* scan through physical windows and convert address */ 101 /* scan through physical windows and convert address */
64 for (i = 0; i < pfc->num_windows; i++) { 102 for (i = 0; i < pfc->num_windows; i++) {
65 window = pfc->window + i; 103 window = pfc->windows + i;
66 104
67 if (address < window->phys) 105 if (address < window->phys)
68 continue; 106 continue;
@@ -147,7 +185,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
147 unsigned long *maskp, 185 unsigned long *maskp,
148 unsigned long *posp) 186 unsigned long *posp)
149{ 187{
150 int k; 188 unsigned int k;
151 189
152 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); 190 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
153 191
@@ -196,7 +234,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
196{ 234{
197 const struct pinmux_cfg_reg *config_reg; 235 const struct pinmux_cfg_reg *config_reg;
198 unsigned long r_width, f_width, curr_width, ncomb; 236 unsigned long r_width, f_width, curr_width, ncomb;
199 int k, m, n, pos, bit_pos; 237 unsigned int k, m, n, pos, bit_pos;
200 238
201 k = 0; 239 k = 0;
202 while (1) { 240 while (1) {
@@ -238,7 +276,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
238 u16 *enum_idp) 276 u16 *enum_idp)
239{ 277{
240 const u16 *data = pfc->info->gpio_data; 278 const u16 *data = pfc->info->gpio_data;
241 int k; 279 unsigned int k;
242 280
243 if (pos) { 281 if (pos) {
244 *enum_idp = data[pos + 1]; 282 *enum_idp = data[pos + 1];
@@ -481,7 +519,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
481 pfc->info = info; 519 pfc->info = info;
482 pfc->dev = &pdev->dev; 520 pfc->dev = &pdev->dev;
483 521
484 ret = sh_pfc_ioremap(pfc, pdev); 522 ret = sh_pfc_map_resources(pfc, pdev);
485 if (unlikely(ret < 0)) 523 if (unlikely(ret < 0))
486 return ret; 524 return ret;
487 525
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 11ea87268658..b7b0e6ccf305 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -37,7 +37,9 @@ struct sh_pfc {
37 spinlock_t lock; 37 spinlock_t lock;
38 38
39 unsigned int num_windows; 39 unsigned int num_windows;
40 struct sh_pfc_window *window; 40 struct sh_pfc_window *windows;
41 unsigned int num_irqs;
42 unsigned int *irqs;
41 43
42 struct sh_pfc_pin_range *ranges; 44 struct sh_pfc_pin_range *ranges;
43 unsigned int nr_ranges; 45 unsigned int nr_ranges;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 04bf52b64fb3..63480815e1af 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -204,18 +204,24 @@ static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
204static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) 204static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
205{ 205{
206 struct sh_pfc *pfc = gpio_to_pfc(gc); 206 struct sh_pfc *pfc = gpio_to_pfc(gc);
207 int i, k; 207 unsigned int i, k;
208 208
209 for (i = 0; i < pfc->info->gpio_irq_size; i++) { 209 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
210 unsigned short *gpios = pfc->info->gpio_irq[i].gpios; 210 short *gpios = pfc->info->gpio_irq[i].gpios;
211 211
212 for (k = 0; gpios[k]; k++) { 212 for (k = 0; gpios[k] >= 0; k++) {
213 if (gpios[k] == offset) 213 if (gpios[k] == offset)
214 return pfc->info->gpio_irq[i].irq; 214 goto found;
215 } 215 }
216 } 216 }
217 217
218 return -ENOSYS; 218 return -ENOSYS;
219
220found:
221 if (pfc->num_irqs)
222 return pfc->irqs[i];
223 else
224 return pfc->info->gpio_irq[i].irq;
219} 225}
220 226
221static int gpio_pin_setup(struct sh_pfc_chip *chip) 227static int gpio_pin_setup(struct sh_pfc_chip *chip)
@@ -347,7 +353,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
347 * GPIOs. 353 * GPIOs.
348 */ 354 */
349 for (i = 0; i < pfc->num_windows; ++i) { 355 for (i = 0; i < pfc->num_windows; ++i) {
350 struct sh_pfc_window *window = &pfc->window[i]; 356 struct sh_pfc_window *window = &pfc->windows[i];
351 357
352 if (pfc->info->data_regs[0].reg >= window->phys && 358 if (pfc->info->data_regs[0].reg >= window->phys &&
353 pfc->info->data_regs[0].reg < window->phys + window->size) 359 pfc->info->data_regs[0].reg < window->phys + window->size)
@@ -357,8 +363,14 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
357 if (i == pfc->num_windows) 363 if (i == pfc->num_windows)
358 return 0; 364 return 0;
359 365
366 /* If we have IRQ resources make sure their number is correct. */
367 if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) {
368 dev_err(pfc->dev, "invalid number of IRQ resources\n");
369 return -EINVAL;
370 }
371
360 /* Register the real GPIOs chip. */ 372 /* Register the real GPIOs chip. */
361 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]); 373 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
362 if (IS_ERR(chip)) 374 if (IS_ERR(chip))
363 return PTR_ERR(chip); 375 return PTR_ERR(chip);
364 376
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index d25fd4ea0a1d..32dd478f28e3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2061,17 +2061,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
2061 SH_PFC_FUNCTION(sdhi2), 2061 SH_PFC_FUNCTION(sdhi2),
2062}; 2062};
2063 2063
2064#undef PORTCR
2065#define PORTCR(nr, reg) \
2066 { \
2067 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2068 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2069 PORT##nr##_FN0, PORT##nr##_FN1, \
2070 PORT##nr##_FN2, PORT##nr##_FN3, \
2071 PORT##nr##_FN4, PORT##nr##_FN5, \
2072 PORT##nr##_FN6, PORT##nr##_FN7 } \
2073 }
2074
2075static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2064static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2076 PORTCR(0, 0xe6050000), 2065 PORTCR(0, 0xe6050000),
2077 PORTCR(1, 0xe6050001), 2066 PORTCR(1, 0xe6050001),
@@ -2691,7 +2680,7 @@ static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2691{ 2680{
2692 void __iomem *addr; 2681 void __iomem *addr;
2693 2682
2694 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; 2683 addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2695 2684
2696 switch (ioread8(addr) & PORTCR_PULMD_MASK) { 2685 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2697 case PORTCR_PULMD_UP: 2686 case PORTCR_PULMD_UP:
@@ -2710,7 +2699,7 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2710 void __iomem *addr; 2699 void __iomem *addr;
2711 u32 value; 2700 u32 value;
2712 2701
2713 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; 2702 addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2714 value = ioread8(addr) & ~PORTCR_PULMD_MASK; 2703 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2715 2704
2716 switch (bias) { 2705 switch (bias) {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bc5eb453a45c..61e258577881 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3234,17 +3234,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
3234 SH_PFC_FUNCTION(tpu0), 3234 SH_PFC_FUNCTION(tpu0),
3235}; 3235};
3236 3236
3237#undef PORTCR
3238#define PORTCR(nr, reg) \
3239 { \
3240 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3241 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3242 PORT##nr##_FN0, PORT##nr##_FN1, \
3243 PORT##nr##_FN2, PORT##nr##_FN3, \
3244 PORT##nr##_FN4, PORT##nr##_FN5, \
3245 PORT##nr##_FN6, PORT##nr##_FN7 } \
3246 }
3247
3248static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3237static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3249 PORTCR(0, 0xe6050000), /* PORT0CR */ 3238 PORTCR(0, 0xe6050000), /* PORT0CR */
3250 PORTCR(1, 0xe6050001), /* PORT1CR */ 3239 PORTCR(1, 0xe6050001), /* PORT1CR */
@@ -3721,7 +3710,7 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3721 &r8a7740_portcr_offsets[i]; 3710 &r8a7740_portcr_offsets[i];
3722 3711
3723 if (pin <= group->end_pin) 3712 if (pin <= group->end_pin)
3724 return pfc->window->virt + group->offset + pin; 3713 return pfc->windows->virt + group->offset + pin;
3725 } 3714 }
3726 3715
3727 return NULL; 3716 return NULL;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 72786fc93958..293a51a7434e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1739,6 +1739,56 @@ static struct sh_pfc_pin pinmux_pins[] = {
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), 1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1740}; 1740};
1741 1741
1742/* - AUDIO CLOCK ------------------------------------------------------------ */
1743static const unsigned int audio_clk_a_pins[] = {
1744 /* CLK A */
1745 RCAR_GP_PIN(4, 25),
1746};
1747static const unsigned int audio_clk_a_mux[] = {
1748 AUDIO_CLKA_MARK,
1749};
1750static const unsigned int audio_clk_b_pins[] = {
1751 /* CLK B */
1752 RCAR_GP_PIN(4, 26),
1753};
1754static const unsigned int audio_clk_b_mux[] = {
1755 AUDIO_CLKB_MARK,
1756};
1757static const unsigned int audio_clk_c_pins[] = {
1758 /* CLK C */
1759 RCAR_GP_PIN(5, 27),
1760};
1761static const unsigned int audio_clk_c_mux[] = {
1762 AUDIO_CLKC_MARK,
1763};
1764static const unsigned int audio_clkout_pins[] = {
1765 /* CLK OUT */
1766 RCAR_GP_PIN(5, 16),
1767};
1768static const unsigned int audio_clkout_mux[] = {
1769 AUDIO_CLKOUT_MARK,
1770};
1771static const unsigned int audio_clkout_b_pins[] = {
1772 /* CLK OUT B */
1773 RCAR_GP_PIN(0, 23),
1774};
1775static const unsigned int audio_clkout_b_mux[] = {
1776 AUDIO_CLKOUT_B_MARK,
1777};
1778static const unsigned int audio_clkout_c_pins[] = {
1779 /* CLK OUT C */
1780 RCAR_GP_PIN(5, 27),
1781};
1782static const unsigned int audio_clkout_c_mux[] = {
1783 AUDIO_CLKOUT_C_MARK,
1784};
1785static const unsigned int audio_clkout_d_pins[] = {
1786 /* CLK OUT D */
1787 RCAR_GP_PIN(5, 20),
1788};
1789static const unsigned int audio_clkout_d_mux[] = {
1790 AUDIO_CLKOUT_D_MARK,
1791};
1742/* - DU RGB ----------------------------------------------------------------- */ 1792/* - DU RGB ----------------------------------------------------------------- */
1743static const unsigned int du_rgb666_pins[] = { 1793static const unsigned int du_rgb666_pins[] = {
1744 /* R[7:2], G[7:2], B[7:2] */ 1794 /* R[7:2], G[7:2], B[7:2] */
@@ -2961,6 +3011,189 @@ static const unsigned int sdhi3_wp_pins[] = {
2961static const unsigned int sdhi3_wp_mux[] = { 3011static const unsigned int sdhi3_wp_mux[] = {
2962 SD3_WP_MARK, 3012 SD3_WP_MARK,
2963}; 3013};
3014/* - SSI -------------------------------------------------------------------- */
3015static const unsigned int ssi0_data_pins[] = {
3016 /* SDATA0 */
3017 RCAR_GP_PIN(4, 5),
3018};
3019static const unsigned int ssi0_data_mux[] = {
3020 SSI_SDATA0_MARK,
3021};
3022static const unsigned int ssi0129_ctrl_pins[] = {
3023 /* SCK, WS */
3024 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3025};
3026static const unsigned int ssi0129_ctrl_mux[] = {
3027 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3028};
3029static const unsigned int ssi1_data_pins[] = {
3030 /* SDATA1 */
3031 RCAR_GP_PIN(4, 6),
3032};
3033static const unsigned int ssi1_data_mux[] = {
3034 SSI_SDATA1_MARK,
3035};
3036static const unsigned int ssi1_ctrl_pins[] = {
3037 /* SCK, WS */
3038 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3039};
3040static const unsigned int ssi1_ctrl_mux[] = {
3041 SSI_SCK1_MARK, SSI_WS1_MARK,
3042};
3043static const unsigned int ssi2_data_pins[] = {
3044 /* SDATA2 */
3045 RCAR_GP_PIN(4, 7),
3046};
3047static const unsigned int ssi2_data_mux[] = {
3048 SSI_SDATA2_MARK,
3049};
3050static const unsigned int ssi2_ctrl_pins[] = {
3051 /* SCK, WS */
3052 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3053};
3054static const unsigned int ssi2_ctrl_mux[] = {
3055 SSI_SCK2_MARK, SSI_WS2_MARK,
3056};
3057static const unsigned int ssi3_data_pins[] = {
3058 /* SDATA3 */
3059 RCAR_GP_PIN(4, 10),
3060};
3061static const unsigned int ssi3_data_mux[] = {
3062 SSI_SDATA3_MARK
3063};
3064static const unsigned int ssi34_ctrl_pins[] = {
3065 /* SCK, WS */
3066 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3067};
3068static const unsigned int ssi34_ctrl_mux[] = {
3069 SSI_SCK34_MARK, SSI_WS34_MARK,
3070};
3071static const unsigned int ssi4_data_pins[] = {
3072 /* SDATA4 */
3073 RCAR_GP_PIN(4, 13),
3074};
3075static const unsigned int ssi4_data_mux[] = {
3076 SSI_SDATA4_MARK,
3077};
3078static const unsigned int ssi4_ctrl_pins[] = {
3079 /* SCK, WS */
3080 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3081};
3082static const unsigned int ssi4_ctrl_mux[] = {
3083 SSI_SCK4_MARK, SSI_WS4_MARK,
3084};
3085static const unsigned int ssi5_pins[] = {
3086 /* SDATA5, SCK, WS */
3087 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3088};
3089static const unsigned int ssi5_mux[] = {
3090 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3091};
3092static const unsigned int ssi5_b_pins[] = {
3093 /* SDATA5, SCK, WS */
3094 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3095};
3096static const unsigned int ssi5_b_mux[] = {
3097 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3098};
3099static const unsigned int ssi5_c_pins[] = {
3100 /* SDATA5, SCK, WS */
3101 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3102};
3103static const unsigned int ssi5_c_mux[] = {
3104 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3105};
3106static const unsigned int ssi6_pins[] = {
3107 /* SDATA6, SCK, WS */
3108 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3109};
3110static const unsigned int ssi6_mux[] = {
3111 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3112};
3113static const unsigned int ssi6_b_pins[] = {
3114 /* SDATA6, SCK, WS */
3115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3116};
3117static const unsigned int ssi6_b_mux[] = {
3118 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3119};
3120static const unsigned int ssi7_data_pins[] = {
3121 /* SDATA7 */
3122 RCAR_GP_PIN(4, 22),
3123};
3124static const unsigned int ssi7_data_mux[] = {
3125 SSI_SDATA7_MARK,
3126};
3127static const unsigned int ssi7_b_data_pins[] = {
3128 /* SDATA7 */
3129 RCAR_GP_PIN(4, 22),
3130};
3131static const unsigned int ssi7_b_data_mux[] = {
3132 SSI_SDATA7_B_MARK,
3133};
3134static const unsigned int ssi7_c_data_pins[] = {
3135 /* SDATA7 */
3136 RCAR_GP_PIN(1, 26),
3137};
3138static const unsigned int ssi7_c_data_mux[] = {
3139 SSI_SDATA7_C_MARK,
3140};
3141static const unsigned int ssi78_ctrl_pins[] = {
3142 /* SCK, WS */
3143 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3144};
3145static const unsigned int ssi78_ctrl_mux[] = {
3146 SSI_SCK78_MARK, SSI_WS78_MARK,
3147};
3148static const unsigned int ssi78_b_ctrl_pins[] = {
3149 /* SCK, WS */
3150 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3151};
3152static const unsigned int ssi78_b_ctrl_mux[] = {
3153 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3154};
3155static const unsigned int ssi78_c_ctrl_pins[] = {
3156 /* SCK, WS */
3157 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3158};
3159static const unsigned int ssi78_c_ctrl_mux[] = {
3160 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3161};
3162static const unsigned int ssi8_data_pins[] = {
3163 /* SDATA8 */
3164 RCAR_GP_PIN(4, 23),
3165};
3166static const unsigned int ssi8_data_mux[] = {
3167 SSI_SDATA8_MARK,
3168};
3169static const unsigned int ssi8_b_data_pins[] = {
3170 /* SDATA8 */
3171 RCAR_GP_PIN(4, 23),
3172};
3173static const unsigned int ssi8_b_data_mux[] = {
3174 SSI_SDATA8_B_MARK,
3175};
3176static const unsigned int ssi8_c_data_pins[] = {
3177 /* SDATA8 */
3178 RCAR_GP_PIN(1, 27),
3179};
3180static const unsigned int ssi8_c_data_mux[] = {
3181 SSI_SDATA8_C_MARK,
3182};
3183static const unsigned int ssi9_data_pins[] = {
3184 /* SDATA9 */
3185 RCAR_GP_PIN(4, 24),
3186};
3187static const unsigned int ssi9_data_mux[] = {
3188 SSI_SDATA9_MARK,
3189};
3190static const unsigned int ssi9_ctrl_pins[] = {
3191 /* SCK, WS */
3192 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3193};
3194static const unsigned int ssi9_ctrl_mux[] = {
3195 SSI_SCK9_MARK, SSI_WS9_MARK,
3196};
2964/* - TPU0 ------------------------------------------------------------------- */ 3197/* - TPU0 ------------------------------------------------------------------- */
2965static const unsigned int tpu0_to0_pins[] = { 3198static const unsigned int tpu0_to0_pins[] = {
2966 /* TO */ 3199 /* TO */
@@ -3014,59 +3247,110 @@ static const unsigned int usb2_pins[] = {
3014static const unsigned int usb2_mux[] = { 3247static const unsigned int usb2_mux[] = {
3015 USB2_PWEN_MARK, USB2_OVC_MARK, 3248 USB2_PWEN_MARK, USB2_OVC_MARK,
3016}; 3249};
3017/* - VIN0 ------------------------------------------------------------------- */ 3250
3018static const unsigned int vin0_data_g_pins[] = { 3251union vin_data {
3019 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 3252 unsigned int data24[24];
3020 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3253 unsigned int data20[20];
3021 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3254 unsigned int data16[16];
3022}; 3255 unsigned int data12[12];
3023static const unsigned int vin0_data_g_mux[] = { 3256 unsigned int data10[10];
3024 VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK, 3257 unsigned int data8[8];
3025 VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK, 3258 unsigned int data4[4];
3026 VI0_G6_MARK, VI0_G7_MARK,
3027}; 3259};
3028static const unsigned int vin0_data_r_pins[] = { 3260
3029 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3261#define VIN_DATA_PIN_GROUP(n, s) \
3030 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3262 { \
3031 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3263 .name = #n#s, \
3264 .pins = n##_pins.data##s, \
3265 .mux = n##_mux.data##s, \
3266 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
3267 }
3268
3269/* - VIN0 ------------------------------------------------------------------- */
3270static const union vin_data vin0_data_pins = {
3271 .data24 = {
3272 /* B */
3273 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3274 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3275 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3276 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3277 /* G */
3278 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3279 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3280 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3281 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3282 /* R */
3283 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3284 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3285 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3286 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3287 },
3032}; 3288};
3033static const unsigned int vin0_data_r_mux[] = { 3289static const union vin_data vin0_data_mux = {
3034 VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK, 3290 .data24 = {
3035 VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK, 3291 /* B */
3036 VI0_R6_MARK, VI0_R7_MARK, 3292 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3293 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3294 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3295 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3296 /* G */
3297 VI0_G0_MARK, VI0_G1_MARK,
3298 VI0_G2_MARK, VI0_G3_MARK,
3299 VI0_G4_MARK, VI0_G5_MARK,
3300 VI0_G6_MARK, VI0_G7_MARK,
3301 /* R */
3302 VI0_R0_MARK, VI0_R1_MARK,
3303 VI0_R2_MARK, VI0_R3_MARK,
3304 VI0_R4_MARK, VI0_R5_MARK,
3305 VI0_R6_MARK, VI0_R7_MARK,
3306 },
3037}; 3307};
3038static const unsigned int vin0_data_b_pins[] = { 3308static const unsigned int vin0_data18_pins[] = {
3039 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3309 /* B */
3040 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3310 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3311 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3041 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3312 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3313 /* G */
3314 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3315 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3316 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3317 /* R */
3318 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3319 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3320 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3042}; 3321};
3043static const unsigned int vin0_data_b_mux[] = { 3322static const unsigned int vin0_data18_mux[] = {
3044 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, 3323 /* B */
3045 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3324 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3325 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3046 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3326 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3327 /* G */
3328 VI0_G2_MARK, VI0_G3_MARK,
3329 VI0_G4_MARK, VI0_G5_MARK,
3330 VI0_G6_MARK, VI0_G7_MARK,
3331 /* R */
3332 VI0_R2_MARK, VI0_R3_MARK,
3333 VI0_R4_MARK, VI0_R5_MARK,
3334 VI0_R6_MARK, VI0_R7_MARK,
3047}; 3335};
3048static const unsigned int vin0_hsync_signal_pins[] = { 3336static const unsigned int vin0_sync_pins[] = {
3049 RCAR_GP_PIN(0, 12), 3337 RCAR_GP_PIN(0, 12), /* HSYNC */
3338 RCAR_GP_PIN(0, 13), /* VSYNC */
3050}; 3339};
3051static const unsigned int vin0_hsync_signal_mux[] = { 3340static const unsigned int vin0_sync_mux[] = {
3052 VI0_HSYNC_N_MARK, 3341 VI0_HSYNC_N_MARK,
3053};
3054static const unsigned int vin0_vsync_signal_pins[] = {
3055 RCAR_GP_PIN(0, 13),
3056};
3057static const unsigned int vin0_vsync_signal_mux[] = {
3058 VI0_VSYNC_N_MARK, 3342 VI0_VSYNC_N_MARK,
3059}; 3343};
3060static const unsigned int vin0_field_signal_pins[] = { 3344static const unsigned int vin0_field_pins[] = {
3061 RCAR_GP_PIN(0, 15), 3345 RCAR_GP_PIN(0, 15),
3062}; 3346};
3063static const unsigned int vin0_field_signal_mux[] = { 3347static const unsigned int vin0_field_mux[] = {
3064 VI0_FIELD_MARK, 3348 VI0_FIELD_MARK,
3065}; 3349};
3066static const unsigned int vin0_data_enable_pins[] = { 3350static const unsigned int vin0_clkenb_pins[] = {
3067 RCAR_GP_PIN(0, 14), 3351 RCAR_GP_PIN(0, 14),
3068}; 3352};
3069static const unsigned int vin0_data_enable_mux[] = { 3353static const unsigned int vin0_clkenb_mux[] = {
3070 VI0_CLKENB_MARK, 3354 VI0_CLKENB_MARK,
3071}; 3355};
3072static const unsigned int vin0_clk_pins[] = { 3356static const unsigned int vin0_clk_pins[] = {
@@ -3076,15 +3360,91 @@ static const unsigned int vin0_clk_mux[] = {
3076 VI0_CLK_MARK, 3360 VI0_CLK_MARK,
3077}; 3361};
3078/* - VIN1 ------------------------------------------------------------------- */ 3362/* - VIN1 ------------------------------------------------------------------- */
3079static const unsigned int vin1_data_pins[] = { 3363static const union vin_data vin1_data_pins = {
3080 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3364 .data24 = {
3081 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3365 /* B */
3082 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3366 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3367 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3368 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3369 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3370 /* G */
3371 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3372 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3373 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3374 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3375 /* R */
3376 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3377 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3378 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3379 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3380 },
3083}; 3381};
3084static const unsigned int vin1_data_mux[] = { 3382static const union vin_data vin1_data_mux = {
3085 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, 3383 .data24 = {
3086 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3384 /* B */
3385 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3386 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3387 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3388 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3389 /* G */
3390 VI1_G0_MARK, VI1_G1_MARK,
3391 VI1_G2_MARK, VI1_G3_MARK,
3392 VI1_G4_MARK, VI1_G5_MARK,
3393 VI1_G6_MARK, VI1_G7_MARK,
3394 /* R */
3395 VI1_R0_MARK, VI1_R1_MARK,
3396 VI1_R2_MARK, VI1_R3_MARK,
3397 VI1_R4_MARK, VI1_R5_MARK,
3398 VI1_R6_MARK, VI1_R7_MARK,
3399 },
3400};
3401static const unsigned int vin1_data18_pins[] = {
3402 /* B */
3403 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3404 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3405 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3406 /* G */
3407 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3408 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3409 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3410 /* R */
3411 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3412 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3413 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3414};
3415static const unsigned int vin1_data18_mux[] = {
3416 /* B */
3417 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3418 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3087 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3419 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3420 /* G */
3421 VI1_G2_MARK, VI1_G3_MARK,
3422 VI1_G4_MARK, VI1_G5_MARK,
3423 VI1_G6_MARK, VI1_G7_MARK,
3424 /* R */
3425 VI1_R2_MARK, VI1_R3_MARK,
3426 VI1_R4_MARK, VI1_R5_MARK,
3427 VI1_R6_MARK, VI1_R7_MARK,
3428};
3429static const unsigned int vin1_sync_pins[] = {
3430 RCAR_GP_PIN(1, 24), /* HSYNC */
3431 RCAR_GP_PIN(1, 25), /* VSYNC */
3432};
3433static const unsigned int vin1_sync_mux[] = {
3434 VI1_HSYNC_N_MARK,
3435 VI1_VSYNC_N_MARK,
3436};
3437static const unsigned int vin1_field_pins[] = {
3438 RCAR_GP_PIN(1, 13),
3439};
3440static const unsigned int vin1_field_mux[] = {
3441 VI1_FIELD_MARK,
3442};
3443static const unsigned int vin1_clkenb_pins[] = {
3444 RCAR_GP_PIN(1, 26),
3445};
3446static const unsigned int vin1_clkenb_mux[] = {
3447 VI1_CLKENB_MARK,
3088}; 3448};
3089static const unsigned int vin1_clk_pins[] = { 3449static const unsigned int vin1_clk_pins[] = {
3090 RCAR_GP_PIN(2, 9), 3450 RCAR_GP_PIN(2, 9),
@@ -3092,8 +3452,147 @@ static const unsigned int vin1_clk_pins[] = {
3092static const unsigned int vin1_clk_mux[] = { 3452static const unsigned int vin1_clk_mux[] = {
3093 VI1_CLK_MARK, 3453 VI1_CLK_MARK,
3094}; 3454};
3455/* - VIN2 ----------------------------------------------------------------- */
3456static const union vin_data vin2_data_pins = {
3457 .data24 = {
3458 /* B */
3459 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3460 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3461 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3462 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3463 /* G */
3464 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3465 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3466 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3467 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3468 /* R */
3469 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3470 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3471 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3472 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3473 },
3474};
3475static const union vin_data vin2_data_mux = {
3476 .data24 = {
3477 /* B */
3478 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3479 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3480 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3481 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3482 /* G */
3483 VI2_G0_MARK, VI2_G1_MARK,
3484 VI2_G2_MARK, VI2_G3_MARK,
3485 VI2_G4_MARK, VI2_G5_MARK,
3486 VI2_G6_MARK, VI2_G7_MARK,
3487 /* R */
3488 VI2_R0_MARK, VI2_R1_MARK,
3489 VI2_R2_MARK, VI2_R3_MARK,
3490 VI2_R4_MARK, VI2_R5_MARK,
3491 VI2_R6_MARK, VI2_R7_MARK,
3492 },
3493};
3494static const unsigned int vin2_data18_pins[] = {
3495 /* B */
3496 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3497 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3498 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3499 /* G */
3500 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3501 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3502 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3503 /* R */
3504 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3505 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3506 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3507};
3508static const unsigned int vin2_data18_mux[] = {
3509 /* B */
3510 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3511 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3512 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3513 /* G */
3514 VI2_G2_MARK, VI2_G3_MARK,
3515 VI2_G4_MARK, VI2_G5_MARK,
3516 VI2_G6_MARK, VI2_G7_MARK,
3517 /* R */
3518 VI2_R2_MARK, VI2_R3_MARK,
3519 VI2_R4_MARK, VI2_R5_MARK,
3520 VI2_R6_MARK, VI2_R7_MARK,
3521};
3522static const unsigned int vin2_sync_pins[] = {
3523 RCAR_GP_PIN(1, 16), /* HSYNC */
3524 RCAR_GP_PIN(1, 21), /* VSYNC */
3525};
3526static const unsigned int vin2_sync_mux[] = {
3527 VI2_HSYNC_N_MARK,
3528 VI2_VSYNC_N_MARK,
3529};
3530static const unsigned int vin2_field_pins[] = {
3531 RCAR_GP_PIN(1, 9),
3532};
3533static const unsigned int vin2_field_mux[] = {
3534 VI2_FIELD_MARK,
3535};
3536static const unsigned int vin2_clkenb_pins[] = {
3537 RCAR_GP_PIN(1, 8),
3538};
3539static const unsigned int vin2_clkenb_mux[] = {
3540 VI2_CLKENB_MARK,
3541};
3542static const unsigned int vin2_clk_pins[] = {
3543 RCAR_GP_PIN(1, 11),
3544};
3545static const unsigned int vin2_clk_mux[] = {
3546 VI2_CLK_MARK,
3547};
3548/* - VIN3 ----------------------------------------------------------------- */
3549static const unsigned int vin3_data8_pins[] = {
3550 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3551 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3552 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3553 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3554};
3555static const unsigned int vin3_data8_mux[] = {
3556 VI3_DATA0_MARK, VI3_DATA1_MARK,
3557 VI3_DATA2_MARK, VI3_DATA3_MARK,
3558 VI3_DATA4_MARK, VI3_DATA5_MARK,
3559 VI3_DATA6_MARK, VI3_DATA7_MARK,
3560};
3561static const unsigned int vin3_sync_pins[] = {
3562 RCAR_GP_PIN(1, 16), /* HSYNC */
3563 RCAR_GP_PIN(1, 17), /* VSYNC */
3564};
3565static const unsigned int vin3_sync_mux[] = {
3566 VI3_HSYNC_N_MARK,
3567 VI2_VSYNC_N_MARK,
3568};
3569static const unsigned int vin3_field_pins[] = {
3570 RCAR_GP_PIN(1, 15),
3571};
3572static const unsigned int vin3_field_mux[] = {
3573 VI3_FIELD_MARK,
3574};
3575static const unsigned int vin3_clkenb_pins[] = {
3576 RCAR_GP_PIN(1, 14),
3577};
3578static const unsigned int vin3_clkenb_mux[] = {
3579 VI3_CLKENB_MARK,
3580};
3581static const unsigned int vin3_clk_pins[] = {
3582 RCAR_GP_PIN(1, 23),
3583};
3584static const unsigned int vin3_clk_mux[] = {
3585 VI3_CLK_MARK,
3586};
3095 3587
3096static const struct sh_pfc_pin_group pinmux_groups[] = { 3588static const struct sh_pfc_pin_group pinmux_groups[] = {
3589 SH_PFC_PIN_GROUP(audio_clk_a),
3590 SH_PFC_PIN_GROUP(audio_clk_b),
3591 SH_PFC_PIN_GROUP(audio_clk_c),
3592 SH_PFC_PIN_GROUP(audio_clkout),
3593 SH_PFC_PIN_GROUP(audio_clkout_b),
3594 SH_PFC_PIN_GROUP(audio_clkout_c),
3595 SH_PFC_PIN_GROUP(audio_clkout_d),
3097 SH_PFC_PIN_GROUP(du_rgb666), 3596 SH_PFC_PIN_GROUP(du_rgb666),
3098 SH_PFC_PIN_GROUP(du_rgb888), 3597 SH_PFC_PIN_GROUP(du_rgb888),
3099 SH_PFC_PIN_GROUP(du_clk_out_0), 3598 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -3259,6 +3758,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3259 SH_PFC_PIN_GROUP(sdhi3_ctrl), 3758 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3260 SH_PFC_PIN_GROUP(sdhi3_cd), 3759 SH_PFC_PIN_GROUP(sdhi3_cd),
3261 SH_PFC_PIN_GROUP(sdhi3_wp), 3760 SH_PFC_PIN_GROUP(sdhi3_wp),
3761 SH_PFC_PIN_GROUP(ssi0_data),
3762 SH_PFC_PIN_GROUP(ssi0129_ctrl),
3763 SH_PFC_PIN_GROUP(ssi1_data),
3764 SH_PFC_PIN_GROUP(ssi1_ctrl),
3765 SH_PFC_PIN_GROUP(ssi2_data),
3766 SH_PFC_PIN_GROUP(ssi2_ctrl),
3767 SH_PFC_PIN_GROUP(ssi3_data),
3768 SH_PFC_PIN_GROUP(ssi34_ctrl),
3769 SH_PFC_PIN_GROUP(ssi4_data),
3770 SH_PFC_PIN_GROUP(ssi4_ctrl),
3771 SH_PFC_PIN_GROUP(ssi5),
3772 SH_PFC_PIN_GROUP(ssi5_b),
3773 SH_PFC_PIN_GROUP(ssi5_c),
3774 SH_PFC_PIN_GROUP(ssi6),
3775 SH_PFC_PIN_GROUP(ssi6_b),
3776 SH_PFC_PIN_GROUP(ssi7_data),
3777 SH_PFC_PIN_GROUP(ssi7_b_data),
3778 SH_PFC_PIN_GROUP(ssi7_c_data),
3779 SH_PFC_PIN_GROUP(ssi78_ctrl),
3780 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
3781 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
3782 SH_PFC_PIN_GROUP(ssi8_data),
3783 SH_PFC_PIN_GROUP(ssi8_b_data),
3784 SH_PFC_PIN_GROUP(ssi8_c_data),
3785 SH_PFC_PIN_GROUP(ssi9_data),
3786 SH_PFC_PIN_GROUP(ssi9_ctrl),
3262 SH_PFC_PIN_GROUP(tpu0_to0), 3787 SH_PFC_PIN_GROUP(tpu0_to0),
3263 SH_PFC_PIN_GROUP(tpu0_to1), 3788 SH_PFC_PIN_GROUP(tpu0_to1),
3264 SH_PFC_PIN_GROUP(tpu0_to2), 3789 SH_PFC_PIN_GROUP(tpu0_to2),
@@ -3266,16 +3791,54 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3266 SH_PFC_PIN_GROUP(usb0), 3791 SH_PFC_PIN_GROUP(usb0),
3267 SH_PFC_PIN_GROUP(usb1), 3792 SH_PFC_PIN_GROUP(usb1),
3268 SH_PFC_PIN_GROUP(usb2), 3793 SH_PFC_PIN_GROUP(usb2),
3269 SH_PFC_PIN_GROUP(vin0_data_g), 3794 VIN_DATA_PIN_GROUP(vin0_data, 24),
3270 SH_PFC_PIN_GROUP(vin0_data_r), 3795 VIN_DATA_PIN_GROUP(vin0_data, 20),
3271 SH_PFC_PIN_GROUP(vin0_data_b), 3796 SH_PFC_PIN_GROUP(vin0_data18),
3272 SH_PFC_PIN_GROUP(vin0_hsync_signal), 3797 VIN_DATA_PIN_GROUP(vin0_data, 16),
3273 SH_PFC_PIN_GROUP(vin0_vsync_signal), 3798 VIN_DATA_PIN_GROUP(vin0_data, 12),
3274 SH_PFC_PIN_GROUP(vin0_field_signal), 3799 VIN_DATA_PIN_GROUP(vin0_data, 10),
3275 SH_PFC_PIN_GROUP(vin0_data_enable), 3800 VIN_DATA_PIN_GROUP(vin0_data, 8),
3801 VIN_DATA_PIN_GROUP(vin0_data, 4),
3802 SH_PFC_PIN_GROUP(vin0_sync),
3803 SH_PFC_PIN_GROUP(vin0_field),
3804 SH_PFC_PIN_GROUP(vin0_clkenb),
3276 SH_PFC_PIN_GROUP(vin0_clk), 3805 SH_PFC_PIN_GROUP(vin0_clk),
3277 SH_PFC_PIN_GROUP(vin1_data), 3806 VIN_DATA_PIN_GROUP(vin1_data, 24),
3807 VIN_DATA_PIN_GROUP(vin1_data, 20),
3808 SH_PFC_PIN_GROUP(vin1_data18),
3809 VIN_DATA_PIN_GROUP(vin1_data, 16),
3810 VIN_DATA_PIN_GROUP(vin1_data, 12),
3811 VIN_DATA_PIN_GROUP(vin1_data, 10),
3812 VIN_DATA_PIN_GROUP(vin1_data, 8),
3813 VIN_DATA_PIN_GROUP(vin1_data, 4),
3814 SH_PFC_PIN_GROUP(vin1_sync),
3815 SH_PFC_PIN_GROUP(vin1_field),
3816 SH_PFC_PIN_GROUP(vin1_clkenb),
3278 SH_PFC_PIN_GROUP(vin1_clk), 3817 SH_PFC_PIN_GROUP(vin1_clk),
3818 VIN_DATA_PIN_GROUP(vin2_data, 24),
3819 SH_PFC_PIN_GROUP(vin2_data18),
3820 VIN_DATA_PIN_GROUP(vin2_data, 16),
3821 VIN_DATA_PIN_GROUP(vin2_data, 8),
3822 VIN_DATA_PIN_GROUP(vin2_data, 4),
3823 SH_PFC_PIN_GROUP(vin2_sync),
3824 SH_PFC_PIN_GROUP(vin2_field),
3825 SH_PFC_PIN_GROUP(vin2_clkenb),
3826 SH_PFC_PIN_GROUP(vin2_clk),
3827 SH_PFC_PIN_GROUP(vin3_data8),
3828 SH_PFC_PIN_GROUP(vin3_sync),
3829 SH_PFC_PIN_GROUP(vin3_field),
3830 SH_PFC_PIN_GROUP(vin3_clkenb),
3831 SH_PFC_PIN_GROUP(vin3_clk),
3832};
3833
3834static const char * const audio_clk_groups[] = {
3835 "audio_clk_a",
3836 "audio_clk_b",
3837 "audio_clk_c",
3838 "audio_clkout",
3839 "audio_clkout_b",
3840 "audio_clkout_c",
3841 "audio_clkout_d",
3279}; 3842};
3280 3843
3281static const char * const du_groups[] = { 3844static const char * const du_groups[] = {
@@ -3533,6 +4096,35 @@ static const char * const sdhi3_groups[] = {
3533 "sdhi3_wp", 4096 "sdhi3_wp",
3534}; 4097};
3535 4098
4099static const char * const ssi_groups[] = {
4100 "ssi0_data",
4101 "ssi0129_ctrl",
4102 "ssi1_data",
4103 "ssi1_ctrl",
4104 "ssi2_data",
4105 "ssi2_ctrl",
4106 "ssi3_data",
4107 "ssi34_ctrl",
4108 "ssi4_data",
4109 "ssi4_ctrl",
4110 "ssi5",
4111 "ssi5_b",
4112 "ssi5_c",
4113 "ssi6",
4114 "ssi6_b",
4115 "ssi7_data",
4116 "ssi7_b_data",
4117 "ssi7_c_data",
4118 "ssi78_ctrl",
4119 "ssi78_b_ctrl",
4120 "ssi78_c_ctrl",
4121 "ssi8_data",
4122 "ssi8_b_data",
4123 "ssi8_c_data",
4124 "ssi9_data",
4125 "ssi9_ctrl",
4126};
4127
3536static const char * const tpu0_groups[] = { 4128static const char * const tpu0_groups[] = {
3537 "tpu0_to0", 4129 "tpu0_to0",
3538 "tpu0_to1", 4130 "tpu0_to1",
@@ -3553,22 +4145,57 @@ static const char * const usb2_groups[] = {
3553}; 4145};
3554 4146
3555static const char * const vin0_groups[] = { 4147static const char * const vin0_groups[] = {
3556 "vin0_data_g", 4148 "vin0_data24",
3557 "vin0_data_r", 4149 "vin0_data20",
3558 "vin0_data_b", 4150 "vin0_data18",
3559 "vin0_hsync_signal", 4151 "vin0_data16",
3560 "vin0_vsync_signal", 4152 "vin0_data12",
3561 "vin0_field_signal", 4153 "vin0_data10",
3562 "vin0_data_enable", 4154 "vin0_data8",
4155 "vin0_data4",
4156 "vin0_sync",
4157 "vin0_field",
4158 "vin0_clkenb",
3563 "vin0_clk", 4159 "vin0_clk",
3564}; 4160};
3565 4161
3566static const char * const vin1_groups[] = { 4162static const char * const vin1_groups[] = {
3567 "vin1_data", 4163 "vin1_data24",
4164 "vin1_data20",
4165 "vin1_data18",
4166 "vin1_data16",
4167 "vin1_data12",
4168 "vin1_data10",
4169 "vin1_data8",
4170 "vin1_data4",
4171 "vin1_sync",
4172 "vin1_field",
4173 "vin1_clkenb",
3568 "vin1_clk", 4174 "vin1_clk",
3569}; 4175};
3570 4176
4177static const char * const vin2_groups[] = {
4178 "vin2_data24",
4179 "vin2_data18",
4180 "vin2_data16",
4181 "vin2_data8",
4182 "vin2_data4",
4183 "vin2_sync",
4184 "vin2_field",
4185 "vin2_clkenb",
4186 "vin2_clk",
4187};
4188
4189static const char * const vin3_groups[] = {
4190 "vin3_data8",
4191 "vin3_sync",
4192 "vin3_field",
4193 "vin3_clkenb",
4194 "vin3_clk",
4195};
4196
3571static const struct sh_pfc_function pinmux_functions[] = { 4197static const struct sh_pfc_function pinmux_functions[] = {
4198 SH_PFC_FUNCTION(audio_clk),
3572 SH_PFC_FUNCTION(du), 4199 SH_PFC_FUNCTION(du),
3573 SH_PFC_FUNCTION(du0), 4200 SH_PFC_FUNCTION(du0),
3574 SH_PFC_FUNCTION(du1), 4201 SH_PFC_FUNCTION(du1),
@@ -3599,12 +4226,15 @@ static const struct sh_pfc_function pinmux_functions[] = {
3599 SH_PFC_FUNCTION(sdhi1), 4226 SH_PFC_FUNCTION(sdhi1),
3600 SH_PFC_FUNCTION(sdhi2), 4227 SH_PFC_FUNCTION(sdhi2),
3601 SH_PFC_FUNCTION(sdhi3), 4228 SH_PFC_FUNCTION(sdhi3),
4229 SH_PFC_FUNCTION(ssi),
3602 SH_PFC_FUNCTION(tpu0), 4230 SH_PFC_FUNCTION(tpu0),
3603 SH_PFC_FUNCTION(usb0), 4231 SH_PFC_FUNCTION(usb0),
3604 SH_PFC_FUNCTION(usb1), 4232 SH_PFC_FUNCTION(usb1),
3605 SH_PFC_FUNCTION(usb2), 4233 SH_PFC_FUNCTION(usb2),
3606 SH_PFC_FUNCTION(vin0), 4234 SH_PFC_FUNCTION(vin0),
3607 SH_PFC_FUNCTION(vin1), 4235 SH_PFC_FUNCTION(vin1),
4236 SH_PFC_FUNCTION(vin2),
4237 SH_PFC_FUNCTION(vin3),
3608}; 4238};
3609 4239
3610static struct pinmux_cfg_reg pinmux_config_regs[] = { 4240static struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index bf76a654c02f..ea02d37bab7c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1730,11 +1730,11 @@ static const unsigned int du_clk_out_1_pins[] = {
1730static const unsigned int du_clk_out_1_mux[] = { 1730static const unsigned int du_clk_out_1_mux[] = {
1731 DU1_DOTCLKOUT1_MARK 1731 DU1_DOTCLKOUT1_MARK
1732}; 1732};
1733static const unsigned int du_sync_1_pins[] = { 1733static const unsigned int du_sync_pins[] = {
1734 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */ 1734 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1735 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 1735 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1736}; 1736};
1737static const unsigned int du_sync_1_mux[] = { 1737static const unsigned int du_sync_mux[] = {
1738 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 1738 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1739 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 1739 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1740}; 1740};
@@ -1742,6 +1742,9 @@ static const unsigned int du_cde_disp_pins[] = {
1742 /* CDE DISP */ 1742 /* CDE DISP */
1743 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30), 1743 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1744}; 1744};
1745static const unsigned int du_cde_disp_mux[] = {
1746 DU1_CDE_MARK, DU1_DISP_MARK
1747};
1745static const unsigned int du0_clk_in_pins[] = { 1748static const unsigned int du0_clk_in_pins[] = {
1746 /* CLKIN */ 1749 /* CLKIN */
1747 RCAR_GP_PIN(6, 31), 1750 RCAR_GP_PIN(6, 31),
@@ -1749,15 +1752,26 @@ static const unsigned int du0_clk_in_pins[] = {
1749static const unsigned int du0_clk_in_mux[] = { 1752static const unsigned int du0_clk_in_mux[] = {
1750 DU0_DOTCLKIN_MARK 1753 DU0_DOTCLKIN_MARK
1751}; 1754};
1752static const unsigned int du_cde_disp_mux[] = {
1753 DU1_CDE_MARK, DU1_DISP_MARK
1754};
1755static const unsigned int du1_clk_in_pins[] = { 1755static const unsigned int du1_clk_in_pins[] = {
1756 /* CLKIN */ 1756 /* CLKIN */
1757 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), RCAR_GP_PIN(3, 24), 1757 RCAR_GP_PIN(3, 24),
1758}; 1758};
1759static const unsigned int du1_clk_in_mux[] = { 1759static const unsigned int du1_clk_in_mux[] = {
1760 DU1_DOTCLKIN_C_MARK, DU1_DOTCLKIN_B_MARK, DU1_DOTCLKIN_MARK 1760 DU1_DOTCLKIN_MARK
1761};
1762static const unsigned int du1_clk_in_b_pins[] = {
1763 /* CLKIN */
1764 RCAR_GP_PIN(7, 19),
1765};
1766static const unsigned int du1_clk_in_b_mux[] = {
1767 DU1_DOTCLKIN_B_MARK,
1768};
1769static const unsigned int du1_clk_in_c_pins[] = {
1770 /* CLKIN */
1771 RCAR_GP_PIN(7, 20),
1772};
1773static const unsigned int du1_clk_in_c_mux[] = {
1774 DU1_DOTCLKIN_C_MARK,
1761}; 1775};
1762/* - ETH -------------------------------------------------------------------- */ 1776/* - ETH -------------------------------------------------------------------- */
1763static const unsigned int eth_link_pins[] = { 1777static const unsigned int eth_link_pins[] = {
@@ -2670,10 +2684,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2670 SH_PFC_PIN_GROUP(du_rgb888), 2684 SH_PFC_PIN_GROUP(du_rgb888),
2671 SH_PFC_PIN_GROUP(du_clk_out_0), 2685 SH_PFC_PIN_GROUP(du_clk_out_0),
2672 SH_PFC_PIN_GROUP(du_clk_out_1), 2686 SH_PFC_PIN_GROUP(du_clk_out_1),
2673 SH_PFC_PIN_GROUP(du_sync_1), 2687 SH_PFC_PIN_GROUP(du_sync),
2674 SH_PFC_PIN_GROUP(du_cde_disp), 2688 SH_PFC_PIN_GROUP(du_cde_disp),
2675 SH_PFC_PIN_GROUP(du0_clk_in), 2689 SH_PFC_PIN_GROUP(du0_clk_in),
2676 SH_PFC_PIN_GROUP(du1_clk_in), 2690 SH_PFC_PIN_GROUP(du1_clk_in),
2691 SH_PFC_PIN_GROUP(du1_clk_in_b),
2692 SH_PFC_PIN_GROUP(du1_clk_in_c),
2677 SH_PFC_PIN_GROUP(eth_link), 2693 SH_PFC_PIN_GROUP(eth_link),
2678 SH_PFC_PIN_GROUP(eth_magic), 2694 SH_PFC_PIN_GROUP(eth_magic),
2679 SH_PFC_PIN_GROUP(eth_mdio), 2695 SH_PFC_PIN_GROUP(eth_mdio),
@@ -2805,7 +2821,7 @@ static const char * const du_groups[] = {
2805 "du_rgb888", 2821 "du_rgb888",
2806 "du_clk_out_0", 2822 "du_clk_out_0",
2807 "du_clk_out_1", 2823 "du_clk_out_1",
2808 "du_sync_1", 2824 "du_sync",
2809 "du_cde_disp", 2825 "du_cde_disp",
2810}; 2826};
2811 2827
@@ -2815,6 +2831,8 @@ static const char * const du0_groups[] = {
2815 2831
2816static const char * const du1_groups[] = { 2832static const char * const du1_groups[] = {
2817 "du1_clk_in", 2833 "du1_clk_in",
2834 "du1_clk_in_b",
2835 "du1_clk_in_c",
2818}; 2836};
2819 2837
2820static const char * const eth_groups[] = { 2838static const char * const eth_groups[] = {
@@ -2840,20 +2858,29 @@ static const char * const mmc_groups[] = {
2840 2858
2841static const char * const msiof0_groups[] = { 2859static const char * const msiof0_groups[] = {
2842 "msiof0_clk", 2860 "msiof0_clk",
2843 "msiof0_ctrl", 2861 "msiof0_sync",
2844 "msiof0_data", 2862 "msiof0_ss1",
2863 "msiof0_ss2",
2864 "msiof0_rx",
2865 "msiof0_tx",
2845}; 2866};
2846 2867
2847static const char * const msiof1_groups[] = { 2868static const char * const msiof1_groups[] = {
2848 "msiof1_clk", 2869 "msiof1_clk",
2849 "msiof1_ctrl", 2870 "msiof1_sync",
2850 "msiof1_data", 2871 "msiof1_ss1",
2872 "msiof1_ss2",
2873 "msiof1_rx",
2874 "msiof1_tx",
2851}; 2875};
2852 2876
2853static const char * const msiof2_groups[] = { 2877static const char * const msiof2_groups[] = {
2854 "msiof2_clk", 2878 "msiof2_clk",
2855 "msiof2_ctrl", 2879 "msiof2_sync",
2856 "msiof2_data", 2880 "msiof2_ss1",
2881 "msiof2_ss2",
2882 "msiof2_rx",
2883 "msiof2_tx",
2857}; 2884};
2858 2885
2859static const char * const scif0_groups[] = { 2886static const char * const scif0_groups[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index cc097b693820..9f66a5025db0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -2118,17 +2118,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
2118 SH_PFC_FUNCTION(usb1), 2118 SH_PFC_FUNCTION(usb1),
2119}; 2119};
2120 2120
2121#undef PORTCR
2122#define PORTCR(nr, reg) \
2123 { \
2124 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2125 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2126 PORT##nr##_FN0, PORT##nr##_FN1, \
2127 PORT##nr##_FN2, PORT##nr##_FN3, \
2128 PORT##nr##_FN4, PORT##nr##_FN5, \
2129 PORT##nr##_FN6, PORT##nr##_FN7 } \
2130 }
2131
2132static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2121static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2133 PORTCR(0, 0xE6051000), /* PORT0CR */ 2122 PORTCR(0, 0xE6051000), /* PORT0CR */
2134 PORTCR(1, 0xE6051001), /* PORT1CR */ 2123 PORTCR(1, 0xE6051001), /* PORT1CR */
@@ -2585,7 +2574,7 @@ static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2585 &sh7372_portcr_offsets[i]; 2574 &sh7372_portcr_offsets[i];
2586 2575
2587 if (pin <= group->end_pin) 2576 if (pin <= group->end_pin)
2588 return pfc->window->virt + group->offset + pin; 2577 return pfc->windows->virt + group->offset + pin;
2589 } 2578 }
2590 2579
2591 return NULL; 2580 return NULL;
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 7e278a97e411..dc7c7fb33805 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3138,16 +3138,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
3138 SH_PFC_FUNCTION(usb), 3138 SH_PFC_FUNCTION(usb),
3139}; 3139};
3140 3140
3141#undef PORTCR
3142#define PORTCR(nr, reg) \
3143 { \
3144 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3145 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3146 PORT##nr##_FN0, PORT##nr##_FN1, \
3147 PORT##nr##_FN2, PORT##nr##_FN3, \
3148 PORT##nr##_FN4, PORT##nr##_FN5, \
3149 PORT##nr##_FN6, PORT##nr##_FN7 } \
3150 }
3151static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3141static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3152 PORTCR(0, 0xe6050000), /* PORT0CR */ 3142 PORTCR(0, 0xe6050000), /* PORT0CR */
3153 PORTCR(1, 0xe6050001), /* PORT1CR */ 3143 PORTCR(1, 0xe6050001), /* PORT1CR */
@@ -3661,38 +3651,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3661}; 3651};
3662 3652
3663static const struct pinmux_irq pinmux_irqs[] = { 3653static const struct pinmux_irq pinmux_irqs[] = {
3664 PINMUX_IRQ(irq_pin(19), 9),
3665 PINMUX_IRQ(irq_pin(1), 10),
3666 PINMUX_IRQ(irq_pin(0), 11), 3654 PINMUX_IRQ(irq_pin(0), 11),
3655 PINMUX_IRQ(irq_pin(1), 10),
3656 PINMUX_IRQ(irq_pin(2), 149),
3657 PINMUX_IRQ(irq_pin(3), 224),
3658 PINMUX_IRQ(irq_pin(4), 159),
3659 PINMUX_IRQ(irq_pin(5), 227),
3660 PINMUX_IRQ(irq_pin(6), 147),
3661 PINMUX_IRQ(irq_pin(7), 150),
3662 PINMUX_IRQ(irq_pin(8), 223),
3663 PINMUX_IRQ(irq_pin(9), 56, 308),
3664 PINMUX_IRQ(irq_pin(10), 54),
3665 PINMUX_IRQ(irq_pin(11), 238),
3666 PINMUX_IRQ(irq_pin(12), 156),
3667 PINMUX_IRQ(irq_pin(13), 239),
3668 PINMUX_IRQ(irq_pin(14), 251),
3669 PINMUX_IRQ(irq_pin(15), 0),
3670 PINMUX_IRQ(irq_pin(16), 249),
3671 PINMUX_IRQ(irq_pin(17), 234),
3667 PINMUX_IRQ(irq_pin(18), 13), 3672 PINMUX_IRQ(irq_pin(18), 13),
3673 PINMUX_IRQ(irq_pin(19), 9),
3668 PINMUX_IRQ(irq_pin(20), 14), 3674 PINMUX_IRQ(irq_pin(20), 14),
3669 PINMUX_IRQ(irq_pin(21), 15), 3675 PINMUX_IRQ(irq_pin(21), 15),
3670 PINMUX_IRQ(irq_pin(31), 26),
3671 PINMUX_IRQ(irq_pin(30), 27),
3672 PINMUX_IRQ(irq_pin(29), 28),
3673 PINMUX_IRQ(irq_pin(22), 40), 3676 PINMUX_IRQ(irq_pin(22), 40),
3674 PINMUX_IRQ(irq_pin(23), 53), 3677 PINMUX_IRQ(irq_pin(23), 53),
3675 PINMUX_IRQ(irq_pin(10), 54), 3678 PINMUX_IRQ(irq_pin(24), 118),
3676 PINMUX_IRQ(irq_pin(9), 56), 3679 PINMUX_IRQ(irq_pin(25), 164),
3677 PINMUX_IRQ(irq_pin(26), 115), 3680 PINMUX_IRQ(irq_pin(26), 115),
3678 PINMUX_IRQ(irq_pin(27), 116), 3681 PINMUX_IRQ(irq_pin(27), 116),
3679 PINMUX_IRQ(irq_pin(28), 117), 3682 PINMUX_IRQ(irq_pin(28), 117),
3680 PINMUX_IRQ(irq_pin(24), 118), 3683 PINMUX_IRQ(irq_pin(29), 28),
3681 PINMUX_IRQ(irq_pin(6), 147), 3684 PINMUX_IRQ(irq_pin(30), 27),
3682 PINMUX_IRQ(irq_pin(2), 149), 3685 PINMUX_IRQ(irq_pin(31), 26),
3683 PINMUX_IRQ(irq_pin(7), 150),
3684 PINMUX_IRQ(irq_pin(12), 156),
3685 PINMUX_IRQ(irq_pin(4), 159),
3686 PINMUX_IRQ(irq_pin(25), 164),
3687 PINMUX_IRQ(irq_pin(8), 223),
3688 PINMUX_IRQ(irq_pin(3), 224),
3689 PINMUX_IRQ(irq_pin(5), 227),
3690 PINMUX_IRQ(irq_pin(17), 234),
3691 PINMUX_IRQ(irq_pin(11), 238),
3692 PINMUX_IRQ(irq_pin(13), 239),
3693 PINMUX_IRQ(irq_pin(16), 249),
3694 PINMUX_IRQ(irq_pin(14), 251),
3695 PINMUX_IRQ(irq_pin(9), 308),
3696}; 3686};
3697 3687
3698/* ----------------------------------------------------------------------------- 3688/* -----------------------------------------------------------------------------
@@ -3702,7 +3692,7 @@ static const struct pinmux_irq pinmux_irqs[] = {
3702static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) 3692static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
3703{ 3693{
3704 struct sh_pfc *pfc = reg->reg_data; 3694 struct sh_pfc *pfc = reg->reg_data;
3705 void __iomem *addr = pfc->window[1].virt + 4; 3695 void __iomem *addr = pfc->windows[1].virt + 4;
3706 unsigned long flags; 3696 unsigned long flags;
3707 u32 value; 3697 u32 value;
3708 3698
@@ -3735,7 +3725,7 @@ static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
3735static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) 3725static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
3736{ 3726{
3737 struct sh_pfc *pfc = reg->reg_data; 3727 struct sh_pfc *pfc = reg->reg_data;
3738 void __iomem *addr = pfc->window[1].virt + 4; 3728 void __iomem *addr = pfc->windows[1].virt + 4;
3739 unsigned long flags; 3729 unsigned long flags;
3740 u32 value; 3730 u32 value;
3741 3731
@@ -3794,7 +3784,7 @@ static const unsigned int sh73a0_portcr_offsets[] = {
3794 3784
3795static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 3785static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3796{ 3786{
3797 void __iomem *addr = pfc->window->virt 3787 void __iomem *addr = pfc->windows->virt
3798 + sh73a0_portcr_offsets[pin >> 5] + pin; 3788 + sh73a0_portcr_offsets[pin >> 5] + pin;
3799 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; 3789 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3800 3790
@@ -3812,7 +3802,7 @@ static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3812static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 3802static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3813 unsigned int bias) 3803 unsigned int bias)
3814{ 3804{
3815 void __iomem *addr = pfc->window->virt 3805 void __iomem *addr = pfc->windows->virt
3816 + sh73a0_portcr_offsets[pin >> 5] + pin; 3806 + sh73a0_portcr_offsets[pin >> 5] + pin;
3817 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; 3807 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3818 3808
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 11bd0d970a52..e17ccab54f2d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -94,11 +94,11 @@ struct pinmux_data_reg {
94 94
95struct pinmux_irq { 95struct pinmux_irq {
96 int irq; 96 int irq;
97 unsigned short *gpios; 97 short *gpios;
98}; 98};
99 99
100#define PINMUX_IRQ(irq_nr, ids...) \ 100#define PINMUX_IRQ(irq_nr, ids...) \
101 { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ 101 { .irq = irq_nr, .gpios = (short []) { ids, -1 } }
102 102
103struct pinmux_range { 103struct pinmux_range {
104 u16 begin; 104 u16 begin;
@@ -304,8 +304,7 @@ struct sh_pfc_soc_info {
304#define PORTCR(nr, reg) \ 304#define PORTCR(nr, reg) \
305 { \ 305 { \
306 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ 306 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
307 _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ 307 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
308 PORT##nr##_IN_PU, PORT##nr##_OUT), \
309 PORT##nr##_FN0, PORT##nr##_FN1, \ 308 PORT##nr##_FN0, PORT##nr##_FN1, \
310 PORT##nr##_FN2, PORT##nr##_FN3, \ 309 PORT##nr##_FN2, PORT##nr##_FN3, \
311 PORT##nr##_FN4, PORT##nr##_FN5, \ 310 PORT##nr##_FN4, PORT##nr##_FN5, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 19:09:54 -0500