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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-09 03:08:04 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-09 03:08:04 -0400
commitde390bba797aa9a554bc1769b6a8771605854d79 (patch)
treece95610d4a70ec0a7307a30cfd1a66fdf0c901ab /drivers/pinctrl
parent50e0d10232db05c6776afcf6098459bff47e8b15 (diff)
parent382fc33b4a04e2dde89b4c69a6880e0c7d9761e2 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle: "This is the MIPS update for 3.7. A fair chunk of them are platform updates to the Cavium Octeon SOC (which involves machine generated header files of considerable size), Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx platforms. Support for the commercial MIPS simulator MIPSsim has been removed as MIPS Technologies is shifting away from this product and Qemu is offering various more powerful platforms. The generic MIPS code can now also probe for no-execute / write-only TLB features implemented without the full SmartMIPS extension as permitted by the latest MIPS processor architecture. Lots of small changes to generic code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits) MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x MIPS: BCM63XX: Properly handle mac address octet overflow MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user. MIPS: Replace `-' in defconfig filename wth `_' for consistency. MIPS: Wire kcmp syscall. MIPS: MIPSsim: Remove the MIPSsim platform. MIPS: NOTIFY_RESUME is not needed in TIF masks MIPS: Merge the identical "return from syscall" per-ABI code MIPS: Unobfuscate _TIF..._MASK MIPS: Prevent hitting do_notify_resume() with !user_mode(regs). MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. MIPS: Add base architecture support for RI and XI. MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. MIPS: uasm: Add INS and EXT instructions. MIPS: Avoid pipeline stalls on some MIPS32R2 cores. MIPS: Make VPE count to be one-based. MIPS: Add new end of interrupt functionality for GIC. MIPS: Add EIC support for GIC. MIPS: Code clean-ups for the GIC. ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig16
-rw-r--r--drivers/pinctrl/Makefile3
-rw-r--r--drivers/pinctrl/pinctrl-falcon.c468
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.c342
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.h194
-rw-r--r--drivers/pinctrl/pinctrl-xway.c781
6 files changed, 1804 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 33e3df9e39ca..7bf914df6e91 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -68,10 +68,21 @@ config PINCTRL_IMX6Q
68 help 68 help
69 Say Y here to enable the imx6q pinctrl driver 69 Say Y here to enable the imx6q pinctrl driver
70 70
71config PINCTRL_LANTIQ
72 bool
73 depends on LANTIQ
74 select PINMUX
75 select PINCONF
76
71config PINCTRL_PXA3xx 77config PINCTRL_PXA3xx
72 bool 78 bool
73 select PINMUX 79 select PINMUX
74 80
81config PINCTRL_FALCON
82 bool
83 depends on SOC_FALCON
84 depends on PINCTRL_LANTIQ
85
75config PINCTRL_MMP2 86config PINCTRL_MMP2
76 bool "MMP2 pin controller driver" 87 bool "MMP2 pin controller driver"
77 depends on ARCH_MMP 88 depends on ARCH_MMP
@@ -199,6 +210,11 @@ config PINCTRL_ARMADA_XP
199 210
200source "drivers/pinctrl/spear/Kconfig" 211source "drivers/pinctrl/spear/Kconfig"
201 212
213config PINCTRL_XWAY
214 bool
215 depends on SOC_TYPE_XWAY
216 depends on PINCTRL_LANTIQ
217
202endmenu 218endmenu
203 219
204endif 220endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f162e0196300..f395ba5cec25 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
16obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o 16obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
17obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 17obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
18obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o 18obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
19obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o 20obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
20obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 21obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
21obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 22obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
@@ -40,5 +41,7 @@ obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
40obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o 41obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
41obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o 42obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
42obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o 43obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
44obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
45obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
43 46
44obj-$(CONFIG_PLAT_SPEAR) += spear/ 47obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
new file mode 100644
index 000000000000..ee7305903470
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -0,0 +1,468 @@
1/*
2 * linux/drivers/pinctrl/pinmux-falcon.c
3 * based on linux/drivers/pinctrl/pinmux-pxa910.c
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
8 *
9 * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
10 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
11 */
12
13#include <linux/gpio.h>
14#include <linux/interrupt.h>
15#include <linux/slab.h>
16#include <linux/export.h>
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_platform.h>
21#include <linux/of_address.h>
22#include <linux/of_gpio.h>
23#include <linux/platform_device.h>
24
25#include "pinctrl-lantiq.h"
26
27#include <lantiq_soc.h>
28
29/* Multiplexer Control Register */
30#define LTQ_PADC_MUX(x) (x * 0x4)
31/* Pull Up Enable Register */
32#define LTQ_PADC_PUEN 0x80
33/* Pull Down Enable Register */
34#define LTQ_PADC_PDEN 0x84
35/* Slew Rate Control Register */
36#define LTQ_PADC_SRC 0x88
37/* Drive Current Control Register */
38#define LTQ_PADC_DCC 0x8C
39/* Pad Control Availability Register */
40#define LTQ_PADC_AVAIL 0xF0
41
42#define pad_r32(p, reg) ltq_r32(p + reg)
43#define pad_w32(p, val, reg) ltq_w32(val, p + reg)
44#define pad_w32_mask(c, clear, set, reg) \
45 pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
46
47#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
48
49#define PORTS 5
50#define PINS 32
51#define PORT(x) (x / PINS)
52#define PORT_PIN(x) (x % PINS)
53
54#define MFP_FALCON(a, f0, f1, f2, f3) \
55{ \
56 .name = #a, \
57 .pin = a, \
58 .func = { \
59 FALCON_MUX_##f0, \
60 FALCON_MUX_##f1, \
61 FALCON_MUX_##f2, \
62 FALCON_MUX_##f3, \
63 }, \
64}
65
66#define GRP_MUX(a, m, p) \
67{ \
68 .name = a, \
69 .mux = FALCON_MUX_##m, \
70 .pins = p, \
71 .npins = ARRAY_SIZE(p), \
72}
73
74enum falcon_mux {
75 FALCON_MUX_GPIO = 0,
76 FALCON_MUX_RST,
77 FALCON_MUX_NTR,
78 FALCON_MUX_MDIO,
79 FALCON_MUX_LED,
80 FALCON_MUX_SPI,
81 FALCON_MUX_ASC,
82 FALCON_MUX_I2C,
83 FALCON_MUX_HOSTIF,
84 FALCON_MUX_SLIC,
85 FALCON_MUX_JTAG,
86 FALCON_MUX_PCM,
87 FALCON_MUX_MII,
88 FALCON_MUX_PHY,
89 FALCON_MUX_NONE = 0xffff,
90};
91
92static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
93static int pad_count[PORTS];
94
95static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
96{
97 int base = bank * PINS;
98 int i;
99
100 for (i = 0; i < len; i++) {
101 /* strlen("ioXYZ") + 1 = 6 */
102 char *name = kzalloc(6, GFP_KERNEL);
103 snprintf(name, 6, "io%d", base + i);
104 d[i].number = base + i;
105 d[i].name = name;
106 }
107 pad_count[bank] = len;
108}
109
110static struct ltq_mfp_pin falcon_mfp[] = {
111 /* pin f0 f1 f2 f3 */
112 MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
113 MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
114 MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
115 MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
116 MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
117 MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE),
118 MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
119 MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
120 MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
121 MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
122 MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
123 MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
124 MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
125 MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
126 MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
127 MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
128 MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
129 MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
130 MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
131 MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
132 MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
133 MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
134 MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
135 MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
136 MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
137 MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
138 MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
139 MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
140 MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
141 MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
142 MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
143 MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
144 MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
145 MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
146 MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
147 MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
148 MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
149 MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
150 MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
151 MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
152 MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
153 MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
154 MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
155 MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
156 MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
157 MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
158 MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
159 MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
160 MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
161 MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
162 MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
163 MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
164 MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
165 MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
166};
167
168static const unsigned pins_por[] = {GPIO0};
169static const unsigned pins_ntr[] = {GPIO4};
170static const unsigned pins_ntr8k[] = {GPIO5};
171static const unsigned pins_hrst[] = {GPIO6};
172static const unsigned pins_mdio[] = {GPIO7, GPIO8};
173static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11,
174 GPIO12, GPIO13, GPIO14};
175static const unsigned pins_asc0[] = {GPIO32, GPIO33};
176static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
177static const unsigned pins_spi_cs0[] = {GPIO37};
178static const unsigned pins_spi_cs1[] = {GPIO38};
179static const unsigned pins_i2c[] = {GPIO39, GPIO40};
180static const unsigned pins_jtag[] = {GPIO41};
181static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
182static const unsigned pins_pcm[] = {GPIO44, GPIO45};
183static const unsigned pins_asc1[] = {GPIO44, GPIO45};
184
185static struct ltq_pin_group falcon_grps[] = {
186 GRP_MUX("por", RST, pins_por),
187 GRP_MUX("ntr", NTR, pins_ntr),
188 GRP_MUX("ntr8k", NTR, pins_ntr8k),
189 GRP_MUX("hrst", RST, pins_hrst),
190 GRP_MUX("mdio", MDIO, pins_mdio),
191 GRP_MUX("bootled", LED, pins_bled),
192 GRP_MUX("asc0", ASC, pins_asc0),
193 GRP_MUX("spi", SPI, pins_spi),
194 GRP_MUX("spi cs0", SPI, pins_spi_cs0),
195 GRP_MUX("spi cs1", SPI, pins_spi_cs1),
196 GRP_MUX("i2c", I2C, pins_i2c),
197 GRP_MUX("jtag", JTAG, pins_jtag),
198 GRP_MUX("slic", SLIC, pins_slic),
199 GRP_MUX("pcm", PCM, pins_pcm),
200 GRP_MUX("asc1", ASC, pins_asc1),
201};
202
203static const char * const ltq_rst_grps[] = {"por", "hrst"};
204static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"};
205static const char * const ltq_mdio_grps[] = {"mdio"};
206static const char * const ltq_bled_grps[] = {"bootled"};
207static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
208static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
209static const char * const ltq_i2c_grps[] = {"i2c"};
210static const char * const ltq_jtag_grps[] = {"jtag"};
211static const char * const ltq_slic_grps[] = {"slic"};
212static const char * const ltq_pcm_grps[] = {"pcm"};
213
214static struct ltq_pmx_func falcon_funcs[] = {
215 {"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
216 {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
217 {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
218 {"led", ARRAY_AND_SIZE(ltq_bled_grps)},
219 {"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
220 {"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
221 {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
222 {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
223 {"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
224 {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
225};
226
227
228
229
230/* --------- pinconf related code --------- */
231static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
232 unsigned group, unsigned long *config)
233{
234 return -ENOTSUPP;
235}
236
237static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
238 unsigned group, unsigned long config)
239{
240 return -ENOTSUPP;
241}
242
243static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
244 unsigned pin, unsigned long *config)
245{
246 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
247 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
248 void __iomem *mem = info->membase[PORT(pin)];
249
250 switch (param) {
251 case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
252 *config = LTQ_PINCONF_PACK(param,
253 !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
254 break;
255
256 case LTQ_PINCONF_PARAM_SLEW_RATE:
257 *config = LTQ_PINCONF_PACK(param,
258 !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
259 break;
260
261 case LTQ_PINCONF_PARAM_PULL:
262 if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
263 *config = LTQ_PINCONF_PACK(param, 1);
264 else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
265 *config = LTQ_PINCONF_PACK(param, 2);
266 else
267 *config = LTQ_PINCONF_PACK(param, 0);
268
269 break;
270
271 default:
272 return -ENOTSUPP;
273 }
274
275 return 0;
276}
277
278static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
279 unsigned pin, unsigned long config)
280{
281 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
282 int arg = LTQ_PINCONF_UNPACK_ARG(config);
283 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
284 void __iomem *mem = info->membase[PORT(pin)];
285 u32 reg;
286
287 switch (param) {
288 case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
289 reg = LTQ_PADC_DCC;
290 break;
291
292 case LTQ_PINCONF_PARAM_SLEW_RATE:
293 reg = LTQ_PADC_SRC;
294 break;
295
296 case LTQ_PINCONF_PARAM_PULL:
297 if (arg == 1)
298 reg = LTQ_PADC_PDEN;
299 else
300 reg = LTQ_PADC_PUEN;
301 break;
302
303 default:
304 pr_err("%s: Invalid config param %04x\n",
305 pinctrl_dev_get_name(pctrldev), param);
306 return -ENOTSUPP;
307 }
308
309 pad_w32(mem, BIT(PORT_PIN(pin)), reg);
310 if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
311 return -ENOTSUPP;
312 return 0;
313}
314
315static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
316 struct seq_file *s, unsigned offset)
317{
318}
319
320static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
321 struct seq_file *s, unsigned selector)
322{
323}
324
325struct pinconf_ops falcon_pinconf_ops = {
326 .pin_config_get = falcon_pinconf_get,
327 .pin_config_set = falcon_pinconf_set,
328 .pin_config_group_get = falcon_pinconf_group_get,
329 .pin_config_group_set = falcon_pinconf_group_set,
330 .pin_config_dbg_show = falcon_pinconf_dbg_show,
331 .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
332};
333
334static struct pinctrl_desc falcon_pctrl_desc = {
335 .owner = THIS_MODULE,
336 .pins = falcon_pads,
337 .confops = &falcon_pinconf_ops,
338};
339
340static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
341 int mfp, int mux)
342{
343 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
344 int port = PORT(info->mfp[mfp].pin);
345
346 if ((port >= PORTS) || (!info->membase[port]))
347 return -ENODEV;
348
349 pad_w32(info->membase[port], mux,
350 LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
351 return 0;
352}
353
354static const struct ltq_cfg_param falcon_cfg_params[] = {
355 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
356 {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
357 {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
358};
359
360static struct ltq_pinmux_info falcon_info = {
361 .desc = &falcon_pctrl_desc,
362 .apply_mux = falcon_mux_apply,
363};
364
365
366
367
368/* --------- register the pinctrl layer --------- */
369
370int pinctrl_falcon_get_range_size(int id)
371{
372 u32 avail;
373
374 if ((id >= PORTS) || (!falcon_info.membase[id]))
375 return -EINVAL;
376
377 avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
378
379 return fls(avail);
380}
381
382void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
383{
384 pinctrl_add_gpio_range(falcon_info.pctrl, range);
385}
386
387static int pinctrl_falcon_probe(struct platform_device *pdev)
388{
389 struct device_node *np;
390 int pad_count = 0;
391 int ret = 0;
392
393 /* load and remap the pad resources of the different banks */
394 for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
395 struct platform_device *ppdev = of_find_device_by_node(np);
396 const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
397 struct resource res;
398 u32 avail;
399 int pins;
400
401 if (!ppdev) {
402 dev_err(&pdev->dev, "failed to find pad pdev\n");
403 continue;
404 }
405 if (!bank || *bank >= PORTS)
406 continue;
407 if (of_address_to_resource(np, 0, &res))
408 continue;
409 falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
410 if (IS_ERR(falcon_info.clk[*bank])) {
411 dev_err(&ppdev->dev, "failed to get clock\n");
412 return PTR_ERR(falcon_info.clk[*bank]);
413 }
414 falcon_info.membase[*bank] =
415 devm_request_and_ioremap(&pdev->dev, &res);
416 if (!falcon_info.membase[*bank]) {
417 dev_err(&pdev->dev,
418 "Failed to remap memory for bank %d\n",
419 *bank);
420 return -ENOMEM;
421 }
422 avail = pad_r32(falcon_info.membase[*bank],
423 LTQ_PADC_AVAIL);
424 pins = fls(avail);
425 lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
426 pad_count += pins;
427 clk_enable(falcon_info.clk[*bank]);
428 dev_dbg(&pdev->dev, "found %s with %d pads\n",
429 res.name, pins);
430 }
431 dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
432 falcon_pctrl_desc.name = dev_name(&pdev->dev);
433 falcon_pctrl_desc.npins = pad_count;
434
435 falcon_info.mfp = falcon_mfp;
436 falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
437 falcon_info.grps = falcon_grps;
438 falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
439 falcon_info.funcs = falcon_funcs;
440 falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
441
442 ret = ltq_pinctrl_register(pdev, &falcon_info);
443 if (!ret)
444 dev_info(&pdev->dev, "Init done\n");
445 return ret;
446}
447
448static const struct of_device_id falcon_match[] = {
449 { .compatible = "lantiq,pinctrl-falcon" },
450 {},
451};
452MODULE_DEVICE_TABLE(of, falcon_match);
453
454static struct platform_driver pinctrl_falcon_driver = {
455 .probe = pinctrl_falcon_probe,
456 .driver = {
457 .name = "pinctrl-falcon",
458 .owner = THIS_MODULE,
459 .of_match_table = falcon_match,
460 },
461};
462
463int __init pinctrl_falcon_init(void)
464{
465 return platform_driver_register(&pinctrl_falcon_driver);
466}
467
468core_initcall_sync(pinctrl_falcon_init);
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
new file mode 100644
index 000000000000..07ba7682cf22
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -0,0 +1,342 @@
1/*
2 * linux/drivers/pinctrl/pinctrl-lantiq.c
3 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 *
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
10 */
11
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/of.h>
18
19#include "pinctrl-lantiq.h"
20
21static int ltq_get_group_count(struct pinctrl_dev *pctrldev)
22{
23 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
24 return info->num_grps;
25}
26
27static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev,
28 unsigned selector)
29{
30 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
31 if (selector >= info->num_grps)
32 return NULL;
33 return info->grps[selector].name;
34}
35
36static int ltq_get_group_pins(struct pinctrl_dev *pctrldev,
37 unsigned selector,
38 const unsigned **pins,
39 unsigned *num_pins)
40{
41 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
42 if (selector >= info->num_grps)
43 return -EINVAL;
44 *pins = info->grps[selector].pins;
45 *num_pins = info->grps[selector].npins;
46 return 0;
47}
48
49void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
50 struct pinctrl_map *map, unsigned num_maps)
51{
52 int i;
53
54 for (i = 0; i < num_maps; i++)
55 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
56 kfree(map[i].data.configs.configs);
57 kfree(map);
58}
59
60static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
61 struct seq_file *s,
62 unsigned offset)
63{
64 seq_printf(s, " %s", dev_name(pctldev->dev));
65}
66
67static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
68 struct device_node *np,
69 struct pinctrl_map **map)
70{
71 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
72 unsigned long configs[3];
73 unsigned num_configs = 0;
74 struct property *prop;
75 const char *group, *pin;
76 const char *function;
77 int ret, i;
78
79 ret = of_property_read_string(np, "lantiq,function", &function);
80 if (!ret) {
81 of_property_for_each_string(np, "lantiq,groups", prop, group) {
82 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
83 (*map)->name = function;
84 (*map)->data.mux.group = group;
85 (*map)->data.mux.function = function;
86 (*map)++;
87 }
88 if (of_find_property(np, "lantiq,pins", NULL))
89 dev_err(pctldev->dev,
90 "%s mixes pins and groups settings\n",
91 np->name);
92 return 0;
93 }
94
95 for (i = 0; i < info->num_params; i++) {
96 u32 val;
97 int ret = of_property_read_u32(np,
98 info->params[i].property, &val);
99 if (!ret)
100 configs[num_configs++] =
101 LTQ_PINCONF_PACK(info->params[i].param,
102 val);
103 }
104
105 if (!num_configs)
106 return -EINVAL;
107
108 of_property_for_each_string(np, "lantiq,pins", prop, pin) {
109 (*map)->data.configs.configs = kmemdup(configs,
110 num_configs * sizeof(unsigned long),
111 GFP_KERNEL);
112 (*map)->type = PIN_MAP_TYPE_CONFIGS_PIN;
113 (*map)->name = pin;
114 (*map)->data.configs.group_or_pin = pin;
115 (*map)->data.configs.num_configs = num_configs;
116 (*map)++;
117 }
118 return 0;
119}
120
121static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
122{
123 int ret;
124
125 ret = of_property_count_strings(np, "lantiq,groups");
126 if (ret < 0)
127 ret = of_property_count_strings(np, "lantiq,pins");
128 return ret;
129}
130
131int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
132 struct device_node *np_config,
133 struct pinctrl_map **map,
134 unsigned *num_maps)
135{
136 struct pinctrl_map *tmp;
137 struct device_node *np;
138 int ret;
139
140 *num_maps = 0;
141 for_each_child_of_node(np_config, np)
142 *num_maps += ltq_pinctrl_dt_subnode_size(np);
143 *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
144 if (!*map)
145 return -ENOMEM;
146 tmp = *map;
147
148 for_each_child_of_node(np_config, np) {
149 ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
150 if (ret < 0) {
151 ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps);
152 return ret;
153 }
154 }
155 return 0;
156}
157
158static struct pinctrl_ops ltq_pctrl_ops = {
159 .get_groups_count = ltq_get_group_count,
160 .get_group_name = ltq_get_group_name,
161 .get_group_pins = ltq_get_group_pins,
162 .pin_dbg_show = ltq_pinctrl_pin_dbg_show,
163 .dt_node_to_map = ltq_pinctrl_dt_node_to_map,
164 .dt_free_map = ltq_pinctrl_dt_free_map,
165};
166
167static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev)
168{
169 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
170
171 return info->num_funcs;
172}
173
174static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev,
175 unsigned selector)
176{
177 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
178
179 if (selector >= info->num_funcs)
180 return NULL;
181
182 return info->funcs[selector].name;
183}
184
185static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev,
186 unsigned func,
187 const char * const **groups,
188 unsigned * const num_groups)
189{
190 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
191
192 *groups = info->funcs[func].groups;
193 *num_groups = info->funcs[func].num_groups;
194
195 return 0;
196}
197
198/* Return function number. If failure, return negative value. */
199static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux)
200{
201 int i;
202 for (i = 0; i < LTQ_MAX_MUX; i++) {
203 if (mfp->func[i] == mux)
204 break;
205 }
206 if (i >= LTQ_MAX_MUX)
207 return -EINVAL;
208 return i;
209}
210
211/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */
212static int match_mfp(const struct ltq_pinmux_info *info, int pin)
213{
214 int i;
215 for (i = 0; i < info->num_mfp; i++) {
216 if (info->mfp[i].pin == pin)
217 return i;
218 }
219 return -1;
220}
221
222/* check whether current pin configuration is valid. Negative for failure */
223static int match_group_mux(const struct ltq_pin_group *grp,
224 const struct ltq_pinmux_info *info,
225 unsigned mux)
226{
227 int i, pin, ret = 0;
228 for (i = 0; i < grp->npins; i++) {
229 pin = match_mfp(info, grp->pins[i]);
230 if (pin < 0) {
231 dev_err(info->dev, "could not find mfp for pin %d\n",
232 grp->pins[i]);
233 return -EINVAL;
234 }
235 ret = match_mux(&info->mfp[pin], mux);
236 if (ret < 0) {
237 dev_err(info->dev, "Can't find mux %d on pin%d\n",
238 mux, pin);
239 break;
240 }
241 }
242 return ret;
243}
244
245static int ltq_pmx_enable(struct pinctrl_dev *pctrldev,
246 unsigned func,
247 unsigned group)
248{
249 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
250 const struct ltq_pin_group *pin_grp = &info->grps[group];
251 int i, pin, pin_func, ret;
252
253 if (!pin_grp->npins ||
254 (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) {
255 dev_err(info->dev, "Failed to set the pin group: %s\n",
256 info->grps[group].name);
257 return -EINVAL;
258 }
259 for (i = 0; i < pin_grp->npins; i++) {
260 pin = match_mfp(info, pin_grp->pins[i]);
261 if (pin < 0) {
262 dev_err(info->dev, "could not find mfp for pin %d\n",
263 pin_grp->pins[i]);
264 return -EINVAL;
265 }
266 pin_func = match_mux(&info->mfp[pin], pin_grp->mux);
267 ret = info->apply_mux(pctrldev, pin, pin_func);
268 if (ret) {
269 dev_err(info->dev,
270 "failed to apply mux %d for pin %d\n",
271 pin_func, pin);
272 return ret;
273 }
274 }
275 return 0;
276}
277
278static void ltq_pmx_disable(struct pinctrl_dev *pctrldev,
279 unsigned func,
280 unsigned group)
281{
282 /*
283 * Nothing to do here. However, pinconf_check_ops() requires this
284 * callback to be defined.
285 */
286}
287
288static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
289 struct pinctrl_gpio_range *range,
290 unsigned pin)
291{
292 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
293 int mfp = match_mfp(info, pin + (range->id * 32));
294 int pin_func;
295
296 if (mfp < 0) {
297 dev_err(info->dev, "could not find mfp for pin %d\n", pin);
298 return -EINVAL;
299 }
300
301 pin_func = match_mux(&info->mfp[mfp], 0);
302 if (pin_func < 0) {
303 dev_err(info->dev, "No GPIO function on pin%d\n", mfp);
304 return -EINVAL;
305 }
306
307 return info->apply_mux(pctrldev, mfp, pin_func);
308}
309
310static struct pinmux_ops ltq_pmx_ops = {
311 .get_functions_count = ltq_pmx_func_count,
312 .get_function_name = ltq_pmx_func_name,
313 .get_function_groups = ltq_pmx_get_groups,
314 .enable = ltq_pmx_enable,
315 .disable = ltq_pmx_disable,
316 .gpio_request_enable = ltq_pmx_gpio_request_enable,
317};
318
319/*
320 * allow different socs to register with the generic part of the lanti
321 * pinctrl code
322 */
323int ltq_pinctrl_register(struct platform_device *pdev,
324 struct ltq_pinmux_info *info)
325{
326 struct pinctrl_desc *desc;
327
328 if (!info)
329 return -EINVAL;
330 desc = info->desc;
331 desc->pctlops = &ltq_pctrl_ops;
332 desc->pmxops = &ltq_pmx_ops;
333 info->dev = &pdev->dev;
334
335 info->pctrl = pinctrl_register(desc, &pdev->dev, info);
336 if (!info->pctrl) {
337 dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n");
338 return -EINVAL;
339 }
340 platform_set_drvdata(pdev, info);
341 return 0;
342}
diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h
new file mode 100644
index 000000000000..4419d32a0ade
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-lantiq.h
@@ -0,0 +1,194 @@
1/*
2 * linux/drivers/pinctrl/pinctrl-lantiq.h
3 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 *
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
10 */
11
12#ifndef __PINCTRL_LANTIQ_H
13
14#include <linux/clkdev.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/pinctrl/machine.h>
20
21#include "core.h"
22
23#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
24
25#define LTQ_MAX_MUX 4
26#define MFPR_FUNC_MASK 0x3
27
28#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))
29#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
30#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
31
32enum ltq_pinconf_param {
33 LTQ_PINCONF_PARAM_PULL,
34 LTQ_PINCONF_PARAM_OPEN_DRAIN,
35 LTQ_PINCONF_PARAM_DRIVE_CURRENT,
36 LTQ_PINCONF_PARAM_SLEW_RATE,
37};
38
39struct ltq_cfg_param {
40 const char *property;
41 enum ltq_pinconf_param param;
42};
43
44struct ltq_mfp_pin {
45 const char *name;
46 const unsigned int pin;
47 const unsigned short func[LTQ_MAX_MUX];
48};
49
50struct ltq_pin_group {
51 const char *name;
52 const unsigned mux;
53 const unsigned *pins;
54 const unsigned npins;
55};
56
57struct ltq_pmx_func {
58 const char *name;
59 const char * const *groups;
60 const unsigned num_groups;
61};
62
63struct ltq_pinmux_info {
64 struct device *dev;
65 struct pinctrl_dev *pctrl;
66
67 /* we need to manage up to 5 pad controllers */
68 void __iomem *membase[5];
69
70 /* the descriptor for the subsystem */
71 struct pinctrl_desc *desc;
72
73 /* we expose our pads to the subsystem */
74 struct pinctrl_pin_desc *pads;
75
76 /* the number of pads. this varies between socs */
77 unsigned int num_pads;
78
79 /* these are our multifunction pins */
80 const struct ltq_mfp_pin *mfp;
81 unsigned int num_mfp;
82
83 /* a number of multifunction pins can be grouped together */
84 const struct ltq_pin_group *grps;
85 unsigned int num_grps;
86
87 /* a mapping between function string and id */
88 const struct ltq_pmx_func *funcs;
89 unsigned int num_funcs;
90
91 /* the pinconf options that we are able to read from the DT */
92 const struct ltq_cfg_param *params;
93 unsigned int num_params;
94
95 /* the pad controller can have a irq mapping */
96 const unsigned *exin;
97 unsigned int num_exin;
98
99 /* we need 5 clocks max */
100 struct clk *clk[5];
101
102 /* soc specific callback used to apply muxing */
103 int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
104};
105
106enum ltq_pin {
107 GPIO0 = 0,
108 GPIO1,
109 GPIO2,
110 GPIO3,
111 GPIO4,
112 GPIO5,
113 GPIO6,
114 GPIO7,
115 GPIO8,
116 GPIO9,
117 GPIO10, /* 10 */
118 GPIO11,
119 GPIO12,
120 GPIO13,
121 GPIO14,
122 GPIO15,
123 GPIO16,
124 GPIO17,
125 GPIO18,
126 GPIO19,
127 GPIO20, /* 20 */
128 GPIO21,
129 GPIO22,
130 GPIO23,
131 GPIO24,
132 GPIO25,
133 GPIO26,
134 GPIO27,
135 GPIO28,
136 GPIO29,
137 GPIO30, /* 30 */
138 GPIO31,
139 GPIO32,
140 GPIO33,
141 GPIO34,
142 GPIO35,
143 GPIO36,
144 GPIO37,
145 GPIO38,
146 GPIO39,
147 GPIO40, /* 40 */
148 GPIO41,
149 GPIO42,
150 GPIO43,
151 GPIO44,
152 GPIO45,
153 GPIO46,
154 GPIO47,
155 GPIO48,
156 GPIO49,
157 GPIO50, /* 50 */
158 GPIO51,
159 GPIO52,
160 GPIO53,
161 GPIO54,
162 GPIO55,
163
164 GPIO64,
165 GPIO65,
166 GPIO66,
167 GPIO67,
168 GPIO68,
169 GPIO69,
170 GPIO70,
171 GPIO71,
172 GPIO72,
173 GPIO73,
174 GPIO74,
175 GPIO75,
176 GPIO76,
177 GPIO77,
178 GPIO78,
179 GPIO79,
180 GPIO80,
181 GPIO81,
182 GPIO82,
183 GPIO83,
184 GPIO84,
185 GPIO85,
186 GPIO86,
187 GPIO87,
188 GPIO88,
189};
190
191extern int ltq_pinctrl_register(struct platform_device *pdev,
192 struct ltq_pinmux_info *info);
193extern int ltq_pinctrl_unregister(struct platform_device *pdev);
194#endif /* __PINCTRL_PXA3XX_H */
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
new file mode 100644
index 000000000000..f8d917d40c92
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -0,0 +1,781 @@
1/*
2 * linux/drivers/pinctrl/pinmux-xway.c
3 * based on linux/drivers/pinctrl/pinmux-pxa910.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 *
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
10 */
11
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/of_platform.h>
15#include <linux/of_address.h>
16#include <linux/of_gpio.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/device.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/platform_device.h>
23
24#include "pinctrl-lantiq.h"
25
26#include <lantiq_soc.h>
27
28/* we have 3 1/2 banks of 16 bit each */
29#define PINS 16
30#define PORT3 3
31#define PORT(x) (x / PINS)
32#define PORT_PIN(x) (x % PINS)
33
34/* we have 2 mux bits that can be set for each pin */
35#define MUX_ALT0 0x1
36#define MUX_ALT1 0x2
37
38/*
39 * each bank has this offset apart from the 1/2 bank that is mixed into the
40 * other 3 ranges
41 */
42#define REG_OFF 0x30
43
44/* these are the offsets to our registers */
45#define GPIO_BASE(p) (REG_OFF * PORT(p))
46#define GPIO_OUT(p) GPIO_BASE(p)
47#define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
48#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
49#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
50#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
51#define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
52#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
53#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
54
55/* the 1/2 port needs special offsets for some registers */
56#define GPIO3_OD (GPIO_BASE(0) + 0x24)
57#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
58#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
59#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
60
61/* macros to help us access the registers */
62#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
63#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
64#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
65
66#define MFP_XWAY(a, f0, f1, f2, f3) \
67 { \
68 .name = #a, \
69 .pin = a, \
70 .func = { \
71 XWAY_MUX_##f0, \
72 XWAY_MUX_##f1, \
73 XWAY_MUX_##f2, \
74 XWAY_MUX_##f3, \
75 }, \
76 }
77
78#define GRP_MUX(a, m, p) \
79 { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
80
81#define FUNC_MUX(f, m) \
82 { .func = f, .mux = XWAY_MUX_##m, }
83
84#define XWAY_MAX_PIN 32
85#define XR9_MAX_PIN 56
86
87enum xway_mux {
88 XWAY_MUX_GPIO = 0,
89 XWAY_MUX_SPI,
90 XWAY_MUX_ASC,
91 XWAY_MUX_PCI,
92 XWAY_MUX_CGU,
93 XWAY_MUX_EBU,
94 XWAY_MUX_JTAG,
95 XWAY_MUX_EXIN,
96 XWAY_MUX_TDM,
97 XWAY_MUX_STP,
98 XWAY_MUX_SIN,
99 XWAY_MUX_GPT,
100 XWAY_MUX_NMI,
101 XWAY_MUX_MDIO,
102 XWAY_MUX_MII,
103 XWAY_MUX_EPHY,
104 XWAY_MUX_DFE,
105 XWAY_MUX_SDIO,
106 XWAY_MUX_NONE = 0xffff,
107};
108
109static const struct ltq_mfp_pin xway_mfp[] = {
110 /* pin f0 f1 f2 f3 */
111 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
112 MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
113 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
114 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
115 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
116 MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE),
117 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
118 MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE),
119 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
120 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
121 MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
122 MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
123 MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE),
124 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
125 MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE),
126 MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
127 MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
128 MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
129 MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
130 MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE),
131 MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE),
132 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
133 MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
134 MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
135 MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
136 MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC),
137 MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM),
138 MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC),
139 MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE),
140 MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE),
141 MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE),
142 MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
143 MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU),
144 MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU),
145 MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU),
146 MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU),
147 MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU),
148 MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
149 MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
150 MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE),
151 MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE),
152 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
153 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
154 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
155 MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN),
156 MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN),
157 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
158 MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN),
159 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
160 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
161 MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
162 MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
163 MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
164 MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
165 MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
166 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
167};
168
169static const struct ltq_mfp_pin ase_mfp[] = {
170 /* pin f0 f1 f2 f3 */
171 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
172 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
173 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
174 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
175 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
176 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
177 MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
178 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
179 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
180 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
181 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
182 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
183 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
184 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
185 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
186 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
187 MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
188 MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
189 MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
190 MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
191 MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
192 MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO),
193 MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
194 MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
195 MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII),
196 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
197 MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
198 MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII),
199 MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
200 MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
201 MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
202 MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
203};
204
205static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
206static const unsigned pins_asc0[] = {GPIO11, GPIO12};
207static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
208static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
209static const unsigned pins_nmi[] = {GPIO8};
210static const unsigned pins_mdio[] = {GPIO42, GPIO43};
211
212static const unsigned pins_ebu_a24[] = {GPIO13};
213static const unsigned pins_ebu_clk[] = {GPIO21};
214static const unsigned pins_ebu_cs1[] = {GPIO23};
215static const unsigned pins_ebu_a23[] = {GPIO24};
216static const unsigned pins_ebu_wait[] = {GPIO26};
217static const unsigned pins_ebu_a25[] = {GPIO31};
218static const unsigned pins_ebu_rdy[] = {GPIO48};
219static const unsigned pins_ebu_rd[] = {GPIO49};
220
221static const unsigned pins_nand_ale[] = {GPIO13};
222static const unsigned pins_nand_cs1[] = {GPIO23};
223static const unsigned pins_nand_cle[] = {GPIO24};
224static const unsigned pins_nand_rdy[] = {GPIO48};
225static const unsigned pins_nand_rd[] = {GPIO49};
226
227static const unsigned pins_exin0[] = {GPIO0};
228static const unsigned pins_exin1[] = {GPIO1};
229static const unsigned pins_exin2[] = {GPIO2};
230static const unsigned pins_exin3[] = {GPIO39};
231static const unsigned pins_exin4[] = {GPIO46};
232static const unsigned pins_exin5[] = {GPIO9};
233
234static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
235static const unsigned pins_spi_cs1[] = {GPIO15};
236static const unsigned pins_spi_cs2[] = {GPIO21};
237static const unsigned pins_spi_cs3[] = {GPIO13};
238static const unsigned pins_spi_cs4[] = {GPIO10};
239static const unsigned pins_spi_cs5[] = {GPIO9};
240static const unsigned pins_spi_cs6[] = {GPIO11};
241
242static const unsigned pins_gpt1[] = {GPIO28};
243static const unsigned pins_gpt2[] = {GPIO21};
244static const unsigned pins_gpt3[] = {GPIO6};
245
246static const unsigned pins_clkout0[] = {GPIO8};
247static const unsigned pins_clkout1[] = {GPIO7};
248static const unsigned pins_clkout2[] = {GPIO3};
249static const unsigned pins_clkout3[] = {GPIO2};
250
251static const unsigned pins_pci_gnt1[] = {GPIO30};
252static const unsigned pins_pci_gnt2[] = {GPIO23};
253static const unsigned pins_pci_gnt3[] = {GPIO19};
254static const unsigned pins_pci_gnt4[] = {GPIO38};
255static const unsigned pins_pci_req1[] = {GPIO29};
256static const unsigned pins_pci_req2[] = {GPIO31};
257static const unsigned pins_pci_req3[] = {GPIO3};
258static const unsigned pins_pci_req4[] = {GPIO37};
259
260static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
261static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
262static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
263static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4};
264static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2};
265
266static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10};
267static const unsigned ase_pins_spi_cs1[] = {GPIO7};
268static const unsigned ase_pins_spi_cs2[] = {GPIO15};
269static const unsigned ase_pins_spi_cs3[] = {GPIO14};
270
271static const unsigned ase_pins_exin0[] = {GPIO6};
272static const unsigned ase_pins_exin1[] = {GPIO29};
273static const unsigned ase_pins_exin2[] = {GPIO0};
274
275static const unsigned ase_pins_gpt1[] = {GPIO5};
276static const unsigned ase_pins_gpt2[] = {GPIO4};
277static const unsigned ase_pins_gpt3[] = {GPIO25};
278
279static const struct ltq_pin_group xway_grps[] = {
280 GRP_MUX("exin0", EXIN, pins_exin0),
281 GRP_MUX("exin1", EXIN, pins_exin1),
282 GRP_MUX("exin2", EXIN, pins_exin2),
283 GRP_MUX("jtag", JTAG, pins_jtag),
284 GRP_MUX("ebu a23", EBU, pins_ebu_a23),
285 GRP_MUX("ebu a24", EBU, pins_ebu_a24),
286 GRP_MUX("ebu a25", EBU, pins_ebu_a25),
287 GRP_MUX("ebu clk", EBU, pins_ebu_clk),
288 GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
289 GRP_MUX("ebu wait", EBU, pins_ebu_wait),
290 GRP_MUX("nand ale", EBU, pins_nand_ale),
291 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
292 GRP_MUX("nand cle", EBU, pins_nand_cle),
293 GRP_MUX("spi", SPI, pins_spi),
294 GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
295 GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
296 GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
297 GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
298 GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
299 GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
300 GRP_MUX("asc0", ASC, pins_asc0),
301 GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
302 GRP_MUX("stp", STP, pins_stp),
303 GRP_MUX("nmi", NMI, pins_nmi),
304 GRP_MUX("gpt1", GPT, pins_gpt1),
305 GRP_MUX("gpt2", GPT, pins_gpt2),
306 GRP_MUX("gpt3", GPT, pins_gpt3),
307 GRP_MUX("clkout0", CGU, pins_clkout0),
308 GRP_MUX("clkout1", CGU, pins_clkout1),
309 GRP_MUX("clkout2", CGU, pins_clkout2),
310 GRP_MUX("clkout3", CGU, pins_clkout3),
311 GRP_MUX("gnt1", PCI, pins_pci_gnt1),
312 GRP_MUX("gnt2", PCI, pins_pci_gnt2),
313 GRP_MUX("gnt3", PCI, pins_pci_gnt3),
314 GRP_MUX("req1", PCI, pins_pci_req1),
315 GRP_MUX("req2", PCI, pins_pci_req2),
316 GRP_MUX("req3", PCI, pins_pci_req3),
317/* xrx only */
318 GRP_MUX("nand rdy", EBU, pins_nand_rdy),
319 GRP_MUX("nand rd", EBU, pins_nand_rd),
320 GRP_MUX("exin3", EXIN, pins_exin3),
321 GRP_MUX("exin4", EXIN, pins_exin4),
322 GRP_MUX("exin5", EXIN, pins_exin5),
323 GRP_MUX("gnt4", PCI, pins_pci_gnt4),
324 GRP_MUX("req4", PCI, pins_pci_gnt4),
325 GRP_MUX("mdio", MDIO, pins_mdio),
326};
327
328static const struct ltq_pin_group ase_grps[] = {
329 GRP_MUX("exin0", EXIN, ase_pins_exin0),
330 GRP_MUX("exin1", EXIN, ase_pins_exin1),
331 GRP_MUX("exin2", EXIN, ase_pins_exin2),
332 GRP_MUX("jtag", JTAG, ase_pins_jtag),
333 GRP_MUX("stp", STP, ase_pins_stp),
334 GRP_MUX("asc", ASC, ase_pins_asc),
335 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
336 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
337 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
338 GRP_MUX("ephy", EPHY, ase_pins_ephy),
339 GRP_MUX("dfe", DFE, ase_pins_dfe),
340 GRP_MUX("spi", SPI, ase_pins_spi),
341 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
342 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
343 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
344};
345
346static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
347 "gnt3", "req1",
348 "req2", "req3"};
349static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
350 "spi_cs2", "spi_cs3",
351 "spi_cs4", "spi_cs5",
352 "spi_cs6"};
353static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
354 "clkout2", "clkout3"};
355static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
356 "ebu a25", "ebu cs1",
357 "ebu wait", "ebu clk",
358 "nand ale", "nand cs1",
359 "nand cle"};
360static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
361static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
362static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
363static const char * const xway_jtag_grps[] = {"jtag"};
364static const char * const xway_stp_grps[] = {"stp"};
365static const char * const xway_nmi_grps[] = {"nmi"};
366
367/* ar9/vr9/gr9 */
368static const char * const xrx_mdio_grps[] = {"mdio"};
369static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
370 "ebu a25", "ebu cs1",
371 "ebu wait", "ebu clk",
372 "nand ale", "nand cs1",
373 "nand cle", "nand rdy",
374 "nand rd"};
375static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
376 "exin3", "exin4", "exin5"};
377static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
378 "gnt3", "gnt4",
379 "req1", "req2",
380 "req3", "req4"};
381
382/* ase */
383static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
384static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
385static const char * const ase_dfe_grps[] = {"dfe"};
386static const char * const ase_ephy_grps[] = {"ephy"};
387static const char * const ase_asc_grps[] = {"asc"};
388static const char * const ase_jtag_grps[] = {"jtag"};
389static const char * const ase_stp_grps[] = {"stp"};
390static const char * const ase_spi_grps[] = {"spi", "spi_cs1",
391 "spi_cs2", "spi_cs3"};
392
393static const struct ltq_pmx_func danube_funcs[] = {
394 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
395 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
396 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
397 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
398 {"exin", ARRAY_AND_SIZE(xway_exin_grps)},
399 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
400 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
401 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
402 {"pci", ARRAY_AND_SIZE(xway_pci_grps)},
403 {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)},
404};
405
406static const struct ltq_pmx_func xrx_funcs[] = {
407 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
408 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
409 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
410 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
411 {"exin", ARRAY_AND_SIZE(xrx_exin_grps)},
412 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
413 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
414 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
415 {"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
416 {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
417 {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
418};
419
420static const struct ltq_pmx_func ase_funcs[] = {
421 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
422 {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
423 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
424 {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
425 {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
426 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
427 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
428 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
429};
430
431/* --------- pinconf related code --------- */
432static int xway_pinconf_get(struct pinctrl_dev *pctldev,
433 unsigned pin,
434 unsigned long *config)
435{
436 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
437 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
438 int port = PORT(pin);
439 u32 reg;
440
441 switch (param) {
442 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
443 if (port == PORT3)
444 reg = GPIO3_OD;
445 else
446 reg = GPIO_OD(port);
447 *config = LTQ_PINCONF_PACK(param,
448 !!gpio_getbit(info->membase[0], reg, PORT_PIN(port)));
449 break;
450
451 case LTQ_PINCONF_PARAM_PULL:
452 if (port == PORT3)
453 reg = GPIO3_PUDEN;
454 else
455 reg = GPIO_PUDEN(port);
456 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) {
457 *config = LTQ_PINCONF_PACK(param, 0);
458 break;
459 }
460
461 if (port == PORT3)
462 reg = GPIO3_PUDSEL;
463 else
464 reg = GPIO_PUDSEL(port);
465 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port)))
466 *config = LTQ_PINCONF_PACK(param, 2);
467 else
468 *config = LTQ_PINCONF_PACK(param, 1);
469 break;
470
471 default:
472 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
473 return -ENOTSUPP;
474 }
475 return 0;
476}
477
478static int xway_pinconf_set(struct pinctrl_dev *pctldev,
479 unsigned pin,
480 unsigned long config)
481{
482 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
483 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
484 int arg = LTQ_PINCONF_UNPACK_ARG(config);
485 int port = PORT(pin);
486 u32 reg;
487
488 switch (param) {
489 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
490 if (port == PORT3)
491 reg = GPIO3_OD;
492 else
493 reg = GPIO_OD(port);
494 gpio_setbit(info->membase[0], reg, PORT_PIN(port));
495 break;
496
497 case LTQ_PINCONF_PARAM_PULL:
498 if (port == PORT3)
499 reg = GPIO3_PUDEN;
500 else
501 reg = GPIO_PUDEN(port);
502 if (arg == 0) {
503 gpio_clearbit(info->membase[0], reg, PORT_PIN(port));
504 break;
505 }
506 gpio_setbit(info->membase[0], reg, PORT_PIN(port));
507
508 if (port == PORT3)
509 reg = GPIO3_PUDSEL;
510 else
511 reg = GPIO_PUDSEL(port);
512 if (arg == 1)
513 gpio_clearbit(info->membase[0], reg, PORT_PIN(port));
514 else if (arg == 2)
515 gpio_setbit(info->membase[0], reg, PORT_PIN(port));
516 else
517 dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
518 break;
519
520 default:
521 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
522 return -ENOTSUPP;
523 }
524 return 0;
525}
526
527struct pinconf_ops xway_pinconf_ops = {
528 .pin_config_get = xway_pinconf_get,
529 .pin_config_set = xway_pinconf_set,
530};
531
532static struct pinctrl_desc xway_pctrl_desc = {
533 .owner = THIS_MODULE,
534 .confops = &xway_pinconf_ops,
535};
536
537static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
538 int pin, int mux)
539{
540 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
541 int port = PORT(pin);
542 u32 alt1_reg = GPIO_ALT1(pin);
543
544 if (port == PORT3)
545 alt1_reg = GPIO3_ALT1;
546
547 if (mux & MUX_ALT0)
548 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
549 else
550 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
551
552 if (mux & MUX_ALT1)
553 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
554 else
555 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
556
557 return 0;
558}
559
560static const struct ltq_cfg_param xway_cfg_params[] = {
561 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
562 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
563};
564
565static struct ltq_pinmux_info xway_info = {
566 .desc = &xway_pctrl_desc,
567 .apply_mux = xway_mux_apply,
568 .params = xway_cfg_params,
569 .num_params = ARRAY_SIZE(xway_cfg_params),
570};
571
572/* --------- gpio_chip related code --------- */
573static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
574{
575 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
576
577 if (val)
578 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
579 else
580 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
581}
582
583static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
584{
585 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
586
587 return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
588}
589
590static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
591{
592 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
593
594 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
595
596 return 0;
597}
598
599static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
600{
601 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
602
603 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
604 xway_gpio_set(chip, pin, val);
605
606 return 0;
607}
608
609static int xway_gpio_req(struct gpio_chip *chip, unsigned offset)
610{
611 int gpio = chip->base + offset;
612
613 return pinctrl_request_gpio(gpio);
614}
615
616static void xway_gpio_free(struct gpio_chip *chip, unsigned offset)
617{
618 int gpio = chip->base + offset;
619
620 pinctrl_free_gpio(gpio);
621}
622
623static struct gpio_chip xway_chip = {
624 .label = "gpio-xway",
625 .direction_input = xway_gpio_dir_in,
626 .direction_output = xway_gpio_dir_out,
627 .get = xway_gpio_get,
628 .set = xway_gpio_set,
629 .request = xway_gpio_req,
630 .free = xway_gpio_free,
631 .base = -1,
632};
633
634
635/* --------- register the pinctrl layer --------- */
636static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
637static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0};
638
639static struct pinctrl_xway_soc {
640 int pin_count;
641 const struct ltq_mfp_pin *mfp;
642 const struct ltq_pin_group *grps;
643 unsigned int num_grps;
644 const struct ltq_pmx_func *funcs;
645 unsigned int num_funcs;
646 const unsigned *exin;
647 unsigned int num_exin;
648} soc_cfg[] = {
649 /* legacy xway */
650 {XWAY_MAX_PIN, xway_mfp,
651 xway_grps, ARRAY_SIZE(xway_grps),
652 danube_funcs, ARRAY_SIZE(danube_funcs),
653 xway_exin_pin_map, 3},
654 /* xway xr9 series */
655 {XR9_MAX_PIN, xway_mfp,
656 xway_grps, ARRAY_SIZE(xway_grps),
657 xrx_funcs, ARRAY_SIZE(xrx_funcs),
658 xway_exin_pin_map, 6},
659 /* xway ase series */
660 {XWAY_MAX_PIN, ase_mfp,
661 ase_grps, ARRAY_SIZE(ase_grps),
662 ase_funcs, ARRAY_SIZE(ase_funcs),
663 ase_exin_pins_map, 3},
664};
665
666static struct pinctrl_gpio_range xway_gpio_range = {
667 .name = "XWAY GPIO",
668 .gc = &xway_chip,
669};
670
671static const struct of_device_id xway_match[] = {
672 { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]},
673 { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]},
674 { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]},
675 {},
676};
677MODULE_DEVICE_TABLE(of, xway_match);
678
679static int __devinit pinmux_xway_probe(struct platform_device *pdev)
680{
681 const struct of_device_id *match;
682 const struct pinctrl_xway_soc *xway_soc;
683 struct resource *res;
684 int ret, i;
685
686 /* get and remap our register range */
687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 if (!res) {
689 dev_err(&pdev->dev, "Failed to get resource\n");
690 return -ENOENT;
691 }
692 xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res);
693 if (!xway_info.membase[0]) {
694 dev_err(&pdev->dev, "Failed to remap resource\n");
695 return -ENOMEM;
696 }
697
698 match = of_match_device(xway_match, &pdev->dev);
699 if (match)
700 xway_soc = (const struct pinctrl_xway_soc *) match->data;
701 else
702 xway_soc = &soc_cfg[0];
703
704 /* find out how many pads we have */
705 xway_chip.ngpio = xway_soc->pin_count;
706
707 /* load our pad descriptors */
708 xway_info.pads = devm_kzalloc(&pdev->dev,
709 sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio,
710 GFP_KERNEL);
711 if (!xway_info.pads) {
712 dev_err(&pdev->dev, "Failed to allocate pads\n");
713 return -ENOMEM;
714 }
715 for (i = 0; i < xway_chip.ngpio; i++) {
716 /* strlen("ioXY") + 1 = 5 */
717 char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
718
719 if (!name) {
720 dev_err(&pdev->dev, "Failed to allocate pad name\n");
721 return -ENOMEM;
722 }
723 snprintf(name, 5, "io%d", i);
724 xway_info.pads[i].number = GPIO0 + i;
725 xway_info.pads[i].name = name;
726 }
727 xway_pctrl_desc.pins = xway_info.pads;
728
729 /* load the gpio chip */
730 xway_chip.dev = &pdev->dev;
731 of_gpiochip_add(&xway_chip);
732 ret = gpiochip_add(&xway_chip);
733 if (ret) {
734 dev_err(&pdev->dev, "Failed to register gpio chip\n");
735 return ret;
736 }
737
738 /* setup the data needed by pinctrl */
739 xway_pctrl_desc.name = dev_name(&pdev->dev);
740 xway_pctrl_desc.npins = xway_chip.ngpio;
741
742 xway_info.num_pads = xway_chip.ngpio;
743 xway_info.num_mfp = xway_chip.ngpio;
744 xway_info.mfp = xway_soc->mfp;
745 xway_info.grps = xway_soc->grps;
746 xway_info.num_grps = xway_soc->num_grps;
747 xway_info.funcs = xway_soc->funcs;
748 xway_info.num_funcs = xway_soc->num_funcs;
749 xway_info.exin = xway_soc->exin;
750 xway_info.num_exin = xway_soc->num_exin;
751
752 /* register with the generic lantiq layer */
753 ret = ltq_pinctrl_register(pdev, &xway_info);
754 if (ret) {
755 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
756 return ret;
757 }
758
759 /* finish with registering the gpio range in pinctrl */
760 xway_gpio_range.npins = xway_chip.ngpio;
761 xway_gpio_range.base = xway_chip.base;
762 pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
763 dev_info(&pdev->dev, "Init done\n");
764 return 0;
765}
766
767static struct platform_driver pinmux_xway_driver = {
768 .probe = pinmux_xway_probe,
769 .driver = {
770 .name = "pinctrl-xway",
771 .owner = THIS_MODULE,
772 .of_match_table = xway_match,
773 },
774};
775
776static int __init pinmux_xway_init(void)
777{
778 return platform_driver_register(&pinmux_xway_driver);
779}
780
781core_initcall_sync(pinmux_xway_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 04:54:41 -0500