diff options
author | Stephen Warren <swarren@nvidia.com> | 2014-03-05 16:53:32 -0500 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2014-03-11 06:16:28 -0400 |
commit | a76cbd7eba1fa4b623fa35e2cb0ef5de1c504e2f (patch) | |
tree | 82e83c421abed568a8e3f256a549447111995fb5 /drivers/pinctrl | |
parent | 893a7d11a185c5d4d1cf47d94880a973ef55e2a0 (diff) |
pinctrl: tegra: fix some typos and inconsistencies
drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it.
pinctrl-tegra124.c had quite a few typos. Fix those.
pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys
and the function lists in tegra124_groups[]. Fix those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/pinctrl-tegra114.c | 5 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-tegra124.c | 41 |
2 files changed, 17 insertions, 29 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c index 93c9e3899d5e..46da27ff2d64 100644 --- a/drivers/pinctrl/pinctrl-tegra114.c +++ b/drivers/pinctrl/pinctrl-tegra114.c | |||
@@ -1341,11 +1341,6 @@ static const unsigned drive_uda_pins[] = { | |||
1341 | TEGRA_PIN_ULPI_STP_PY3, | 1341 | TEGRA_PIN_ULPI_STP_PY3, |
1342 | }; | 1342 | }; |
1343 | 1343 | ||
1344 | static const unsigned drive_dev3_pins[] = { | ||
1345 | TEGRA_PIN_CLK3_OUT_PEE0, | ||
1346 | TEGRA_PIN_CLK3_REQ_PEE1, | ||
1347 | }; | ||
1348 | |||
1349 | enum tegra_mux { | 1344 | enum tegra_mux { |
1350 | TEGRA_MUX_BLINK, | 1345 | TEGRA_MUX_BLINK, |
1351 | TEGRA_MUX_CEC, | 1346 | TEGRA_MUX_CEC, |
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c index c20e0e1dda83..7c6b7b63320f 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/pinctrl-tegra124.c | |||
@@ -325,13 +325,13 @@ static const struct pinctrl_pin_desc tegra124_pins[] = { | |||
325 | PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"), | 325 | PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"), |
326 | PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"), | 326 | PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"), |
327 | PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"), | 327 | PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"), |
328 | PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"), | 328 | PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"), |
329 | PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"), | 329 | PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"), |
330 | PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"), | 330 | PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"), |
331 | PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"), | 331 | PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"), |
332 | PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"), | 332 | PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"), |
333 | PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"), | 333 | PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"), |
334 | PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"), | 334 | PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"), |
335 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"), | 335 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"), |
336 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"), | 336 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"), |
337 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"), | 337 | PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"), |
@@ -1608,12 +1608,12 @@ static const char * const cpu_groups[] = { | |||
1608 | }; | 1608 | }; |
1609 | 1609 | ||
1610 | static const char * const dap_groups[] = { | 1610 | static const char * const dap_groups[] = { |
1611 | "dap_mclk1_pee2", | 1611 | "dap_mclk1_req_pee2", |
1612 | "clk2_req_pcc5", | 1612 | "clk2_req_pcc5", |
1613 | }; | 1613 | }; |
1614 | 1614 | ||
1615 | static const char * const dap1_groups[] = { | 1615 | static const char * const dap1_groups[] = { |
1616 | "dap_mclk1_pee2", | 1616 | "dap_mclk1_req_pee2", |
1617 | }; | 1617 | }; |
1618 | 1618 | ||
1619 | static const char * const dap2_groups[] = { | 1619 | static const char * const dap2_groups[] = { |
@@ -2013,8 +2013,8 @@ static const char * const rsvd2_groups[] = { | |||
2013 | "gen1_i2c_scl_pc4", | 2013 | "gen1_i2c_scl_pc4", |
2014 | "gen1_i2c_sda_pc5", | 2014 | "gen1_i2c_sda_pc5", |
2015 | 2015 | ||
2016 | "clk2_out_pee0", | 2016 | "clk3_out_pee0", |
2017 | "clk2_req_pee1", | 2017 | "clk3_req_pee1", |
2018 | "pc7", | 2018 | "pc7", |
2019 | "pi5", | 2019 | "pi5", |
2020 | "pj0", | 2020 | "pj0", |
@@ -2130,7 +2130,7 @@ static const char * const rsvd3_groups[] = { | |||
2130 | "clk3_req_pee1", | 2130 | "clk3_req_pee1", |
2131 | 2131 | ||
2132 | "sdmmc4_dat5_paa5", | 2132 | "sdmmc4_dat5_paa5", |
2133 | "gpio_pcc1", | 2133 | "pcc1", |
2134 | "cam_i2c_scl_pbb1", | 2134 | "cam_i2c_scl_pbb1", |
2135 | "cam_i2c_sda_pbb2", | 2135 | "cam_i2c_sda_pbb2", |
2136 | "pbb5", | 2136 | "pbb5", |
@@ -2195,11 +2195,6 @@ static const char * const rsvd4_groups[] = { | |||
2195 | "ddc_scl_pv4", | 2195 | "ddc_scl_pv4", |
2196 | "ddc_sda_pv5", | 2196 | "ddc_sda_pv5", |
2197 | 2197 | ||
2198 | "uart2_rts_n_pj6", | ||
2199 | "uart2_cts_n_pj5", | ||
2200 | "uart3_txd_pw6", | ||
2201 | "uart3_rxd_pw7", | ||
2202 | |||
2203 | "pu0", | 2198 | "pu0", |
2204 | "pu1", | 2199 | "pu1", |
2205 | "pu2", | 2200 | "pu2", |
@@ -2234,6 +2229,7 @@ static const char * const rsvd4_groups[] = { | |||
2234 | "gen2_i2c_scl_pt5", | 2229 | "gen2_i2c_scl_pt5", |
2235 | "gen2_i2c_sda_pt6", | 2230 | "gen2_i2c_sda_pt6", |
2236 | 2231 | ||
2232 | "sdmmc4_clk_pcc4", | ||
2237 | "sdmmc4_cmd_pt7", | 2233 | "sdmmc4_cmd_pt7", |
2238 | "sdmmc4_dat0_paa0", | 2234 | "sdmmc4_dat0_paa0", |
2239 | "sdmmc4_dat1_paa1", | 2235 | "sdmmc4_dat1_paa1", |
@@ -2271,7 +2267,7 @@ static const char * const rsvd4_groups[] = { | |||
2271 | "dap1_din_pn1", | 2267 | "dap1_din_pn1", |
2272 | "dap1_sclk_pn3", | 2268 | "dap1_sclk_pn3", |
2273 | "dap_mclk1_req_pee2", | 2269 | "dap_mclk1_req_pee2", |
2274 | "dap_mclk1_pw5", | 2270 | "dap_mclk1_pw4", |
2275 | 2271 | ||
2276 | "dap2_fs_pa2", | 2272 | "dap2_fs_pa2", |
2277 | "dap2_din_pa4", | 2273 | "dap2_din_pa4", |
@@ -2312,8 +2308,6 @@ static const char * const sdmmc1_groups[] = { | |||
2312 | "sdmmc1_dat2_py5", | 2308 | "sdmmc1_dat2_py5", |
2313 | "sdmmc1_dat1_py6", | 2309 | "sdmmc1_dat1_py6", |
2314 | "sdmmc1_dat0_py7", | 2310 | "sdmmc1_dat0_py7", |
2315 | "clk2_out_pw5", | ||
2316 | "clk2_req_pcc", | ||
2317 | "uart3_cts_n_pa1", | 2311 | "uart3_cts_n_pa1", |
2318 | "sdmmc1_wp_n_pv3", | 2312 | "sdmmc1_wp_n_pv3", |
2319 | }; | 2313 | }; |
@@ -2412,7 +2406,6 @@ static const char * const spi2_groups[] = { | |||
2412 | 2406 | ||
2413 | "kb_row13_ps5", | 2407 | "kb_row13_ps5", |
2414 | "kb_row14_ps6", | 2408 | "kb_row14_ps6", |
2415 | "kb_row15_ps7", | ||
2416 | "kb_col0_pq0", | 2409 | "kb_col0_pq0", |
2417 | "kb_col1_pq1", | 2410 | "kb_col1_pq1", |
2418 | "kb_col2_pq2", | 2411 | "kb_col2_pq2", |
@@ -2558,7 +2551,7 @@ static const char * const uartc_groups[] = { | |||
2558 | "uart3_cts_n_pa1", | 2551 | "uart3_cts_n_pa1", |
2559 | "uart3_rts_n_pc0", | 2552 | "uart3_rts_n_pc0", |
2560 | "kb_row16_pt0", | 2553 | "kb_row16_pt0", |
2561 | "kn_row17_pt1", | 2554 | "kb_row17_pt1", |
2562 | }; | 2555 | }; |
2563 | 2556 | ||
2564 | static const char * const uartd_groups[] = { | 2557 | static const char * const uartd_groups[] = { |
@@ -2964,9 +2957,9 @@ static const struct tegra_pingroup tegra124_groups[] = { | |||
2964 | PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N), | 2957 | PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N), |
2965 | PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N), | 2958 | PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N), |
2966 | PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N), | 2959 | PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N), |
2967 | PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD1, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N), | 2960 | PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N), |
2968 | PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N), | 2961 | PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N), |
2969 | PINGROUP(pcc1, I2S4, RSVD1, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N), | 2962 | PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N), |
2970 | PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N), | 2963 | PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N), |
2971 | PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N), | 2964 | PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N), |
2972 | PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N), | 2965 | PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N), |