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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-02 19:20:20 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-02 19:20:20 -0400
commit06fe918e9f177dc2a0592b0ad40a6ce4920b2033 (patch)
treeea58ad79ba9688e8033d8ea762682fc664031b8c /drivers/pinctrl
parentdff8360a4a079692e65e55fbaa6c5dc605528403 (diff)
parente1b2dc70cd5b00e17c703163a463d82354b1cc76 (diff)
Merge tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl changes from Linus Walleij: "Some of this stuff is hitting arch/arm/* and have been ACKed by the ARM SoC folks, or it's device tree bindings pertaining to the specific driver. These are the bulk pinctrl changes for kernel v3.7: - Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs, provide platform config for the Nomadik. - Add a driver for the i.MX35. - Add a driver for the BCM2835, an advanced GPIO expander. - Various fixes and clean-ups and minor improvements for the core, Nomadik, pinctr-single, sirf drivers. - Some platform config for the ux500." * tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits) pinctrl: add bcm2835 driver pinctrl: clarify idle vs sleep states pinctrl/nomadik: use irq_find_mapping() pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input pinctrl: sirf: add missing pins to pinctrl list pinctrl: sirf: fix a typo in sirfsoc_gpio_probe pinctrl: pinctrl-single: add debugfs pin h/w state info ARM: ux500: 8500: update I2C sleep states pinctrl pinctrl: Fix potential memory leak in pinctrl_register_one_pin() ARM: ux500: tidy up pin sleep modes ARM: ux500: fix spi2 pin group pinctrl: imx: remove duplicated const pinctrl: document semantics vs GPIO ARM: ux500: 8500: use hsit_a_2 group for HSI pinctrl: use kasprintf() in pinmux_request_gpio() pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux pinctrl/nomadik : add MC1_a_2 pin MC1 function group list pinctrl: pinctrl-single: Make sure we do not change bits outside of mask ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig21
-rw-r--r--drivers/pinctrl/Makefile4
-rw-r--r--drivers/pinctrl/core.c4
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c1075
-rw-r--r--drivers/pinctrl/pinctrl-imx.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx35.c1595
-rw-r--r--drivers/pinctrl/pinctrl-imx51.c490
-rw-r--r--drivers/pinctrl/pinctrl-imx53.c402
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c5
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8540.c999
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-stn8815.c357
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c10
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h27
-rw-r--r--drivers/pinctrl/pinctrl-single.c56
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c23
-rw-r--r--drivers/pinctrl/pinmux.c5
16 files changed, 4602 insertions, 473 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 34e94c7f68ca..1ef6e1e8c6c6 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -26,11 +26,24 @@ config DEBUG_PINCTRL
26 help 26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28 28
29config PINCTRL_BCM2835
30 bool
31 select PINMUX
32 select PINCONF
33
29config PINCTRL_IMX 34config PINCTRL_IMX
30 bool 35 bool
31 select PINMUX 36 select PINMUX
32 select PINCONF 37 select PINCONF
33 38
39config PINCTRL_IMX35
40 bool "IMX35 pinctrl driver"
41 depends on OF
42 depends on SOC_IMX35
43 select PINCTRL_IMX
44 help
45 Say Y here to enable the imx35 pinctrl driver
46
34config PINCTRL_IMX51 47config PINCTRL_IMX51
35 bool "IMX51 pinctrl driver" 48 bool "IMX51 pinctrl driver"
36 depends on OF 49 depends on OF
@@ -86,10 +99,18 @@ config PINCTRL_NOMADIK
86 select PINMUX 99 select PINMUX
87 select PINCONF 100 select PINCONF
88 101
102config PINCTRL_STN8815
103 bool "STN8815 pin controller driver"
104 depends on PINCTRL_NOMADIK && ARCH_NOMADIK
105
89config PINCTRL_DB8500 106config PINCTRL_DB8500
90 bool "DB8500 pin controller driver" 107 bool "DB8500 pin controller driver"
91 depends on PINCTRL_NOMADIK && ARCH_U8500 108 depends on PINCTRL_NOMADIK && ARCH_U8500
92 109
110config PINCTRL_DB8540
111 bool "DB8540 pin controller driver"
112 depends on PINCTRL_NOMADIK && ARCH_U8500
113
93config PINCTRL_PXA168 114config PINCTRL_PXA168
94 bool "PXA168 pin controller driver" 115 bool "PXA168 pin controller driver"
95 depends on ARCH_MMP 116 depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6a88113e11d9..698527dce29d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,7 +9,9 @@ ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o 9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif 10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
12obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 13obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
14obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
13obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o 15obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
14obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o 16obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
15obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 17obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
@@ -19,7 +21,9 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
19obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 21obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
20obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 22obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
21obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o 23obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
24obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
22obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 25obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
26obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
23obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 27obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
24obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 28obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
25obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 29obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index dc5c126e398a..0f1ec9e8ff14 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -230,8 +230,10 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
230 pindesc->name = name; 230 pindesc->name = name;
231 } else { 231 } else {
232 pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number); 232 pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number);
233 if (pindesc->name == NULL) 233 if (pindesc->name == NULL) {
234 kfree(pindesc);
234 return -ENOMEM; 235 return -ENOMEM;
236 }
235 pindesc->dynamic_name = true; 237 pindesc->dynamic_name = true;
236 } 238 }
237 239
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
new file mode 100644
index 000000000000..a4adee633fa9
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -0,0 +1,1075 @@
1/*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/bitmap.h>
22#include <linux/bug.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <linux/err.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/irqdesc.h>
31#include <linux/irqdomain.h>
32#include <linux/irq.h>
33#include <linux/module.h>
34#include <linux/of_address.h>
35#include <linux/of.h>
36#include <linux/of_irq.h>
37#include <linux/pinctrl/consumer.h>
38#include <linux/pinctrl/machine.h>
39#include <linux/pinctrl/pinconf.h>
40#include <linux/pinctrl/pinctrl.h>
41#include <linux/pinctrl/pinmux.h>
42#include <linux/platform_device.h>
43#include <linux/seq_file.h>
44#include <linux/slab.h>
45#include <linux/spinlock.h>
46#include <linux/types.h>
47
48#define MODULE_NAME "pinctrl-bcm2835"
49#define BCM2835_NUM_GPIOS 54
50#define BCM2835_NUM_BANKS 2
51
52#define BCM2835_PIN_BITMAP_SZ \
53 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
54
55/* GPIO register offsets */
56#define GPFSEL0 0x0 /* Function Select */
57#define GPSET0 0x1c /* Pin Output Set */
58#define GPCLR0 0x28 /* Pin Output Clear */
59#define GPLEV0 0x34 /* Pin Level */
60#define GPEDS0 0x40 /* Pin Event Detect Status */
61#define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
62#define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
63#define GPHEN0 0x64 /* Pin High Detect Enable */
64#define GPLEN0 0x70 /* Pin Low Detect Enable */
65#define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
66#define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
67#define GPPUD 0x94 /* Pin Pull-up/down Enable */
68#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
69
70#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
71#define FSEL_SHIFT(p) (((p) % 10) * 3)
72#define GPIO_REG_OFFSET(p) ((p) / 32)
73#define GPIO_REG_SHIFT(p) ((p) % 32)
74
75enum bcm2835_pinconf_param {
76 /* argument: bcm2835_pinconf_pull */
77 BCM2835_PINCONF_PARAM_PULL,
78};
79
80enum bcm2835_pinconf_pull {
81 BCM2835_PINCONFIG_PULL_NONE,
82 BCM2835_PINCONFIG_PULL_DOWN,
83 BCM2835_PINCONFIG_PULL_UP,
84};
85
86#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
87#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
88#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
89
90struct bcm2835_gpio_irqdata {
91 struct bcm2835_pinctrl *pc;
92 int bank;
93};
94
95struct bcm2835_pinctrl {
96 struct device *dev;
97 void __iomem *base;
98 int irq[BCM2835_NUM_BANKS];
99
100 /* note: locking assumes each bank will have its own unsigned long */
101 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
102 unsigned int irq_type[BCM2835_NUM_GPIOS];
103
104 struct pinctrl_dev *pctl_dev;
105 struct irq_domain *irq_domain;
106 struct gpio_chip gpio_chip;
107 struct pinctrl_gpio_range gpio_range;
108
109 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
110 spinlock_t irq_lock[BCM2835_NUM_BANKS];
111};
112
113static struct lock_class_key gpio_lock_class;
114
115/* pins are just named GPIO0..GPIO53 */
116#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
117struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
118 BCM2835_GPIO_PIN(0),
119 BCM2835_GPIO_PIN(1),
120 BCM2835_GPIO_PIN(2),
121 BCM2835_GPIO_PIN(3),
122 BCM2835_GPIO_PIN(4),
123 BCM2835_GPIO_PIN(5),
124 BCM2835_GPIO_PIN(6),
125 BCM2835_GPIO_PIN(7),
126 BCM2835_GPIO_PIN(8),
127 BCM2835_GPIO_PIN(9),
128 BCM2835_GPIO_PIN(10),
129 BCM2835_GPIO_PIN(11),
130 BCM2835_GPIO_PIN(12),
131 BCM2835_GPIO_PIN(13),
132 BCM2835_GPIO_PIN(14),
133 BCM2835_GPIO_PIN(15),
134 BCM2835_GPIO_PIN(16),
135 BCM2835_GPIO_PIN(17),
136 BCM2835_GPIO_PIN(18),
137 BCM2835_GPIO_PIN(19),
138 BCM2835_GPIO_PIN(20),
139 BCM2835_GPIO_PIN(21),
140 BCM2835_GPIO_PIN(22),
141 BCM2835_GPIO_PIN(23),
142 BCM2835_GPIO_PIN(24),
143 BCM2835_GPIO_PIN(25),
144 BCM2835_GPIO_PIN(26),
145 BCM2835_GPIO_PIN(27),
146 BCM2835_GPIO_PIN(28),
147 BCM2835_GPIO_PIN(29),
148 BCM2835_GPIO_PIN(30),
149 BCM2835_GPIO_PIN(31),
150 BCM2835_GPIO_PIN(32),
151 BCM2835_GPIO_PIN(33),
152 BCM2835_GPIO_PIN(34),
153 BCM2835_GPIO_PIN(35),
154 BCM2835_GPIO_PIN(36),
155 BCM2835_GPIO_PIN(37),
156 BCM2835_GPIO_PIN(38),
157 BCM2835_GPIO_PIN(39),
158 BCM2835_GPIO_PIN(40),
159 BCM2835_GPIO_PIN(41),
160 BCM2835_GPIO_PIN(42),
161 BCM2835_GPIO_PIN(43),
162 BCM2835_GPIO_PIN(44),
163 BCM2835_GPIO_PIN(45),
164 BCM2835_GPIO_PIN(46),
165 BCM2835_GPIO_PIN(47),
166 BCM2835_GPIO_PIN(48),
167 BCM2835_GPIO_PIN(49),
168 BCM2835_GPIO_PIN(50),
169 BCM2835_GPIO_PIN(51),
170 BCM2835_GPIO_PIN(52),
171 BCM2835_GPIO_PIN(53),
172};
173
174/* one pin per group */
175static const char * const bcm2835_gpio_groups[] = {
176 "gpio0",
177 "gpio1",
178 "gpio2",
179 "gpio3",
180 "gpio4",
181 "gpio5",
182 "gpio6",
183 "gpio7",
184 "gpio8",
185 "gpio9",
186 "gpio10",
187 "gpio11",
188 "gpio12",
189 "gpio13",
190 "gpio14",
191 "gpio15",
192 "gpio16",
193 "gpio17",
194 "gpio18",
195 "gpio19",
196 "gpio20",
197 "gpio21",
198 "gpio22",
199 "gpio23",
200 "gpio24",
201 "gpio25",
202 "gpio26",
203 "gpio27",
204 "gpio28",
205 "gpio29",
206 "gpio30",
207 "gpio31",
208 "gpio32",
209 "gpio33",
210 "gpio34",
211 "gpio35",
212 "gpio36",
213 "gpio37",
214 "gpio38",
215 "gpio39",
216 "gpio40",
217 "gpio41",
218 "gpio42",
219 "gpio43",
220 "gpio44",
221 "gpio45",
222 "gpio46",
223 "gpio47",
224 "gpio48",
225 "gpio49",
226 "gpio50",
227 "gpio51",
228 "gpio52",
229 "gpio53",
230};
231
232enum bcm2835_fsel {
233 BCM2835_FSEL_GPIO_IN = 0,
234 BCM2835_FSEL_GPIO_OUT = 1,
235 BCM2835_FSEL_ALT0 = 4,
236 BCM2835_FSEL_ALT1 = 5,
237 BCM2835_FSEL_ALT2 = 6,
238 BCM2835_FSEL_ALT3 = 7,
239 BCM2835_FSEL_ALT4 = 3,
240 BCM2835_FSEL_ALT5 = 2,
241 BCM2835_FSEL_COUNT = 8,
242 BCM2835_FSEL_MASK = 0x7,
243};
244
245static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
246 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
247 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
248 [BCM2835_FSEL_ALT0] = "alt0",
249 [BCM2835_FSEL_ALT1] = "alt1",
250 [BCM2835_FSEL_ALT2] = "alt2",
251 [BCM2835_FSEL_ALT3] = "alt3",
252 [BCM2835_FSEL_ALT4] = "alt4",
253 [BCM2835_FSEL_ALT5] = "alt5",
254};
255
256static const char * const irq_type_names[] = {
257 [IRQ_TYPE_NONE] = "none",
258 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
259 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
260 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
261 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
262 [IRQ_TYPE_LEVEL_LOW] = "level-low",
263};
264
265static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
266{
267 return readl(pc->base + reg);
268}
269
270static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
271 u32 val)
272{
273 writel(val, pc->base + reg);
274}
275
276static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
277 unsigned bit)
278{
279 reg += GPIO_REG_OFFSET(bit) * 4;
280 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
281}
282
283/* note NOT a read/modify/write cycle */
284static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
285 unsigned reg, unsigned bit)
286{
287 reg += GPIO_REG_OFFSET(bit) * 4;
288 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
289}
290
291static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
292 struct bcm2835_pinctrl *pc, unsigned pin)
293{
294 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
295 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
296
297 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
298 bcm2835_functions[status]);
299
300 return status;
301}
302
303static inline void bcm2835_pinctrl_fsel_set(
304 struct bcm2835_pinctrl *pc, unsigned pin,
305 enum bcm2835_fsel fsel)
306{
307 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
308 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
309
310 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
311 bcm2835_functions[cur]);
312
313 if (cur == fsel)
314 return;
315
316 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
317 /* always transition through GPIO_IN */
318 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
319 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
320
321 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
322 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
323 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
324 }
325
326 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
327 val |= fsel << FSEL_SHIFT(pin);
328
329 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
330 bcm2835_functions[fsel]);
331 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
332}
333
334static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset)
335{
336 return pinctrl_request_gpio(chip->base + offset);
337}
338
339static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset)
340{
341 pinctrl_free_gpio(chip->base + offset);
342}
343
344static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
345{
346 return pinctrl_gpio_direction_input(chip->base + offset);
347}
348
349static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
350{
351 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
352
353 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
354}
355
356static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
357 unsigned offset, int value)
358{
359 return pinctrl_gpio_direction_output(chip->base + offset);
360}
361
362static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
363{
364 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
365
366 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
367}
368
369static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
370{
371 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
372
373 return irq_linear_revmap(pc->irq_domain, offset);
374}
375
376static struct gpio_chip bcm2835_gpio_chip __devinitconst = {
377 .label = MODULE_NAME,
378 .owner = THIS_MODULE,
379 .request = bcm2835_gpio_request,
380 .free = bcm2835_gpio_free,
381 .direction_input = bcm2835_gpio_direction_input,
382 .direction_output = bcm2835_gpio_direction_output,
383 .get = bcm2835_gpio_get,
384 .set = bcm2835_gpio_set,
385 .to_irq = bcm2835_gpio_to_irq,
386 .base = -1,
387 .ngpio = BCM2835_NUM_GPIOS,
388 .can_sleep = 0,
389};
390
391static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
392{
393 struct bcm2835_gpio_irqdata *irqdata = dev_id;
394 struct bcm2835_pinctrl *pc = irqdata->pc;
395 int bank = irqdata->bank;
396 unsigned long events;
397 unsigned offset;
398 unsigned gpio;
399 unsigned int type;
400
401 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
402 events &= pc->enabled_irq_map[bank];
403 for_each_set_bit(offset, &events, 32) {
404 gpio = (32 * bank) + offset;
405 type = pc->irq_type[gpio];
406
407 /* ack edge triggered IRQs immediately */
408 if (!(type & IRQ_TYPE_LEVEL_MASK))
409 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
410
411 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
412
413 /* ack level triggered IRQ after handling them */
414 if (type & IRQ_TYPE_LEVEL_MASK)
415 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
416 }
417 return events ? IRQ_HANDLED : IRQ_NONE;
418}
419
420static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
421 unsigned reg, unsigned offset, bool enable)
422{
423 u32 value;
424 reg += GPIO_REG_OFFSET(offset) * 4;
425 value = bcm2835_gpio_rd(pc, reg);
426 if (enable)
427 value |= BIT(GPIO_REG_SHIFT(offset));
428 else
429 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
430 bcm2835_gpio_wr(pc, reg, value);
431}
432
433/* fast path for IRQ handler */
434static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
435 unsigned offset, bool enable)
436{
437 switch (pc->irq_type[offset]) {
438 case IRQ_TYPE_EDGE_RISING:
439 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
440 break;
441
442 case IRQ_TYPE_EDGE_FALLING:
443 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
444 break;
445
446 case IRQ_TYPE_EDGE_BOTH:
447 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
448 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
449 break;
450
451 case IRQ_TYPE_LEVEL_HIGH:
452 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
453 break;
454
455 case IRQ_TYPE_LEVEL_LOW:
456 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
457 break;
458 }
459}
460
461static void bcm2835_gpio_irq_enable(struct irq_data *data)
462{
463 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
464 unsigned gpio = irqd_to_hwirq(data);
465 unsigned offset = GPIO_REG_SHIFT(gpio);
466 unsigned bank = GPIO_REG_OFFSET(gpio);
467 unsigned long flags;
468
469 spin_lock_irqsave(&pc->irq_lock[bank], flags);
470 set_bit(offset, &pc->enabled_irq_map[bank]);
471 bcm2835_gpio_irq_config(pc, gpio, true);
472 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
473}
474
475static void bcm2835_gpio_irq_disable(struct irq_data *data)
476{
477 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
478 unsigned gpio = irqd_to_hwirq(data);
479 unsigned offset = GPIO_REG_SHIFT(gpio);
480 unsigned bank = GPIO_REG_OFFSET(gpio);
481 unsigned long flags;
482
483 spin_lock_irqsave(&pc->irq_lock[bank], flags);
484 bcm2835_gpio_irq_config(pc, gpio, false);
485 clear_bit(offset, &pc->enabled_irq_map[bank]);
486 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
487}
488
489static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
490 unsigned offset, unsigned int type)
491{
492 switch (type) {
493 case IRQ_TYPE_NONE:
494 case IRQ_TYPE_EDGE_RISING:
495 case IRQ_TYPE_EDGE_FALLING:
496 case IRQ_TYPE_EDGE_BOTH:
497 case IRQ_TYPE_LEVEL_HIGH:
498 case IRQ_TYPE_LEVEL_LOW:
499 pc->irq_type[offset] = type;
500 break;
501
502 default:
503 return -EINVAL;
504 }
505 return 0;
506}
507
508/* slower path for reconfiguring IRQ type */
509static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
510 unsigned offset, unsigned int type)
511{
512 switch (type) {
513 case IRQ_TYPE_NONE:
514 if (pc->irq_type[offset] != type) {
515 bcm2835_gpio_irq_config(pc, offset, false);
516 pc->irq_type[offset] = type;
517 }
518 break;
519
520 case IRQ_TYPE_EDGE_RISING:
521 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
522 /* RISING already enabled, disable FALLING */
523 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
524 bcm2835_gpio_irq_config(pc, offset, false);
525 pc->irq_type[offset] = type;
526 } else if (pc->irq_type[offset] != type) {
527 bcm2835_gpio_irq_config(pc, offset, false);
528 pc->irq_type[offset] = type;
529 bcm2835_gpio_irq_config(pc, offset, true);
530 }
531 break;
532
533 case IRQ_TYPE_EDGE_FALLING:
534 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
535 /* FALLING already enabled, disable RISING */
536 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
537 bcm2835_gpio_irq_config(pc, offset, false);
538 pc->irq_type[offset] = type;
539 } else if (pc->irq_type[offset] != type) {
540 bcm2835_gpio_irq_config(pc, offset, false);
541 pc->irq_type[offset] = type;
542 bcm2835_gpio_irq_config(pc, offset, true);
543 }
544 break;
545
546 case IRQ_TYPE_EDGE_BOTH:
547 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
548 /* RISING already enabled, enable FALLING too */
549 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
550 bcm2835_gpio_irq_config(pc, offset, true);
551 pc->irq_type[offset] = type;
552 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
553 /* FALLING already enabled, enable RISING too */
554 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
555 bcm2835_gpio_irq_config(pc, offset, true);
556 pc->irq_type[offset] = type;
557 } else if (pc->irq_type[offset] != type) {
558 bcm2835_gpio_irq_config(pc, offset, false);
559 pc->irq_type[offset] = type;
560 bcm2835_gpio_irq_config(pc, offset, true);
561 }
562 break;
563
564 case IRQ_TYPE_LEVEL_HIGH:
565 case IRQ_TYPE_LEVEL_LOW:
566 if (pc->irq_type[offset] != type) {
567 bcm2835_gpio_irq_config(pc, offset, false);
568 pc->irq_type[offset] = type;
569 bcm2835_gpio_irq_config(pc, offset, true);
570 }
571 break;
572
573 default:
574 return -EINVAL;
575 }
576 return 0;
577}
578
579static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
580{
581 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
582 unsigned gpio = irqd_to_hwirq(data);
583 unsigned offset = GPIO_REG_SHIFT(gpio);
584 unsigned bank = GPIO_REG_OFFSET(gpio);
585 unsigned long flags;
586 int ret;
587
588 spin_lock_irqsave(&pc->irq_lock[bank], flags);
589
590 if (test_bit(offset, &pc->enabled_irq_map[bank]))
591 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
592 else
593 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
594
595 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
596
597 return ret;
598}
599
600static struct irq_chip bcm2835_gpio_irq_chip = {
601 .name = MODULE_NAME,
602 .irq_enable = bcm2835_gpio_irq_enable,
603 .irq_disable = bcm2835_gpio_irq_disable,
604 .irq_set_type = bcm2835_gpio_irq_set_type,
605};
606
607static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
608{
609 return ARRAY_SIZE(bcm2835_gpio_groups);
610}
611
612static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
613 unsigned selector)
614{
615 return bcm2835_gpio_groups[selector];
616}
617
618static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
619 unsigned selector,
620 const unsigned **pins,
621 unsigned *num_pins)
622{
623 *pins = &bcm2835_gpio_pins[selector].number;
624 *num_pins = 1;
625
626 return 0;
627}
628
629static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
630 struct seq_file *s,
631 unsigned offset)
632{
633 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
634 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
635 const char *fname = bcm2835_functions[fsel];
636 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
637 int irq = irq_find_mapping(pc->irq_domain, offset);
638
639 seq_printf(s, "function %s in %s; irq %d (%s)",
640 fname, value ? "hi" : "lo",
641 irq, irq_type_names[pc->irq_type[offset]]);
642}
643
644static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
645 struct pinctrl_map *maps, unsigned num_maps)
646{
647 int i;
648
649 for (i = 0; i < num_maps; i++)
650 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
651 kfree(maps[i].data.configs.configs);
652
653 kfree(maps);
654}
655
656static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
657 struct device_node *np, u32 pin, u32 fnum,
658 struct pinctrl_map **maps)
659{
660 struct pinctrl_map *map = *maps;
661
662 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
663 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
664 of_node_full_name(np), fnum);
665 return -EINVAL;
666 }
667
668 map->type = PIN_MAP_TYPE_MUX_GROUP;
669 map->data.mux.group = bcm2835_gpio_groups[pin];
670 map->data.mux.function = bcm2835_functions[fnum];
671 (*maps)++;
672
673 return 0;
674}
675
676static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
677 struct device_node *np, u32 pin, u32 pull,
678 struct pinctrl_map **maps)
679{
680 struct pinctrl_map *map = *maps;
681 unsigned long *configs;
682
683 if (pull > 2) {
684 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
685 of_node_full_name(np), pull);
686 return -EINVAL;
687 }
688
689 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
690 if (!configs)
691 return -ENOMEM;
692 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
693
694 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
695 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
696 map->data.configs.configs = configs;
697 map->data.configs.num_configs = 1;
698 (*maps)++;
699
700 return 0;
701}
702
703static inline u32 prop_u32(struct property *p, int i)
704{
705 return be32_to_cpup(((__be32 *)p->value) + i);
706}
707
708static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
709 struct device_node *np,
710 struct pinctrl_map **map, unsigned *num_maps)
711{
712 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
713 struct property *pins, *funcs, *pulls;
714 int num_pins, num_funcs, num_pulls, maps_per_pin;
715 struct pinctrl_map *maps, *cur_map;
716 int i, err;
717 u32 pin, func, pull;
718
719 pins = of_find_property(np, "brcm,pins", NULL);
720 if (!pins) {
721 dev_err(pc->dev, "%s: missing brcm,pins property\n",
722 of_node_full_name(np));
723 return -EINVAL;
724 }
725
726 funcs = of_find_property(np, "brcm,function", NULL);
727 pulls = of_find_property(np, "brcm,pull", NULL);
728
729 if (!funcs && !pulls) {
730 dev_err(pc->dev,
731 "%s: neither brcm,function nor brcm,pull specified\n",
732 of_node_full_name(np));
733 return -EINVAL;
734 }
735
736 num_pins = pins->length / 4;
737 num_funcs = funcs ? (funcs->length / 4) : 0;
738 num_pulls = pulls ? (pulls->length / 4) : 0;
739
740 if (num_funcs > 1 && num_funcs != num_pins) {
741 dev_err(pc->dev,
742 "%s: brcm,function must have 1 or %d entries\n",
743 of_node_full_name(np), num_pins);
744 return -EINVAL;
745 }
746
747 if (num_pulls > 1 && num_pulls != num_pins) {
748 dev_err(pc->dev,
749 "%s: brcm,pull must have 1 or %d entries\n",
750 of_node_full_name(np), num_pins);
751 return -EINVAL;
752 }
753
754 maps_per_pin = 0;
755 if (num_funcs)
756 maps_per_pin++;
757 if (num_pulls)
758 maps_per_pin++;
759 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
760 GFP_KERNEL);
761 if (!maps)
762 return -ENOMEM;
763
764 for (i = 0; i < num_pins; i++) {
765 pin = prop_u32(pins, i);
766 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
767 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
768 of_node_full_name(np), pin);
769 err = -EINVAL;
770 goto out;
771 }
772
773 if (num_funcs) {
774 func = prop_u32(funcs, (num_funcs > 1) ? i : 0);
775 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
776 func, &cur_map);
777 if (err)
778 goto out;
779 }
780 if (num_pulls) {
781 pull = prop_u32(pulls, (num_pulls > 1) ? i : 0);
782 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
783 pull, &cur_map);
784 if (err)
785 goto out;
786 }
787 }
788
789 *map = maps;
790 *num_maps = num_pins * maps_per_pin;
791
792 return 0;
793
794out:
795 kfree(maps);
796 return err;
797}
798
799static struct pinctrl_ops bcm2835_pctl_ops = {
800 .get_groups_count = bcm2835_pctl_get_groups_count,
801 .get_group_name = bcm2835_pctl_get_group_name,
802 .get_group_pins = bcm2835_pctl_get_group_pins,
803 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
804 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
805 .dt_free_map = bcm2835_pctl_dt_free_map,
806};
807
808static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
809{
810 return BCM2835_FSEL_COUNT;
811}
812
813static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
814 unsigned selector)
815{
816 return bcm2835_functions[selector];
817}
818
819static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
820 unsigned selector,
821 const char * const **groups,
822 unsigned * const num_groups)
823{
824 /* every pin can do every function */
825 *groups = bcm2835_gpio_groups;
826 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
827
828 return 0;
829}
830
831static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
832 unsigned func_selector,
833 unsigned group_selector)
834{
835 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
836
837 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
838
839 return 0;
840}
841
842static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
843 unsigned func_selector,
844 unsigned group_selector)
845{
846 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
847
848 /* disable by setting to GPIO_IN */
849 bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
850}
851
852static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
853 struct pinctrl_gpio_range *range,
854 unsigned offset)
855{
856 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
857
858 /* disable by setting to GPIO_IN */
859 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
860}
861
862static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
863 struct pinctrl_gpio_range *range,
864 unsigned offset,
865 bool input)
866{
867 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
868 enum bcm2835_fsel fsel = input ?
869 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
870
871 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
872
873 return 0;
874}
875
876static struct pinmux_ops bcm2835_pmx_ops = {
877 .get_functions_count = bcm2835_pmx_get_functions_count,
878 .get_function_name = bcm2835_pmx_get_function_name,
879 .get_function_groups = bcm2835_pmx_get_function_groups,
880 .enable = bcm2835_pmx_enable,
881 .disable = bcm2835_pmx_disable,
882 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
883 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
884};
885
886static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
887 unsigned pin, unsigned long *config)
888{
889 /* No way to read back config in HW */
890 return -ENOTSUPP;
891}
892
893static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
894 unsigned pin, unsigned long config)
895{
896 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
897 enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config);
898 u16 arg = BCM2835_PINCONF_UNPACK_ARG(config);
899 u32 off, bit;
900
901 if (param != BCM2835_PINCONF_PARAM_PULL)
902 return -EINVAL;
903
904 off = GPIO_REG_OFFSET(pin);
905 bit = GPIO_REG_SHIFT(pin);
906
907 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
908 /*
909 * Docs say to wait 150 cycles, but not of what. We assume a
910 * 1 MHz clock here, which is pretty slow...
911 */
912 udelay(150);
913 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
914 udelay(150);
915 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
916
917 return 0;
918}
919
920struct pinconf_ops bcm2835_pinconf_ops = {
921 .pin_config_get = bcm2835_pinconf_get,
922 .pin_config_set = bcm2835_pinconf_set,
923};
924
925static struct pinctrl_desc bcm2835_pinctrl_desc = {
926 .name = MODULE_NAME,
927 .pins = bcm2835_gpio_pins,
928 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
929 .pctlops = &bcm2835_pctl_ops,
930 .pmxops = &bcm2835_pmx_ops,
931 .confops = &bcm2835_pinconf_ops,
932 .owner = THIS_MODULE,
933};
934
935static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range __devinitconst = {
936 .name = MODULE_NAME,
937 .npins = BCM2835_NUM_GPIOS,
938};
939
940static int __devinit bcm2835_pinctrl_probe(struct platform_device *pdev)
941{
942 struct device *dev = &pdev->dev;
943 struct device_node *np = dev->of_node;
944 struct bcm2835_pinctrl *pc;
945 struct resource iomem;
946 int err, i;
947 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
948 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
949
950 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
951 if (!pc)
952 return -ENOMEM;
953
954 platform_set_drvdata(pdev, pc);
955 pc->dev = dev;
956
957 err = of_address_to_resource(np, 0, &iomem);
958 if (err) {
959 dev_err(dev, "could not get IO memory\n");
960 return err;
961 }
962
963 pc->base = devm_request_and_ioremap(&pdev->dev, &iomem);
964 if (!pc->base)
965 return -EADDRNOTAVAIL;
966
967 pc->gpio_chip = bcm2835_gpio_chip;
968 pc->gpio_chip.dev = dev;
969 pc->gpio_chip.of_node = np;
970
971 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
972 &irq_domain_simple_ops, NULL);
973 if (!pc->irq_domain) {
974 dev_err(dev, "could not create IRQ domain\n");
975 return -ENOMEM;
976 }
977
978 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
979 int irq = irq_create_mapping(pc->irq_domain, i);
980 irq_set_lockdep_class(irq, &gpio_lock_class);
981 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
982 handle_simple_irq);
983 irq_set_chip_data(irq, pc);
984 set_irq_flags(irq, IRQF_VALID);
985 }
986
987 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
988 unsigned long events;
989 unsigned offset;
990 int len;
991 char *name;
992
993 /* clear event detection flags */
994 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
995 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
996 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
997 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
998 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
999 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1000
1001 /* clear all the events */
1002 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1003 for_each_set_bit(offset, &events, 32)
1004 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1005
1006 pc->irq[i] = irq_of_parse_and_map(np, i);
1007 pc->irq_data[i].pc = pc;
1008 pc->irq_data[i].bank = i;
1009 spin_lock_init(&pc->irq_lock[i]);
1010
1011 len = strlen(dev_name(pc->dev)) + 16;
1012 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1013 if (!name)
1014 return -ENOMEM;
1015 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1016
1017 err = devm_request_irq(dev, pc->irq[i],
1018 bcm2835_gpio_irq_handler, IRQF_SHARED,
1019 name, &pc->irq_data[i]);
1020 if (err) {
1021 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1022 return err;
1023 }
1024 }
1025
1026 err = gpiochip_add(&pc->gpio_chip);
1027 if (err) {
1028 dev_err(dev, "could not add GPIO chip\n");
1029 return err;
1030 }
1031
1032 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
1033 if (!pc->pctl_dev) {
1034 gpiochip_remove(&pc->gpio_chip);
1035 return PTR_ERR(pc->pctl_dev);
1036 }
1037
1038 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1039 pc->gpio_range.base = pc->gpio_chip.base;
1040 pc->gpio_range.gc = &pc->gpio_chip;
1041 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1042
1043 return 0;
1044}
1045
1046static int __devexit bcm2835_pinctrl_remove(struct platform_device *pdev)
1047{
1048 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1049
1050 pinctrl_unregister(pc->pctl_dev);
1051 gpiochip_remove(&pc->gpio_chip);
1052
1053 return 0;
1054}
1055
1056static struct of_device_id bcm2835_pinctrl_match[] __devinitconst = {
1057 { .compatible = "brcm,bcm2835-gpio" },
1058 {}
1059};
1060MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1061
1062static struct platform_driver bcm2835_pinctrl_driver = {
1063 .probe = bcm2835_pinctrl_probe,
1064 .remove = bcm2835_pinctrl_remove,
1065 .driver = {
1066 .name = MODULE_NAME,
1067 .owner = THIS_MODULE,
1068 .of_match_table = bcm2835_pinctrl_match,
1069 },
1070};
1071module_platform_driver(bcm2835_pinctrl_driver);
1072
1073MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1074MODULE_DESCRIPTION("BCM2835 Pin control driver");
1075MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 44e97265cd7d..63866d95357d 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -432,7 +432,7 @@ static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
432{ 432{
433 unsigned int pin_func_id; 433 unsigned int pin_func_id;
434 int ret, size; 434 int ret, size;
435 const const __be32 *list; 435 const __be32 *list;
436 int i, j; 436 int i, j;
437 u32 config; 437 u32 config;
438 438
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
new file mode 100644
index 000000000000..82f109e26f27
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -0,0 +1,1595 @@
1/*
2 * imx35 pinctrl driver.
3 *
4 * This driver was mostly copied from the imx51 pinctrl driver which has:
5 *
6 * Copyright (C) 2012 Freescale Semiconductor, Inc.
7 * Copyright (C) 2012 Linaro, Inc.
8 *
9 * Author: Dong Aisheng <dong.aisheng@linaro.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include <linux/err.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/pinctrl.h>
23
24#include "pinctrl-imx.h"
25
26enum imx35_pads {
27 MX35_PAD_CAPTURE = 0,
28 MX35_PAD_COMPARE = 1,
29 MX35_PAD_WDOG_RST = 2,
30 MX35_PAD_GPIO1_0 = 3,
31 MX35_PAD_GPIO1_1 = 4,
32 MX35_PAD_GPIO2_0 = 5,
33 MX35_PAD_GPIO3_0 = 6,
34 MX35_PAD_RESET_IN_B = 7,
35 MX35_PAD_POR_B = 8,
36 MX35_PAD_CLKO = 9,
37 MX35_PAD_BOOT_MODE0 = 10,
38 MX35_PAD_BOOT_MODE1 = 11,
39 MX35_PAD_CLK_MODE0 = 12,
40 MX35_PAD_CLK_MODE1 = 13,
41 MX35_PAD_POWER_FAIL = 14,
42 MX35_PAD_VSTBY = 15,
43 MX35_PAD_A0 = 16,
44 MX35_PAD_A1 = 17,
45 MX35_PAD_A2 = 18,
46 MX35_PAD_A3 = 19,
47 MX35_PAD_A4 = 20,
48 MX35_PAD_A5 = 21,
49 MX35_PAD_A6 = 22,
50 MX35_PAD_A7 = 23,
51 MX35_PAD_A8 = 24,
52 MX35_PAD_A9 = 25,
53 MX35_PAD_A10 = 26,
54 MX35_PAD_MA10 = 27,
55 MX35_PAD_A11 = 28,
56 MX35_PAD_A12 = 29,
57 MX35_PAD_A13 = 30,
58 MX35_PAD_A14 = 31,
59 MX35_PAD_A15 = 32,
60 MX35_PAD_A16 = 33,
61 MX35_PAD_A17 = 34,
62 MX35_PAD_A18 = 35,
63 MX35_PAD_A19 = 36,
64 MX35_PAD_A20 = 37,
65 MX35_PAD_A21 = 38,
66 MX35_PAD_A22 = 39,
67 MX35_PAD_A23 = 40,
68 MX35_PAD_A24 = 41,
69 MX35_PAD_A25 = 42,
70 MX35_PAD_SDBA1 = 43,
71 MX35_PAD_SDBA0 = 44,
72 MX35_PAD_SD0 = 45,
73 MX35_PAD_SD1 = 46,
74 MX35_PAD_SD2 = 47,
75 MX35_PAD_SD3 = 48,
76 MX35_PAD_SD4 = 49,
77 MX35_PAD_SD5 = 50,
78 MX35_PAD_SD6 = 51,
79 MX35_PAD_SD7 = 52,
80 MX35_PAD_SD8 = 53,
81 MX35_PAD_SD9 = 54,
82 MX35_PAD_SD10 = 55,
83 MX35_PAD_SD11 = 56,
84 MX35_PAD_SD12 = 57,
85 MX35_PAD_SD13 = 58,
86 MX35_PAD_SD14 = 59,
87 MX35_PAD_SD15 = 60,
88 MX35_PAD_SD16 = 61,
89 MX35_PAD_SD17 = 62,
90 MX35_PAD_SD18 = 63,
91 MX35_PAD_SD19 = 64,
92 MX35_PAD_SD20 = 65,
93 MX35_PAD_SD21 = 66,
94 MX35_PAD_SD22 = 67,
95 MX35_PAD_SD23 = 68,
96 MX35_PAD_SD24 = 69,
97 MX35_PAD_SD25 = 70,
98 MX35_PAD_SD26 = 71,
99 MX35_PAD_SD27 = 72,
100 MX35_PAD_SD28 = 73,
101 MX35_PAD_SD29 = 74,
102 MX35_PAD_SD30 = 75,
103 MX35_PAD_SD31 = 76,
104 MX35_PAD_DQM0 = 77,
105 MX35_PAD_DQM1 = 78,
106 MX35_PAD_DQM2 = 79,
107 MX35_PAD_DQM3 = 80,
108 MX35_PAD_EB0 = 81,
109 MX35_PAD_EB1 = 82,
110 MX35_PAD_OE = 83,
111 MX35_PAD_CS0 = 84,
112 MX35_PAD_CS1 = 85,
113 MX35_PAD_CS2 = 86,
114 MX35_PAD_CS3 = 87,
115 MX35_PAD_CS4 = 88,
116 MX35_PAD_CS5 = 89,
117 MX35_PAD_NF_CE0 = 90,
118 MX35_PAD_ECB = 91,
119 MX35_PAD_LBA = 92,
120 MX35_PAD_BCLK = 93,
121 MX35_PAD_RW = 94,
122 MX35_PAD_RAS = 95,
123 MX35_PAD_CAS = 96,
124 MX35_PAD_SDWE = 97,
125 MX35_PAD_SDCKE0 = 98,
126 MX35_PAD_SDCKE1 = 99,
127 MX35_PAD_SDCLK = 100,
128 MX35_PAD_SDQS0 = 101,
129 MX35_PAD_SDQS1 = 102,
130 MX35_PAD_SDQS2 = 103,
131 MX35_PAD_SDQS3 = 104,
132 MX35_PAD_NFWE_B = 105,
133 MX35_PAD_NFRE_B = 106,
134 MX35_PAD_NFALE = 107,
135 MX35_PAD_NFCLE = 108,
136 MX35_PAD_NFWP_B = 109,
137 MX35_PAD_NFRB = 110,
138 MX35_PAD_D15 = 111,
139 MX35_PAD_D14 = 112,
140 MX35_PAD_D13 = 113,
141 MX35_PAD_D12 = 114,
142 MX35_PAD_D11 = 115,
143 MX35_PAD_D10 = 116,
144 MX35_PAD_D9 = 117,
145 MX35_PAD_D8 = 118,
146 MX35_PAD_D7 = 119,
147 MX35_PAD_D6 = 120,
148 MX35_PAD_D5 = 121,
149 MX35_PAD_D4 = 122,
150 MX35_PAD_D3 = 123,
151 MX35_PAD_D2 = 124,
152 MX35_PAD_D1 = 125,
153 MX35_PAD_D0 = 126,
154 MX35_PAD_CSI_D8 = 127,
155 MX35_PAD_CSI_D9 = 128,
156 MX35_PAD_CSI_D10 = 129,
157 MX35_PAD_CSI_D11 = 130,
158 MX35_PAD_CSI_D12 = 131,
159 MX35_PAD_CSI_D13 = 132,
160 MX35_PAD_CSI_D14 = 133,
161 MX35_PAD_CSI_D15 = 134,
162 MX35_PAD_CSI_MCLK = 135,
163 MX35_PAD_CSI_VSYNC = 136,
164 MX35_PAD_CSI_HSYNC = 137,
165 MX35_PAD_CSI_PIXCLK = 138,
166 MX35_PAD_I2C1_CLK = 139,
167 MX35_PAD_I2C1_DAT = 140,
168 MX35_PAD_I2C2_CLK = 141,
169 MX35_PAD_I2C2_DAT = 142,
170 MX35_PAD_STXD4 = 143,
171 MX35_PAD_SRXD4 = 144,
172 MX35_PAD_SCK4 = 145,
173 MX35_PAD_STXFS4 = 146,
174 MX35_PAD_STXD5 = 147,
175 MX35_PAD_SRXD5 = 148,
176 MX35_PAD_SCK5 = 149,
177 MX35_PAD_STXFS5 = 150,
178 MX35_PAD_SCKR = 151,
179 MX35_PAD_FSR = 152,
180 MX35_PAD_HCKR = 153,
181 MX35_PAD_SCKT = 154,
182 MX35_PAD_FST = 155,
183 MX35_PAD_HCKT = 156,
184 MX35_PAD_TX5_RX0 = 157,
185 MX35_PAD_TX4_RX1 = 158,
186 MX35_PAD_TX3_RX2 = 159,
187 MX35_PAD_TX2_RX3 = 160,
188 MX35_PAD_TX1 = 161,
189 MX35_PAD_TX0 = 162,
190 MX35_PAD_CSPI1_MOSI = 163,
191 MX35_PAD_CSPI1_MISO = 164,
192 MX35_PAD_CSPI1_SS0 = 165,
193 MX35_PAD_CSPI1_SS1 = 166,
194 MX35_PAD_CSPI1_SCLK = 167,
195 MX35_PAD_CSPI1_SPI_RDY = 168,
196 MX35_PAD_RXD1 = 169,
197 MX35_PAD_TXD1 = 170,
198 MX35_PAD_RTS1 = 171,
199 MX35_PAD_CTS1 = 172,
200 MX35_PAD_RXD2 = 173,
201 MX35_PAD_TXD2 = 174,
202 MX35_PAD_RTS2 = 175,
203 MX35_PAD_CTS2 = 176,
204 MX35_PAD_RTCK = 177,
205 MX35_PAD_TCK = 178,
206 MX35_PAD_TMS = 179,
207 MX35_PAD_TDI = 180,
208 MX35_PAD_TDO = 181,
209 MX35_PAD_TRSTB = 182,
210 MX35_PAD_DE_B = 183,
211 MX35_PAD_SJC_MOD = 184,
212 MX35_PAD_USBOTG_PWR = 185,
213 MX35_PAD_USBOTG_OC = 186,
214 MX35_PAD_LD0 = 187,
215 MX35_PAD_LD1 = 188,
216 MX35_PAD_LD2 = 189,
217 MX35_PAD_LD3 = 190,
218 MX35_PAD_LD4 = 191,
219 MX35_PAD_LD5 = 192,
220 MX35_PAD_LD6 = 193,
221 MX35_PAD_LD7 = 194,
222 MX35_PAD_LD8 = 195,
223 MX35_PAD_LD9 = 196,
224 MX35_PAD_LD10 = 197,
225 MX35_PAD_LD11 = 198,
226 MX35_PAD_LD12 = 199,
227 MX35_PAD_LD13 = 200,
228 MX35_PAD_LD14 = 201,
229 MX35_PAD_LD15 = 202,
230 MX35_PAD_LD16 = 203,
231 MX35_PAD_LD17 = 204,
232 MX35_PAD_LD18 = 205,
233 MX35_PAD_LD19 = 206,
234 MX35_PAD_LD20 = 207,
235 MX35_PAD_LD21 = 208,
236 MX35_PAD_LD22 = 209,
237 MX35_PAD_LD23 = 210,
238 MX35_PAD_D3_HSYNC = 211,
239 MX35_PAD_D3_FPSHIFT = 212,
240 MX35_PAD_D3_DRDY = 213,
241 MX35_PAD_CONTRAST = 214,
242 MX35_PAD_D3_VSYNC = 215,
243 MX35_PAD_D3_REV = 216,
244 MX35_PAD_D3_CLS = 217,
245 MX35_PAD_D3_SPL = 218,
246 MX35_PAD_SD1_CMD = 219,
247 MX35_PAD_SD1_CLK = 220,
248 MX35_PAD_SD1_DATA0 = 221,
249 MX35_PAD_SD1_DATA1 = 222,
250 MX35_PAD_SD1_DATA2 = 223,
251 MX35_PAD_SD1_DATA3 = 224,
252 MX35_PAD_SD2_CMD = 225,
253 MX35_PAD_SD2_CLK = 226,
254 MX35_PAD_SD2_DATA0 = 227,
255 MX35_PAD_SD2_DATA1 = 228,
256 MX35_PAD_SD2_DATA2 = 229,
257 MX35_PAD_SD2_DATA3 = 230,
258 MX35_PAD_ATA_CS0 = 231,
259 MX35_PAD_ATA_CS1 = 232,
260 MX35_PAD_ATA_DIOR = 233,
261 MX35_PAD_ATA_DIOW = 234,
262 MX35_PAD_ATA_DMACK = 235,
263 MX35_PAD_ATA_RESET_B = 236,
264 MX35_PAD_ATA_IORDY = 237,
265 MX35_PAD_ATA_DATA0 = 238,
266 MX35_PAD_ATA_DATA1 = 239,
267 MX35_PAD_ATA_DATA2 = 240,
268 MX35_PAD_ATA_DATA3 = 241,
269 MX35_PAD_ATA_DATA4 = 242,
270 MX35_PAD_ATA_DATA5 = 243,
271 MX35_PAD_ATA_DATA6 = 244,
272 MX35_PAD_ATA_DATA7 = 245,
273 MX35_PAD_ATA_DATA8 = 246,
274 MX35_PAD_ATA_DATA9 = 247,
275 MX35_PAD_ATA_DATA10 = 248,
276 MX35_PAD_ATA_DATA11 = 249,
277 MX35_PAD_ATA_DATA12 = 250,
278 MX35_PAD_ATA_DATA13 = 251,
279 MX35_PAD_ATA_DATA14 = 252,
280 MX35_PAD_ATA_DATA15 = 253,
281 MX35_PAD_ATA_INTRQ = 254,
282 MX35_PAD_ATA_BUFF_EN = 255,
283 MX35_PAD_ATA_DMARQ = 256,
284 MX35_PAD_ATA_DA0 = 257,
285 MX35_PAD_ATA_DA1 = 258,
286 MX35_PAD_ATA_DA2 = 259,
287 MX35_PAD_MLB_CLK = 260,
288 MX35_PAD_MLB_DAT = 261,
289 MX35_PAD_MLB_SIG = 262,
290 MX35_PAD_FEC_TX_CLK = 263,
291 MX35_PAD_FEC_RX_CLK = 264,
292 MX35_PAD_FEC_RX_DV = 265,
293 MX35_PAD_FEC_COL = 266,
294 MX35_PAD_FEC_RDATA0 = 267,
295 MX35_PAD_FEC_TDATA0 = 268,
296 MX35_PAD_FEC_TX_EN = 269,
297 MX35_PAD_FEC_MDC = 270,
298 MX35_PAD_FEC_MDIO = 271,
299 MX35_PAD_FEC_TX_ERR = 272,
300 MX35_PAD_FEC_RX_ERR = 273,
301 MX35_PAD_FEC_CRS = 274,
302 MX35_PAD_FEC_RDATA1 = 275,
303 MX35_PAD_FEC_TDATA1 = 276,
304 MX35_PAD_FEC_RDATA2 = 277,
305 MX35_PAD_FEC_TDATA2 = 278,
306 MX35_PAD_FEC_RDATA3 = 279,
307 MX35_PAD_FEC_TDATA3 = 280,
308 MX35_PAD_EXT_ARMCLK = 281,
309 MX35_PAD_TEST_MODE = 282,
310};
311
312/* imx35 register maps */
313static struct imx_pin_reg imx35_pin_regs[] = {
314 [0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */
315 [1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */
316 [2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */
317 [3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */
318 [4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */
319 [5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */
320 [6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */
321 [7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */
322 [8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */
323 [9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */
324 [10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */
325 [11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */
326 [12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */
327 [13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */
328 [14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */
329 [15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */
330 [16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */
331 [17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */
332 [18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */
333 [19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */
334 [20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */
335 [21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */
336 [22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */
337 [23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */
338 [24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */
339 [25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */
340 [26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */
341 [27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */
342 [28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */
343 [29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */
344 [30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */
345 [31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */
346 [32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */
347 [33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */
348 [34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */
349 [35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */
350 [36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */
351 [37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */
352 [38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */
353 [39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */
354 [40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */
355 [41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */
356 [42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */
357 [43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */
358 [44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */
359 [45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */
360 [46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */
361 [47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */
362 [48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */
363 [49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */
364 [50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */
365 [51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */
366 [52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */
367 [53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */
368 [54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */
369 [55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */
370 [56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */
371 [57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */
372 [58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */
373 [59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */
374 [60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */
375 [61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */
376 [62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */
377 [63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */
378 [64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */
379 [65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */
380 [66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */
381 [67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */
382 [68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */
383 [69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */
384 [70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */
385 [71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */
386 [72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */
387 [73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */
388 [74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */
389 [75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */
390 [76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */
391 [77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */
392 [78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */
393 [79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */
394 [80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */
395 [81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */
396 [82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */
397 [83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */
398 [84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */
399 [85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */
400 [86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */
401 [87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */
402 [88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */
403 [89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */
404 [90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */
405 [91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */
406 [92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */
407 [93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */
408 [94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */
409 [95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */
410 [96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */
411 [97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */
412 [98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */
413 [99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */
414 [100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */
415 [101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */
416 [102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */
417 [103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */
418 [104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */
419 [105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */
420 [106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */
421 [107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */
422 [108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */
423 [109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */
424 [110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */
425 [111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */
426 [112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */
427 [113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */
428 [114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */
429 [115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */
430 [116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */
431 [117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */
432 [118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */
433 [119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */
434 [120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */
435 [121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */
436 [122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */
437 [123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */
438 [124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */
439 [125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */
440 [126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */
441 [127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */
442 [128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */
443 [129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */
444 [130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */
445 [131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */
446 [132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */
447 [133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */
448 [134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */
449 [135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */
450 [136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */
451 [137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */
452 [138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */
453 [139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */
454 [140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */
455 [141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */
456 [142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */
457 [143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */
458 [144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */
459 [145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */
460 [146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */
461 [147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */
462 [148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */
463 [149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */
464 [150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */
465 [151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */
466 [152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */
467 [153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */
468 [154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */
469 [155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */
470 [156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */
471 [157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */
472 [158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */
473 [159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */
474 [160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */
475 [161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */
476 [162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */
477 [163] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */
478 [164] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */
479 [165] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */
480 [166] = IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */
481 [167] = IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */
482 [168] = IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */
483 [169] = IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */
484 [170] = IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */
485 [171] = IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */
486 [172] = IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */
487 [173] = IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */
488 [174] = IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */
489 [175] = IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */
490 [176] = IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */
491 [177] = IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */
492 [178] = IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */
493 [179] = IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */
494 [180] = IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */
495 [181] = IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */
496 [182] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */
497 [183] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */
498 [184] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */
499 [185] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */
500 [186] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */
501 [187] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */
502 [188] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */
503 [189] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */
504 [190] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */
505 [191] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */
506 [192] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */
507 [193] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */
508 [194] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */
509 [195] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */
510 [196] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */
511 [197] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */
512 [198] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */
513 [199] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */
514 [200] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */
515 [201] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */
516 [202] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */
517 [203] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */
518 [204] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */
519 [205] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */
520 [206] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */
521 [207] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */
522 [208] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */
523 [209] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */
524 [210] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */
525 [211] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */
526 [212] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */
527 [213] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */
528 [214] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */
529 [215] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */
530 [216] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */
531 [217] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */
532 [218] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */
533 [219] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */
534 [220] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */
535 [221] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */
536 [222] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */
537 [223] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
538 [224] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */
539 [225] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */
540 [226] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */
541 [227] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */
542 [228] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
543 [229] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */
544 [230] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */
545 [231] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */
546 [232] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */
547 [233] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */
548 [234] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */
549 [235] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */
550 [236] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */
551 [237] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */
552 [238] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */
553 [239] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */
554 [240] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */
555 [241] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */
556 [242] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */
557 [243] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */
558 [244] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */
559 [245] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */
560 [246] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */
561 [247] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */
562 [248] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */
563 [249] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */
564 [250] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */
565 [251] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */
566 [252] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */
567 [253] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */
568 [254] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */
569 [255] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */
570 [256] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */
571 [257] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */
572 [258] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */
573 [259] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */
574 [260] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */
575 [261] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */
576 [262] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */
577 [263] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */
578 [264] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */
579 [265] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */
580 [266] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */
581 [267] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */
582 [268] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */
583 [269] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */
584 [270] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */
585 [271] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */
586 [272] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */
587 [273] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */
588 [274] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */
589 [275] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */
590 [276] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */
591 [277] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */
592 [278] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */
593 [279] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */
594 [280] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */
595 [281] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */
596 [282] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */
597 [283] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */
598 [284] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */
599 [285] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */
600 [286] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */
601 [287] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */
602 [288] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */
603 [289] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */
604 [290] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */
605 [291] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
606 [292] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */
607 [293] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */
608 [294] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */
609 [295] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */
610 [296] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */
611 [297] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */
612 [298] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
613 [299] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */
614 [300] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */
615 [301] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */
616 [302] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */
617 [303] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */
618 [304] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */
619 [305] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */
620 [306] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */
621 [307] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */
622 [308] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */
623 [309] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */
624 [310] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */
625 [311] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */
626 [312] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */
627 [313] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */
628 [314] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */
629 [315] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */
630 [316] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */
631 [317] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */
632 [318] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */
633 [319] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */
634 [320] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */
635 [321] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */
636 [322] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */
637 [323] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */
638 [324] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */
639 [325] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */
640 [326] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */
641 [327] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */
642 [328] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */
643 [329] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */
644 [330] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */
645 [331] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */
646 [332] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */
647 [333] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */
648 [334] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */
649 [335] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */
650 [336] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */
651 [337] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */
652 [338] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */
653 [339] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */
654 [340] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */
655 [341] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */
656 [342] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */
657 [343] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */
658 [344] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */
659 [345] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */
660 [346] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */
661 [347] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */
662 [348] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */
663 [349] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */
664 [350] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */
665 [351] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */
666 [352] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */
667 [353] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */
668 [354] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */
669 [355] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */
670 [356] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */
671 [357] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */
672 [358] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */
673 [359] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */
674 [360] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */
675 [361] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */
676 [362] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */
677 [363] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */
678 [364] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */
679 [365] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */
680 [366] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */
681 [367] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */
682 [368] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */
683 [369] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */
684 [370] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */
685 [371] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */
686 [372] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */
687 [373] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */
688 [374] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */
689 [375] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */
690 [376] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */
691 [377] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */
692 [378] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */
693 [379] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */
694 [380] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */
695 [381] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */
696 [382] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */
697 [383] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */
698 [384] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */
699 [385] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */
700 [386] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */
701 [387] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */
702 [388] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */
703 [389] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */
704 [390] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */
705 [391] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */
706 [392] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */
707 [393] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */
708 [394] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */
709 [395] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */
710 [396] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */
711 [397] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */
712 [398] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */
713 [399] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */
714 [400] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */
715 [401] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */
716 [402] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */
717 [403] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */
718 [404] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */
719 [405] = IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */
720 [406] = IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */
721 [407] = IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */
722 [408] = IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */
723 [409] = IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */
724 [410] = IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */
725 [411] = IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */
726 [412] = IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */
727 [413] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */
728 [414] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */
729 [415] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */
730 [416] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */
731 [417] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */
732 [418] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */
733 [419] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */
734 [420] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */
735 [421] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */
736 [422] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */
737 [423] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */
738 [424] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */
739 [425] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */
740 [426] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */
741 [427] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */
742 [428] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */
743 [429] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */
744 [430] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */
745 [431] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */
746 [432] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */
747 [433] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */
748 [434] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */
749 [435] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */
750 [436] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */
751 [437] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */
752 [438] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */
753 [439] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */
754 [440] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */
755 [441] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */
756 [442] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */
757 [443] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */
758 [444] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */
759 [445] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */
760 [446] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */
761 [447] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */
762 [448] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */
763 [449] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */
764 [450] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */
765 [451] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */
766 [452] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */
767 [453] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */
768 [454] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */
769 [455] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */
770 [456] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */
771 [457] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */
772 [458] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */
773 [459] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */
774 [460] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */
775 [461] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */
776 [462] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */
777 [463] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */
778 [464] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */
779 [465] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */
780 [466] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */
781 [467] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */
782 [468] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */
783 [469] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */
784 [470] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */
785 [471] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */
786 [472] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */
787 [473] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */
788 [474] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */
789 [475] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */
790 [476] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */
791 [477] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */
792 [478] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */
793 [479] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */
794 [480] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */
795 [481] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */
796 [482] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */
797 [483] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */
798 [484] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */
799 [485] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */
800 [486] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */
801 [487] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */
802 [488] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */
803 [489] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */
804 [490] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */
805 [491] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */
806 [492] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */
807 [493] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */
808 [494] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */
809 [495] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */
810 [496] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */
811 [497] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */
812 [498] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */
813 [499] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */
814 [500] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */
815 [501] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */
816 [502] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */
817 [503] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */
818 [504] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */
819 [505] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */
820 [506] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */
821 [507] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */
822 [508] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */
823 [509] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */
824 [510] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */
825 [511] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */
826 [512] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */
827 [513] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */
828 [514] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */
829 [515] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */
830 [516] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */
831 [517] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */
832 [518] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */
833 [519] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */
834 [520] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */
835 [521] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */
836 [522] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */
837 [523] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */
838 [524] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */
839 [525] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */
840 [526] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */
841 [527] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */
842 [528] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */
843 [529] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */
844 [530] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */
845 [531] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */
846 [532] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */
847 [533] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */
848 [534] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */
849 [535] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */
850 [536] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */
851 [537] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */
852 [538] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */
853 [539] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */
854 [540] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */
855 [541] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */
856 [542] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */
857 [543] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */
858 [544] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */
859 [545] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */
860 [546] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */
861 [547] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */
862 [548] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */
863 [549] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */
864 [550] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */
865 [551] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */
866 [552] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */
867 [553] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */
868 [554] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */
869 [555] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */
870 [556] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */
871 [557] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */
872 [558] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */
873 [559] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */
874 [560] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */
875 [561] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */
876 [562] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */
877 [563] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */
878 [564] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */
879 [565] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */
880 [566] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */
881 [567] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */
882 [568] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */
883 [569] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */
884 [570] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */
885 [571] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */
886 [572] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */
887 [573] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */
888 [574] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */
889 [575] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */
890 [576] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */
891 [577] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */
892 [578] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */
893 [579] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */
894 [580] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */
895 [581] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */
896 [582] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */
897 [583] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */
898 [584] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */
899 [585] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */
900 [586] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */
901 [587] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */
902 [588] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */
903 [589] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */
904 [590] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */
905 [591] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */
906 [592] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */
907 [593] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */
908 [594] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */
909 [595] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */
910 [596] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */
911 [597] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */
912 [598] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */
913 [599] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */
914 [600] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */
915 [601] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */
916 [602] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */
917 [603] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */
918 [604] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */
919 [605] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */
920 [606] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */
921 [607] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */
922 [608] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */
923 [609] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */
924 [610] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */
925 [611] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */
926 [612] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */
927 [613] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */
928 [614] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */
929 [615] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */
930 [616] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */
931 [617] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */
932 [618] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */
933 [619] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */
934 [620] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */
935 [621] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */
936 [622] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */
937 [623] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */
938 [624] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */
939 [625] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */
940 [626] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */
941 [627] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */
942 [628] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */
943 [629] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */
944 [630] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */
945 [631] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */
946 [632] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */
947 [633] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */
948 [634] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */
949 [635] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */
950 [636] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */
951 [637] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */
952 [638] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */
953 [639] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */
954 [640] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */
955 [641] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */
956 [642] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */
957 [643] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */
958 [644] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */
959 [645] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */
960 [646] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */
961 [647] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */
962 [648] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */
963 [649] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */
964 [650] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */
965 [651] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */
966 [652] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */
967 [653] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */
968 [654] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */
969 [655] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */
970 [656] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */
971 [657] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */
972 [658] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */
973 [659] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */
974 [660] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */
975 [661] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */
976 [662] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */
977 [663] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */
978 [664] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */
979 [665] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */
980 [666] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */
981 [667] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */
982 [668] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */
983 [669] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */
984 [670] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */
985 [671] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */
986 [672] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */
987 [673] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */
988 [674] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */
989 [675] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */
990 [676] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */
991 [677] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */
992 [678] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */
993 [679] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */
994 [680] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */
995 [681] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */
996 [682] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */
997 [683] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */
998 [684] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */
999 [685] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */
1000 [686] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */
1001 [687] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */
1002 [688] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */
1003 [689] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */
1004 [690] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */
1005 [691] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */
1006 [692] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */
1007 [693] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */
1008 [694] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */
1009 [695] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */
1010 [696] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */
1011 [697] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */
1012 [698] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */
1013 [699] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */
1014 [700] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */
1015 [701] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */
1016 [702] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */
1017 [703] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */
1018 [704] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */
1019 [705] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */
1020 [706] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */
1021 [707] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */
1022 [708] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */
1023 [709] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */
1024 [710] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */
1025 [711] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */
1026 [712] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */
1027 [713] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */
1028 [714] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */
1029 [715] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */
1030 [716] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */
1031 [717] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */
1032 [718] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */
1033 [719] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */
1034 [720] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */
1035 [721] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */
1036 [722] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */
1037 [723] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */
1038 [724] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */
1039 [725] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */
1040 [726] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */
1041 [727] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */
1042 [728] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */
1043 [729] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */
1044 [730] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */
1045 [731] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */
1046 [732] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */
1047 [733] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */
1048 [734] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */
1049 [735] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */
1050 [736] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */
1051 [737] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */
1052 [738] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */
1053 [739] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */
1054 [740] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */
1055 [741] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */
1056 [742] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */
1057 [743] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */
1058 [744] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */
1059 [745] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */
1060 [746] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */
1061 [747] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */
1062 [748] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */
1063 [749] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */
1064 [750] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */
1065 [751] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */
1066 [752] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */
1067 [753] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */
1068 [754] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */
1069 [755] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */
1070 [756] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */
1071 [757] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */
1072 [758] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */
1073 [759] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */
1074 [760] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */
1075 [761] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */
1076 [762] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */
1077 [763] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */
1078 [764] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */
1079 [765] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */
1080 [766] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */
1081 [767] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */
1082 [768] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */
1083 [769] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */
1084 [770] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */
1085 [771] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */
1086 [772] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */
1087 [773] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */
1088 [774] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */
1089 [775] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */
1090 [776] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */
1091 [777] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */
1092 [778] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */
1093 [779] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */
1094 [780] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */
1095 [781] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */
1096 [782] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */
1097 [783] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */
1098 [784] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */
1099 [785] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */
1100 [786] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */
1101 [787] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */
1102 [788] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */
1103 [789] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */
1104 [790] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */
1105 [791] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */
1106 [792] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */
1107 [793] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */
1108 [794] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */
1109 [795] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */
1110 [796] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */
1111 [797] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */
1112 [798] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */
1113 [799] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */
1114 [800] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */
1115 [801] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */
1116 [802] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */
1117 [803] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */
1118 [804] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */
1119 [805] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */
1120 [806] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */
1121 [807] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */
1122 [808] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */
1123 [809] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */
1124 [810] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */
1125 [811] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */
1126 [812] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */
1127 [813] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */
1128 [814] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */
1129 [815] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */
1130 [816] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */
1131 [817] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */
1132 [818] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */
1133 [819] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */
1134 [820] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */
1135 [821] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */
1136 [822] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */
1137 [823] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */
1138 [824] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */
1139 [825] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */
1140 [826] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */
1141 [827] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */
1142 [828] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */
1143 [829] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */
1144 [830] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */
1145 [831] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */
1146 [832] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */
1147 [833] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */
1148 [834] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */
1149 [835] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */
1150 [836] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */
1151 [837] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */
1152 [838] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */
1153 [839] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */
1154 [840] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */
1155 [841] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */
1156 [842] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */
1157 [843] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */
1158 [844] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */
1159 [845] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */
1160 [846] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */
1161 [847] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */
1162 [848] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */
1163 [849] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */
1164 [850] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */
1165 [851] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */
1166 [852] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */
1167 [853] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */
1168 [854] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */
1169 [855] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */
1170 [856] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */
1171 [857] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */
1172 [858] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */
1173 [859] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */
1174 [860] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */
1175 [861] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */
1176 [862] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */
1177 [863] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */
1178 [864] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */
1179 [865] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */
1180 [866] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */
1181 [867] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */
1182 [868] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */
1183 [869] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */
1184 [870] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */
1185 [871] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */
1186 [872] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */
1187 [873] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */
1188 [874] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */
1189 [875] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */
1190 [876] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */
1191 [877] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */
1192 [878] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */
1193 [879] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */
1194 [880] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */
1195 [881] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */
1196 [882] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */
1197 [883] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */
1198 [884] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */
1199 [885] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */
1200 [886] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */
1201 [887] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */
1202 [888] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */
1203 [889] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */
1204 [890] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */
1205 [891] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */
1206 [892] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */
1207 [893] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */
1208 [894] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */
1209 [895] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */
1210 [896] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */
1211 [897] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */
1212 [898] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */
1213 [899] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */
1214 [900] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */
1215 [901] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */
1216 [902] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */
1217 [903] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */
1218 [904] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */
1219 [905] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */
1220 [906] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */
1221 [907] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */
1222 [908] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */
1223 [909] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */
1224 [910] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */
1225 [911] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */
1226 [912] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */
1227 [913] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */
1228 [914] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */
1229 [915] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */
1230 [916] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */
1231 [917] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */
1232 [918] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */
1233 [919] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */
1234 [920] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */
1235 [921] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */
1236 [922] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */
1237 [923] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */
1238 [924] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */
1239 [925] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */
1240 [926] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */
1241 [927] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */
1242 [928] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */
1243 [929] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */
1244 [930] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */
1245 [931] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */
1246 [932] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */
1247 [933] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */
1248 [934] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */
1249 [935] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */
1250 [936] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */
1251 [937] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */
1252 [938] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */
1253 [939] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */
1254 [940] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */
1255 [941] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */
1256 [942] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */
1257 [943] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */
1258 [944] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */
1259 [945] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */
1260 [946] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */
1261 [947] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */
1262 [948] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */
1263 [949] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */
1264 [950] = IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */
1265 [951] = IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */
1266};
1267
1268/* Pad names for the pinmux subsystem */
1269static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
1270 IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
1271 IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
1272 IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
1273 IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
1274 IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
1275 IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
1276 IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
1277 IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
1278 IMX_PINCTRL_PIN(MX35_PAD_POR_B),
1279 IMX_PINCTRL_PIN(MX35_PAD_CLKO),
1280 IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
1281 IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
1282 IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
1283 IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
1284 IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
1285 IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
1286 IMX_PINCTRL_PIN(MX35_PAD_A0),
1287 IMX_PINCTRL_PIN(MX35_PAD_A1),
1288 IMX_PINCTRL_PIN(MX35_PAD_A2),
1289 IMX_PINCTRL_PIN(MX35_PAD_A3),
1290 IMX_PINCTRL_PIN(MX35_PAD_A4),
1291 IMX_PINCTRL_PIN(MX35_PAD_A5),
1292 IMX_PINCTRL_PIN(MX35_PAD_A6),
1293 IMX_PINCTRL_PIN(MX35_PAD_A7),
1294 IMX_PINCTRL_PIN(MX35_PAD_A8),
1295 IMX_PINCTRL_PIN(MX35_PAD_A9),
1296 IMX_PINCTRL_PIN(MX35_PAD_A10),
1297 IMX_PINCTRL_PIN(MX35_PAD_MA10),
1298 IMX_PINCTRL_PIN(MX35_PAD_A11),
1299 IMX_PINCTRL_PIN(MX35_PAD_A12),
1300 IMX_PINCTRL_PIN(MX35_PAD_A13),
1301 IMX_PINCTRL_PIN(MX35_PAD_A14),
1302 IMX_PINCTRL_PIN(MX35_PAD_A15),
1303 IMX_PINCTRL_PIN(MX35_PAD_A16),
1304 IMX_PINCTRL_PIN(MX35_PAD_A17),
1305 IMX_PINCTRL_PIN(MX35_PAD_A18),
1306 IMX_PINCTRL_PIN(MX35_PAD_A19),
1307 IMX_PINCTRL_PIN(MX35_PAD_A20),
1308 IMX_PINCTRL_PIN(MX35_PAD_A21),
1309 IMX_PINCTRL_PIN(MX35_PAD_A22),
1310 IMX_PINCTRL_PIN(MX35_PAD_A23),
1311 IMX_PINCTRL_PIN(MX35_PAD_A24),
1312 IMX_PINCTRL_PIN(MX35_PAD_A25),
1313 IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
1314 IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
1315 IMX_PINCTRL_PIN(MX35_PAD_SD0),
1316 IMX_PINCTRL_PIN(MX35_PAD_SD1),
1317 IMX_PINCTRL_PIN(MX35_PAD_SD2),
1318 IMX_PINCTRL_PIN(MX35_PAD_SD3),
1319 IMX_PINCTRL_PIN(MX35_PAD_SD4),
1320 IMX_PINCTRL_PIN(MX35_PAD_SD5),
1321 IMX_PINCTRL_PIN(MX35_PAD_SD6),
1322 IMX_PINCTRL_PIN(MX35_PAD_SD7),
1323 IMX_PINCTRL_PIN(MX35_PAD_SD8),
1324 IMX_PINCTRL_PIN(MX35_PAD_SD9),
1325 IMX_PINCTRL_PIN(MX35_PAD_SD10),
1326 IMX_PINCTRL_PIN(MX35_PAD_SD11),
1327 IMX_PINCTRL_PIN(MX35_PAD_SD12),
1328 IMX_PINCTRL_PIN(MX35_PAD_SD13),
1329 IMX_PINCTRL_PIN(MX35_PAD_SD14),
1330 IMX_PINCTRL_PIN(MX35_PAD_SD15),
1331 IMX_PINCTRL_PIN(MX35_PAD_SD16),
1332 IMX_PINCTRL_PIN(MX35_PAD_SD17),
1333 IMX_PINCTRL_PIN(MX35_PAD_SD18),
1334 IMX_PINCTRL_PIN(MX35_PAD_SD19),
1335 IMX_PINCTRL_PIN(MX35_PAD_SD20),
1336 IMX_PINCTRL_PIN(MX35_PAD_SD21),
1337 IMX_PINCTRL_PIN(MX35_PAD_SD22),
1338 IMX_PINCTRL_PIN(MX35_PAD_SD23),
1339 IMX_PINCTRL_PIN(MX35_PAD_SD24),
1340 IMX_PINCTRL_PIN(MX35_PAD_SD25),
1341 IMX_PINCTRL_PIN(MX35_PAD_SD26),
1342 IMX_PINCTRL_PIN(MX35_PAD_SD27),
1343 IMX_PINCTRL_PIN(MX35_PAD_SD28),
1344 IMX_PINCTRL_PIN(MX35_PAD_SD29),
1345 IMX_PINCTRL_PIN(MX35_PAD_SD30),
1346 IMX_PINCTRL_PIN(MX35_PAD_SD31),
1347 IMX_PINCTRL_PIN(MX35_PAD_DQM0),
1348 IMX_PINCTRL_PIN(MX35_PAD_DQM1),
1349 IMX_PINCTRL_PIN(MX35_PAD_DQM2),
1350 IMX_PINCTRL_PIN(MX35_PAD_DQM3),
1351 IMX_PINCTRL_PIN(MX35_PAD_EB0),
1352 IMX_PINCTRL_PIN(MX35_PAD_EB1),
1353 IMX_PINCTRL_PIN(MX35_PAD_OE),
1354 IMX_PINCTRL_PIN(MX35_PAD_CS0),
1355 IMX_PINCTRL_PIN(MX35_PAD_CS1),
1356 IMX_PINCTRL_PIN(MX35_PAD_CS2),
1357 IMX_PINCTRL_PIN(MX35_PAD_CS3),
1358 IMX_PINCTRL_PIN(MX35_PAD_CS4),
1359 IMX_PINCTRL_PIN(MX35_PAD_CS5),
1360 IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
1361 IMX_PINCTRL_PIN(MX35_PAD_ECB),
1362 IMX_PINCTRL_PIN(MX35_PAD_LBA),
1363 IMX_PINCTRL_PIN(MX35_PAD_BCLK),
1364 IMX_PINCTRL_PIN(MX35_PAD_RW),
1365 IMX_PINCTRL_PIN(MX35_PAD_RAS),
1366 IMX_PINCTRL_PIN(MX35_PAD_CAS),
1367 IMX_PINCTRL_PIN(MX35_PAD_SDWE),
1368 IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
1369 IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
1370 IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
1371 IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
1372 IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
1373 IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
1374 IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
1375 IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
1376 IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
1377 IMX_PINCTRL_PIN(MX35_PAD_NFALE),
1378 IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
1379 IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
1380 IMX_PINCTRL_PIN(MX35_PAD_NFRB),
1381 IMX_PINCTRL_PIN(MX35_PAD_D15),
1382 IMX_PINCTRL_PIN(MX35_PAD_D14),
1383 IMX_PINCTRL_PIN(MX35_PAD_D13),
1384 IMX_PINCTRL_PIN(MX35_PAD_D12),
1385 IMX_PINCTRL_PIN(MX35_PAD_D11),
1386 IMX_PINCTRL_PIN(MX35_PAD_D10),
1387 IMX_PINCTRL_PIN(MX35_PAD_D9),
1388 IMX_PINCTRL_PIN(MX35_PAD_D8),
1389 IMX_PINCTRL_PIN(MX35_PAD_D7),
1390 IMX_PINCTRL_PIN(MX35_PAD_D6),
1391 IMX_PINCTRL_PIN(MX35_PAD_D5),
1392 IMX_PINCTRL_PIN(MX35_PAD_D4),
1393 IMX_PINCTRL_PIN(MX35_PAD_D3),
1394 IMX_PINCTRL_PIN(MX35_PAD_D2),
1395 IMX_PINCTRL_PIN(MX35_PAD_D1),
1396 IMX_PINCTRL_PIN(MX35_PAD_D0),
1397 IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
1398 IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
1399 IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
1400 IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
1401 IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
1402 IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
1403 IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
1404 IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
1405 IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
1406 IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
1407 IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
1408 IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
1409 IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
1410 IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
1411 IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
1412 IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
1413 IMX_PINCTRL_PIN(MX35_PAD_STXD4),
1414 IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
1415 IMX_PINCTRL_PIN(MX35_PAD_SCK4),
1416 IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
1417 IMX_PINCTRL_PIN(MX35_PAD_STXD5),
1418 IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
1419 IMX_PINCTRL_PIN(MX35_PAD_SCK5),
1420 IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
1421 IMX_PINCTRL_PIN(MX35_PAD_SCKR),
1422 IMX_PINCTRL_PIN(MX35_PAD_FSR),
1423 IMX_PINCTRL_PIN(MX35_PAD_HCKR),
1424 IMX_PINCTRL_PIN(MX35_PAD_SCKT),
1425 IMX_PINCTRL_PIN(MX35_PAD_FST),
1426 IMX_PINCTRL_PIN(MX35_PAD_HCKT),
1427 IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
1428 IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
1429 IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
1430 IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
1431 IMX_PINCTRL_PIN(MX35_PAD_TX1),
1432 IMX_PINCTRL_PIN(MX35_PAD_TX0),
1433 IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
1434 IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
1435 IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
1436 IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
1437 IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
1438 IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
1439 IMX_PINCTRL_PIN(MX35_PAD_RXD1),
1440 IMX_PINCTRL_PIN(MX35_PAD_TXD1),
1441 IMX_PINCTRL_PIN(MX35_PAD_RTS1),
1442 IMX_PINCTRL_PIN(MX35_PAD_CTS1),
1443 IMX_PINCTRL_PIN(MX35_PAD_RXD2),
1444 IMX_PINCTRL_PIN(MX35_PAD_TXD2),
1445 IMX_PINCTRL_PIN(MX35_PAD_RTS2),
1446 IMX_PINCTRL_PIN(MX35_PAD_CTS2),
1447 IMX_PINCTRL_PIN(MX35_PAD_RTCK),
1448 IMX_PINCTRL_PIN(MX35_PAD_TCK),
1449 IMX_PINCTRL_PIN(MX35_PAD_TMS),
1450 IMX_PINCTRL_PIN(MX35_PAD_TDI),
1451 IMX_PINCTRL_PIN(MX35_PAD_TDO),
1452 IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
1453 IMX_PINCTRL_PIN(MX35_PAD_DE_B),
1454 IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
1455 IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
1456 IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
1457 IMX_PINCTRL_PIN(MX35_PAD_LD0),
1458 IMX_PINCTRL_PIN(MX35_PAD_LD1),
1459 IMX_PINCTRL_PIN(MX35_PAD_LD2),
1460 IMX_PINCTRL_PIN(MX35_PAD_LD3),
1461 IMX_PINCTRL_PIN(MX35_PAD_LD4),
1462 IMX_PINCTRL_PIN(MX35_PAD_LD5),
1463 IMX_PINCTRL_PIN(MX35_PAD_LD6),
1464 IMX_PINCTRL_PIN(MX35_PAD_LD7),
1465 IMX_PINCTRL_PIN(MX35_PAD_LD8),
1466 IMX_PINCTRL_PIN(MX35_PAD_LD9),
1467 IMX_PINCTRL_PIN(MX35_PAD_LD10),
1468 IMX_PINCTRL_PIN(MX35_PAD_LD11),
1469 IMX_PINCTRL_PIN(MX35_PAD_LD12),
1470 IMX_PINCTRL_PIN(MX35_PAD_LD13),
1471 IMX_PINCTRL_PIN(MX35_PAD_LD14),
1472 IMX_PINCTRL_PIN(MX35_PAD_LD15),
1473 IMX_PINCTRL_PIN(MX35_PAD_LD16),
1474 IMX_PINCTRL_PIN(MX35_PAD_LD17),
1475 IMX_PINCTRL_PIN(MX35_PAD_LD18),
1476 IMX_PINCTRL_PIN(MX35_PAD_LD19),
1477 IMX_PINCTRL_PIN(MX35_PAD_LD20),
1478 IMX_PINCTRL_PIN(MX35_PAD_LD21),
1479 IMX_PINCTRL_PIN(MX35_PAD_LD22),
1480 IMX_PINCTRL_PIN(MX35_PAD_LD23),
1481 IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
1482 IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
1483 IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
1484 IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
1485 IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
1486 IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
1487 IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
1488 IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
1489 IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
1490 IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
1491 IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
1492 IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
1493 IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
1494 IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
1495 IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
1496 IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
1497 IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
1498 IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
1499 IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
1500 IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
1501 IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
1502 IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
1503 IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
1504 IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
1505 IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
1506 IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
1507 IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
1508 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
1509 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
1510 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
1511 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
1512 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
1513 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
1514 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
1515 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
1516 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
1517 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
1518 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
1519 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
1520 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
1521 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
1522 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
1523 IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
1524 IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
1525 IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
1526 IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
1527 IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
1528 IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
1529 IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
1530 IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
1531 IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
1532 IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
1533 IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
1534 IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
1535 IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
1536 IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
1537 IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
1538 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
1539 IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
1540 IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
1541 IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
1542 IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
1543 IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
1544 IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
1545 IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
1546 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
1547 IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
1548 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
1549 IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
1550 IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
1551 IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
1552 IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
1553};
1554
1555static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
1556 .pins = imx35_pinctrl_pads,
1557 .npins = ARRAY_SIZE(imx35_pinctrl_pads),
1558 .pin_regs = imx35_pin_regs,
1559 .npin_regs = ARRAY_SIZE(imx35_pin_regs),
1560};
1561
1562static struct of_device_id imx35_pinctrl_of_match[] __devinitdata = {
1563 { .compatible = "fsl,imx35-iomuxc", },
1564 { /* sentinel */ }
1565};
1566
1567static int __devinit imx35_pinctrl_probe(struct platform_device *pdev)
1568{
1569 return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
1570}
1571
1572static struct platform_driver imx35_pinctrl_driver = {
1573 .driver = {
1574 .name = "imx35-pinctrl",
1575 .owner = THIS_MODULE,
1576 .of_match_table = of_match_ptr(imx35_pinctrl_of_match),
1577 },
1578 .probe = imx35_pinctrl_probe,
1579 .remove = __devexit_p(imx_pinctrl_remove),
1580};
1581
1582static int __init imx35_pinctrl_init(void)
1583{
1584 return platform_driver_register(&imx35_pinctrl_driver);
1585}
1586arch_initcall(imx35_pinctrl_init);
1587
1588static void __exit imx35_pinctrl_exit(void)
1589{
1590 platform_driver_unregister(&imx35_pinctrl_driver);
1591}
1592module_exit(imx35_pinctrl_exit);
1593MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
1594MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
1595MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index 9fd02162a3c2..fb8468966779 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -23,251 +23,251 @@
23#include "pinctrl-imx.h" 23#include "pinctrl-imx.h"
24 24
25enum imx51_pads { 25enum imx51_pads {
26 MX51_PAD_EIM_D16 = 1, 26 MX51_PAD_EIM_D16 = 0,
27 MX51_PAD_EIM_D17 = 2, 27 MX51_PAD_EIM_D17 = 1,
28 MX51_PAD_EIM_D18 = 3, 28 MX51_PAD_EIM_D18 = 2,
29 MX51_PAD_EIM_D19 = 4, 29 MX51_PAD_EIM_D19 = 3,
30 MX51_PAD_EIM_D20 = 5, 30 MX51_PAD_EIM_D20 = 4,
31 MX51_PAD_EIM_D21 = 6, 31 MX51_PAD_EIM_D21 = 5,
32 MX51_PAD_EIM_D22 = 7, 32 MX51_PAD_EIM_D22 = 6,
33 MX51_PAD_EIM_D23 = 8, 33 MX51_PAD_EIM_D23 = 7,
34 MX51_PAD_EIM_D24 = 9, 34 MX51_PAD_EIM_D24 = 8,
35 MX51_PAD_EIM_D25 = 10, 35 MX51_PAD_EIM_D25 = 9,
36 MX51_PAD_EIM_D26 = 11, 36 MX51_PAD_EIM_D26 = 10,
37 MX51_PAD_EIM_D27 = 12, 37 MX51_PAD_EIM_D27 = 11,
38 MX51_PAD_EIM_D28 = 13, 38 MX51_PAD_EIM_D28 = 12,
39 MX51_PAD_EIM_D29 = 14, 39 MX51_PAD_EIM_D29 = 13,
40 MX51_PAD_EIM_D30 = 15, 40 MX51_PAD_EIM_D30 = 14,
41 MX51_PAD_EIM_D31 = 16, 41 MX51_PAD_EIM_D31 = 15,
42 MX51_PAD_EIM_A16 = 17, 42 MX51_PAD_EIM_A16 = 16,
43 MX51_PAD_EIM_A17 = 18, 43 MX51_PAD_EIM_A17 = 17,
44 MX51_PAD_EIM_A18 = 19, 44 MX51_PAD_EIM_A18 = 18,
45 MX51_PAD_EIM_A19 = 20, 45 MX51_PAD_EIM_A19 = 19,
46 MX51_PAD_EIM_A20 = 21, 46 MX51_PAD_EIM_A20 = 20,
47 MX51_PAD_EIM_A21 = 22, 47 MX51_PAD_EIM_A21 = 21,
48 MX51_PAD_EIM_A22 = 23, 48 MX51_PAD_EIM_A22 = 22,
49 MX51_PAD_EIM_A23 = 24, 49 MX51_PAD_EIM_A23 = 23,
50 MX51_PAD_EIM_A24 = 25, 50 MX51_PAD_EIM_A24 = 24,
51 MX51_PAD_EIM_A25 = 26, 51 MX51_PAD_EIM_A25 = 25,
52 MX51_PAD_EIM_A26 = 27, 52 MX51_PAD_EIM_A26 = 26,
53 MX51_PAD_EIM_A27 = 28, 53 MX51_PAD_EIM_A27 = 27,
54 MX51_PAD_EIM_EB0 = 29, 54 MX51_PAD_EIM_EB0 = 28,
55 MX51_PAD_EIM_EB1 = 30, 55 MX51_PAD_EIM_EB1 = 29,
56 MX51_PAD_EIM_EB2 = 31, 56 MX51_PAD_EIM_EB2 = 30,
57 MX51_PAD_EIM_EB3 = 32, 57 MX51_PAD_EIM_EB3 = 31,
58 MX51_PAD_EIM_OE = 33, 58 MX51_PAD_EIM_OE = 32,
59 MX51_PAD_EIM_CS0 = 34, 59 MX51_PAD_EIM_CS0 = 33,
60 MX51_PAD_EIM_CS1 = 35, 60 MX51_PAD_EIM_CS1 = 34,
61 MX51_PAD_EIM_CS2 = 36, 61 MX51_PAD_EIM_CS2 = 35,
62 MX51_PAD_EIM_CS3 = 37, 62 MX51_PAD_EIM_CS3 = 36,
63 MX51_PAD_EIM_CS4 = 38, 63 MX51_PAD_EIM_CS4 = 37,
64 MX51_PAD_EIM_CS5 = 39, 64 MX51_PAD_EIM_CS5 = 38,
65 MX51_PAD_EIM_DTACK = 40, 65 MX51_PAD_EIM_DTACK = 39,
66 MX51_PAD_EIM_LBA = 41, 66 MX51_PAD_EIM_LBA = 40,
67 MX51_PAD_EIM_CRE = 42, 67 MX51_PAD_EIM_CRE = 41,
68 MX51_PAD_DRAM_CS1 = 43, 68 MX51_PAD_DRAM_CS1 = 42,
69 MX51_PAD_NANDF_WE_B = 44, 69 MX51_PAD_NANDF_WE_B = 43,
70 MX51_PAD_NANDF_RE_B = 45, 70 MX51_PAD_NANDF_RE_B = 44,
71 MX51_PAD_NANDF_ALE = 46, 71 MX51_PAD_NANDF_ALE = 45,
72 MX51_PAD_NANDF_CLE = 47, 72 MX51_PAD_NANDF_CLE = 46,
73 MX51_PAD_NANDF_WP_B = 48, 73 MX51_PAD_NANDF_WP_B = 47,
74 MX51_PAD_NANDF_RB0 = 49, 74 MX51_PAD_NANDF_RB0 = 48,
75 MX51_PAD_NANDF_RB1 = 50, 75 MX51_PAD_NANDF_RB1 = 49,
76 MX51_PAD_NANDF_RB2 = 51, 76 MX51_PAD_NANDF_RB2 = 50,
77 MX51_PAD_NANDF_RB3 = 52, 77 MX51_PAD_NANDF_RB3 = 51,
78 MX51_PAD_GPIO_NAND = 53, 78 MX51_PAD_GPIO_NAND = 52,
79 MX51_PAD_NANDF_CS0 = 54, 79 MX51_PAD_NANDF_CS0 = 53,
80 MX51_PAD_NANDF_CS1 = 55, 80 MX51_PAD_NANDF_CS1 = 54,
81 MX51_PAD_NANDF_CS2 = 56, 81 MX51_PAD_NANDF_CS2 = 55,
82 MX51_PAD_NANDF_CS3 = 57, 82 MX51_PAD_NANDF_CS3 = 56,
83 MX51_PAD_NANDF_CS4 = 58, 83 MX51_PAD_NANDF_CS4 = 57,
84 MX51_PAD_NANDF_CS5 = 59, 84 MX51_PAD_NANDF_CS5 = 58,
85 MX51_PAD_NANDF_CS6 = 60, 85 MX51_PAD_NANDF_CS6 = 59,
86 MX51_PAD_NANDF_CS7 = 61, 86 MX51_PAD_NANDF_CS7 = 60,
87 MX51_PAD_NANDF_RDY_INT = 62, 87 MX51_PAD_NANDF_RDY_INT = 61,
88 MX51_PAD_NANDF_D15 = 63, 88 MX51_PAD_NANDF_D15 = 62,
89 MX51_PAD_NANDF_D14 = 64, 89 MX51_PAD_NANDF_D14 = 63,
90 MX51_PAD_NANDF_D13 = 65, 90 MX51_PAD_NANDF_D13 = 64,
91 MX51_PAD_NANDF_D12 = 66, 91 MX51_PAD_NANDF_D12 = 65,
92 MX51_PAD_NANDF_D11 = 67, 92 MX51_PAD_NANDF_D11 = 66,
93 MX51_PAD_NANDF_D10 = 68, 93 MX51_PAD_NANDF_D10 = 67,
94 MX51_PAD_NANDF_D9 = 69, 94 MX51_PAD_NANDF_D9 = 68,
95 MX51_PAD_NANDF_D8 = 70, 95 MX51_PAD_NANDF_D8 = 69,
96 MX51_PAD_NANDF_D7 = 71, 96 MX51_PAD_NANDF_D7 = 70,
97 MX51_PAD_NANDF_D6 = 72, 97 MX51_PAD_NANDF_D6 = 71,
98 MX51_PAD_NANDF_D5 = 73, 98 MX51_PAD_NANDF_D5 = 72,
99 MX51_PAD_NANDF_D4 = 74, 99 MX51_PAD_NANDF_D4 = 73,
100 MX51_PAD_NANDF_D3 = 75, 100 MX51_PAD_NANDF_D3 = 74,
101 MX51_PAD_NANDF_D2 = 76, 101 MX51_PAD_NANDF_D2 = 75,
102 MX51_PAD_NANDF_D1 = 77, 102 MX51_PAD_NANDF_D1 = 76,
103 MX51_PAD_NANDF_D0 = 78, 103 MX51_PAD_NANDF_D0 = 77,
104 MX51_PAD_CSI1_D8 = 79, 104 MX51_PAD_CSI1_D8 = 78,
105 MX51_PAD_CSI1_D9 = 80, 105 MX51_PAD_CSI1_D9 = 79,
106 MX51_PAD_CSI1_D10 = 81, 106 MX51_PAD_CSI1_D10 = 80,
107 MX51_PAD_CSI1_D11 = 82, 107 MX51_PAD_CSI1_D11 = 81,
108 MX51_PAD_CSI1_D12 = 83, 108 MX51_PAD_CSI1_D12 = 82,
109 MX51_PAD_CSI1_D13 = 84, 109 MX51_PAD_CSI1_D13 = 83,
110 MX51_PAD_CSI1_D14 = 85, 110 MX51_PAD_CSI1_D14 = 84,
111 MX51_PAD_CSI1_D15 = 86, 111 MX51_PAD_CSI1_D15 = 85,
112 MX51_PAD_CSI1_D16 = 87, 112 MX51_PAD_CSI1_D16 = 86,
113 MX51_PAD_CSI1_D17 = 88, 113 MX51_PAD_CSI1_D17 = 87,
114 MX51_PAD_CSI1_D18 = 89, 114 MX51_PAD_CSI1_D18 = 88,
115 MX51_PAD_CSI1_D19 = 90, 115 MX51_PAD_CSI1_D19 = 89,
116 MX51_PAD_CSI1_VSYNC = 91, 116 MX51_PAD_CSI1_VSYNC = 90,
117 MX51_PAD_CSI1_HSYNC = 92, 117 MX51_PAD_CSI1_HSYNC = 91,
118 MX51_PAD_CSI1_PIXCLK = 93, 118 MX51_PAD_CSI1_PIXCLK = 92,
119 MX51_PAD_CSI1_MCLK = 94, 119 MX51_PAD_CSI1_MCLK = 93,
120 MX51_PAD_CSI2_D12 = 95, 120 MX51_PAD_CSI2_D12 = 94,
121 MX51_PAD_CSI2_D13 = 96, 121 MX51_PAD_CSI2_D13 = 95,
122 MX51_PAD_CSI2_D14 = 97, 122 MX51_PAD_CSI2_D14 = 96,
123 MX51_PAD_CSI2_D15 = 98, 123 MX51_PAD_CSI2_D15 = 97,
124 MX51_PAD_CSI2_D16 = 99, 124 MX51_PAD_CSI2_D16 = 98,
125 MX51_PAD_CSI2_D17 = 100, 125 MX51_PAD_CSI2_D17 = 99,
126 MX51_PAD_CSI2_D18 = 101, 126 MX51_PAD_CSI2_D18 = 100,
127 MX51_PAD_CSI2_D19 = 102, 127 MX51_PAD_CSI2_D19 = 101,
128 MX51_PAD_CSI2_VSYNC = 103, 128 MX51_PAD_CSI2_VSYNC = 102,
129 MX51_PAD_CSI2_HSYNC = 104, 129 MX51_PAD_CSI2_HSYNC = 103,
130 MX51_PAD_CSI2_PIXCLK = 105, 130 MX51_PAD_CSI2_PIXCLK = 104,
131 MX51_PAD_I2C1_CLK = 106, 131 MX51_PAD_I2C1_CLK = 105,
132 MX51_PAD_I2C1_DAT = 107, 132 MX51_PAD_I2C1_DAT = 106,
133 MX51_PAD_AUD3_BB_TXD = 108, 133 MX51_PAD_AUD3_BB_TXD = 107,
134 MX51_PAD_AUD3_BB_RXD = 109, 134 MX51_PAD_AUD3_BB_RXD = 108,
135 MX51_PAD_AUD3_BB_CK = 110, 135 MX51_PAD_AUD3_BB_CK = 109,
136 MX51_PAD_AUD3_BB_FS = 111, 136 MX51_PAD_AUD3_BB_FS = 110,
137 MX51_PAD_CSPI1_MOSI = 112, 137 MX51_PAD_CSPI1_MOSI = 111,
138 MX51_PAD_CSPI1_MISO = 113, 138 MX51_PAD_CSPI1_MISO = 112,
139 MX51_PAD_CSPI1_SS0 = 114, 139 MX51_PAD_CSPI1_SS0 = 113,
140 MX51_PAD_CSPI1_SS1 = 115, 140 MX51_PAD_CSPI1_SS1 = 114,
141 MX51_PAD_CSPI1_RDY = 116, 141 MX51_PAD_CSPI1_RDY = 115,
142 MX51_PAD_CSPI1_SCLK = 117, 142 MX51_PAD_CSPI1_SCLK = 116,
143 MX51_PAD_UART1_RXD = 118, 143 MX51_PAD_UART1_RXD = 117,
144 MX51_PAD_UART1_TXD = 119, 144 MX51_PAD_UART1_TXD = 118,
145 MX51_PAD_UART1_RTS = 120, 145 MX51_PAD_UART1_RTS = 119,
146 MX51_PAD_UART1_CTS = 121, 146 MX51_PAD_UART1_CTS = 120,
147 MX51_PAD_UART2_RXD = 122, 147 MX51_PAD_UART2_RXD = 121,
148 MX51_PAD_UART2_TXD = 123, 148 MX51_PAD_UART2_TXD = 122,
149 MX51_PAD_UART3_RXD = 124, 149 MX51_PAD_UART3_RXD = 123,
150 MX51_PAD_UART3_TXD = 125, 150 MX51_PAD_UART3_TXD = 124,
151 MX51_PAD_OWIRE_LINE = 126, 151 MX51_PAD_OWIRE_LINE = 125,
152 MX51_PAD_KEY_ROW0 = 127, 152 MX51_PAD_KEY_ROW0 = 126,
153 MX51_PAD_KEY_ROW1 = 128, 153 MX51_PAD_KEY_ROW1 = 127,
154 MX51_PAD_KEY_ROW2 = 129, 154 MX51_PAD_KEY_ROW2 = 128,
155 MX51_PAD_KEY_ROW3 = 130, 155 MX51_PAD_KEY_ROW3 = 129,
156 MX51_PAD_KEY_COL0 = 131, 156 MX51_PAD_KEY_COL0 = 130,
157 MX51_PAD_KEY_COL1 = 132, 157 MX51_PAD_KEY_COL1 = 131,
158 MX51_PAD_KEY_COL2 = 133, 158 MX51_PAD_KEY_COL2 = 132,
159 MX51_PAD_KEY_COL3 = 134, 159 MX51_PAD_KEY_COL3 = 133,
160 MX51_PAD_KEY_COL4 = 135, 160 MX51_PAD_KEY_COL4 = 134,
161 MX51_PAD_KEY_COL5 = 136, 161 MX51_PAD_KEY_COL5 = 135,
162 MX51_PAD_USBH1_CLK = 137, 162 MX51_PAD_USBH1_CLK = 136,
163 MX51_PAD_USBH1_DIR = 138, 163 MX51_PAD_USBH1_DIR = 137,
164 MX51_PAD_USBH1_STP = 139, 164 MX51_PAD_USBH1_STP = 138,
165 MX51_PAD_USBH1_NXT = 140, 165 MX51_PAD_USBH1_NXT = 139,
166 MX51_PAD_USBH1_DATA0 = 141, 166 MX51_PAD_USBH1_DATA0 = 140,
167 MX51_PAD_USBH1_DATA1 = 142, 167 MX51_PAD_USBH1_DATA1 = 141,
168 MX51_PAD_USBH1_DATA2 = 143, 168 MX51_PAD_USBH1_DATA2 = 142,
169 MX51_PAD_USBH1_DATA3 = 144, 169 MX51_PAD_USBH1_DATA3 = 143,
170 MX51_PAD_USBH1_DATA4 = 145, 170 MX51_PAD_USBH1_DATA4 = 144,
171 MX51_PAD_USBH1_DATA5 = 146, 171 MX51_PAD_USBH1_DATA5 = 145,
172 MX51_PAD_USBH1_DATA6 = 147, 172 MX51_PAD_USBH1_DATA6 = 146,
173 MX51_PAD_USBH1_DATA7 = 148, 173 MX51_PAD_USBH1_DATA7 = 147,
174 MX51_PAD_DI1_PIN11 = 149, 174 MX51_PAD_DI1_PIN11 = 148,
175 MX51_PAD_DI1_PIN12 = 150, 175 MX51_PAD_DI1_PIN12 = 149,
176 MX51_PAD_DI1_PIN13 = 151, 176 MX51_PAD_DI1_PIN13 = 150,
177 MX51_PAD_DI1_D0_CS = 152, 177 MX51_PAD_DI1_D0_CS = 151,
178 MX51_PAD_DI1_D1_CS = 153, 178 MX51_PAD_DI1_D1_CS = 152,
179 MX51_PAD_DISPB2_SER_DIN = 154, 179 MX51_PAD_DISPB2_SER_DIN = 153,
180 MX51_PAD_DISPB2_SER_DIO = 155, 180 MX51_PAD_DISPB2_SER_DIO = 154,
181 MX51_PAD_DISPB2_SER_CLK = 156, 181 MX51_PAD_DISPB2_SER_CLK = 155,
182 MX51_PAD_DISPB2_SER_RS = 157, 182 MX51_PAD_DISPB2_SER_RS = 156,
183 MX51_PAD_DISP1_DAT0 = 158, 183 MX51_PAD_DISP1_DAT0 = 157,
184 MX51_PAD_DISP1_DAT1 = 159, 184 MX51_PAD_DISP1_DAT1 = 158,
185 MX51_PAD_DISP1_DAT2 = 160, 185 MX51_PAD_DISP1_DAT2 = 159,
186 MX51_PAD_DISP1_DAT3 = 161, 186 MX51_PAD_DISP1_DAT3 = 160,
187 MX51_PAD_DISP1_DAT4 = 162, 187 MX51_PAD_DISP1_DAT4 = 161,
188 MX51_PAD_DISP1_DAT5 = 163, 188 MX51_PAD_DISP1_DAT5 = 162,
189 MX51_PAD_DISP1_DAT6 = 164, 189 MX51_PAD_DISP1_DAT6 = 163,
190 MX51_PAD_DISP1_DAT7 = 165, 190 MX51_PAD_DISP1_DAT7 = 164,
191 MX51_PAD_DISP1_DAT8 = 166, 191 MX51_PAD_DISP1_DAT8 = 165,
192 MX51_PAD_DISP1_DAT9 = 167, 192 MX51_PAD_DISP1_DAT9 = 166,
193 MX51_PAD_DISP1_DAT10 = 168, 193 MX51_PAD_DISP1_DAT10 = 167,
194 MX51_PAD_DISP1_DAT11 = 169, 194 MX51_PAD_DISP1_DAT11 = 168,
195 MX51_PAD_DISP1_DAT12 = 170, 195 MX51_PAD_DISP1_DAT12 = 169,
196 MX51_PAD_DISP1_DAT13 = 171, 196 MX51_PAD_DISP1_DAT13 = 170,
197 MX51_PAD_DISP1_DAT14 = 172, 197 MX51_PAD_DISP1_DAT14 = 171,
198 MX51_PAD_DISP1_DAT15 = 173, 198 MX51_PAD_DISP1_DAT15 = 172,
199 MX51_PAD_DISP1_DAT16 = 174, 199 MX51_PAD_DISP1_DAT16 = 173,
200 MX51_PAD_DISP1_DAT17 = 175, 200 MX51_PAD_DISP1_DAT17 = 174,
201 MX51_PAD_DISP1_DAT18 = 176, 201 MX51_PAD_DISP1_DAT18 = 175,
202 MX51_PAD_DISP1_DAT19 = 177, 202 MX51_PAD_DISP1_DAT19 = 176,
203 MX51_PAD_DISP1_DAT20 = 178, 203 MX51_PAD_DISP1_DAT20 = 177,
204 MX51_PAD_DISP1_DAT21 = 179, 204 MX51_PAD_DISP1_DAT21 = 178,
205 MX51_PAD_DISP1_DAT22 = 180, 205 MX51_PAD_DISP1_DAT22 = 179,
206 MX51_PAD_DISP1_DAT23 = 181, 206 MX51_PAD_DISP1_DAT23 = 180,
207 MX51_PAD_DI1_PIN3 = 182, 207 MX51_PAD_DI1_PIN3 = 181,
208 MX51_PAD_DI1_PIN2 = 183, 208 MX51_PAD_DI1_PIN2 = 182,
209 MX51_PAD_DI_GP2 = 184, 209 MX51_PAD_DI_GP2 = 183,
210 MX51_PAD_DI_GP3 = 185, 210 MX51_PAD_DI_GP3 = 184,
211 MX51_PAD_DI2_PIN4 = 186, 211 MX51_PAD_DI2_PIN4 = 185,
212 MX51_PAD_DI2_PIN2 = 187, 212 MX51_PAD_DI2_PIN2 = 186,
213 MX51_PAD_DI2_PIN3 = 188, 213 MX51_PAD_DI2_PIN3 = 187,
214 MX51_PAD_DI2_DISP_CLK = 189, 214 MX51_PAD_DI2_DISP_CLK = 188,
215 MX51_PAD_DI_GP4 = 190, 215 MX51_PAD_DI_GP4 = 189,
216 MX51_PAD_DISP2_DAT0 = 191, 216 MX51_PAD_DISP2_DAT0 = 190,
217 MX51_PAD_DISP2_DAT1 = 192, 217 MX51_PAD_DISP2_DAT1 = 191,
218 MX51_PAD_DISP2_DAT2 = 193, 218 MX51_PAD_DISP2_DAT2 = 192,
219 MX51_PAD_DISP2_DAT3 = 194, 219 MX51_PAD_DISP2_DAT3 = 193,
220 MX51_PAD_DISP2_DAT4 = 195, 220 MX51_PAD_DISP2_DAT4 = 194,
221 MX51_PAD_DISP2_DAT5 = 196, 221 MX51_PAD_DISP2_DAT5 = 195,
222 MX51_PAD_DISP2_DAT6 = 197, 222 MX51_PAD_DISP2_DAT6 = 196,
223 MX51_PAD_DISP2_DAT7 = 198, 223 MX51_PAD_DISP2_DAT7 = 197,
224 MX51_PAD_DISP2_DAT8 = 199, 224 MX51_PAD_DISP2_DAT8 = 198,
225 MX51_PAD_DISP2_DAT9 = 200, 225 MX51_PAD_DISP2_DAT9 = 199,
226 MX51_PAD_DISP2_DAT10 = 201, 226 MX51_PAD_DISP2_DAT10 = 200,
227 MX51_PAD_DISP2_DAT11 = 202, 227 MX51_PAD_DISP2_DAT11 = 201,
228 MX51_PAD_DISP2_DAT12 = 203, 228 MX51_PAD_DISP2_DAT12 = 202,
229 MX51_PAD_DISP2_DAT13 = 204, 229 MX51_PAD_DISP2_DAT13 = 203,
230 MX51_PAD_DISP2_DAT14 = 205, 230 MX51_PAD_DISP2_DAT14 = 204,
231 MX51_PAD_DISP2_DAT15 = 206, 231 MX51_PAD_DISP2_DAT15 = 205,
232 MX51_PAD_SD1_CMD = 207, 232 MX51_PAD_SD1_CMD = 206,
233 MX51_PAD_SD1_CLK = 208, 233 MX51_PAD_SD1_CLK = 207,
234 MX51_PAD_SD1_DATA0 = 209, 234 MX51_PAD_SD1_DATA0 = 208,
235 MX51_PAD_EIM_DA0 = 210, 235 MX51_PAD_EIM_DA0 = 209,
236 MX51_PAD_EIM_DA1 = 211, 236 MX51_PAD_EIM_DA1 = 210,
237 MX51_PAD_EIM_DA2 = 212, 237 MX51_PAD_EIM_DA2 = 211,
238 MX51_PAD_EIM_DA3 = 213, 238 MX51_PAD_EIM_DA3 = 212,
239 MX51_PAD_SD1_DATA1 = 214, 239 MX51_PAD_SD1_DATA1 = 213,
240 MX51_PAD_EIM_DA4 = 215, 240 MX51_PAD_EIM_DA4 = 214,
241 MX51_PAD_EIM_DA5 = 216, 241 MX51_PAD_EIM_DA5 = 215,
242 MX51_PAD_EIM_DA6 = 217, 242 MX51_PAD_EIM_DA6 = 216,
243 MX51_PAD_EIM_DA7 = 218, 243 MX51_PAD_EIM_DA7 = 217,
244 MX51_PAD_SD1_DATA2 = 219, 244 MX51_PAD_SD1_DATA2 = 218,
245 MX51_PAD_EIM_DA10 = 220, 245 MX51_PAD_EIM_DA10 = 219,
246 MX51_PAD_EIM_DA11 = 221, 246 MX51_PAD_EIM_DA11 = 220,
247 MX51_PAD_EIM_DA8 = 222, 247 MX51_PAD_EIM_DA8 = 221,
248 MX51_PAD_EIM_DA9 = 223, 248 MX51_PAD_EIM_DA9 = 222,
249 MX51_PAD_SD1_DATA3 = 224, 249 MX51_PAD_SD1_DATA3 = 223,
250 MX51_PAD_GPIO1_0 = 225, 250 MX51_PAD_GPIO1_0 = 224,
251 MX51_PAD_GPIO1_1 = 226, 251 MX51_PAD_GPIO1_1 = 225,
252 MX51_PAD_EIM_DA12 = 227, 252 MX51_PAD_EIM_DA12 = 226,
253 MX51_PAD_EIM_DA13 = 228, 253 MX51_PAD_EIM_DA13 = 227,
254 MX51_PAD_EIM_DA14 = 229, 254 MX51_PAD_EIM_DA14 = 228,
255 MX51_PAD_EIM_DA15 = 230, 255 MX51_PAD_EIM_DA15 = 229,
256 MX51_PAD_SD2_CMD = 231, 256 MX51_PAD_SD2_CMD = 230,
257 MX51_PAD_SD2_CLK = 232, 257 MX51_PAD_SD2_CLK = 231,
258 MX51_PAD_SD2_DATA0 = 233, 258 MX51_PAD_SD2_DATA0 = 232,
259 MX51_PAD_SD2_DATA1 = 234, 259 MX51_PAD_SD2_DATA1 = 233,
260 MX51_PAD_SD2_DATA2 = 235, 260 MX51_PAD_SD2_DATA2 = 234,
261 MX51_PAD_SD2_DATA3 = 236, 261 MX51_PAD_SD2_DATA3 = 235,
262 MX51_PAD_GPIO1_2 = 237, 262 MX51_PAD_GPIO1_2 = 236,
263 MX51_PAD_GPIO1_3 = 238, 263 MX51_PAD_GPIO1_3 = 237,
264 MX51_PAD_PMIC_INT_REQ = 239, 264 MX51_PAD_PMIC_INT_REQ = 238,
265 MX51_PAD_GPIO1_4 = 240, 265 MX51_PAD_GPIO1_4 = 239,
266 MX51_PAD_GPIO1_5 = 241, 266 MX51_PAD_GPIO1_5 = 240,
267 MX51_PAD_GPIO1_6 = 242, 267 MX51_PAD_GPIO1_6 = 241,
268 MX51_PAD_GPIO1_7 = 243, 268 MX51_PAD_GPIO1_7 = 242,
269 MX51_PAD_GPIO1_8 = 244, 269 MX51_PAD_GPIO1_8 = 243,
270 MX51_PAD_GPIO1_9 = 245, 270 MX51_PAD_GPIO1_9 = 244,
271}; 271};
272 272
273/* imx51 register maps */ 273/* imx51 register maps */
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
index 1f49e16a9bcd..783feb1ce064 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -23,207 +23,207 @@
23#include "pinctrl-imx.h" 23#include "pinctrl-imx.h"
24 24
25enum imx53_pads { 25enum imx53_pads {
26 MX53_PAD_GPIO_19 = 1, 26 MX53_PAD_GPIO_19 = 0,
27 MX53_PAD_KEY_COL0 = 2, 27 MX53_PAD_KEY_COL0 = 1,
28 MX53_PAD_KEY_ROW0 = 3, 28 MX53_PAD_KEY_ROW0 = 2,
29 MX53_PAD_KEY_COL1 = 4, 29 MX53_PAD_KEY_COL1 = 3,
30 MX53_PAD_KEY_ROW1 = 5, 30 MX53_PAD_KEY_ROW1 = 4,
31 MX53_PAD_KEY_COL2 = 6, 31 MX53_PAD_KEY_COL2 = 5,
32 MX53_PAD_KEY_ROW2 = 7, 32 MX53_PAD_KEY_ROW2 = 6,
33 MX53_PAD_KEY_COL3 = 8, 33 MX53_PAD_KEY_COL3 = 7,
34 MX53_PAD_KEY_ROW3 = 9, 34 MX53_PAD_KEY_ROW3 = 8,
35 MX53_PAD_KEY_COL4 = 10, 35 MX53_PAD_KEY_COL4 = 9,
36 MX53_PAD_KEY_ROW4 = 11, 36 MX53_PAD_KEY_ROW4 = 10,
37 MX53_PAD_DI0_DISP_CLK = 12, 37 MX53_PAD_DI0_DISP_CLK = 11,
38 MX53_PAD_DI0_PIN15 = 13, 38 MX53_PAD_DI0_PIN15 = 12,
39 MX53_PAD_DI0_PIN2 = 14, 39 MX53_PAD_DI0_PIN2 = 13,
40 MX53_PAD_DI0_PIN3 = 15, 40 MX53_PAD_DI0_PIN3 = 14,
41 MX53_PAD_DI0_PIN4 = 16, 41 MX53_PAD_DI0_PIN4 = 15,
42 MX53_PAD_DISP0_DAT0 = 17, 42 MX53_PAD_DISP0_DAT0 = 16,
43 MX53_PAD_DISP0_DAT1 = 18, 43 MX53_PAD_DISP0_DAT1 = 17,
44 MX53_PAD_DISP0_DAT2 = 19, 44 MX53_PAD_DISP0_DAT2 = 18,
45 MX53_PAD_DISP0_DAT3 = 20, 45 MX53_PAD_DISP0_DAT3 = 19,
46 MX53_PAD_DISP0_DAT4 = 21, 46 MX53_PAD_DISP0_DAT4 = 20,
47 MX53_PAD_DISP0_DAT5 = 22, 47 MX53_PAD_DISP0_DAT5 = 21,
48 MX53_PAD_DISP0_DAT6 = 23, 48 MX53_PAD_DISP0_DAT6 = 22,
49 MX53_PAD_DISP0_DAT7 = 24, 49 MX53_PAD_DISP0_DAT7 = 23,
50 MX53_PAD_DISP0_DAT8 = 25, 50 MX53_PAD_DISP0_DAT8 = 24,
51 MX53_PAD_DISP0_DAT9 = 26, 51 MX53_PAD_DISP0_DAT9 = 25,
52 MX53_PAD_DISP0_DAT10 = 27, 52 MX53_PAD_DISP0_DAT10 = 26,
53 MX53_PAD_DISP0_DAT11 = 28, 53 MX53_PAD_DISP0_DAT11 = 27,
54 MX53_PAD_DISP0_DAT12 = 29, 54 MX53_PAD_DISP0_DAT12 = 28,
55 MX53_PAD_DISP0_DAT13 = 30, 55 MX53_PAD_DISP0_DAT13 = 29,
56 MX53_PAD_DISP0_DAT14 = 31, 56 MX53_PAD_DISP0_DAT14 = 30,
57 MX53_PAD_DISP0_DAT15 = 32, 57 MX53_PAD_DISP0_DAT15 = 31,
58 MX53_PAD_DISP0_DAT16 = 33, 58 MX53_PAD_DISP0_DAT16 = 32,
59 MX53_PAD_DISP0_DAT17 = 34, 59 MX53_PAD_DISP0_DAT17 = 33,
60 MX53_PAD_DISP0_DAT18 = 35, 60 MX53_PAD_DISP0_DAT18 = 34,
61 MX53_PAD_DISP0_DAT19 = 36, 61 MX53_PAD_DISP0_DAT19 = 35,
62 MX53_PAD_DISP0_DAT20 = 37, 62 MX53_PAD_DISP0_DAT20 = 36,
63 MX53_PAD_DISP0_DAT21 = 38, 63 MX53_PAD_DISP0_DAT21 = 37,
64 MX53_PAD_DISP0_DAT22 = 39, 64 MX53_PAD_DISP0_DAT22 = 38,
65 MX53_PAD_DISP0_DAT23 = 40, 65 MX53_PAD_DISP0_DAT23 = 39,
66 MX53_PAD_CSI0_PIXCLK = 41, 66 MX53_PAD_CSI0_PIXCLK = 40,
67 MX53_PAD_CSI0_MCLK = 42, 67 MX53_PAD_CSI0_MCLK = 41,
68 MX53_PAD_CSI0_DATA_EN = 43, 68 MX53_PAD_CSI0_DATA_EN = 42,
69 MX53_PAD_CSI0_VSYNC = 44, 69 MX53_PAD_CSI0_VSYNC = 43,
70 MX53_PAD_CSI0_DAT4 = 45, 70 MX53_PAD_CSI0_DAT4 = 44,
71 MX53_PAD_CSI0_DAT5 = 46, 71 MX53_PAD_CSI0_DAT5 = 45,
72 MX53_PAD_CSI0_DAT6 = 47, 72 MX53_PAD_CSI0_DAT6 = 46,
73 MX53_PAD_CSI0_DAT7 = 48, 73 MX53_PAD_CSI0_DAT7 = 47,
74 MX53_PAD_CSI0_DAT8 = 49, 74 MX53_PAD_CSI0_DAT8 = 48,
75 MX53_PAD_CSI0_DAT9 = 50, 75 MX53_PAD_CSI0_DAT9 = 49,
76 MX53_PAD_CSI0_DAT10 = 51, 76 MX53_PAD_CSI0_DAT10 = 50,
77 MX53_PAD_CSI0_DAT11 = 52, 77 MX53_PAD_CSI0_DAT11 = 51,
78 MX53_PAD_CSI0_DAT12 = 53, 78 MX53_PAD_CSI0_DAT12 = 52,
79 MX53_PAD_CSI0_DAT13 = 54, 79 MX53_PAD_CSI0_DAT13 = 53,
80 MX53_PAD_CSI0_DAT14 = 55, 80 MX53_PAD_CSI0_DAT14 = 54,
81 MX53_PAD_CSI0_DAT15 = 56, 81 MX53_PAD_CSI0_DAT15 = 55,
82 MX53_PAD_CSI0_DAT16 = 57, 82 MX53_PAD_CSI0_DAT16 = 56,
83 MX53_PAD_CSI0_DAT17 = 58, 83 MX53_PAD_CSI0_DAT17 = 57,
84 MX53_PAD_CSI0_DAT18 = 59, 84 MX53_PAD_CSI0_DAT18 = 58,
85 MX53_PAD_CSI0_DAT19 = 60, 85 MX53_PAD_CSI0_DAT19 = 59,
86 MX53_PAD_EIM_A25 = 61, 86 MX53_PAD_EIM_A25 = 60,
87 MX53_PAD_EIM_EB2 = 62, 87 MX53_PAD_EIM_EB2 = 61,
88 MX53_PAD_EIM_D16 = 63, 88 MX53_PAD_EIM_D16 = 62,
89 MX53_PAD_EIM_D17 = 64, 89 MX53_PAD_EIM_D17 = 63,
90 MX53_PAD_EIM_D18 = 65, 90 MX53_PAD_EIM_D18 = 64,
91 MX53_PAD_EIM_D19 = 66, 91 MX53_PAD_EIM_D19 = 65,
92 MX53_PAD_EIM_D20 = 67, 92 MX53_PAD_EIM_D20 = 66,
93 MX53_PAD_EIM_D21 = 68, 93 MX53_PAD_EIM_D21 = 67,
94 MX53_PAD_EIM_D22 = 69, 94 MX53_PAD_EIM_D22 = 68,
95 MX53_PAD_EIM_D23 = 70, 95 MX53_PAD_EIM_D23 = 69,
96 MX53_PAD_EIM_EB3 = 71, 96 MX53_PAD_EIM_EB3 = 70,
97 MX53_PAD_EIM_D24 = 72, 97 MX53_PAD_EIM_D24 = 71,
98 MX53_PAD_EIM_D25 = 73, 98 MX53_PAD_EIM_D25 = 72,
99 MX53_PAD_EIM_D26 = 74, 99 MX53_PAD_EIM_D26 = 73,
100 MX53_PAD_EIM_D27 = 75, 100 MX53_PAD_EIM_D27 = 74,
101 MX53_PAD_EIM_D28 = 76, 101 MX53_PAD_EIM_D28 = 75,
102 MX53_PAD_EIM_D29 = 77, 102 MX53_PAD_EIM_D29 = 76,
103 MX53_PAD_EIM_D30 = 78, 103 MX53_PAD_EIM_D30 = 77,
104 MX53_PAD_EIM_D31 = 79, 104 MX53_PAD_EIM_D31 = 78,
105 MX53_PAD_EIM_A24 = 80, 105 MX53_PAD_EIM_A24 = 79,
106 MX53_PAD_EIM_A23 = 81, 106 MX53_PAD_EIM_A23 = 80,
107 MX53_PAD_EIM_A22 = 82, 107 MX53_PAD_EIM_A22 = 81,
108 MX53_PAD_EIM_A21 = 83, 108 MX53_PAD_EIM_A21 = 82,
109 MX53_PAD_EIM_A20 = 84, 109 MX53_PAD_EIM_A20 = 83,
110 MX53_PAD_EIM_A19 = 85, 110 MX53_PAD_EIM_A19 = 84,
111 MX53_PAD_EIM_A18 = 86, 111 MX53_PAD_EIM_A18 = 85,
112 MX53_PAD_EIM_A17 = 87, 112 MX53_PAD_EIM_A17 = 86,
113 MX53_PAD_EIM_A16 = 88, 113 MX53_PAD_EIM_A16 = 87,
114 MX53_PAD_EIM_CS0 = 89, 114 MX53_PAD_EIM_CS0 = 88,
115 MX53_PAD_EIM_CS1 = 90, 115 MX53_PAD_EIM_CS1 = 89,
116 MX53_PAD_EIM_OE = 91, 116 MX53_PAD_EIM_OE = 90,
117 MX53_PAD_EIM_RW = 92, 117 MX53_PAD_EIM_RW = 91,
118 MX53_PAD_EIM_LBA = 93, 118 MX53_PAD_EIM_LBA = 92,
119 MX53_PAD_EIM_EB0 = 94, 119 MX53_PAD_EIM_EB0 = 93,
120 MX53_PAD_EIM_EB1 = 95, 120 MX53_PAD_EIM_EB1 = 94,
121 MX53_PAD_EIM_DA0 = 96, 121 MX53_PAD_EIM_DA0 = 95,
122 MX53_PAD_EIM_DA1 = 97, 122 MX53_PAD_EIM_DA1 = 96,
123 MX53_PAD_EIM_DA2 = 98, 123 MX53_PAD_EIM_DA2 = 97,
124 MX53_PAD_EIM_DA3 = 99, 124 MX53_PAD_EIM_DA3 = 98,
125 MX53_PAD_EIM_DA4 = 100, 125 MX53_PAD_EIM_DA4 = 99,
126 MX53_PAD_EIM_DA5 = 101, 126 MX53_PAD_EIM_DA5 = 100,
127 MX53_PAD_EIM_DA6 = 102, 127 MX53_PAD_EIM_DA6 = 101,
128 MX53_PAD_EIM_DA7 = 103, 128 MX53_PAD_EIM_DA7 = 102,
129 MX53_PAD_EIM_DA8 = 104, 129 MX53_PAD_EIM_DA8 = 103,
130 MX53_PAD_EIM_DA9 = 105, 130 MX53_PAD_EIM_DA9 = 104,
131 MX53_PAD_EIM_DA10 = 106, 131 MX53_PAD_EIM_DA10 = 105,
132 MX53_PAD_EIM_DA11 = 107, 132 MX53_PAD_EIM_DA11 = 106,
133 MX53_PAD_EIM_DA12 = 108, 133 MX53_PAD_EIM_DA12 = 107,
134 MX53_PAD_EIM_DA13 = 109, 134 MX53_PAD_EIM_DA13 = 108,
135 MX53_PAD_EIM_DA14 = 110, 135 MX53_PAD_EIM_DA14 = 109,
136 MX53_PAD_EIM_DA15 = 111, 136 MX53_PAD_EIM_DA15 = 110,
137 MX53_PAD_NANDF_WE_B = 112, 137 MX53_PAD_NANDF_WE_B = 111,
138 MX53_PAD_NANDF_RE_B = 113, 138 MX53_PAD_NANDF_RE_B = 112,
139 MX53_PAD_EIM_WAIT = 114, 139 MX53_PAD_EIM_WAIT = 113,
140 MX53_PAD_LVDS1_TX3_P = 115, 140 MX53_PAD_LVDS1_TX3_P = 114,
141 MX53_PAD_LVDS1_TX2_P = 116, 141 MX53_PAD_LVDS1_TX2_P = 115,
142 MX53_PAD_LVDS1_CLK_P = 117, 142 MX53_PAD_LVDS1_CLK_P = 116,
143 MX53_PAD_LVDS1_TX1_P = 118, 143 MX53_PAD_LVDS1_TX1_P = 117,
144 MX53_PAD_LVDS1_TX0_P = 119, 144 MX53_PAD_LVDS1_TX0_P = 118,
145 MX53_PAD_LVDS0_TX3_P = 120, 145 MX53_PAD_LVDS0_TX3_P = 119,
146 MX53_PAD_LVDS0_CLK_P = 121, 146 MX53_PAD_LVDS0_CLK_P = 120,
147 MX53_PAD_LVDS0_TX2_P = 122, 147 MX53_PAD_LVDS0_TX2_P = 121,
148 MX53_PAD_LVDS0_TX1_P = 123, 148 MX53_PAD_LVDS0_TX1_P = 122,
149 MX53_PAD_LVDS0_TX0_P = 124, 149 MX53_PAD_LVDS0_TX0_P = 123,
150 MX53_PAD_GPIO_10 = 125, 150 MX53_PAD_GPIO_10 = 124,
151 MX53_PAD_GPIO_11 = 126, 151 MX53_PAD_GPIO_11 = 125,
152 MX53_PAD_GPIO_12 = 127, 152 MX53_PAD_GPIO_12 = 126,
153 MX53_PAD_GPIO_13 = 128, 153 MX53_PAD_GPIO_13 = 127,
154 MX53_PAD_GPIO_14 = 129, 154 MX53_PAD_GPIO_14 = 128,
155 MX53_PAD_NANDF_CLE = 130, 155 MX53_PAD_NANDF_CLE = 129,
156 MX53_PAD_NANDF_ALE = 131, 156 MX53_PAD_NANDF_ALE = 130,
157 MX53_PAD_NANDF_WP_B = 132, 157 MX53_PAD_NANDF_WP_B = 131,
158 MX53_PAD_NANDF_RB0 = 133, 158 MX53_PAD_NANDF_RB0 = 132,
159 MX53_PAD_NANDF_CS0 = 134, 159 MX53_PAD_NANDF_CS0 = 133,
160 MX53_PAD_NANDF_CS1 = 135, 160 MX53_PAD_NANDF_CS1 = 134,
161 MX53_PAD_NANDF_CS2 = 136, 161 MX53_PAD_NANDF_CS2 = 135,
162 MX53_PAD_NANDF_CS3 = 137, 162 MX53_PAD_NANDF_CS3 = 136,
163 MX53_PAD_FEC_MDIO = 138, 163 MX53_PAD_FEC_MDIO = 137,
164 MX53_PAD_FEC_REF_CLK = 139, 164 MX53_PAD_FEC_REF_CLK = 138,
165 MX53_PAD_FEC_RX_ER = 140, 165 MX53_PAD_FEC_RX_ER = 139,
166 MX53_PAD_FEC_CRS_DV = 141, 166 MX53_PAD_FEC_CRS_DV = 140,
167 MX53_PAD_FEC_RXD1 = 142, 167 MX53_PAD_FEC_RXD1 = 141,
168 MX53_PAD_FEC_RXD0 = 143, 168 MX53_PAD_FEC_RXD0 = 142,
169 MX53_PAD_FEC_TX_EN = 144, 169 MX53_PAD_FEC_TX_EN = 143,
170 MX53_PAD_FEC_TXD1 = 145, 170 MX53_PAD_FEC_TXD1 = 144,
171 MX53_PAD_FEC_TXD0 = 146, 171 MX53_PAD_FEC_TXD0 = 145,
172 MX53_PAD_FEC_MDC = 147, 172 MX53_PAD_FEC_MDC = 146,
173 MX53_PAD_PATA_DIOW = 148, 173 MX53_PAD_PATA_DIOW = 147,
174 MX53_PAD_PATA_DMACK = 149, 174 MX53_PAD_PATA_DMACK = 148,
175 MX53_PAD_PATA_DMARQ = 150, 175 MX53_PAD_PATA_DMARQ = 149,
176 MX53_PAD_PATA_BUFFER_EN = 151, 176 MX53_PAD_PATA_BUFFER_EN = 150,
177 MX53_PAD_PATA_INTRQ = 152, 177 MX53_PAD_PATA_INTRQ = 151,
178 MX53_PAD_PATA_DIOR = 153, 178 MX53_PAD_PATA_DIOR = 152,
179 MX53_PAD_PATA_RESET_B = 154, 179 MX53_PAD_PATA_RESET_B = 153,
180 MX53_PAD_PATA_IORDY = 155, 180 MX53_PAD_PATA_IORDY = 154,
181 MX53_PAD_PATA_DA_0 = 156, 181 MX53_PAD_PATA_DA_0 = 155,
182 MX53_PAD_PATA_DA_1 = 157, 182 MX53_PAD_PATA_DA_1 = 156,
183 MX53_PAD_PATA_DA_2 = 158, 183 MX53_PAD_PATA_DA_2 = 157,
184 MX53_PAD_PATA_CS_0 = 159, 184 MX53_PAD_PATA_CS_0 = 158,
185 MX53_PAD_PATA_CS_1 = 160, 185 MX53_PAD_PATA_CS_1 = 159,
186 MX53_PAD_PATA_DATA0 = 161, 186 MX53_PAD_PATA_DATA0 = 160,
187 MX53_PAD_PATA_DATA1 = 162, 187 MX53_PAD_PATA_DATA1 = 161,
188 MX53_PAD_PATA_DATA2 = 163, 188 MX53_PAD_PATA_DATA2 = 162,
189 MX53_PAD_PATA_DATA3 = 164, 189 MX53_PAD_PATA_DATA3 = 163,
190 MX53_PAD_PATA_DATA4 = 165, 190 MX53_PAD_PATA_DATA4 = 164,
191 MX53_PAD_PATA_DATA5 = 166, 191 MX53_PAD_PATA_DATA5 = 165,
192 MX53_PAD_PATA_DATA6 = 167, 192 MX53_PAD_PATA_DATA6 = 166,
193 MX53_PAD_PATA_DATA7 = 168, 193 MX53_PAD_PATA_DATA7 = 167,
194 MX53_PAD_PATA_DATA8 = 169, 194 MX53_PAD_PATA_DATA8 = 168,
195 MX53_PAD_PATA_DATA9 = 170, 195 MX53_PAD_PATA_DATA9 = 169,
196 MX53_PAD_PATA_DATA10 = 171, 196 MX53_PAD_PATA_DATA10 = 170,
197 MX53_PAD_PATA_DATA11 = 172, 197 MX53_PAD_PATA_DATA11 = 171,
198 MX53_PAD_PATA_DATA12 = 173, 198 MX53_PAD_PATA_DATA12 = 172,
199 MX53_PAD_PATA_DATA13 = 174, 199 MX53_PAD_PATA_DATA13 = 173,
200 MX53_PAD_PATA_DATA14 = 175, 200 MX53_PAD_PATA_DATA14 = 174,
201 MX53_PAD_PATA_DATA15 = 176, 201 MX53_PAD_PATA_DATA15 = 175,
202 MX53_PAD_SD1_DATA0 = 177, 202 MX53_PAD_SD1_DATA0 = 176,
203 MX53_PAD_SD1_DATA1 = 178, 203 MX53_PAD_SD1_DATA1 = 177,
204 MX53_PAD_SD1_CMD = 179, 204 MX53_PAD_SD1_CMD = 178,
205 MX53_PAD_SD1_DATA2 = 180, 205 MX53_PAD_SD1_DATA2 = 179,
206 MX53_PAD_SD1_CLK = 181, 206 MX53_PAD_SD1_CLK = 180,
207 MX53_PAD_SD1_DATA3 = 182, 207 MX53_PAD_SD1_DATA3 = 181,
208 MX53_PAD_SD2_CLK = 183, 208 MX53_PAD_SD2_CLK = 182,
209 MX53_PAD_SD2_CMD = 184, 209 MX53_PAD_SD2_CMD = 183,
210 MX53_PAD_SD2_DATA3 = 185, 210 MX53_PAD_SD2_DATA3 = 184,
211 MX53_PAD_SD2_DATA2 = 186, 211 MX53_PAD_SD2_DATA2 = 185,
212 MX53_PAD_SD2_DATA1 = 187, 212 MX53_PAD_SD2_DATA1 = 186,
213 MX53_PAD_SD2_DATA0 = 188, 213 MX53_PAD_SD2_DATA0 = 187,
214 MX53_PAD_GPIO_0 = 189, 214 MX53_PAD_GPIO_0 = 188,
215 MX53_PAD_GPIO_1 = 190, 215 MX53_PAD_GPIO_1 = 189,
216 MX53_PAD_GPIO_9 = 191, 216 MX53_PAD_GPIO_9 = 190,
217 MX53_PAD_GPIO_3 = 192, 217 MX53_PAD_GPIO_3 = 191,
218 MX53_PAD_GPIO_6 = 193, 218 MX53_PAD_GPIO_6 = 192,
219 MX53_PAD_GPIO_2 = 194, 219 MX53_PAD_GPIO_2 = 193,
220 MX53_PAD_GPIO_4 = 195, 220 MX53_PAD_GPIO_4 = 194,
221 MX53_PAD_GPIO_5 = 196, 221 MX53_PAD_GPIO_5 = 195,
222 MX53_PAD_GPIO_7 = 197, 222 MX53_PAD_GPIO_7 = 196,
223 MX53_PAD_GPIO_8 = 198, 223 MX53_PAD_GPIO_8 = 197,
224 MX53_PAD_GPIO_16 = 199, 224 MX53_PAD_GPIO_16 = 198,
225 MX53_PAD_GPIO_17 = 200, 225 MX53_PAD_GPIO_17 = 199,
226 MX53_PAD_GPIO_18 = 201, 226 MX53_PAD_GPIO_18 = 200,
227}; 227};
228 228
229/* imx53 register maps */ 229/* imx53 register maps */
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index a39fb7a6fc51..ec6209dd7c39 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -465,6 +465,8 @@ static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
465static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, 465static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
466 DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, 466 DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
467 DB8500_PIN_AH15 }; 467 DB8500_PIN_AH15 };
468static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15,
469 DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,DB8500_PIN_AH15 };
468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, 470static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
469 DB8500_PIN_AH12, DB8500_PIN_AH11 }; 471 DB8500_PIN_AH12, DB8500_PIN_AH11 };
470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10, 472static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10,
@@ -641,6 +643,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
641 DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), 643 DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
642 DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), 644 DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
643 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), 645 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
646 DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
644 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), 647 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
645 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), 648 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
646 DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), 649 DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
@@ -768,7 +771,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
768/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ 771/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
769DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); 772DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
770DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); 773DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
771DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1"); 774DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1");
772DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2"); 775DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
773DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1"); 776DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
774DB8500_FUNC_GROUPS(usb, "usb_a_1"); 777DB8500_FUNC_GROUPS(usb, "usb_a_1");
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
new file mode 100644
index 000000000000..3daf665c84c3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -0,0 +1,999 @@
1#include <linux/kernel.h>
2#include <linux/pinctrl/pinctrl.h>
3#include "pinctrl-nomadik.h"
4
5/* All the pins that can be used for GPIO and some other functions */
6#define _GPIO(offset) (offset)
7
8#define DB8540_PIN_AH6 _GPIO(0)
9#define DB8540_PIN_AG7 _GPIO(1)
10#define DB8540_PIN_AF2 _GPIO(2)
11#define DB8540_PIN_AD3 _GPIO(3)
12#define DB8540_PIN_AF6 _GPIO(4)
13#define DB8540_PIN_AG6 _GPIO(5)
14#define DB8540_PIN_AD5 _GPIO(6)
15#define DB8540_PIN_AF7 _GPIO(7)
16#define DB8540_PIN_AG5 _GPIO(8)
17#define DB8540_PIN_AH5 _GPIO(9)
18#define DB8540_PIN_AE4 _GPIO(10)
19#define DB8540_PIN_AD1 _GPIO(11)
20#define DB8540_PIN_AD2 _GPIO(12)
21#define DB8540_PIN_AC2 _GPIO(13)
22#define DB8540_PIN_AC4 _GPIO(14)
23#define DB8540_PIN_AC3 _GPIO(15)
24#define DB8540_PIN_AH7 _GPIO(16)
25#define DB8540_PIN_AE7 _GPIO(17)
26/* Hole */
27#define DB8540_PIN_AF8 _GPIO(22)
28#define DB8540_PIN_AH11 _GPIO(23)
29#define DB8540_PIN_AG11 _GPIO(24)
30#define DB8540_PIN_AF11 _GPIO(25)
31#define DB8540_PIN_AH10 _GPIO(26)
32#define DB8540_PIN_AG10 _GPIO(27)
33#define DB8540_PIN_AF10 _GPIO(28)
34/* Hole */
35#define DB8540_PIN_AD4 _GPIO(33)
36#define DB8540_PIN_AF3 _GPIO(34)
37#define DB8540_PIN_AF5 _GPIO(35)
38#define DB8540_PIN_AG4 _GPIO(36)
39#define DB8540_PIN_AF9 _GPIO(37)
40#define DB8540_PIN_AE8 _GPIO(38)
41/* Hole */
42#define DB8540_PIN_M26 _GPIO(64)
43#define DB8540_PIN_M25 _GPIO(65)
44#define DB8540_PIN_M27 _GPIO(66)
45#define DB8540_PIN_N25 _GPIO(67)
46/* Hole */
47#define DB8540_PIN_M28 _GPIO(70)
48#define DB8540_PIN_N26 _GPIO(71)
49#define DB8540_PIN_M22 _GPIO(72)
50#define DB8540_PIN_N22 _GPIO(73)
51#define DB8540_PIN_N27 _GPIO(74)
52#define DB8540_PIN_N28 _GPIO(75)
53#define DB8540_PIN_P22 _GPIO(76)
54#define DB8540_PIN_P28 _GPIO(77)
55#define DB8540_PIN_P26 _GPIO(78)
56#define DB8540_PIN_T22 _GPIO(79)
57#define DB8540_PIN_R27 _GPIO(80)
58#define DB8540_PIN_P27 _GPIO(81)
59#define DB8540_PIN_R26 _GPIO(82)
60#define DB8540_PIN_R25 _GPIO(83)
61#define DB8540_PIN_U22 _GPIO(84)
62#define DB8540_PIN_T27 _GPIO(85)
63#define DB8540_PIN_T25 _GPIO(86)
64#define DB8540_PIN_T26 _GPIO(87)
65/* Hole */
66#define DB8540_PIN_AF20 _GPIO(116)
67#define DB8540_PIN_AG21 _GPIO(117)
68#define DB8540_PIN_AH19 _GPIO(118)
69#define DB8540_PIN_AE19 _GPIO(119)
70#define DB8540_PIN_AG18 _GPIO(120)
71#define DB8540_PIN_AH17 _GPIO(121)
72#define DB8540_PIN_AF19 _GPIO(122)
73#define DB8540_PIN_AF18 _GPIO(123)
74#define DB8540_PIN_AE18 _GPIO(124)
75#define DB8540_PIN_AG17 _GPIO(125)
76#define DB8540_PIN_AF17 _GPIO(126)
77#define DB8540_PIN_AE17 _GPIO(127)
78#define DB8540_PIN_AC27 _GPIO(128)
79#define DB8540_PIN_AD27 _GPIO(129)
80#define DB8540_PIN_AE28 _GPIO(130)
81#define DB8540_PIN_AG26 _GPIO(131)
82#define DB8540_PIN_AF25 _GPIO(132)
83#define DB8540_PIN_AE27 _GPIO(133)
84#define DB8540_PIN_AF27 _GPIO(134)
85#define DB8540_PIN_AG28 _GPIO(135)
86#define DB8540_PIN_AF28 _GPIO(136)
87#define DB8540_PIN_AG25 _GPIO(137)
88#define DB8540_PIN_AG24 _GPIO(138)
89#define DB8540_PIN_AD25 _GPIO(139)
90#define DB8540_PIN_AH25 _GPIO(140)
91#define DB8540_PIN_AF26 _GPIO(141)
92#define DB8540_PIN_AF23 _GPIO(142)
93#define DB8540_PIN_AG23 _GPIO(143)
94#define DB8540_PIN_AE25 _GPIO(144)
95#define DB8540_PIN_AH24 _GPIO(145)
96#define DB8540_PIN_AJ25 _GPIO(146)
97#define DB8540_PIN_AG27 _GPIO(147)
98#define DB8540_PIN_AH23 _GPIO(148)
99#define DB8540_PIN_AE26 _GPIO(149)
100#define DB8540_PIN_AE24 _GPIO(150)
101#define DB8540_PIN_AJ24 _GPIO(151)
102#define DB8540_PIN_AE21 _GPIO(152)
103#define DB8540_PIN_AG22 _GPIO(153)
104#define DB8540_PIN_AF21 _GPIO(154)
105#define DB8540_PIN_AF24 _GPIO(155)
106#define DB8540_PIN_AH22 _GPIO(156)
107#define DB8540_PIN_AJ23 _GPIO(157)
108#define DB8540_PIN_AH21 _GPIO(158)
109#define DB8540_PIN_AG20 _GPIO(159)
110#define DB8540_PIN_AE23 _GPIO(160)
111#define DB8540_PIN_AH20 _GPIO(161)
112#define DB8540_PIN_AG19 _GPIO(162)
113#define DB8540_PIN_AF22 _GPIO(163)
114#define DB8540_PIN_AJ21 _GPIO(164)
115#define DB8540_PIN_AD26 _GPIO(165)
116#define DB8540_PIN_AD28 _GPIO(166)
117#define DB8540_PIN_AC28 _GPIO(167)
118#define DB8540_PIN_AC26 _GPIO(168)
119/* Hole */
120#define DB8540_PIN_J3 _GPIO(192)
121#define DB8540_PIN_H1 _GPIO(193)
122#define DB8540_PIN_J2 _GPIO(194)
123#define DB8540_PIN_H2 _GPIO(195)
124#define DB8540_PIN_H3 _GPIO(196)
125#define DB8540_PIN_H4 _GPIO(197)
126#define DB8540_PIN_G2 _GPIO(198)
127#define DB8540_PIN_G3 _GPIO(199)
128#define DB8540_PIN_G4 _GPIO(200)
129#define DB8540_PIN_F2 _GPIO(201)
130#define DB8540_PIN_C6 _GPIO(202)
131#define DB8540_PIN_B6 _GPIO(203)
132#define DB8540_PIN_B7 _GPIO(204)
133#define DB8540_PIN_A7 _GPIO(205)
134#define DB8540_PIN_D7 _GPIO(206)
135#define DB8540_PIN_D8 _GPIO(207)
136#define DB8540_PIN_F3 _GPIO(208)
137#define DB8540_PIN_E2 _GPIO(209)
138#define DB8540_PIN_C7 _GPIO(210)
139#define DB8540_PIN_B8 _GPIO(211)
140#define DB8540_PIN_C10 _GPIO(212)
141#define DB8540_PIN_C8 _GPIO(213)
142#define DB8540_PIN_C9 _GPIO(214)
143/* Hole */
144#define DB8540_PIN_B9 _GPIO(219)
145#define DB8540_PIN_A10 _GPIO(220)
146#define DB8540_PIN_D9 _GPIO(221)
147#define DB8540_PIN_B11 _GPIO(222)
148#define DB8540_PIN_B10 _GPIO(223)
149#define DB8540_PIN_E10 _GPIO(224)
150#define DB8540_PIN_B12 _GPIO(225)
151#define DB8540_PIN_D10 _GPIO(226)
152#define DB8540_PIN_D11 _GPIO(227)
153#define DB8540_PIN_AJ6 _GPIO(228)
154#define DB8540_PIN_B13 _GPIO(229)
155#define DB8540_PIN_C12 _GPIO(230)
156#define DB8540_PIN_B14 _GPIO(231)
157#define DB8540_PIN_E11 _GPIO(232)
158/* Hole */
159#define DB8540_PIN_D12 _GPIO(256)
160#define DB8540_PIN_D15 _GPIO(257)
161#define DB8540_PIN_C13 _GPIO(258)
162#define DB8540_PIN_C14 _GPIO(259)
163#define DB8540_PIN_C18 _GPIO(260)
164#define DB8540_PIN_C16 _GPIO(261)
165#define DB8540_PIN_B16 _GPIO(262)
166#define DB8540_PIN_D18 _GPIO(263)
167#define DB8540_PIN_C15 _GPIO(264)
168#define DB8540_PIN_C17 _GPIO(265)
169#define DB8540_PIN_B17 _GPIO(266)
170#define DB8540_PIN_D17 _GPIO(267)
171
172/*
173 * The names of the pins are denoted by GPIO number and ball name, even
174 * though they can be used for other things than GPIO, this is the first
175 * column in the table of the data sheet and often used on schematics and
176 * such.
177 */
178static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
179 PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"),
180 PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"),
181 PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"),
182 PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"),
183 PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"),
184 PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"),
185 PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"),
186 PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"),
187 PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"),
188 PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"),
189 PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"),
190 PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"),
191 PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"),
192 PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"),
193 PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"),
194 PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"),
195 PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"),
196 PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"),
197 /* Hole */
198 PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"),
199 PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"),
200 PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"),
201 PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"),
202 PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"),
203 PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"),
204 PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"),
205 /* Hole */
206 PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"),
207 PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"),
208 PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"),
209 PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"),
210 PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"),
211 PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"),
212 /* Hole */
213 PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"),
214 PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"),
215 PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"),
216 PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"),
217 /* Hole */
218 PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"),
219 PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"),
220 PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"),
221 PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"),
222 PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"),
223 PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"),
224 PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"),
225 PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"),
226 PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"),
227 PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"),
228 PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"),
229 PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"),
230 PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"),
231 PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"),
232 PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"),
233 PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"),
234 PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"),
235 PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"),
236 /* Hole */
237 PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"),
238 PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"),
239 PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"),
240 PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"),
241 PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"),
242 PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"),
243 PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"),
244 PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"),
245 PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"),
246 PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"),
247 PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"),
248 PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"),
249 PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"),
250 PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"),
251 PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"),
252 PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"),
253 PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"),
254 PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"),
255 PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"),
256 PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"),
257 PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"),
258 PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"),
259 PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"),
260 PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"),
261 PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"),
262 PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"),
263 PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"),
264 PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"),
265 PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"),
266 PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"),
267 PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"),
268 PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"),
269 PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"),
270 PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"),
271 PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"),
272 PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"),
273 PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"),
274 PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"),
275 PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"),
276 PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"),
277 PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"),
278 PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"),
279 PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"),
280 PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"),
281 PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"),
282 PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"),
283 PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"),
284 PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"),
285 PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"),
286 PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"),
287 PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"),
288 PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"),
289 PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"),
290 /* Hole */
291 PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"),
292 PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"),
293 PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"),
294 PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"),
295 PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"),
296 PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"),
297 PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"),
298 PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"),
299 PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"),
300 PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"),
301 PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"),
302 PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"),
303 PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"),
304 PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"),
305 PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"),
306 PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"),
307 PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"),
308 PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"),
309 PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"),
310 PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"),
311 PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"),
312 PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"),
313 PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"),
314 /* Hole */
315 PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"),
316 PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"),
317 PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"),
318 PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"),
319 PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"),
320 PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"),
321 PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"),
322 PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"),
323 PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"),
324 PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"),
325 PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"),
326 PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"),
327 PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"),
328 PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"),
329 /* Hole */
330 PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"),
331 PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"),
332 PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"),
333 PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"),
334 PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"),
335 PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"),
336 PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"),
337 PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"),
338 PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"),
339 PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"),
340 PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"),
341 PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
342};
343
344#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \
345 .pin_base = b, .npins = c }
346
347/*
348 * This matches the 32-pin gpio chips registered by the GPIO portion. This
349 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
350 */
351static struct pinctrl_gpio_range nmk_db8540_ranges[] = {
352 DB8540_GPIO_RANGE(0, 0, 18),
353 DB8540_GPIO_RANGE(0, 22, 7),
354 DB8540_GPIO_RANGE(1, 33, 6),
355 DB8540_GPIO_RANGE(2, 64, 4),
356 DB8540_GPIO_RANGE(2, 70, 18),
357 DB8540_GPIO_RANGE(3, 116, 12),
358 DB8540_GPIO_RANGE(4, 128, 32),
359 DB8540_GPIO_RANGE(5, 160, 9),
360 DB8540_GPIO_RANGE(6, 192, 23),
361 DB8540_GPIO_RANGE(6, 219, 5),
362 DB8540_GPIO_RANGE(7, 224, 9),
363 DB8540_GPIO_RANGE(8, 256, 12),
364};
365
366/*
367 * Read the pin group names like this:
368 * u0_a_1 = first groups of pins for uart0 on alt function a
369 * i2c2_b_2 = second group of pins for i2c2 on alt function b
370 *
371 * The groups are arranged as sets per altfunction column, so we can
372 * mux in one group at a time by selecting the same altfunction for them
373 * all. When functions require pins on different altfunctions, you need
374 * to combine several groups.
375 */
376
377/* Altfunction A column */
378static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7,
379 DB8540_PIN_AF2, DB8540_PIN_AD3 };
380static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
381static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
382/* Image processor I2C line, this is driven by image processor firmware */
383static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
384static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
385/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
386static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
387static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2,
388 DB8540_PIN_AC4 };
389static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7,
390 DB8540_PIN_AE7 };
391/* Basic pins of the MMC/SD card 0 interface */
392static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
393 DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10};
394/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
395static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
396static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 };
397
398static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 };
399static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 };
400/* LCD interface */
401static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
402 DB8540_PIN_M27, DB8540_PIN_N25 };
403static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 };
404static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 };
405static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
406 DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
407 DB8540_PIN_P22, DB8540_PIN_P28 };
408/* D8 thru D11 often used as TVOUT lines */
409static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22,
410 DB8540_PIN_R27, DB8540_PIN_P27 };
411static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
412 DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
413 DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
414 DB8540_PIN_AG20, DB8540_PIN_AE23 };
415static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
416 DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
417/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
418static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27,
419 DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27,
420 DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25,
421 DB8540_PIN_AG24 };
422static const unsigned ssp1_a_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
423 DB8540_PIN_AF26, DB8540_PIN_AF23 };
424static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
425 DB8540_PIN_AH24, DB8540_PIN_AJ25 };
426static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 };
427/*
428 * Image processor GPIO pins are named "ipgpio" and have their own
429 * numberspace
430 */
431static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 };
432static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 };
433/* modem i2s interface */
434static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28,
435 DB8540_PIN_AC28, DB8540_PIN_AC26 };
436static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21,
437 DB8540_PIN_AH19, DB8540_PIN_AE19 };
438static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
439static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19,
440 DB8540_PIN_AF18 };
441static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 };
442static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 };
443static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2,
444 DB8540_PIN_H2 };
445static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 };
446static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2,
447 DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6,
448 DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7,
449 DB8540_PIN_D8 };
450static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2,
451 DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
452 DB8540_PIN_C9 };
453/* mc1_a_2_pins exclude MC1_FBCLK */
454static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3, DB8540_PIN_C7,
455 DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
456 DB8540_PIN_C9 };
457static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
458 DB8540_PIN_D9 };
459static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
460 DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 };
461static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
462 DB8540_PIN_E10, DB8540_PIN_B12 };
463static const unsigned clkout_a_1_pins[] = { DB8540_PIN_D11, DB8540_PIN_AJ6 };
464static const unsigned clkout_a_2_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
465static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 };
466static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15,
467 DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16,
468 DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17,
469 DB8540_PIN_B17, DB8540_PIN_D17 };
470/* Altfunction B colum */
471static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 };
472static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 };
473static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
474static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
475static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
476static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
477static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
478static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 };
479static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
480 DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
481static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 };
482static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
483static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21,
484 DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25,
485 DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22,
486 DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28,
487 DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
488 DB8540_PIN_R26, DB8540_PIN_R25 };
489static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 };
490static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
491 DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
492 DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
493 DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28,
494 DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27,
495 DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24,
496 DB8540_PIN_AD25 };
497static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 };
498static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 };
499static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 };
500static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 };
501static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 };
502static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 };
503static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 };
504static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 };
505static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19,
506 DB8540_PIN_AE19 };
507static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
508static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
509static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 };
510static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17,
511 DB8540_PIN_AE17 };
512static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 };
513static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 };
514static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 };
515static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10,
516 DB8540_PIN_C8, DB8540_PIN_C9 };
517static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
518 DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10,
519 DB8540_PIN_B12 };
520static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 };
521static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 };
522static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 };
523static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 };
524
525/* Altfunction C column */
526static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 };
527static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 };
528static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 };
529static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 };
530static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 };
531static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3,
532 DB8540_PIN_AF5, DB8540_PIN_AG4 };
533static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24,
534 DB8540_PIN_AE21 };
535static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 };
536static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 };
537static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 };
538static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 };
539static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
540 DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
541static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 };
542static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 };
543static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 };
544static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 };
545static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 };
546static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 };
547static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
548 DB8540_PIN_U22 };
549static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 };
550static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
551 DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
552 DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
553 DB8540_PIN_AJ21};
554static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 };
555static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 };
556static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 };
557static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 };
558static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 };
559static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 };
560static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
561 DB8540_PIN_AF26, DB8540_PIN_AF23 };
562static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
563 DB8540_PIN_AH24 };
564static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 };
565static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 };
566static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18,
567 DB8540_PIN_AH17 };
568static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
569static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 };
570static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 };
571static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10,
572 DB8540_PIN_E10, DB8540_PIN_B12 };
573static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
574
575/* Other alt C1 column */
576static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5,
577 DB8540_PIN_AE4, DB8540_PIN_AD1 };
578static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
579 DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
580static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 };
581static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 };
582static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 };
583static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 };
584static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 };
585static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 };
586static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 };
587static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28,
588 DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27,
589 DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
590 DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27,
591 DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21,
592 DB8540_PIN_T25};
593static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 };
594static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27,
595 DB8540_PIN_T26 };
596static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
597 DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
598 DB8540_PIN_AG20, DB8540_PIN_AE23 };
599static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
600 DB8540_PIN_AG23, DB8540_PIN_AE25 };
601static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 };
602static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 };
603static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 };
604
605/* Other alt C2 column */
606static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
607 DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
608static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 };
609static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 };
610static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
611 DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
612static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 };
613static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28,
614 DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
615 DB8540_PIN_R26, DB8540_PIN_R25 };
616static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27,
617 DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 };
618static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 };
619static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20,
620 DB8540_PIN_AE23 };
621static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
622 DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
623static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 };
624static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26,
625 DB8540_PIN_AE24 };
626
627/* Other alt C3 column */
628static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 };
629static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
630 DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
631 DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
632 DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
633 DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25,
634 DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
635 DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
636 DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19,
637 DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
638
639/* Other alt C4 column */
640static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
641 DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
642 DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
643 DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
644 DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 };
645static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22,
646 DB8540_PIN_T27 };
647static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22,
648 DB8540_PIN_AF21 };
649static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24,
650 DB8540_PIN_AH22 };
651static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23,
652 DB8540_PIN_AH21 };
653static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
654 DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
655static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 };
656
657#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
658 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
659
660static const struct nmk_pingroup nmk_db8540_groups[] = {
661 /* Altfunction A column */
662 DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
663 DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
664 DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
665 DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
666 DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
667 DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
668 DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
669 DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
670 DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
671 DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
672 DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
673 DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A),
674 DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A),
675 DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
676 DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
677 DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
678 DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
679 DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
680 DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
681 DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
682 DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
683 DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
684 DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
685 DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
686 DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
687 DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
688 DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A),
689 DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A),
690 DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A),
691 DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A),
692 DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A),
693 DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
694 DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A),
695 DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A),
696 DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
697 DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
698 DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
699 DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
700 DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
701 DB8540_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
702 DB8540_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
703 DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A),
704 DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
705 /* Altfunction B column */
706 DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B),
707 DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B),
708 DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
709 DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
710 DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
711 DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
712 DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
713 DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
714 DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
715 DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B),
716 DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
717 DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
718 DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B),
719 DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
720 DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
721 DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
722 DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
723 DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
724 DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
725 DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B),
726 DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B),
727 DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B),
728 DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B),
729 DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B),
730 DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B),
731 DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B),
732 DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B),
733 DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
734 DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B),
735 DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
736 DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
737 DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
738 DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
739 DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
740 DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
741 DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B),
742 /* Altfunction C column */
743 DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
744 DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
745 DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
746 DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
747 DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
748 DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
749 DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
750 DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
751 DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
752 DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
753 DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
754 DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
755 DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
756 DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C),
757 DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
758 DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
759 DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
760 DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
761 DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C),
762 DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C),
763 DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
764 DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
765 DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C),
766 DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
767 DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C),
768 DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C),
769 DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C),
770 DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
771 DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C),
772 DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
773 DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C),
774 DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C),
775 DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C),
776 DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C),
777 DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
778 DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
779 DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
780
781 /* Other alt C1 column, these are still configured as alt C */
782 DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C),
783 DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C),
784 DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C),
785 DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C),
786 DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C),
787 DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C),
788 DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C),
789 DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C),
790 DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C),
791 DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C),
792 DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C),
793 DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C),
794 DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
795 DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C),
796 DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C),
797 DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C),
798 DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C),
799
800 /* Other alt C2 column, these are still configured as alt C */
801 DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C),
802 DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C),
803 DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C),
804 DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C),
805 DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C),
806 DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C),
807 DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C),
808 DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C),
809 DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C),
810 DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C),
811 DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C),
812 DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C),
813
814 /* Other alt C3 column, these are still configured as alt C */
815 DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C),
816 DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C),
817
818 /* Other alt C4 column, these are still configured as alt C */
819 DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C),
820 DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C),
821 DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C),
822 DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C),
823 DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C),
824 DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C),
825
826};
827
828/* We use this macro to define the groups applicable to a function */
829#define DB8540_FUNC_GROUPS(a, b...) \
830static const char * const a##_groups[] = { b };
831
832DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1");
833DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout_a_1", "clkout_a_2");
834DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
835DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
836DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
837DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1");
838DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1");
839DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
840DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
841DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1");
842DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2");
843DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2");
844DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1");
845/* The image processor has 8 GPIO pins that can be muxed out */
846DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2",
847 "ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2",
848 "ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2",
849 "ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2",
850 "ipgpio4_c_1", "ipgpio4_c_2",
851 "ipgpio5_c_1", "ipgpio5_c_2",
852 "ipgpio6_c_1", "ipgpio6_c_2",
853 "ipgpio7_b_1", "ipgpio7_c_1");
854DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
855DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
856DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1",
857 "lcdvsi0_a_1", "lcdvsi1_a_1");
858DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1");
859DB8540_FUNC_GROUPS(mc0, "mc0_a_1");
860DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2");
861DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
862DB8540_FUNC_GROUPS(mc3, "mc3_b_1");
863DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
864DB8540_FUNC_GROUPS(mc5, "mc5_c_1");
865DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1",
866 "modaccgpo_oc3_1");
867DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1",
868 "modaccuartrtccts_oc4_1");
869DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1");
870DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1",
871 "modobspwrctrl_oc1_1", "modobspwrrst_c_1",
872 "modobsrefclk_oc1_1", "modobsresout_c_1",
873 "modobsresout_oc1_1", "modobsservice_oc2_1");
874DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1");
875DB8540_FUNC_GROUPS(modrf, "modrf_c_1");
876DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1");
877DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1");
878DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1",
879 "moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1");
880DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1",
881 "moduartstmmux_oc4_1");
882DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1");
883/*
884 * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
885 * switched around by selecting the altfunction A or B.
886 */
887DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1",
888 "msp0txrx_b_1");
889DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1");
890DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1");
891DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1");
892DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
893DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
894DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2");
895/* Select between CS0 on alt B or PS1 on alt C */
896DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1",
897 "smps0_c_1", "smps1_c_1");
898DB8540_FUNC_GROUPS(spi0, "spi0_c_1");
899DB8540_FUNC_GROUPS(spi1, "spi1_b_1");
900DB8540_FUNC_GROUPS(spi2, "spi2_a_1");
901DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1");
902DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1");
903DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1");
904DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1");
905DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1");
906DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1");
907DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
908DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1");
909DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1",
910 "u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2",
911 "u2txrx_oc1_1");
912DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1");
913DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1");
914DB8540_FUNC_GROUPS(usb, "usb_a_1");
915
916
917#define FUNCTION(fname) \
918 { \
919 .name = #fname, \
920 .groups = fname##_groups, \
921 .ngroups = ARRAY_SIZE(fname##_groups), \
922 }
923
924static const struct nmk_function nmk_db8540_functions[] = {
925 FUNCTION(apetrig),
926 FUNCTION(clkout),
927 FUNCTION(ddrtrig),
928 FUNCTION(hsi),
929 FUNCTION(hwobs),
930 FUNCTION(hx),
931 FUNCTION(i2c0),
932 FUNCTION(i2c1),
933 FUNCTION(i2c2),
934 FUNCTION(i2c3),
935 FUNCTION(i2c4),
936 FUNCTION(i2c5),
937 FUNCTION(i2c6),
938 FUNCTION(ipgpio),
939 FUNCTION(ipi2c),
940 FUNCTION(kp),
941 FUNCTION(lcd),
942 FUNCTION(lcdb),
943 FUNCTION(mc0),
944 FUNCTION(mc1),
945 FUNCTION(mc2),
946 FUNCTION(mc3),
947 FUNCTION(mc4),
948 FUNCTION(mc5),
949 FUNCTION(modaccgpo),
950 FUNCTION(modaccuart),
951 FUNCTION(modi2s),
952 FUNCTION(modobs),
953 FUNCTION(modprcmudbg),
954 FUNCTION(modrf),
955 FUNCTION(modsmb),
956 FUNCTION(modtrig),
957 FUNCTION(moduart),
958 FUNCTION(modxmip),
959 FUNCTION(msp0),
960 FUNCTION(msp1),
961 FUNCTION(msp2),
962 FUNCTION(msp4),
963 FUNCTION(pwl),
964 FUNCTION(remap),
965 FUNCTION(sbag),
966 FUNCTION(sm),
967 FUNCTION(spi0),
968 FUNCTION(spi1),
969 FUNCTION(spi2),
970 FUNCTION(spi3),
971 FUNCTION(ssp0),
972 FUNCTION(ssp1),
973 FUNCTION(stmape),
974 FUNCTION(stmmod),
975 FUNCTION(tpui),
976 FUNCTION(u0),
977 FUNCTION(u1),
978 FUNCTION(u2),
979 FUNCTION(u3),
980 FUNCTION(u4),
981 FUNCTION(usb)
982};
983
984static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
985 .gpio_ranges = nmk_db8540_ranges,
986 .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
987 .pins = nmk_db8540_pins,
988 .npins = ARRAY_SIZE(nmk_db8540_pins),
989 .functions = nmk_db8540_functions,
990 .nfunctions = ARRAY_SIZE(nmk_db8540_functions),
991 .groups = nmk_db8540_groups,
992 .ngroups = ARRAY_SIZE(nmk_db8540_groups),
993};
994
995void __devinit
996nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
997{
998 *soc = &nmk_db8540_soc;
999}
diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
new file mode 100644
index 000000000000..7d432c3bc359
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
@@ -0,0 +1,357 @@
1#include <linux/kernel.h>
2#include <linux/pinctrl/pinctrl.h>
3#include "pinctrl-nomadik.h"
4
5/* All the pins that can be used for GPIO and some other functions */
6#define _GPIO(offset) (offset)
7
8#define STN8815_PIN_B4 _GPIO(0)
9#define STN8815_PIN_D5 _GPIO(1)
10#define STN8815_PIN_C5 _GPIO(2)
11#define STN8815_PIN_A4 _GPIO(3)
12#define STN8815_PIN_B5 _GPIO(4)
13#define STN8815_PIN_D6 _GPIO(5)
14#define STN8815_PIN_C6 _GPIO(6)
15#define STN8815_PIN_B6 _GPIO(7)
16#define STN8815_PIN_B10 _GPIO(8)
17#define STN8815_PIN_A10 _GPIO(9)
18#define STN8815_PIN_C11 _GPIO(10)
19#define STN8815_PIN_B11 _GPIO(11)
20#define STN8815_PIN_A11 _GPIO(12)
21#define STN8815_PIN_C12 _GPIO(13)
22#define STN8815_PIN_B12 _GPIO(14)
23#define STN8815_PIN_A12 _GPIO(15)
24#define STN8815_PIN_C13 _GPIO(16)
25#define STN8815_PIN_B13 _GPIO(17)
26#define STN8815_PIN_A13 _GPIO(18)
27#define STN8815_PIN_D13 _GPIO(19)
28#define STN8815_PIN_C14 _GPIO(20)
29#define STN8815_PIN_B14 _GPIO(21)
30#define STN8815_PIN_A14 _GPIO(22)
31#define STN8815_PIN_D15 _GPIO(23)
32#define STN8815_PIN_C15 _GPIO(24)
33#define STN8815_PIN_B15 _GPIO(25)
34#define STN8815_PIN_A15 _GPIO(26)
35#define STN8815_PIN_C16 _GPIO(27)
36#define STN8815_PIN_B16 _GPIO(28)
37#define STN8815_PIN_A16 _GPIO(29)
38#define STN8815_PIN_D17 _GPIO(30)
39#define STN8815_PIN_C17 _GPIO(31)
40#define STN8815_PIN_AB6 _GPIO(32)
41#define STN8815_PIN_AA6 _GPIO(33)
42#define STN8815_PIN_Y6 _GPIO(34)
43#define STN8815_PIN_Y5 _GPIO(35)
44#define STN8815_PIN_AA5 _GPIO(36)
45#define STN8815_PIN_AB5 _GPIO(37)
46#define STN8815_PIN_AB4 _GPIO(38)
47#define STN8815_PIN_Y4 _GPIO(39)
48#define STN8815_PIN_R1 _GPIO(40)
49#define STN8815_PIN_R2 _GPIO(41)
50#define STN8815_PIN_R3 _GPIO(42)
51#define STN8815_PIN_P1 _GPIO(43)
52#define STN8815_PIN_P2 _GPIO(44)
53#define STN8815_PIN_P3 _GPIO(45)
54#define STN8815_PIN_N1 _GPIO(46)
55#define STN8815_PIN_N2 _GPIO(47)
56#define STN8815_PIN_N3 _GPIO(48)
57#define STN8815_PIN_M1 _GPIO(49)
58#define STN8815_PIN_M3 _GPIO(50)
59#define STN8815_PIN_M2 _GPIO(51)
60#define STN8815_PIN_L1 _GPIO(52)
61#define STN8815_PIN_L4 _GPIO(53)
62#define STN8815_PIN_L3 _GPIO(54)
63#define STN8815_PIN_L2 _GPIO(55)
64#define STN8815_PIN_F3 _GPIO(56)
65#define STN8815_PIN_F2 _GPIO(57)
66#define STN8815_PIN_E1 _GPIO(58)
67#define STN8815_PIN_E3 _GPIO(59)
68#define STN8815_PIN_E2 _GPIO(60)
69#define STN8815_PIN_E4 _GPIO(61)
70#define STN8815_PIN_D3 _GPIO(62)
71#define STN8815_PIN_D2 _GPIO(63)
72#define STN8815_PIN_F21 _GPIO(64)
73#define STN8815_PIN_F20 _GPIO(65)
74#define STN8815_PIN_E22 _GPIO(66)
75#define STN8815_PIN_D22 _GPIO(67)
76#define STN8815_PIN_E21 _GPIO(68)
77#define STN8815_PIN_E20 _GPIO(69)
78#define STN8815_PIN_C22 _GPIO(70)
79#define STN8815_PIN_D21 _GPIO(71)
80#define STN8815_PIN_D20 _GPIO(72)
81#define STN8815_PIN_C21 _GPIO(73)
82#define STN8815_PIN_C20 _GPIO(74)
83#define STN8815_PIN_C19 _GPIO(75)
84#define STN8815_PIN_B20 _GPIO(76)
85#define STN8815_PIN_B8 _GPIO(77)
86#define STN8815_PIN_A8 _GPIO(78)
87#define STN8815_PIN_C9 _GPIO(79)
88#define STN8815_PIN_B9 _GPIO(80)
89#define STN8815_PIN_A9 _GPIO(81)
90#define STN8815_PIN_C10 _GPIO(82)
91#define STN8815_PIN_K1 _GPIO(83)
92#define STN8815_PIN_K3 _GPIO(84)
93#define STN8815_PIN_K2 _GPIO(85)
94#define STN8815_PIN_J1 _GPIO(86)
95#define STN8815_PIN_J3 _GPIO(87)
96#define STN8815_PIN_J2 _GPIO(88)
97#define STN8815_PIN_H1 _GPIO(89)
98#define STN8815_PIN_H3 _GPIO(90)
99#define STN8815_PIN_H2 _GPIO(91)
100#define STN8815_PIN_G1 _GPIO(92)
101#define STN8815_PIN_G3 _GPIO(93)
102#define STN8815_PIN_G2 _GPIO(94)
103#define STN8815_PIN_F1 _GPIO(95)
104#define STN8815_PIN_T20 _GPIO(96)
105#define STN8815_PIN_R21 _GPIO(97)
106#define STN8815_PIN_R20 _GPIO(98)
107#define STN8815_PIN_U22 _GPIO(99)
108#define STN8815_PIN_N21 _GPIO(100)
109#define STN8815_PIN_N20 _GPIO(101)
110#define STN8815_PIN_P22 _GPIO(102)
111#define STN8815_PIN_N22 _GPIO(103)
112#define STN8815_PIN_V22 _GPIO(104)
113#define STN8815_PIN_V21 _GPIO(105)
114#define STN8815_PIN_K22 _GPIO(106)
115#define STN8815_PIN_K21 _GPIO(107)
116#define STN8815_PIN_H20 _GPIO(108)
117#define STN8815_PIN_G20 _GPIO(109)
118#define STN8815_PIN_L21 _GPIO(110)
119#define STN8815_PIN_H21 _GPIO(111)
120#define STN8815_PIN_J21 _GPIO(112)
121#define STN8815_PIN_H22 _GPIO(113)
122#define STN8815_PIN_K20 _GPIO(114)
123#define STN8815_PIN_L22 _GPIO(115)
124#define STN8815_PIN_G21 _GPIO(116)
125#define STN8815_PIN_J20 _GPIO(117)
126#define STN8815_PIN_G22 _GPIO(118)
127#define STN8815_PIN_U19 _GPIO(119)
128#define STN8815_PIN_G19 _GPIO(120)
129#define STN8815_PIN_M22 _GPIO(121)
130#define STN8815_PIN_M19 _GPIO(122)
131#define STN8815_PIN_J22 _GPIO(123)
132/* GPIOs 124-127 not routed to pins */
133
134/*
135 * The names of the pins are denoted by GPIO number and ball name, even
136 * though they can be used for other things than GPIO, this is the first
137 * column in the table of the data sheet and often used on schematics and
138 * such.
139 */
140static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
141 PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"),
142 PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"),
143 PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"),
144 PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"),
145 PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"),
146 PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"),
147 PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"),
148 PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"),
149 PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"),
150 PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"),
151 PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"),
152 PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"),
153 PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"),
154 PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"),
155 PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"),
156 PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"),
157 PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"),
158 PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"),
159 PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"),
160 PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"),
161 PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"),
162 PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"),
163 PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"),
164 PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"),
165 PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"),
166 PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"),
167 PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"),
168 PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"),
169 PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"),
170 PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"),
171 PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"),
172 PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"),
173 PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"),
174 PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"),
175 PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"),
176 PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"),
177 PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"),
178 PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"),
179 PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"),
180 PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"),
181 PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"),
182 PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"),
183 PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"),
184 PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"),
185 PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"),
186 PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"),
187 PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"),
188 PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"),
189 PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"),
190 PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"),
191 PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"),
192 PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"),
193 PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"),
194 PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"),
195 PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"),
196 PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"),
197 PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"),
198 PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"),
199 PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"),
200 PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"),
201 PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"),
202 PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"),
203 PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"),
204 PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"),
205 PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"),
206 PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"),
207 PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"),
208 PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"),
209 PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"),
210 PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"),
211 PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"),
212 PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"),
213 PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"),
214 PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"),
215 PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"),
216 PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"),
217 PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"),
218 PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"),
219 PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"),
220 PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"),
221 PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"),
222 PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"),
223 PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"),
224 PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"),
225 PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"),
226 PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"),
227 PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"),
228 PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"),
229 PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"),
230 PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"),
231 PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"),
232 PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"),
233 PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"),
234 PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"),
235 PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"),
236 PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"),
237 PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"),
238 PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"),
239 PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"),
240 PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"),
241 PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"),
242 PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"),
243 PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"),
244 PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"),
245 PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"),
246 PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"),
247 PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"),
248 PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"),
249 PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"),
250 PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"),
251 PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"),
252 PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"),
253 PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"),
254 PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"),
255 PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"),
256 PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"),
257 PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"),
258 PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"),
259 PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"),
260 PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"),
261 PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"),
262 PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"),
263 PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"),
264 PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"),
265};
266
267#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \
268 .pin_base = b, .npins = c }
269
270/*
271 * This matches the 32-pin gpio chips registered by the GPIO portion. This
272 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
273 */
274static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
275 STN8815_GPIO_RANGE(0, 0, 32),
276 STN8815_GPIO_RANGE(1, 32, 32),
277 STN8815_GPIO_RANGE(2, 64, 32),
278 STN8815_GPIO_RANGE(3, 96, 28),
279};
280
281/*
282 * Read the pin group names like this:
283 * u0_a_1 = first groups of pins for uart0 on alt function a
284 * i2c2_b_2 = second group of pins for i2c2 on alt function b
285 */
286
287/* Altfunction A */
288static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5,
289 STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6,
290 STN8815_PIN_C6, STN8815_PIN_B6 };
291static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
292 STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
293 STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
294static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1,
295 STN8815_PIN_F3, STN8815_PIN_F2 };
296static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 };
297static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
298/* Altfunction B */
299static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
300static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
301
302#define STN8815_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
303 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
304
305static const struct nmk_pingroup nmk_stn8815_groups[] = {
306 STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
307 STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
308 STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
309 STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
310 STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
311 STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
312 STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
313};
314
315/* We use this macro to define the groups applicable to a function */
316#define STN8815_FUNC_GROUPS(a, b...) \
317static const char * const a##_groups[] = { b };
318
319STN8815_FUNC_GROUPS(u0, "u0_a_1");
320STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1");
321STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
322STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
323STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
324STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
325
326#define FUNCTION(fname) \
327 { \
328 .name = #fname, \
329 .groups = fname##_groups, \
330 .ngroups = ARRAY_SIZE(fname##_groups), \
331 }
332
333static const struct nmk_function nmk_stn8815_functions[] = {
334 FUNCTION(u0),
335 FUNCTION(mmcsd),
336 FUNCTION(u1),
337 FUNCTION(i2c1),
338 FUNCTION(i2c0),
339 FUNCTION(i2cusb),
340};
341
342static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
343 .gpio_ranges = nmk_stn8815_ranges,
344 .gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
345 .pins = nmk_stn8815_pins,
346 .npins = ARRAY_SIZE(nmk_stn8815_pins),
347 .functions = nmk_stn8815_functions,
348 .nfunctions = ARRAY_SIZE(nmk_stn8815_functions),
349 .groups = nmk_stn8815_groups,
350 .ngroups = ARRAY_SIZE(nmk_stn8815_groups),
351};
352
353void __devinit
354nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
355{
356 *soc = &nmk_stn8815_soc;
357}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 3dde6537adb8..6030a513f3c4 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -819,6 +819,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
819 .irq_set_wake = nmk_gpio_irq_set_wake, 819 .irq_set_wake = nmk_gpio_irq_set_wake,
820 .irq_startup = nmk_gpio_irq_startup, 820 .irq_startup = nmk_gpio_irq_startup,
821 .irq_shutdown = nmk_gpio_irq_shutdown, 821 .irq_shutdown = nmk_gpio_irq_shutdown,
822 .flags = IRQCHIP_MASK_ON_SUSPEND,
822}; 823};
823 824
824static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, 825static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
@@ -826,16 +827,14 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
826{ 827{
827 struct nmk_gpio_chip *nmk_chip; 828 struct nmk_gpio_chip *nmk_chip;
828 struct irq_chip *host_chip = irq_get_chip(irq); 829 struct irq_chip *host_chip = irq_get_chip(irq);
829 unsigned int first_irq;
830 830
831 chained_irq_enter(host_chip, desc); 831 chained_irq_enter(host_chip, desc);
832 832
833 nmk_chip = irq_get_handler_data(irq); 833 nmk_chip = irq_get_handler_data(irq);
834 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
835 while (status) { 834 while (status) {
836 int bit = __ffs(status); 835 int bit = __ffs(status);
837 836
838 generic_handle_irq(first_irq + bit); 837 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
839 status &= ~BIT(bit); 838 status &= ~BIT(bit);
840 } 839 }
841 840
@@ -1720,8 +1719,12 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1720 of_match_device(nmk_pinctrl_match, &pdev->dev)->data; 1719 of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
1721 1720
1722 /* Poke in other ASIC variants here */ 1721 /* Poke in other ASIC variants here */
1722 if (version == PINCTRL_NMK_STN8815)
1723 nmk_pinctrl_stn8815_init(&npct->soc);
1723 if (version == PINCTRL_NMK_DB8500) 1724 if (version == PINCTRL_NMK_DB8500)
1724 nmk_pinctrl_db8500_init(&npct->soc); 1725 nmk_pinctrl_db8500_init(&npct->soc);
1726 if (version == PINCTRL_NMK_DB8540)
1727 nmk_pinctrl_db8540_init(&npct->soc);
1725 1728
1726 /* 1729 /*
1727 * We need all the GPIO drivers to probe FIRST, or we will not be able 1730 * We need all the GPIO drivers to probe FIRST, or we will not be able
@@ -1772,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = {
1772static const struct platform_device_id nmk_pinctrl_id[] = { 1775static const struct platform_device_id nmk_pinctrl_id[] = {
1773 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, 1776 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1774 { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, 1777 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1778 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1775}; 1779};
1776 1780
1777static struct platform_driver nmk_pinctrl_driver = { 1781static struct platform_driver nmk_pinctrl_driver = {
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bc91aed7185d..5c99f1c62dfd 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -6,6 +6,7 @@
6/* Package definitions */ 6/* Package definitions */
7#define PINCTRL_NMK_STN8815 0 7#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1 8#define PINCTRL_NMK_DB8500 1
9#define PINCTRL_NMK_DB8540 2
9 10
10/** 11/**
11 * struct nmk_function - Nomadik pinctrl mux function 12 * struct nmk_function - Nomadik pinctrl mux function
@@ -61,6 +62,19 @@ struct nmk_pinctrl_soc_data {
61 unsigned ngroups; 62 unsigned ngroups;
62}; 63};
63 64
65#ifdef CONFIG_PINCTRL_STN8815
66
67void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
68
69#else
70
71static inline void
72nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
73{
74}
75
76#endif
77
64#ifdef CONFIG_PINCTRL_DB8500 78#ifdef CONFIG_PINCTRL_DB8500
65 79
66void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc); 80void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
@@ -74,4 +88,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
74 88
75#endif 89#endif
76 90
91#ifdef CONFIG_PINCTRL_DB8540
92
93void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
94
95#else
96
97static inline void
98nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
99{
100}
101
102#endif
103
77#endif /* PINCTRL_PINCTRL_NOMADIK_H */ 104#endif /* PINCTRL_PINCTRL_NOMADIK_H */
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 76a4260f20f3..726a729a2ec9 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -26,7 +26,8 @@
26#include "core.h" 26#include "core.h"
27 27
28#define DRIVER_NAME "pinctrl-single" 28#define DRIVER_NAME "pinctrl-single"
29#define PCS_MUX_NAME "pinctrl-single,pins" 29#define PCS_MUX_PINS_NAME "pinctrl-single,pins"
30#define PCS_MUX_BITS_NAME "pinctrl-single,bits"
30#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) 31#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
31#define PCS_OFF_DISABLED ~0U 32#define PCS_OFF_DISABLED ~0U
32 33
@@ -54,6 +55,7 @@ struct pcs_pingroup {
54struct pcs_func_vals { 55struct pcs_func_vals {
55 void __iomem *reg; 56 void __iomem *reg;
56 unsigned val; 57 unsigned val;
58 unsigned mask;
57}; 59};
58 60
59/** 61/**
@@ -139,6 +141,7 @@ struct pcs_device {
139 unsigned fshift; 141 unsigned fshift;
140 unsigned foff; 142 unsigned foff;
141 unsigned fmax; 143 unsigned fmax;
144 bool bits_per_mux;
142 struct pcs_name *names; 145 struct pcs_name *names;
143 struct pcs_data pins; 146 struct pcs_data pins;
144 struct radix_tree_root pgtree; 147 struct radix_tree_root pgtree;
@@ -243,7 +246,15 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
243 struct seq_file *s, 246 struct seq_file *s,
244 unsigned offset) 247 unsigned offset)
245{ 248{
246 seq_printf(s, " " DRIVER_NAME); 249 struct pcs_device *pcs;
250 unsigned val;
251
252 pcs = pinctrl_dev_get_drvdata(pctldev);
253
254 val = pcs->read(pcs->base + offset);
255 val &= pcs->fmask;
256
257 seq_printf(s, "%08x %s " , val, DRIVER_NAME);
247} 258}
248 259
249static void pcs_dt_free_map(struct pinctrl_dev *pctldev, 260static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
@@ -332,12 +343,17 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
332 343
333 for (i = 0; i < func->nvals; i++) { 344 for (i = 0; i < func->nvals; i++) {
334 struct pcs_func_vals *vals; 345 struct pcs_func_vals *vals;
335 unsigned val; 346 unsigned val, mask;
336 347
337 vals = &func->vals[i]; 348 vals = &func->vals[i];
338 val = pcs->read(vals->reg); 349 val = pcs->read(vals->reg);
339 val &= ~pcs->fmask; 350 if (!vals->mask)
340 val |= vals->val; 351 mask = pcs->fmask;
352 else
353 mask = pcs->fmask & vals->mask;
354
355 val &= ~mask;
356 val |= (vals->val & mask);
341 pcs->write(val, vals->reg); 357 pcs->write(val, vals->reg);
342 } 358 }
343 359
@@ -657,18 +673,29 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
657{ 673{
658 struct pcs_func_vals *vals; 674 struct pcs_func_vals *vals;
659 const __be32 *mux; 675 const __be32 *mux;
660 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM; 676 int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
661 struct pcs_function *function; 677 struct pcs_function *function;
662 678
663 mux = of_get_property(np, PCS_MUX_NAME, &size); 679 if (pcs->bits_per_mux) {
664 if ((!mux) || (size < sizeof(*mux) * 2)) { 680 params = 3;
665 dev_err(pcs->dev, "bad data for mux %s\n", 681 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
666 np->name); 682 } else {
683 params = 2;
684 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
685 }
686
687 if (!mux) {
688 dev_err(pcs->dev, "no valid property for %s\n", np->name);
689 return -EINVAL;
690 }
691
692 if (size < (sizeof(*mux) * params)) {
693 dev_err(pcs->dev, "bad data for %s\n", np->name);
667 return -EINVAL; 694 return -EINVAL;
668 } 695 }
669 696
670 size /= sizeof(*mux); /* Number of elements in array */ 697 size /= sizeof(*mux); /* Number of elements in array */
671 rows = size / 2; /* Each row is a key value pair */ 698 rows = size / params;
672 699
673 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); 700 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
674 if (!vals) 701 if (!vals)
@@ -686,6 +713,10 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
686 val = be32_to_cpup(mux + index++); 713 val = be32_to_cpup(mux + index++);
687 vals[found].reg = pcs->base + offset; 714 vals[found].reg = pcs->base + offset;
688 vals[found].val = val; 715 vals[found].val = val;
716 if (params == 3) {
717 val = be32_to_cpup(mux + index++);
718 vals[found].mask = val;
719 }
689 720
690 pin = pcs_get_pin_by_offset(pcs, offset); 721 pin = pcs_get_pin_by_offset(pcs, offset);
691 if (pin < 0) { 722 if (pin < 0) {
@@ -883,6 +914,9 @@ static int __devinit pcs_probe(struct platform_device *pdev)
883 if (ret) 914 if (ret)
884 pcs->foff = PCS_OFF_DISABLED; 915 pcs->foff = PCS_OFF_DISABLED;
885 916
917 pcs->bits_per_mux = of_property_read_bool(np,
918 "pinctrl-single,bit-per-mux");
919
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 if (!res) { 921 if (!res) {
888 dev_err(pcs->dev, "could not get resource\n"); 922 dev_err(pcs->dev, "could not get resource\n");
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 304360cd213e..675497c15149 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -25,6 +25,7 @@
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/of_gpio.h> 27#include <linux/of_gpio.h>
28#include <asm/mach/irq.h>
28 29
29#define DRIVER_NAME "pinmux-sirf" 30#define DRIVER_NAME "pinmux-sirf"
30 31
@@ -69,6 +70,10 @@ static DEFINE_SPINLOCK(sgpio_lock);
69 * refer to CS-131858-DC-6A.xls 70 * refer to CS-131858-DC-6A.xls
70 */ 71 */
71static const struct pinctrl_pin_desc sirfsoc_pads[] = { 72static const struct pinctrl_pin_desc sirfsoc_pads[] = {
73 PINCTRL_PIN(0, "gpio0-0"),
74 PINCTRL_PIN(1, "gpio0-1"),
75 PINCTRL_PIN(2, "gpio0-2"),
76 PINCTRL_PIN(3, "gpio0-3"),
72 PINCTRL_PIN(4, "pwm0"), 77 PINCTRL_PIN(4, "pwm0"),
73 PINCTRL_PIN(5, "pwm1"), 78 PINCTRL_PIN(5, "pwm1"),
74 PINCTRL_PIN(6, "pwm2"), 79 PINCTRL_PIN(6, "pwm2"),
@@ -77,7 +82,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
77 PINCTRL_PIN(9, "odo_0"), 82 PINCTRL_PIN(9, "odo_0"),
78 PINCTRL_PIN(10, "odo_1"), 83 PINCTRL_PIN(10, "odo_1"),
79 PINCTRL_PIN(11, "dr_dir"), 84 PINCTRL_PIN(11, "dr_dir"),
85 PINCTRL_PIN(12, "viprom_fa"),
80 PINCTRL_PIN(13, "scl_1"), 86 PINCTRL_PIN(13, "scl_1"),
87 PINCTRL_PIN(14, "ntrst"),
81 PINCTRL_PIN(15, "sda_1"), 88 PINCTRL_PIN(15, "sda_1"),
82 PINCTRL_PIN(16, "x_ldd[16]"), 89 PINCTRL_PIN(16, "x_ldd[16]"),
83 PINCTRL_PIN(17, "x_ldd[17]"), 90 PINCTRL_PIN(17, "x_ldd[17]"),
@@ -1260,8 +1267,10 @@ static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev)
1260 goto out_no_pmx; 1267 goto out_no_pmx;
1261 } 1268 }
1262 1269
1263 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) 1270 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
1271 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
1264 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); 1272 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1273 }
1265 1274
1266 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); 1275 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1267 1276
@@ -1475,6 +1484,9 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1475 u32 status, ctrl; 1484 u32 status, ctrl;
1476 int idx = 0; 1485 int idx = 0;
1477 unsigned int first_irq; 1486 unsigned int first_irq;
1487 struct irq_chip *chip = irq_get_chip(irq);
1488
1489 chained_irq_enter(chip, desc);
1478 1490
1479 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); 1491 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1480 if (!status) { 1492 if (!status) {
@@ -1503,20 +1515,17 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1503 idx++; 1515 idx++;
1504 status = status >> 1; 1516 status = status >> 1;
1505 } 1517 }
1518
1519 chained_irq_exit(chip, desc);
1506} 1520}
1507 1521
1508static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) 1522static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1509{ 1523{
1510 u32 val; 1524 u32 val;
1511 unsigned long flags;
1512
1513 spin_lock_irqsave(&bank->lock, flags);
1514 1525
1515 val = readl(bank->chip.regs + ctrl_offset); 1526 val = readl(bank->chip.regs + ctrl_offset);
1516 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; 1527 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1517 writel(val, bank->chip.regs + ctrl_offset); 1528 writel(val, bank->chip.regs + ctrl_offset);
1518
1519 spin_unlock_irqrestore(&bank->lock, flags);
1520} 1529}
1521 1530
1522static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) 1531static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -1726,6 +1735,8 @@ static int __devinit sirfsoc_gpio_probe(struct device_node *np)
1726 irq_set_handler_data(bank->parent_irq, bank); 1735 irq_set_handler_data(bank->parent_irq, bank);
1727 } 1736 }
1728 1737
1738 return 0;
1739
1729out: 1740out:
1730 iounmap(regs); 1741 iounmap(regs);
1731 return err; 1742 return err;
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 3d5ac73bd5a7..9301a7a95eff 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -232,14 +232,11 @@ int pinmux_request_gpio(struct pinctrl_dev *pctldev,
232 struct pinctrl_gpio_range *range, 232 struct pinctrl_gpio_range *range,
233 unsigned pin, unsigned gpio) 233 unsigned pin, unsigned gpio)
234{ 234{
235 char gpiostr[16];
236 const char *owner; 235 const char *owner;
237 int ret; 236 int ret;
238 237
239 /* Conjure some name stating what chip and pin this is taken by */ 238 /* Conjure some name stating what chip and pin this is taken by */
240 snprintf(gpiostr, 15, "%s:%d", range->name, gpio); 239 owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio);
241
242 owner = kstrdup(gpiostr, GFP_KERNEL);
243 if (!owner) 240 if (!owner)
244 return -EINVAL; 241 return -EINVAL;
245 242
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 04:42:06 -0500