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authorRongjun Ying <rongjun.ying@csr.com>2014-08-18 04:49:22 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-08-29 02:40:12 -0400
commited36c1a06fc73cab289f66cc60b935951f4a1fa0 (patch)
treed93c176463dbe44218b806d57713c6f3dffe001e /drivers/pinctrl
parentc09f80db583c72f9c6198842cd7e6f71105fdc46 (diff)
pinctrl: atlas6: take mclk pin out of i2s pingroup
The I2S controller can output mclk to external audio codec. But by hardware design, some codecs need mclk and some codecs do not need mclk. So the mclk pin can be an independent pinctrl group, and the card driver can get it or not based on boards. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c41
1 files changed, 24 insertions, 17 deletions
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index b0bd2c4034c5..9cc8faf56a6e 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -377,11 +377,25 @@ static const struct sirfsoc_padmux cko1_padmux = {
377 377
378static const unsigned cko1_pins[] = { 42 }; 378static const unsigned cko1_pins[] = { 42 };
379 379
380static const struct sirfsoc_muxmask i2s_muxmask[] = { 380static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
381 { 381 {
382 .group = 1, 382 .group = 1,
383 .mask = BIT(10), 383 .mask = BIT(10),
384 }, { 384 },
385};
386
387static const struct sirfsoc_padmux i2s_mclk_padmux = {
388 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
389 .muxmask = i2s_mclk_muxmask,
390 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
391 .funcmask = BIT(3),
392 .funcval = BIT(3),
393};
394
395static const unsigned i2s_mclk_pins[] = { 42 };
396
397static const struct sirfsoc_muxmask i2s_muxmask[] = {
398 {
385 .group = 3, 399 .group = 3,
386 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 400 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
387 }, 401 },
@@ -391,17 +405,12 @@ static const struct sirfsoc_padmux i2s_padmux = {
391 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 405 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
392 .muxmask = i2s_muxmask, 406 .muxmask = i2s_muxmask,
393 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 407 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
394 .funcmask = BIT(3),
395 .funcval = BIT(3),
396}; 408};
397 409
398static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 }; 410static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
399 411
400static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { 412static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
401 { 413 {
402 .group = 1,
403 .mask = BIT(10),
404 }, {
405 .group = 3, 414 .group = 3,
406 .mask = BIT(2) | BIT(3) | BIT(4), 415 .mask = BIT(2) | BIT(3) | BIT(4),
407 }, 416 },
@@ -411,17 +420,12 @@ static const struct sirfsoc_padmux i2s_no_din_padmux = {
411 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), 420 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
412 .muxmask = i2s_no_din_muxmask, 421 .muxmask = i2s_no_din_muxmask,
413 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 422 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
414 .funcmask = BIT(3),
415 .funcval = BIT(3),
416}; 423};
417 424
418static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 }; 425static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
419 426
420static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { 427static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
421 { 428 {
422 .group = 1,
423 .mask = BIT(10) | BIT(20) | BIT(23),
424 }, {
425 .group = 3, 429 .group = 3,
426 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 430 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
427 }, 431 },
@@ -431,11 +435,11 @@ static const struct sirfsoc_padmux i2s_6chn_padmux = {
431 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), 435 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
432 .muxmask = i2s_6chn_muxmask, 436 .muxmask = i2s_6chn_muxmask,
433 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 437 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
434 .funcmask = BIT(1) | BIT(3) | BIT(9), 438 .funcmask = BIT(1) | BIT(9),
435 .funcval = BIT(1) | BIT(3) | BIT(9), 439 .funcval = BIT(1) | BIT(9),
436}; 440};
437 441
438static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 }; 442static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
439 443
440static const struct sirfsoc_muxmask ac97_muxmask[] = { 444static const struct sirfsoc_muxmask ac97_muxmask[] = {
441 { 445 {
@@ -977,6 +981,7 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
977 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), 981 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
978 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), 982 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
979 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 983 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
984 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
980 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 985 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
981 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), 986 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
982 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), 987 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
@@ -1029,6 +1034,7 @@ static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1029static const char * const 1034static const char * const
1030 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; 1035 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1031static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 1036static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1037static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1032static const char * const i2sgrp[] = { "i2sgrp" }; 1038static const char * const i2sgrp[] = { "i2sgrp" };
1033static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; 1039static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1034static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; 1040static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
@@ -1089,6 +1095,7 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1089 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", 1095 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1090 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), 1096 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1091 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1097 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1098 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1092 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1099 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1093 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), 1100 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1094 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), 1101 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),