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authorNiklas Söderlund <niso@kth.se>2015-01-25 08:49:52 -0500
committerLinus Walleij <linus.walleij@linaro.org>2015-01-27 02:50:22 -0500
commit1e7d5d849cf4f0c51abb85d6b9a3181cebaf82c5 (patch)
tree4345eacb069f2ad5078c13a34b33e40311d8911c /drivers/pinctrl
parent4c9e473541c52453554dd78bdef8c2deba1d2ff3 (diff)
sh-pfc: Add emev2 pinmux support
Add PFC support for the EMMA Mobile EV2 SoC including pin groups for on-chip devices. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c9
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-emev2.c1711
5 files changed, 1727 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 26187aa5cf5b..3267e928beba 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -20,6 +20,11 @@ config GPIO_SH_PFC
20 This enables support for GPIOs within the SoC's pin function 20 This enables support for GPIOs within the SoC's pin function
21 controller. 21 controller.
22 22
23config PINCTRL_PFC_EMEV2
24 def_bool y
25 depends on ARCH_EMEV2
26 select PINCTRL_SH_PFC
27
23config PINCTRL_PFC_R8A73A4 28config PINCTRL_PFC_R8A73A4
24 def_bool y 29 def_bool y
25 depends on ARCH_R8A73A4 30 depends on ARCH_R8A73A4
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index ad8f4cf9faaa..b66432f883e8 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
3sh-pfc-objs += gpio.o 3sh-pfc-objs += gpio.o
4endif 4endif
5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o 5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
6obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o 7obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 66dc62d2156c..b92057d72e3d 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -439,6 +439,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc)
439 439
440#ifdef CONFIG_OF 440#ifdef CONFIG_OF
441static const struct of_device_id sh_pfc_of_table[] = { 441static const struct of_device_id sh_pfc_of_table[] = {
442#ifdef CONFIG_PINCTRL_PFC_EMEV2
443 {
444 .compatible = "renesas,pfc-emev2",
445 .data = &emev2_pinmux_info,
446 },
447#endif
442#ifdef CONFIG_PINCTRL_PFC_R8A73A4 448#ifdef CONFIG_PINCTRL_PFC_R8A73A4
443 { 449 {
444 .compatible = "renesas,pfc-r8a73a4", 450 .compatible = "renesas,pfc-r8a73a4",
@@ -579,6 +585,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
579} 585}
580 586
581static const struct platform_device_id sh_pfc_id_table[] = { 587static const struct platform_device_id sh_pfc_id_table[] = {
588#ifdef CONFIG_PINCTRL_PFC_EMEV2
589 { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info },
590#endif
582#ifdef CONFIG_PINCTRL_PFC_R8A73A4 591#ifdef CONFIG_PINCTRL_PFC_R8A73A4
583 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, 592 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
584#endif 593#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 3daaa5241c47..1998d13ef8b6 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -65,6 +65,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
65int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); 65int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
66int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); 66int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
67 67
68extern const struct sh_pfc_soc_info emev2_pinmux_info;
68extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 69extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
69extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 70extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
70extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 71extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c
new file mode 100644
index 000000000000..9b3ce5d1265b
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c
@@ -0,0 +1,1711 @@
1/*
2 * Pin Function Controller Support
3 *
4 * Copyright (C) 2015 Niklas Söderlund
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12
13#include "sh_pfc.h"
14
15#define CPU_ALL_PORT(fn, pfx, sfx) \
16 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
17 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
18 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
19 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
20 PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
21 PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
22 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
23 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
24
25enum {
26 PINMUX_RESERVED = 0,
27
28 PINMUX_DATA_BEGIN,
29 PORT_ALL(DATA),
30 PINMUX_DATA_END,
31
32 PINMUX_FUNCTION_BEGIN,
33 PORT_ALL(FN),
34
35 /* GPSR0 */
36 FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21,
37 FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23,
38 FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
39
40 /* GPSR1 */
41 FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40,
42 FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43,
43 FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47,
44 FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
45 FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
46 FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
47 FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
48 FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
49
50 /* GPSR2 */
51 FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73,
52 FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76,
53 FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79,
54 FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82,
55 FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85,
56 FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88,
57 FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91,
58 FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94,
59 FN_AB_1_0_PORT95,
60 FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
61 FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
62
63 /* GPSR3 */
64 FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102,
65 FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99,
66 FN_AB_9_8_PORT98, FN_AB_9_8_PORT97,
67 FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111,
68 FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114,
69 FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117,
70 FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120,
71 FN_USI_9_8_PORT121,
72 FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
73 FN_USI1_DO,
74 FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
75 FN_NTSC_DATA3, FN_NTSC_DATA4,
76
77 /* GPRS4 */
78 FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145,
79 FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148,
80 FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150,
81 FN_UART_1_0_PORT157, FN_UART_1_0_PORT158,
82 FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
83 FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
84 FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
85 FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
86 FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
87 FN_UART1_TX,
88
89 /* CHG_PINSEL_LCD3 */
90 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
91 FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
92 FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
93
94 /* CHG_PINSEL_IIC */
95 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
96
97 /* CHG_PINSEL_AB */
98 FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
99 FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
100 FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
101 FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
102 FN_SEL_AB_7_6_10,
103 FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
104 FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
105 FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
106
107 /* CHG_PINSEL_USI */
108 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
109 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
110 FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
111 FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
112 FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
113
114 /* CHG_PINSEL_HSI */
115 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
116
117 /* CHG_PINSEL_UART */
118 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
119
120 PINMUX_FUNCTION_END,
121
122 PINMUX_MARK_BEGIN,
123
124 /* GPSR0 */
125 JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
126 LCD3_PXCLKB_MARK, SD_CKI_MARK,
127
128 /* GPSR1 */
129 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
130 LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
131 SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
132 SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
133 SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
134 SDI1_CMD_MARK,
135
136 /* GPSR2 */
137 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
138 AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
139
140 /* GPSR3 */
141 AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
142 USI1_DO_MARK,
143 NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
144 NTSC_DATA3_MARK, NTSC_DATA4_MARK,
145
146 /* GPSR3 */
147 NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
148 CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
149 CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
150 CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
151 JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
152 UART1_RX_MARK, UART1_TX_MARK,
153
154 /* CHG_PINSEL_LCD3 */
155 LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
156 LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
157 LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
158 LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
159 LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
160 YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
161 YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
162 YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
163 YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
164 YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
165 TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
166 TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
167 TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
168 TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
169 TP33_DATA14_MARK, TP33_DATA15_MARK,
170
171 /* CHG_PINSEL_IIC */
172 IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
173
174 /* CHG_PINSEL_AB */
175 AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
176 AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
177 AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
178 AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
179 AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
180 AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
181 AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
182 AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
183 AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
184 DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
185 DTV_DATA_A_MARK,
186 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
187 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
188 SDI2_DATA3_MARK,
189 CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
190 CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
191 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
192 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
193 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
194 CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
195 CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
196 CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
197 USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
198 USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
199
200 /* CHG_PINSEL_USI */
201 USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
202 USI0_CS6_MARK,
203 USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
204 USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
205 USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
206 USI3_CS0_MARK,
207 USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
208 USI4_CS0_MARK, USI4_CS1_MARK,
209 PWM0_MARK, PWM1_MARK,
210 DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
211 DTV_DATA_B_MARK,
212
213 /* CHG_PINSEL_HSI */
214 USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
215 USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK,
216
217 /* CHG_PINSEL_UART */
218 UART1_CTSB_MARK, UART1_RTSB_MARK,
219 UART2_RX_MARK, UART2_TX_MARK,
220
221 PINMUX_MARK_END,
222};
223
224/* Pin numbers for pins without a corresponding GPIO port number are computed
225 * from the row and column numbers with a 1000 offset to avoid collisions with
226 * GPIO port numbers. */
227#define PIN_NUMBER(row, col) (1000+((row)-1)*23+(col)-1)
228
229/* Expand to a list of sh_pfc_pin entries (named PORT#).
230 * NOTE: No config are recorded since the driver do not handle pinconf. */
231#define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0)
232#define PINMUX_EMEV_GPIO_ALL() CPU_ALL_PORT(__PIN_CFG, , unused)
233
234static const struct sh_pfc_pin pinmux_pins[] = {
235 PINMUX_EMEV_GPIO_ALL(),
236
237 /* Pins not associated with a GPIO port */
238 SH_PFC_PIN_NAMED(2, 14, B14),
239 SH_PFC_PIN_NAMED(2, 15, B15),
240 SH_PFC_PIN_NAMED(2, 16, B16),
241 SH_PFC_PIN_NAMED(2, 17, B17),
242 SH_PFC_PIN_NAMED(3, 14, C14),
243 SH_PFC_PIN_NAMED(3, 15, C15),
244 SH_PFC_PIN_NAMED(3, 16, C16),
245 SH_PFC_PIN_NAMED(3, 17, C17),
246 SH_PFC_PIN_NAMED(4, 14, D14),
247 SH_PFC_PIN_NAMED(4, 15, D15),
248 SH_PFC_PIN_NAMED(4, 16, D16),
249 SH_PFC_PIN_NAMED(4, 17, D17),
250};
251
252/* Expand to a list of name_DATA, name_FN marks */
253#define __PORT_DATA(pn, pfx, sfx) PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
254#define PINMUX_EMEV_DATA_ALL() CPU_ALL_PORT(__PORT_DATA, , unused)
255
256static const u16 pinmux_data[] = {
257 PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */
258
259 /* GPSR0 */
260 /* V9 */
261 PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL),
262 /* U9 */
263 PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB),
264 /* V8 */
265 PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO),
266 /* U8 */
267 PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI),
268 /* B22*/
269 PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
270 PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
271 /* C21 */
272 PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB),
273 /* A21 */
274 PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
275 PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
276 /* B21 */
277 PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00),
278 PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01),
279 /* C20 */
280 PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00),
281 PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01),
282 /* D19 */
283 PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00),
284 PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01),
285
286 /* GPSR1 */
287 /* A20 */
288 PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0),
289 /* B20 */
290 PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1),
291 /* A19 */
292 PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2),
293 /* B19 */
294 PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3),
295 /* C19 */
296 PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4),
297 /* B18 */
298 PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5),
299 /* C18 */
300 PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
301 PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
302 /* D18 */
303 PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00),
304 PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10),
305 /* A18 */
306 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00),
307 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01),
308 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10),
309 /* A17 */
310 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00),
311 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01),
312 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10),
313 /* B17 */
314 PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
315 PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
316 PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
317 /* C17 */
318 PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
319 PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
320 PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
321 /* D17 */
322 PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
323 PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
324 PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
325 /* B16 */
326 PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
327 PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
328 PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
329 /* C16 */
330 PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
331 PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
332 PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
333 /* D16 */
334 PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
335 PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
336 PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
337 /* A16 */
338 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00),
339 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01),
340 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10),
341 /* A15 */
342 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00),
343 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01),
344 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10),
345 /* B15 */
346 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00),
347 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01),
348 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10),
349 /* C15 */
350 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00),
351 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01),
352 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10),
353 /* D15 */
354 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00),
355 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01),
356 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10),
357 /* B14 */
358 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00),
359 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01),
360 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10),
361 /* C14 */
362 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00),
363 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01),
364 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10),
365 /* D14 */
366 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00),
367 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
368 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
369 /* AA9 */
370 PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL),
371 /* AA8 */
372 PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA),
373 /* Y9 */
374 PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
375 PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
376 /* Y8 */
377 PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
378 PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
379 /* AC19 */
380 PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI),
381 /* AB18 */
382 PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO),
383 /* AC18 */
384 PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI),
385 /* Y12 */
386 PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD),
387 /* AA13 */
388 PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0),
389 /* Y13 */
390 PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1),
391 /* AA14 */
392 PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2),
393 /* Y14 */
394 PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3),
395 /* AA15 */
396 PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4),
397 /* Y15 */
398 PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5),
399 /* AA16 */
400 PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6),
401 /* Y16 */
402 PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7),
403 /* AB22 */
404 PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO),
405 /* AA23 */
406 PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI),
407 /* AC21 */
408 PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD),
409
410 /* GPSR2 */
411 /* AB21 */
412 PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0),
413 /* AB20 */
414 PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1),
415 /* AB19 */
416 PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2),
417 /* AA19 */
418 PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3),
419 /* J23 */
420 PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK),
421 /* D21 */
422 PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0),
423 /* E21 */
424 PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1),
425 /* F20 */
426 PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
427 PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
428 /* G20 */
429 PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00),
430 PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10),
431 /* J20 */
432 PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00),
433 PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10),
434 /* H20 */
435 PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00),
436 PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10),
437 /* L20 */
438 PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00),
439 PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10),
440 /* K20 */
441 PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00),
442 PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10),
443 /* C23 */
444 PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00),
445 PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10),
446 /* C22 */
447 PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00),
448 PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10),
449 /* D23 */
450 PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00),
451 PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10),
452 /* D22 */
453 PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00),
454 PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10),
455 /* E23 */
456 PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00),
457 PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10),
458 /* E22 */
459 PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00),
460 PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10),
461 /* F23 */
462 PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00),
463 PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10),
464 /* F22 */
465 PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00),
466 PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10),
467 /* F21 */
468 PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00),
469 PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01),
470 PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10),
471 PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11),
472 /* G23 */
473 PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00),
474 PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01),
475 PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10),
476 PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11),
477 /* G22 */
478 PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00),
479 PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01),
480 PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10),
481 PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11),
482 /* G21 */
483 PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00),
484 PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01),
485 PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10),
486 PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11),
487 /* H23 */
488 PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00),
489 PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01),
490 PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10),
491 PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11),
492 /* H22 */
493 PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00),
494 PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01),
495 PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10),
496 PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11),
497 /* H21 */
498 PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00),
499 PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01),
500 PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10),
501 /* J22 */
502 PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00),
503 PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01),
504 PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10),
505 /* J21 */
506 PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00),
507 PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10),
508 /* K21 */
509 PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00),
510 PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10),
511 /* L21 */
512 PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00),
513 PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10),
514
515 /* GPSR3 */
516 /* M21 */
517 PINMUX_DATA(AB_A20_MARK, FN_AB_A20),
518 /* N21 */
519 PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
520 PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
521 PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10),
522 /* M20 */
523 PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00),
524 PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01),
525 /* N20 */
526 PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00),
527 PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01),
528 /* L18 */
529 PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00),
530 PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10),
531 /* M18 */
532 PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00),
533 PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10),
534 /* N18 */
535 PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00),
536 PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10),
537 /* L17 */
538 PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00),
539 PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10),
540 /* M17 */
541 PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
542 PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
543 /* B8 */
544 PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1),
545 /* B9 */
546 PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2),
547 /* C10 */
548 PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI),
549 /* D10 */
550 PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO),
551 /* AB5 */
552 PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
553 PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
554 /* AA6 */
555 PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00),
556 PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01),
557 /* AA5 */
558 PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00),
559 PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01),
560 /* Y7 */
561 PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00),
562 PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01),
563 /* AA7 */
564 PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00),
565 PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01),
566 /* Y6 */
567 PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00),
568 PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01),
569 /* AC5 */
570 PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00),
571 PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01),
572 /* AC4 */
573 PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00),
574 PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01),
575 /* AC3 */
576 PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00),
577 PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01),
578 /* AB4 */
579 PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00),
580 PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01),
581 /* AB3 */
582 PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01),
583 /* AA4 */
584 PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
585 PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01),
586 /* Y5 */
587 PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
588 PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
589 /* V20 */
590 PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK),
591 /* P20 */
592 PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0),
593 /* P18 */
594 PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1),
595 /* R20 */
596 PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2),
597 /* R18 */
598 PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3),
599 /* T20 */
600 PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4),
601
602 /* GPRS3 */
603 /* T18 */
604 PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5),
605 /* U20 */
606 PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6),
607 /* U18 */
608 PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7),
609 /* W23 */
610 PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO),
611 /* Y23 */
612 PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI),
613 /* W22 */
614 PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS),
615 /* V21 */
616 PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS),
617 /* T21 */
618 PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0),
619 /* T22 */
620 PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1),
621 /* T23 */
622 PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2),
623 /* U21 */
624 PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3),
625 /* U22 */
626 PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4),
627 /* U23 */
628 PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5),
629 /* V22 */
630 PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6),
631 /* V23 */
632 PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7),
633 /* K22 */
634 PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
635 /* K23 */
636 PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01),
637 /* L23 */
638 PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01),
639 /* L22 */
640 PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01),
641 /* N22 */
642 PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01),
643 /* N23 */
644 PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01),
645 /* M23 */
646 PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01),
647 /* M22 */
648 PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
649 /* D13 */
650 PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO),
651 /* F13 */
652 PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN),
653 /* AA12 */
654 PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS),
655 /* A12 */
656 PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR),
657 /* Y11 */
658 PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX),
659 /* Y10 */
660 PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX),
661 /* AA10 */
662 PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
663 PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
664 /* AB10 */
665 PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00),
666 PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
667};
668
669
670#define EMEV_MUX_PIN(name, pin, mark) \
671 static const unsigned int name##_pins[] = { pin }; \
672 static const unsigned int name##_mux[] = { mark##_MARK }
673
674/* = [ System ] =========== */
675EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
676EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
677EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
678EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
679
680/* = [ External Memory] === */
681static const unsigned int ab_main_pins[] = {
682 /* AB_RDB, AB_WRB */
683 73, 74,
684 /* AB_AD[0:15] */
685 77, 78, 79, 80,
686 81, 82, 83, 84,
687 85, 86, 87, 88,
688 89, 90, 91, 92,
689};
690static const unsigned int ab_main_mux[] = {
691 AB_RDB_MARK, AB_WRB_MARK,
692 AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK,
693 AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK,
694 AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK,
695 AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK,
696};
697
698EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
699EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
700EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
701EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
702EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
703EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
704EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
705EMEV_MUX_PIN(ab_a17, 93, AB_A17);
706EMEV_MUX_PIN(ab_a18, 94, AB_A18);
707EMEV_MUX_PIN(ab_a19, 95, AB_A19);
708EMEV_MUX_PIN(ab_a20, 96, AB_A20);
709EMEV_MUX_PIN(ab_a21, 97, AB_A21);
710EMEV_MUX_PIN(ab_a22, 98, AB_A22);
711EMEV_MUX_PIN(ab_a23, 99, AB_A23);
712EMEV_MUX_PIN(ab_a24, 100, AB_A24);
713EMEV_MUX_PIN(ab_a25, 101, AB_A25);
714EMEV_MUX_PIN(ab_a26, 102, AB_A26);
715EMEV_MUX_PIN(ab_a27, 103, AB_A27);
716EMEV_MUX_PIN(ab_a28, 104, AB_A28);
717EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
718EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
719
720/* = [ CAM ] ============== */
721EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
722static const unsigned int cam_pins[] = {
723 /* CLKI, VS, HS */
724 132, 133, 134,
725 /* CAM_YUV[0:7] */
726 135, 136, 137, 138,
727 139, 140, 141, 142,
728};
729static const unsigned int cam_mux[] = {
730 CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK,
731 CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK,
732 CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
733};
734
735/* = [ CF ] -============== */
736static const unsigned int cf_ctrl_pins[] = {
737 /* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET,
738 * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */
739 71, 72, 73, 74,
740 75, 76, 93, 94,
741 95, 97, 100, 101,
742 102,
743};
744static const unsigned int cf_ctrl_mux[] = {
745 CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK,
746 CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK,
747 CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK,
748 CF_CDB2_MARK,
749};
750
751static const unsigned int cf_data8_pins[] = {
752 /* CF_D[0:8] */
753 77, 78, 79, 80,
754 81, 82, 83, 84,
755};
756static const unsigned int cf_data8_mux[] = {
757 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
758 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
759};
760static const unsigned int cf_data16_pins[] = {
761 /* CF_D[0:15] */
762 77, 78, 79, 80,
763 81, 82, 83, 84,
764 85, 86, 87, 88,
765 89, 90, 91, 92,
766};
767static const unsigned int cf_data16_mux[] = {
768 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
769 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
770 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
771 CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
772};
773
774/* = [ DTV ] ============== */
775static const unsigned int dtv_a_pins[] = {
776 /* BCLK, PSYNC, VALID, DATA */
777 85, 86, 87, 88,
778};
779static const unsigned int dtv_a_mux[] = {
780 DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK,
781};
782
783static const unsigned int dtv_b_pins[] = {
784 /* BCLK, PSYNC, VALID, DATA */
785 109, 110, 111, 112,
786};
787static const unsigned int dtv_b_mux[] = {
788 DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK,
789};
790
791/* = [ IIC0 ] ============= */
792static const unsigned int iic0_pins[] = {
793 /* SCL, SDA */
794 44, 45,
795};
796static const unsigned int iic0_mux[] = {
797 IIC0_SCL_MARK, IIC0_SDA_MARK,
798};
799
800/* = [ IIC1 ] ============= */
801static const unsigned int iic1_pins[] = {
802 /* SCL, SDA */
803 46, 47,
804};
805static const unsigned int iic1_mux[] = {
806 IIC1_SCL_MARK, IIC1_SDA_MARK,
807};
808
809/* = [ JTAG ] ============= */
810static const unsigned int jtag_pins[] = {
811 /* SEL, TDO, TDOEN */
812 2, 151, 152,
813};
814static const unsigned int jtag_mux[] = {
815 JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK,
816};
817
818/* = [ LCD/YUV ] ========== */
819EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
820EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
821EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
822
823static const unsigned int lcd3_sync_pins[] = {
824 /* HS, VS, DE */
825 21, 22, 23,
826};
827static const unsigned int lcd3_sync_mux[] = {
828 LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK,
829};
830
831static const unsigned int lcd3_rgb888_pins[] = {
832 /* R[0:7], G[0:7], B[0:7] */
833 32, 33, 34, 35,
834 36, 37, 38, 39,
835 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
836 PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
837 PIN_NUMBER(4, 16),
838 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
839 PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
840 PIN_NUMBER(4, 14)
841};
842static const unsigned int lcd3_rgb888_mux[] = {
843 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
844 LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK,
845 LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK,
846 LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK,
847 LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
848 LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
849};
850
851EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
852static const unsigned int yuv3_pins[] = {
853 /* CLK_O, HS, VS, DE */
854 18, 21, 22, 23,
855 /* YUV3_D[0:15] */
856 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
857 PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
858 PIN_NUMBER(4, 16),
859 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
860 PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
861 PIN_NUMBER(4, 14),
862};
863static const unsigned int yuv3_mux[] = {
864 YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
865 YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
866 YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK,
867 YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK,
868 YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
869};
870
871/* = [ NTSC ] ============= */
872EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
873static const unsigned int ntsc_data_pins[] = {
874 /* NTSC_DATA[0:7] */
875 123, 124, 125, 126,
876 127, 128, 129, 130,
877};
878static const unsigned int ntsc_data_mux[] = {
879 NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK,
880 NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK,
881};
882
883/* = [ PWM0 ] ============= */
884EMEV_MUX_PIN(pwm0, 120, PWM0);
885
886/* = [ PWM1 ] ============= */
887EMEV_MUX_PIN(pwm1, 121, PWM1);
888
889/* = [ SD ] =============== */
890EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
891
892/* = [ SDIO0 ] ============ */
893static const unsigned int sdi0_ctrl_pins[] = {
894 /* CKO, CKI, CMD */
895 50, 51, 52,
896};
897static const unsigned int sdi0_ctrl_mux[] = {
898 SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
899};
900
901static const unsigned int sdi0_data1_pins[] = {
902 /* SDI0_DATA[0] */
903 53,
904};
905static const unsigned int sdi0_data1_mux[] = {
906 SDI0_DATA0_MARK,
907};
908static const unsigned int sdi0_data4_pins[] = {
909 /* SDI0_DATA[0:3] */
910 53, 54, 55, 56,
911};
912static const unsigned int sdi0_data4_mux[] = {
913 SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
914};
915static const unsigned int sdi0_data8_pins[] = {
916 /* SDI0_DATA[0:7] */
917 53, 54, 55, 56,
918 57, 58, 59, 60
919};
920static const unsigned int sdi0_data8_mux[] = {
921 SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
922 SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
923};
924
925/* = [ SDIO1 ] ============ */
926static const unsigned int sdi1_ctrl_pins[] = {
927 /* CKO, CKI, CMD */
928 61, 62, 63,
929};
930static const unsigned int sdi1_ctrl_mux[] = {
931 SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
932};
933
934static const unsigned int sdi1_data1_pins[] = {
935 /* SDI1_DATA[0] */
936 64,
937};
938static const unsigned int sdi1_data1_mux[] = {
939 SDI1_DATA0_MARK,
940};
941static const unsigned int sdi1_data4_pins[] = {
942 /* SDI1_DATA[0:3] */
943 64, 65, 66, 67,
944};
945static const unsigned int sdi1_data4_mux[] = {
946 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
947};
948
949/* = [ SDIO2 ] ============ */
950static const unsigned int sdi2_ctrl_pins[] = {
951 /* CKO, CKI, CMD */
952 97, 98, 99,
953};
954static const unsigned int sdi2_ctrl_mux[] = {
955 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
956};
957
958static const unsigned int sdi2_data1_pins[] = {
959 /* SDI2_DATA[0] */
960 89,
961};
962static const unsigned int sdi2_data1_mux[] = {
963 SDI2_DATA0_MARK,
964};
965static const unsigned int sdi2_data4_pins[] = {
966 /* SDI2_DATA[0:3] */
967 89, 90, 91, 92,
968};
969static const unsigned int sdi2_data4_mux[] = {
970 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
971};
972
973/* = [ TP33 ] ============= */
974static const unsigned int tp33_pins[] = {
975 /* CLK, CTRL */
976 38, 39,
977 /* TP33_DATA[0:15] */
978 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
979 PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
980 PIN_NUMBER(4, 16),
981 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
982 PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
983 PIN_NUMBER(4, 14),
984};
985static const unsigned int tp33_mux[] = {
986 TP33_CLK_MARK, TP33_CTRL_MARK,
987 TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK,
988 TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK,
989 TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK,
990 TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK,
991};
992
993/* = [ UART1 ] ============ */
994static const unsigned int uart1_data_pins[] = {
995 /* RX, TX */
996 155, 156,
997};
998static const unsigned int uart1_data_mux[] = {
999 UART1_RX_MARK, UART1_TX_MARK,
1000};
1001
1002static const unsigned int uart1_ctrl_pins[] = {
1003 /* CTSB, RTSB */
1004 157, 158,
1005};
1006static const unsigned int uart1_ctrl_mux[] = {
1007 UART1_CTSB_MARK, UART1_RTSB_MARK,
1008};
1009
1010/* = [ UART2 ] ============ */
1011static const unsigned int uart2_data_pins[] = {
1012 /* RX, TX */
1013 157, 158,
1014};
1015static const unsigned int uart2_data_mux[] = {
1016 UART2_RX_MARK, UART2_TX_MARK,
1017};
1018
1019/* = [ UART3 ] ============ */
1020static const unsigned int uart3_data_pins[] = {
1021 /* RX, TX */
1022 46, 47,
1023};
1024static const unsigned int uart3_data_mux[] = {
1025 UART3_RX_MARK, UART3_TX_MARK,
1026};
1027
1028/* = [ USB ] ============== */
1029EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
1030
1031/* = [ USI0 ] ============== */
1032EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
1033EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
1034EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
1035EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
1036EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
1037EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
1038
1039/* = [ USI1 ] ============== */
1040static const unsigned int usi1_pins[] = {
1041 /* DI, DO*/
1042 107, 108,
1043};
1044static const unsigned int usi1_mux[] = {
1045 USI1_DI_MARK, USI1_DO_MARK,
1046};
1047
1048/* = [ USI2 ] ============== */
1049static const unsigned int usi2_pins[] = {
1050 /* CLK, DI, DO*/
1051 109, 110, 111,
1052};
1053static const unsigned int usi2_mux[] = {
1054 USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
1055};
1056EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
1057EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
1058EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
1059
1060/* = [ USI3 ] ============== */
1061static const unsigned int usi3_pins[] = {
1062 /* CLK, DI, DO*/
1063 115, 116, 117,
1064};
1065static const unsigned int usi3_mux[] = {
1066 USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
1067};
1068EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
1069
1070/* = [ USI4 ] ============== */
1071static const unsigned int usi4_pins[] = {
1072 /* CLK, DI, DO*/
1073 119, 120, 121,
1074};
1075static const unsigned int usi4_mux[] = {
1076 USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
1077};
1078EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
1079EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
1080
1081/* = [ USI5 ] ============== */
1082static const unsigned int usi5_a_pins[] = {
1083 /* CLK, DI, DO*/
1084 85, 86, 87,
1085};
1086static const unsigned int usi5_a_mux[] = {
1087 USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
1088};
1089EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
1090EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
1091EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
1092
1093static const unsigned int usi5_b_pins[] = {
1094 /* CLK, DI, DO*/
1095 143, 144, 150,
1096};
1097static const unsigned int usi5_b_mux[] = {
1098 USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK,
1099};
1100EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
1101EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
1102EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
1103EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
1104EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
1105
1106static const struct sh_pfc_pin_group pinmux_groups[] = {
1107 SH_PFC_PIN_GROUP(err_rst_reqb),
1108 SH_PFC_PIN_GROUP(ref_clko),
1109 SH_PFC_PIN_GROUP(ext_clki),
1110 SH_PFC_PIN_GROUP(lowpwr),
1111
1112 SH_PFC_PIN_GROUP(ab_main),
1113 SH_PFC_PIN_GROUP(ab_clk),
1114 SH_PFC_PIN_GROUP(ab_csb0),
1115 SH_PFC_PIN_GROUP(ab_csb1),
1116 SH_PFC_PIN_GROUP(ab_csb2),
1117 SH_PFC_PIN_GROUP(ab_csb3),
1118 SH_PFC_PIN_GROUP(ab_wait),
1119 SH_PFC_PIN_GROUP(ab_adv),
1120 SH_PFC_PIN_GROUP(ab_a17),
1121 SH_PFC_PIN_GROUP(ab_a18),
1122 SH_PFC_PIN_GROUP(ab_a19),
1123 SH_PFC_PIN_GROUP(ab_a20),
1124 SH_PFC_PIN_GROUP(ab_a21),
1125 SH_PFC_PIN_GROUP(ab_a22),
1126 SH_PFC_PIN_GROUP(ab_a23),
1127 SH_PFC_PIN_GROUP(ab_a24),
1128 SH_PFC_PIN_GROUP(ab_a25),
1129 SH_PFC_PIN_GROUP(ab_a26),
1130 SH_PFC_PIN_GROUP(ab_a27),
1131 SH_PFC_PIN_GROUP(ab_a28),
1132 SH_PFC_PIN_GROUP(ab_ben0),
1133 SH_PFC_PIN_GROUP(ab_ben1),
1134
1135 SH_PFC_PIN_GROUP(cam_clko),
1136 SH_PFC_PIN_GROUP(cam),
1137
1138 SH_PFC_PIN_GROUP(cf_ctrl),
1139 SH_PFC_PIN_GROUP(cf_data8),
1140 SH_PFC_PIN_GROUP(cf_data16),
1141
1142 SH_PFC_PIN_GROUP(dtv_a),
1143 SH_PFC_PIN_GROUP(dtv_b),
1144
1145 SH_PFC_PIN_GROUP(iic0),
1146
1147 SH_PFC_PIN_GROUP(iic1),
1148
1149 SH_PFC_PIN_GROUP(jtag),
1150
1151 SH_PFC_PIN_GROUP(lcd3_pxclk),
1152 SH_PFC_PIN_GROUP(lcd3_pxclkb),
1153 SH_PFC_PIN_GROUP(lcd3_clk_i),
1154 SH_PFC_PIN_GROUP(lcd3_sync),
1155 SH_PFC_PIN_GROUP(lcd3_rgb888),
1156 SH_PFC_PIN_GROUP(yuv3_clk_i),
1157 SH_PFC_PIN_GROUP(yuv3),
1158
1159 SH_PFC_PIN_GROUP(ntsc_clk),
1160 SH_PFC_PIN_GROUP(ntsc_data),
1161
1162 SH_PFC_PIN_GROUP(pwm0),
1163
1164 SH_PFC_PIN_GROUP(pwm1),
1165
1166 SH_PFC_PIN_GROUP(sd_cki),
1167
1168 SH_PFC_PIN_GROUP(sdi0_ctrl),
1169 SH_PFC_PIN_GROUP(sdi0_data1),
1170 SH_PFC_PIN_GROUP(sdi0_data4),
1171 SH_PFC_PIN_GROUP(sdi0_data8),
1172
1173 SH_PFC_PIN_GROUP(sdi1_ctrl),
1174 SH_PFC_PIN_GROUP(sdi1_data1),
1175 SH_PFC_PIN_GROUP(sdi1_data4),
1176
1177 SH_PFC_PIN_GROUP(sdi2_ctrl),
1178 SH_PFC_PIN_GROUP(sdi2_data1),
1179 SH_PFC_PIN_GROUP(sdi2_data4),
1180
1181 SH_PFC_PIN_GROUP(tp33),
1182
1183 SH_PFC_PIN_GROUP(uart1_data),
1184 SH_PFC_PIN_GROUP(uart1_ctrl),
1185
1186 SH_PFC_PIN_GROUP(uart2_data),
1187
1188 SH_PFC_PIN_GROUP(uart3_data),
1189
1190 SH_PFC_PIN_GROUP(usb_vbus),
1191
1192 SH_PFC_PIN_GROUP(usi0_cs1),
1193 SH_PFC_PIN_GROUP(usi0_cs2),
1194 SH_PFC_PIN_GROUP(usi0_cs3),
1195 SH_PFC_PIN_GROUP(usi0_cs4),
1196 SH_PFC_PIN_GROUP(usi0_cs5),
1197 SH_PFC_PIN_GROUP(usi0_cs6),
1198
1199 SH_PFC_PIN_GROUP(usi1),
1200
1201 SH_PFC_PIN_GROUP(usi2),
1202 SH_PFC_PIN_GROUP(usi2_cs0),
1203 SH_PFC_PIN_GROUP(usi2_cs1),
1204 SH_PFC_PIN_GROUP(usi2_cs2),
1205
1206 SH_PFC_PIN_GROUP(usi3),
1207 SH_PFC_PIN_GROUP(usi3_cs0),
1208
1209 SH_PFC_PIN_GROUP(usi4),
1210 SH_PFC_PIN_GROUP(usi4_cs0),
1211 SH_PFC_PIN_GROUP(usi4_cs1),
1212
1213 SH_PFC_PIN_GROUP(usi5_a),
1214 SH_PFC_PIN_GROUP(usi5_cs0_a),
1215 SH_PFC_PIN_GROUP(usi5_cs1_a),
1216 SH_PFC_PIN_GROUP(usi5_cs2_a),
1217 SH_PFC_PIN_GROUP(usi5_b),
1218 SH_PFC_PIN_GROUP(usi5_cs0_b),
1219 SH_PFC_PIN_GROUP(usi5_cs1_b),
1220 SH_PFC_PIN_GROUP(usi5_cs2_b),
1221 SH_PFC_PIN_GROUP(usi5_cs3_b),
1222 SH_PFC_PIN_GROUP(usi5_cs4_b),
1223};
1224
1225static const char * const ab_groups[] = {
1226 "ab_main",
1227 "ab_clk",
1228 "ab_csb0",
1229 "ab_csb1",
1230 "ab_csb2",
1231 "ab_csb3",
1232 "ab_wait",
1233 "ab_adv",
1234 "ab_a17",
1235 "ab_a18",
1236 "ab_a19",
1237 "ab_a20",
1238 "ab_a21",
1239 "ab_a22",
1240 "ab_a23",
1241 "ab_a24",
1242 "ab_a25",
1243 "ab_a26",
1244 "ab_a27",
1245 "ab_a28",
1246 "ab_ben0",
1247 "ab_ben1",
1248};
1249
1250static const char * const cam_groups[] = {
1251 "cam_clko",
1252 "cam",
1253};
1254
1255static const char * const cf_groups[] = {
1256 "cf_ctrl",
1257 "cf_data8",
1258 "cf_data16",
1259};
1260
1261static const char * const dtv_groups[] = {
1262 "dtv_a",
1263 "dtv_b",
1264};
1265
1266static const char * const iic0_groups[] = {
1267 "iic0",
1268};
1269
1270static const char * const iic1_groups[] = {
1271 "iic1",
1272};
1273
1274static const char * const jtag_groups[] = {
1275 "jtag",
1276};
1277
1278static const char * const lcd_groups[] = {
1279 "lcd3_pxclk",
1280 "lcd3_pxclkb",
1281 "lcd3_clk_i",
1282 "lcd3_sync",
1283 "lcd3_rgb888",
1284 "yuv3_clk_i",
1285 "yuv3",
1286};
1287
1288static const char * const ntsc_groups[] = {
1289 "ntsc_clk",
1290 "ntsc_data",
1291};
1292
1293static const char * const pwm0_groups[] = {
1294 "pwm0",
1295};
1296
1297static const char * const pwm1_groups[] = {
1298 "pwm1",
1299};
1300
1301static const char * const sd_groups[] = {
1302 "sd_cki",
1303};
1304
1305static const char * const sdi0_groups[] = {
1306 "sdi0_ctrl",
1307 "sdi0_data1",
1308 "sdi0_data4",
1309 "sdi0_data8",
1310};
1311
1312static const char * const sdi1_groups[] = {
1313 "sdi1_ctrl",
1314 "sdi1_data1",
1315 "sdi1_data4",
1316};
1317
1318static const char * const sdi2_groups[] = {
1319 "sdi2_ctrl",
1320 "sdi2_data1",
1321 "sdi2_data4",
1322};
1323
1324static const char * const tp33_groups[] = {
1325 "tp33",
1326};
1327
1328static const char * const uart1_groups[] = {
1329 "uart1_data",
1330 "uart1_ctrl",
1331};
1332
1333static const char * const uart2_groups[] = {
1334 "uart2_data",
1335};
1336
1337static const char * const uart3_groups[] = {
1338 "uart3_data",
1339};
1340
1341static const char * const usb_groups[] = {
1342 "usb_vbus",
1343};
1344
1345static const char * const usi0_groups[] = {
1346 "usi0_cs1",
1347 "usi0_cs2",
1348 "usi0_cs3",
1349 "usi0_cs4",
1350 "usi0_cs5",
1351 "usi0_cs6",
1352};
1353
1354static const char * const usi1_groups[] = {
1355 "usi1",
1356};
1357
1358static const char * const usi2_groups[] = {
1359 "usi2",
1360 "usi2_cs0",
1361 "usi2_cs1",
1362 "usi2_cs2",
1363};
1364
1365static const char * const usi3_groups[] = {
1366 "usi3",
1367 "usi3_cs0",
1368};
1369
1370static const char * const usi4_groups[] = {
1371 "usi4",
1372 "usi4_cs0",
1373 "usi4_cs1",
1374};
1375
1376static const char * const usi5_groups[] = {
1377 "usi5_a",
1378 "usi5_cs0_a",
1379 "usi5_cs1_a",
1380 "usi5_cs2_a",
1381 "usi5_b",
1382 "usi5_cs0_b",
1383 "usi5_cs1_b",
1384 "usi5_cs2_b",
1385 "usi5_cs3_b",
1386 "usi5_cs4_b",
1387};
1388
1389static const struct sh_pfc_function pinmux_functions[] = {
1390 SH_PFC_FUNCTION(ab),
1391 SH_PFC_FUNCTION(cam),
1392 SH_PFC_FUNCTION(cf),
1393 SH_PFC_FUNCTION(dtv),
1394 SH_PFC_FUNCTION(iic0),
1395 SH_PFC_FUNCTION(iic1),
1396 SH_PFC_FUNCTION(jtag),
1397 SH_PFC_FUNCTION(lcd),
1398 SH_PFC_FUNCTION(ntsc),
1399 SH_PFC_FUNCTION(pwm0),
1400 SH_PFC_FUNCTION(pwm1),
1401 SH_PFC_FUNCTION(sd),
1402 SH_PFC_FUNCTION(sdi0),
1403 SH_PFC_FUNCTION(sdi1),
1404 SH_PFC_FUNCTION(sdi2),
1405 SH_PFC_FUNCTION(tp33),
1406 SH_PFC_FUNCTION(uart1),
1407 SH_PFC_FUNCTION(uart2),
1408 SH_PFC_FUNCTION(uart3),
1409 SH_PFC_FUNCTION(usb),
1410 SH_PFC_FUNCTION(usi0),
1411 SH_PFC_FUNCTION(usi1),
1412 SH_PFC_FUNCTION(usi2),
1413 SH_PFC_FUNCTION(usi3),
1414 SH_PFC_FUNCTION(usi4),
1415 SH_PFC_FUNCTION(usi5),
1416};
1417
1418static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1419 { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {
1420 0, PORT31_FN, /* PIN: J18 */
1421 0, PORT30_FN, /* PIN: H18 */
1422 0, PORT29_FN, /* PIN: G18 */
1423 0, PORT28_FN, /* PIN: F18 */
1424 0, PORT27_FN, /* PIN: F17 */
1425 0, PORT26_FN, /* PIN: F16 */
1426 0, PORT25_FN, /* PIN: E20 */
1427 0, PORT24_FN, /* PIN: D20 */
1428 FN_LCD3_1_0_PORT23, PORT23_FN, /* PIN: D19 */
1429 FN_LCD3_1_0_PORT22, PORT22_FN, /* PIN: C20 */
1430 FN_LCD3_1_0_PORT21, PORT21_FN, /* PIN: B21 */
1431 FN_LCD3_1_0_PORT20, PORT20_FN, /* PIN: A21 */
1432 FN_LCD3_PXCLKB, PORT19_FN, /* PIN: C21 */
1433 FN_LCD3_1_0_PORT18, PORT18_FN, /* PIN: B22 */
1434 0, PORT17_FN, /* PIN: W20 */
1435 0, PORT16_FN, /* PIN: W21 */
1436 0, PORT15_FN, /* PIN: Y19 */
1437 0, PORT14_FN, /* PIN: Y20 */
1438 0, PORT13_FN, /* PIN: Y21 */
1439 0, PORT12_FN, /* PIN: AA20 */
1440 0, PORT11_FN, /* PIN: AA21 */
1441 0, PORT10_FN, /* PIN: AA22 */
1442 0, PORT9_FN, /* PIN: V15 */
1443 0, PORT8_FN, /* PIN: V16 */
1444 0, PORT7_FN, /* PIN: V17 */
1445 0, PORT6_FN, /* PIN: V18 */
1446 FN_EXT_CLKI, PORT5_FN, /* PIN: U8 */
1447 FN_REF_CLKO, PORT4_FN, /* PIN: V8 */
1448 FN_ERR_RST_REQB, PORT3_FN, /* PIN: U9 */
1449 FN_JT_SEL, PORT2_FN, /* PIN: V9 */
1450 0, PORT1_FN, /* PIN: U10 */
1451 0, PORT0_FN, /* PIN: V10 */
1452 }
1453 },
1454 { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {
1455 FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */
1456 FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */
1457 FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */
1458 FN_SDI0_DATA7, PORT60_FN, /* PIN: Y16 */
1459 FN_SDI0_DATA6, PORT59_FN, /* PIN: AA16 */
1460 FN_SDI0_DATA5, PORT58_FN, /* PIN: Y15 */
1461 FN_SDI0_DATA4, PORT57_FN, /* PIN: AA15 */
1462 FN_SDI0_DATA3, PORT56_FN, /* PIN: Y14 */
1463 FN_SDI0_DATA2, PORT55_FN, /* PIN: AA14 */
1464 FN_SDI0_DATA1, PORT54_FN, /* PIN: Y13 */
1465 FN_SDI0_DATA0, PORT53_FN, /* PIN: AA13 */
1466 FN_SDI0_CMD, PORT52_FN, /* PIN: Y12 */
1467 FN_SDI0_CKI, PORT51_FN, /* PIN: AC18 */
1468 FN_SDI0_CKO, PORT50_FN, /* PIN: AB18 */
1469 0, PORT49_FN, /* PIN: AB16 */
1470 FN_SD_CKI, PORT48_FN, /* PIN: AC19 */
1471 FN_IIC_1_0_PORT47, PORT47_FN, /* PIN: Y8 */
1472 FN_IIC_1_0_PORT46, PORT46_FN, /* PIN: Y9 */
1473 FN_IIC0_SDA, PORT45_FN, /* PIN: AA8 */
1474 FN_IIC0_SCL, PORT44_FN, /* PIN: AA9 */
1475 FN_LCD3_11_10_PORT43, PORT43_FN, /* PIN: A15 */
1476 FN_LCD3_11_10_PORT42, PORT42_FN, /* PIN: A16 */
1477 FN_LCD3_11_10_PORT41, PORT41_FN, /* PIN: A17 */
1478 FN_LCD3_11_10_PORT40, PORT40_FN, /* PIN: A18 */
1479 FN_LCD3_9_8_PORT39, PORT39_FN, /* PIN: D18 */
1480 FN_LCD3_9_8_PORT38, PORT38_FN, /* PIN: C18 */
1481 FN_LCD3_R5, PORT37_FN, /* PIN: B18 */
1482 FN_LCD3_R4, PORT36_FN, /* PIN: C19 */
1483 FN_LCD3_R3, PORT35_FN, /* PIN: B19 */
1484 FN_LCD3_R2, PORT34_FN, /* PIN: A19 */
1485 FN_LCD3_R1, PORT33_FN, /* PIN: B20 */
1486 FN_LCD3_R0, PORT32_FN, /* PIN: A20 */
1487 }
1488 },
1489 { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {
1490 FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */
1491 FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */
1492 FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */
1493 FN_AB_7_6_PORT92, PORT92_FN, /* PIN: J22 */
1494 FN_AB_7_6_PORT91, PORT91_FN, /* PIN: H21 */
1495 FN_AB_5_4_PORT90, PORT90_FN, /* PIN: H22 */
1496 FN_AB_5_4_PORT89, PORT89_FN, /* PIN: H23 */
1497 FN_AB_3_2_PORT88, PORT88_FN, /* PIN: G21 */
1498 FN_AB_3_2_PORT87, PORT87_FN, /* PIN: G22 */
1499 FN_AB_3_2_PORT86, PORT86_FN, /* PIN: G23 */
1500 FN_AB_3_2_PORT85, PORT85_FN, /* PIN: F21 */
1501 FN_AB_1_0_PORT84, PORT84_FN, /* PIN: F22 */
1502 FN_AB_1_0_PORT83, PORT83_FN, /* PIN: F23 */
1503 FN_AB_1_0_PORT82, PORT82_FN, /* PIN: E22 */
1504 FN_AB_1_0_PORT81, PORT81_FN, /* PIN: E23 */
1505 FN_AB_1_0_PORT80, PORT80_FN, /* PIN: D22 */
1506 FN_AB_1_0_PORT79, PORT79_FN, /* PIN: D23 */
1507 FN_AB_1_0_PORT78, PORT78_FN, /* PIN: C22 */
1508 FN_AB_1_0_PORT77, PORT77_FN, /* PIN: C23 */
1509 FN_AB_1_0_PORT76, PORT76_FN, /* PIN: K20 */
1510 FN_AB_1_0_PORT75, PORT75_FN, /* PIN: L20 */
1511 FN_AB_1_0_PORT74, PORT74_FN, /* PIN: H20 */
1512 FN_AB_1_0_PORT73, PORT73_FN, /* PIN: J20 */
1513 FN_AB_1_0_PORT72, PORT72_FN, /* PIN: G20 */
1514 FN_AB_1_0_PORT71, PORT71_FN, /* PIN: F20 */
1515 FN_AB_CSB1, PORT70_FN, /* PIN: E21 */
1516 FN_AB_CSB0, PORT69_FN, /* PIN: D21 */
1517 FN_AB_CLK, PORT68_FN, /* PIN: J23 */
1518 FN_SDI1_DATA3, PORT67_FN, /* PIN: AA19 */
1519 FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */
1520 FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */
1521 FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */
1522 }
1523 },
1524 { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {
1525 FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */
1526 FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */
1527 FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */
1528 FN_NTSC_DATA1, PORT124_FN, /* PIN: P18 */
1529 FN_NTSC_DATA0, PORT123_FN, /* PIN: P20 */
1530 FN_NTSC_CLK, PORT122_FN, /* PIN: V20 */
1531 FN_USI_9_8_PORT121, PORT121_FN, /* PIN: Y5 */
1532 FN_USI_9_8_PORT120, PORT120_FN, /* PIN: AA4 */
1533 FN_USI_7_6_PORT119, PORT119_FN, /* PIN: AB3 */
1534 FN_USI_5_4_PORT118, PORT118_FN, /* PIN: AB4 */
1535 FN_USI_5_4_PORT117, PORT117_FN, /* PIN: AC3 */
1536 FN_USI_5_4_PORT116, PORT116_FN, /* PIN: AC4 */
1537 FN_USI_5_4_PORT115, PORT115_FN, /* PIN: AC5 */
1538 FN_USI_3_2_PORT114, PORT114_FN, /* PIN: Y6 */
1539 FN_USI_3_2_PORT113, PORT113_FN, /* PIN: AA7 */
1540 FN_USI_1_0_PORT112, PORT112_FN, /* PIN: Y7 */
1541 FN_USI_1_0_PORT111, PORT111_FN, /* PIN: AA5 */
1542 FN_USI_1_0_PORT110, PORT110_FN, /* PIN: AA6 */
1543 FN_USI_1_0_PORT109, PORT109_FN, /* PIN: AB5 */
1544 FN_USI1_DO, PORT108_FN, /* PIN: D10 */
1545 FN_USI1_DI, PORT107_FN, /* PIN: C10 */
1546 FN_USI0_CS2, PORT106_FN, /* PIN: B9 */
1547 FN_USI0_CS1, PORT105_FN, /* PIN: B8 */
1548 FN_AB_13_12_PORT104, PORT104_FN, /* PIN: M17 */
1549 FN_AB_13_12_PORT103, PORT103_FN, /* PIN: L17 */
1550 FN_AB_11_10_PORT102, PORT102_FN, /* PIN: N18 */
1551 FN_AB_11_10_PORT101, PORT101_FN, /* PIN: M18 */
1552 FN_AB_11_10_PORT100, PORT100_FN, /* PIN: L18 */
1553 FN_AB_9_8_PORT99, PORT99_FN, /* PIN: N20 */
1554 FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */
1555 FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */
1556 FN_AB_A20, PORT96_FN, /* PIN: M21 */
1557 }
1558 },
1559 { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {
1560 0, 0,
1561 FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */
1562 FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */
1563 FN_UART1_TX, PORT156_FN, /* PIN: Y10 */
1564 FN_UART1_RX, PORT155_FN, /* PIN: Y11 */
1565 FN_LOWPWR, PORT154_FN, /* PIN: A12 */
1566 FN_USB_VBUS, PORT153_FN, /* PIN: AA12 */
1567 FN_JT_TDOEN, PORT152_FN, /* PIN: F13 */
1568 FN_JT_TDO, PORT151_FN, /* PIN: D13 */
1569 FN_HSI_1_0_PORT150, PORT150_FN, /* PIN: M22 */
1570 FN_HSI_1_0_PORT149, PORT149_FN, /* PIN: M23 */
1571 FN_HSI_1_0_PORT148, PORT148_FN, /* PIN: N23 */
1572 FN_HSI_1_0_PORT147, PORT147_FN, /* PIN: N22 */
1573 FN_HSI_1_0_PORT146, PORT146_FN, /* PIN: L22 */
1574 FN_HSI_1_0_PORT145, PORT145_FN, /* PIN: L23 */
1575 FN_HSI_1_0_PORT144, PORT144_FN, /* PIN: K23 */
1576 FN_HSI_1_0_PORT143, PORT143_FN, /* PIN: K22 */
1577 FN_CAM_YUV7, PORT142_FN, /* PIN: V23 */
1578 FN_CAM_YUV6, PORT141_FN, /* PIN: V22 */
1579 FN_CAM_YUV5, PORT140_FN, /* PIN: U23 */
1580 FN_CAM_YUV4, PORT139_FN, /* PIN: U22 */
1581 FN_CAM_YUV3, PORT138_FN, /* PIN: U21 */
1582 FN_CAM_YUV2, PORT137_FN, /* PIN: T23 */
1583 FN_CAM_YUV1, PORT136_FN, /* PIN: T22 */
1584 FN_CAM_YUV0, PORT135_FN, /* PIN: T21 */
1585 FN_CAM_HS, PORT134_FN, /* PIN: V21 */
1586 FN_CAM_VS, PORT133_FN, /* PIN: W22 */
1587 FN_CAM_CLKI, PORT132_FN, /* PIN: Y23 */
1588 FN_CAM_CLKO, PORT131_FN, /* PIN: W23 */
1589 FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */
1590 FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */
1591 FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */
1592 }
1593 },
1594 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1596 1, 1, 1, 1, 2, 2, 2, 2, 2, 2) {
1597 /* 31 - 12 */
1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1600 0, 0, 0, 0, 0, 0, 0, 0,
1601 /* 11 - 10 */
1602 FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
1603 FN_SEL_LCD3_11_10_10, 0,
1604 /* 9 - 8 */
1605 FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
1606 /* 7 - 2 */
1607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1608 /* 1 - 0 */
1609 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
1610 }
1611 },
1612 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1613 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1614 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
1615 /* 31 - 2 */
1616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1619 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1620 /* 1 - 0 */
1621 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
1622 }
1623 },
1624 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1625 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
1627 /* 31 - 2 */
1628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1632 /* 1 - 0 */
1633 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
1634 }
1635 },
1636 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1638 2, 2, 2, 2, 2, 2, 2, 2) {
1639 /* 31 - 14 */
1640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1642 0, 0, 0, 0,
1643 /* 13 - 12 */
1644 FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
1645 /* 11 - 10 */
1646 FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
1647 /* 9 - 8 */
1648 FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
1649 /* 7 - 6 */
1650 FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
1651 /* 5 - 4 */
1652 FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
1653 FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
1654 /* 3 - 2 */
1655 FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
1656 FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
1657 /* 1 - 0 */
1658 FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
1659 }
1660 },
1661 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1662 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1663 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) {
1664 /* 31 - 10 */
1665 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1667 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1668 /* 9 - 8 */
1669 FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
1670 /* 7 - 6 */
1671 FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
1672 /* 5 - 4 */
1673 FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
1674 /* 3 - 2 */
1675 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
1676 /* 1 - 0 */
1677 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
1678 }
1679 },
1680 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1682 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
1683 /* 31 - 2 */
1684 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1685 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1686 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1688 /* 1 - 0 */
1689 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
1690 }
1691 },
1692 { },
1693};
1694
1695const struct sh_pfc_soc_info emev2_pinmux_info = {
1696 .name = "emev2_pfc",
1697
1698 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1699
1700 .pins = pinmux_pins,
1701 .nr_pins = ARRAY_SIZE(pinmux_pins),
1702 .groups = pinmux_groups,
1703 .nr_groups = ARRAY_SIZE(pinmux_groups),
1704 .functions = pinmux_functions,
1705 .nr_functions = ARRAY_SIZE(pinmux_functions),
1706
1707 .cfg_regs = pinmux_config_regs,
1708
1709 .gpio_data = pinmux_data,
1710 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1711};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 05:27:09 -0500