diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2012-12-15 17:51:29 -0500 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2013-01-24 19:24:26 -0500 |
commit | ccda552eb168590fb35ef840b295014e11721ad5 (patch) | |
tree | 901f8f4f9909ca653f7d104b77e48fceab9c5d5a /drivers/pinctrl | |
parent | 5d5166dc39bcbe2c21d4fca034540133c415dce6 (diff) |
sh-pfc: Add sh7203 pinmux support
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/sh-pfc/Kconfig | 6 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/Makefile | 1 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/core.c | 3 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/core.h | 1 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-sh7203.c | 1591 |
5 files changed, 1602 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 3bde8d7c8f74..c8ce5321e0ff 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig | |||
@@ -31,6 +31,12 @@ config PINCTRL_PFC_R8A7779 | |||
31 | depends on ARCH_R8A7779 | 31 | depends on ARCH_R8A7779 |
32 | select PINCTRL_SH_PFC | 32 | select PINCTRL_SH_PFC |
33 | 33 | ||
34 | config PINCTRL_PFC_SH7203 | ||
35 | def_bool y | ||
36 | depends on CPU_SUBTYPE_SH7203 | ||
37 | depends on GENERIC_GPIO | ||
38 | select PINCTRL_SH_PFC | ||
39 | |||
34 | config PINCTRL_PFC_SH7372 | 40 | config PINCTRL_PFC_SH7372 |
35 | def_bool y | 41 | def_bool y |
36 | depends on ARCH_SH7372 | 42 | depends on ARCH_SH7372 |
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index b404190ce57e..cdd4e73d219b 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile | |||
@@ -5,5 +5,6 @@ endif | |||
5 | obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o | 5 | obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o |
6 | obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o | 6 | obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o |
7 | obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o | 7 | obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o |
8 | obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o | ||
8 | obj-$(CONFIG_PINCTRL_PFC_SH7372) += pfc-sh7372.o | 9 | obj-$(CONFIG_PINCTRL_PFC_SH7372) += pfc-sh7372.o |
9 | obj-$(CONFIG_PINCTRL_PFC_SH73A0) += pfc-sh73a0.o | 10 | obj-$(CONFIG_PINCTRL_PFC_SH73A0) += pfc-sh73a0.o |
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 015c81620af7..5b1426ad4844 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c | |||
@@ -562,6 +562,9 @@ static const struct platform_device_id sh_pfc_id_table[] = { | |||
562 | #ifdef CONFIG_PINCTRL_PFC_R8A7779 | 562 | #ifdef CONFIG_PINCTRL_PFC_R8A7779 |
563 | { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, | 563 | { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, |
564 | #endif | 564 | #endif |
565 | #ifdef CONFIG_PINCTRL_PFC_SH7203 | ||
566 | { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, | ||
567 | #endif | ||
565 | #ifdef CONFIG_PINCTRL_PFC_SH7372 | 568 | #ifdef CONFIG_PINCTRL_PFC_SH7372 |
566 | { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info }, | 569 | { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info }, |
567 | #endif | 570 | #endif |
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 3699266e3445..0723aed8052e 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h | |||
@@ -53,6 +53,7 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, | |||
53 | 53 | ||
54 | extern struct sh_pfc_soc_info r8a7740_pinmux_info; | 54 | extern struct sh_pfc_soc_info r8a7740_pinmux_info; |
55 | extern struct sh_pfc_soc_info r8a7779_pinmux_info; | 55 | extern struct sh_pfc_soc_info r8a7779_pinmux_info; |
56 | extern struct sh_pfc_soc_info sh7203_pinmux_info; | ||
56 | extern struct sh_pfc_soc_info sh7372_pinmux_info; | 57 | extern struct sh_pfc_soc_info sh7372_pinmux_info; |
57 | extern struct sh_pfc_soc_info sh73a0_pinmux_info; | 58 | extern struct sh_pfc_soc_info sh73a0_pinmux_info; |
58 | 59 | ||
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c new file mode 100644 index 000000000000..62bd17329d29 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c | |||
@@ -0,0 +1,1591 @@ | |||
1 | /* | ||
2 | * SH7203 Pinmux | ||
3 | * | ||
4 | * Copyright (C) 2008 Magnus Damm | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/gpio.h> | ||
13 | #include <linux/sh_pfc.h> | ||
14 | #include <cpu/sh7203.h> | ||
15 | |||
16 | enum { | ||
17 | PINMUX_RESERVED = 0, | ||
18 | |||
19 | PINMUX_DATA_BEGIN, | ||
20 | PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, | ||
21 | PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, | ||
22 | PB12_DATA, | ||
23 | PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, | ||
24 | PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, | ||
25 | PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, | ||
26 | PC14_DATA, PC13_DATA, PC12_DATA, | ||
27 | PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA, | ||
28 | PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, | ||
29 | PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, | ||
30 | PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, | ||
31 | PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, | ||
32 | PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, | ||
33 | PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, | ||
34 | PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA, | ||
35 | PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA, | ||
36 | PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, | ||
37 | PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, | ||
38 | PF30_DATA, PF29_DATA, PF28_DATA, | ||
39 | PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA, | ||
40 | PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, | ||
41 | PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA, | ||
42 | PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, | ||
43 | PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, | ||
44 | PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, | ||
45 | PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, | ||
46 | PINMUX_DATA_END, | ||
47 | |||
48 | PINMUX_INPUT_BEGIN, | ||
49 | FORCE_IN, | ||
50 | PA7_IN, PA6_IN, PA5_IN, PA4_IN, | ||
51 | PA3_IN, PA2_IN, PA1_IN, PA0_IN, | ||
52 | PB11_IN, PB10_IN, PB9_IN, PB8_IN, | ||
53 | PC14_IN, PC13_IN, PC12_IN, | ||
54 | PC11_IN, PC10_IN, PC9_IN, PC8_IN, | ||
55 | PC7_IN, PC6_IN, PC5_IN, PC4_IN, | ||
56 | PC3_IN, PC2_IN, PC1_IN, PC0_IN, | ||
57 | PD15_IN, PD14_IN, PD13_IN, PD12_IN, | ||
58 | PD11_IN, PD10_IN, PD9_IN, PD8_IN, | ||
59 | PD7_IN, PD6_IN, PD5_IN, PD4_IN, | ||
60 | PD3_IN, PD2_IN, PD1_IN, PD0_IN, | ||
61 | PE15_IN, PE14_IN, PE13_IN, PE12_IN, | ||
62 | PE11_IN, PE10_IN, PE9_IN, PE8_IN, | ||
63 | PE7_IN, PE6_IN, PE5_IN, PE4_IN, | ||
64 | PE3_IN, PE2_IN, PE1_IN, PE0_IN, | ||
65 | PF30_IN, PF29_IN, PF28_IN, | ||
66 | PF27_IN, PF26_IN, PF25_IN, PF24_IN, | ||
67 | PF23_IN, PF22_IN, PF21_IN, PF20_IN, | ||
68 | PF19_IN, PF18_IN, PF17_IN, PF16_IN, | ||
69 | PF15_IN, PF14_IN, PF13_IN, PF12_IN, | ||
70 | PF11_IN, PF10_IN, PF9_IN, PF8_IN, | ||
71 | PF7_IN, PF6_IN, PF5_IN, PF4_IN, | ||
72 | PF3_IN, PF2_IN, PF1_IN, PF0_IN, | ||
73 | PINMUX_INPUT_END, | ||
74 | |||
75 | PINMUX_OUTPUT_BEGIN, | ||
76 | FORCE_OUT, | ||
77 | PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT, | ||
78 | PC14_OUT, PC13_OUT, PC12_OUT, | ||
79 | PC11_OUT, PC10_OUT, PC9_OUT, PC8_OUT, | ||
80 | PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, | ||
81 | PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, | ||
82 | PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT, | ||
83 | PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT, | ||
84 | PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, | ||
85 | PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, | ||
86 | PE15_OUT, PE14_OUT, PE13_OUT, PE12_OUT, | ||
87 | PE11_OUT, PE10_OUT, PE9_OUT, PE8_OUT, | ||
88 | PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT, | ||
89 | PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, | ||
90 | PF30_OUT, PF29_OUT, PF28_OUT, | ||
91 | PF27_OUT, PF26_OUT, PF25_OUT, PF24_OUT, | ||
92 | PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT, | ||
93 | PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT, | ||
94 | PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT, | ||
95 | PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT, | ||
96 | PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, | ||
97 | PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, | ||
98 | PINMUX_OUTPUT_END, | ||
99 | |||
100 | PINMUX_FUNCTION_BEGIN, | ||
101 | PB11_IOR_IN, PB11_IOR_OUT, | ||
102 | PB10_IOR_IN, PB10_IOR_OUT, | ||
103 | PB9_IOR_IN, PB9_IOR_OUT, | ||
104 | PB8_IOR_IN, PB8_IOR_OUT, | ||
105 | PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, | ||
106 | PB11MD_0, PB11MD_1, | ||
107 | PB10MD_0, PB10MD_1, | ||
108 | PB9MD_00, PB9MD_01, PB9MD_10, | ||
109 | PB8MD_00, PB8MD_01, PB8MD_10, | ||
110 | PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, | ||
111 | PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, | ||
112 | PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, | ||
113 | PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, | ||
114 | PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, | ||
115 | PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, | ||
116 | PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, | ||
117 | PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11, | ||
118 | |||
119 | PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, | ||
120 | |||
121 | PC14MD_0, PC14MD_1, | ||
122 | PC13MD_0, PC13MD_1, | ||
123 | PC12MD_0, PC12MD_1, | ||
124 | PC11MD_00, PC11MD_01, PC11MD_10, | ||
125 | PC10MD_00, PC10MD_01, PC10MD_10, | ||
126 | PC9MD_0, PC9MD_1, | ||
127 | PC8MD_0, PC8MD_1, | ||
128 | PC7MD_0, PC7MD_1, | ||
129 | PC6MD_0, PC6MD_1, | ||
130 | PC5MD_0, PC5MD_1, | ||
131 | PC4MD_0, PC4MD_1, | ||
132 | PC3MD_0, PC3MD_1, | ||
133 | PC2MD_0, PC2MD_1, | ||
134 | PC1MD_0, PC1MD_1, | ||
135 | PC0MD_00, PC0MD_01, PC0MD_10, | ||
136 | |||
137 | PD15MD_000, PD15MD_001, PD15MD_010, PD15MD_100, PD15MD_101, | ||
138 | PD14MD_000, PD14MD_001, PD14MD_010, PD14MD_101, | ||
139 | PD13MD_000, PD13MD_001, PD13MD_010, PD13MD_100, PD13MD_101, | ||
140 | PD12MD_000, PD12MD_001, PD12MD_010, PD12MD_100, PD12MD_101, | ||
141 | PD11MD_000, PD11MD_001, PD11MD_010, PD11MD_100, PD11MD_101, | ||
142 | PD10MD_000, PD10MD_001, PD10MD_010, PD10MD_100, PD10MD_101, | ||
143 | PD9MD_000, PD9MD_001, PD9MD_010, PD9MD_100, PD9MD_101, | ||
144 | PD8MD_000, PD8MD_001, PD8MD_010, PD8MD_100, PD8MD_101, | ||
145 | PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, PD7MD_100, PD7MD_101, | ||
146 | PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, PD6MD_100, PD6MD_101, | ||
147 | PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, PD5MD_100, PD5MD_101, | ||
148 | PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, PD4MD_100, PD4MD_101, | ||
149 | PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, PD3MD_100, PD3MD_101, | ||
150 | PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, PD2MD_100, PD2MD_101, | ||
151 | PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, PD1MD_100, PD1MD_101, | ||
152 | PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, PD0MD_100, PD0MD_101, | ||
153 | |||
154 | PE15MD_00, PE15MD_01, PE15MD_11, | ||
155 | PE14MD_00, PE14MD_01, PE14MD_11, | ||
156 | PE13MD_00, PE13MD_11, | ||
157 | PE12MD_00, PE12MD_11, | ||
158 | PE11MD_000, PE11MD_001, PE11MD_010, PE11MD_100, | ||
159 | PE10MD_000, PE10MD_001, PE10MD_010, PE10MD_100, | ||
160 | PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11, | ||
161 | PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11, | ||
162 | PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, PE7MD_100, | ||
163 | PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, PE6MD_100, | ||
164 | PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, PE5MD_100, | ||
165 | PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, PE4MD_100, | ||
166 | PE3MD_00, PE3MD_01, PE3MD_11, | ||
167 | PE2MD_00, PE2MD_01, PE2MD_11, | ||
168 | PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11, | ||
169 | PE0MD_000, PE0MD_001, PE0MD_011, PE0MD_100, | ||
170 | |||
171 | PF30MD_0, PF30MD_1, | ||
172 | PF29MD_0, PF29MD_1, | ||
173 | PF28MD_0, PF28MD_1, | ||
174 | PF27MD_0, PF27MD_1, | ||
175 | PF26MD_0, PF26MD_1, | ||
176 | PF25MD_0, PF25MD_1, | ||
177 | PF24MD_0, PF24MD_1, | ||
178 | PF23MD_00, PF23MD_01, PF23MD_10, | ||
179 | PF22MD_00, PF22MD_01, PF22MD_10, | ||
180 | PF21MD_00, PF21MD_01, PF21MD_10, | ||
181 | PF20MD_00, PF20MD_01, PF20MD_10, | ||
182 | PF19MD_00, PF19MD_01, PF19MD_10, | ||
183 | PF18MD_00, PF18MD_01, PF18MD_10, | ||
184 | PF17MD_00, PF17MD_01, PF17MD_10, | ||
185 | PF16MD_00, PF16MD_01, PF16MD_10, | ||
186 | PF15MD_00, PF15MD_01, PF15MD_10, | ||
187 | PF14MD_00, PF14MD_01, PF14MD_10, | ||
188 | PF13MD_00, PF13MD_01, PF13MD_10, | ||
189 | PF12MD_00, PF12MD_01, PF12MD_10, | ||
190 | PF11MD_00, PF11MD_01, PF11MD_10, | ||
191 | PF10MD_00, PF10MD_01, PF10MD_10, | ||
192 | PF9MD_00, PF9MD_01, PF9MD_10, | ||
193 | PF8MD_00, PF8MD_01, PF8MD_10, | ||
194 | PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11, | ||
195 | PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11, | ||
196 | PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11, | ||
197 | PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11, | ||
198 | PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11, | ||
199 | PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11, | ||
200 | PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11, | ||
201 | PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11, | ||
202 | PINMUX_FUNCTION_END, | ||
203 | |||
204 | PINMUX_MARK_BEGIN, | ||
205 | PINT7_PB_MARK, PINT6_PB_MARK, PINT5_PB_MARK, PINT4_PB_MARK, | ||
206 | PINT3_PB_MARK, PINT2_PB_MARK, PINT1_PB_MARK, PINT0_PB_MARK, | ||
207 | PINT7_PD_MARK, PINT6_PD_MARK, PINT5_PD_MARK, PINT4_PD_MARK, | ||
208 | PINT3_PD_MARK, PINT2_PD_MARK, PINT1_PD_MARK, PINT0_PD_MARK, | ||
209 | IRQ7_PB_MARK, IRQ6_PB_MARK, IRQ5_PB_MARK, IRQ4_PB_MARK, | ||
210 | IRQ3_PB_MARK, IRQ2_PB_MARK, IRQ1_PB_MARK, IRQ0_PB_MARK, | ||
211 | IRQ7_PD_MARK, IRQ6_PD_MARK, IRQ5_PD_MARK, IRQ4_PD_MARK, | ||
212 | IRQ3_PD_MARK, IRQ2_PD_MARK, IRQ1_PD_MARK, IRQ0_PD_MARK, | ||
213 | IRQ7_PE_MARK, IRQ6_PE_MARK, IRQ5_PE_MARK, IRQ4_PE_MARK, | ||
214 | IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK, | ||
215 | WDTOVF_MARK, IRQOUT_MARK, REFOUT_MARK, IRQOUT_REFOUT_MARK, | ||
216 | UBCTRG_MARK, | ||
217 | CTX1_MARK, CRX1_MARK, CTX0_MARK, CTX0_CTX1_MARK, | ||
218 | CRX0_MARK, CRX0_CRX1_MARK, | ||
219 | SDA3_MARK, SCL3_MARK, | ||
220 | SDA2_MARK, SCL2_MARK, | ||
221 | SDA1_MARK, SCL1_MARK, | ||
222 | SDA0_MARK, SCL0_MARK, | ||
223 | TEND0_PD_MARK, TEND0_PE_MARK, DACK0_PD_MARK, DACK0_PE_MARK, | ||
224 | DREQ0_PD_MARK, DREQ0_PE_MARK, TEND1_PD_MARK, TEND1_PE_MARK, | ||
225 | DACK1_PD_MARK, DACK1_PE_MARK, DREQ1_PD_MARK, DREQ1_PE_MARK, | ||
226 | DACK2_MARK, DREQ2_MARK, DACK3_MARK, DREQ3_MARK, | ||
227 | ADTRG_PD_MARK, ADTRG_PE_MARK, | ||
228 | D31_MARK, D30_MARK, D29_MARK, D28_MARK, | ||
229 | D27_MARK, D26_MARK, D25_MARK, D24_MARK, | ||
230 | D23_MARK, D22_MARK, D21_MARK, D20_MARK, | ||
231 | D19_MARK, D18_MARK, D17_MARK, D16_MARK, | ||
232 | A25_MARK, A24_MARK, A23_MARK, A22_MARK, | ||
233 | A21_MARK, CS4_MARK, MRES_MARK, BS_MARK, | ||
234 | IOIS16_MARK, CS1_MARK, CS6_CE1B_MARK, CE2B_MARK, | ||
235 | CS5_CE1A_MARK, CE2A_MARK, FRAME_MARK, WAIT_MARK, | ||
236 | RDWR_MARK, CKE_MARK, CASU_MARK, BREQ_MARK, | ||
237 | RASU_MARK, BACK_MARK, CASL_MARK, RASL_MARK, | ||
238 | WE3_DQMUU_AH_ICIO_WR_MARK, WE2_DQMUL_ICIORD_MARK, | ||
239 | WE1_DQMLU_WE_MARK, WE0_DQMLL_MARK, | ||
240 | CS3_MARK, CS2_MARK, A1_MARK, A0_MARK, CS7_MARK, | ||
241 | TIOC4D_MARK, TIOC4C_MARK, TIOC4B_MARK, TIOC4A_MARK, | ||
242 | TIOC3D_MARK, TIOC3C_MARK, TIOC3B_MARK, TIOC3A_MARK, | ||
243 | TIOC2B_MARK, TIOC1B_MARK, TIOC2A_MARK, TIOC1A_MARK, | ||
244 | TIOC0D_MARK, TIOC0C_MARK, TIOC0B_MARK, TIOC0A_MARK, | ||
245 | TCLKD_PD_MARK, TCLKC_PD_MARK, TCLKB_PD_MARK, TCLKA_PD_MARK, | ||
246 | TCLKD_PF_MARK, TCLKC_PF_MARK, TCLKB_PF_MARK, TCLKA_PF_MARK, | ||
247 | SCS0_PD_MARK, SSO0_PD_MARK, SSI0_PD_MARK, SSCK0_PD_MARK, | ||
248 | SCS0_PF_MARK, SSO0_PF_MARK, SSI0_PF_MARK, SSCK0_PF_MARK, | ||
249 | SCS1_PD_MARK, SSO1_PD_MARK, SSI1_PD_MARK, SSCK1_PD_MARK, | ||
250 | SCS1_PF_MARK, SSO1_PF_MARK, SSI1_PF_MARK, SSCK1_PF_MARK, | ||
251 | TXD0_MARK, RXD0_MARK, SCK0_MARK, | ||
252 | TXD1_MARK, RXD1_MARK, SCK1_MARK, | ||
253 | TXD2_MARK, RXD2_MARK, SCK2_MARK, | ||
254 | RTS3_MARK, CTS3_MARK, TXD3_MARK, | ||
255 | RXD3_MARK, SCK3_MARK, | ||
256 | AUDIO_CLK_MARK, | ||
257 | SSIDATA3_MARK, SSIWS3_MARK, SSISCK3_MARK, | ||
258 | SSIDATA2_MARK, SSIWS2_MARK, SSISCK2_MARK, | ||
259 | SSIDATA1_MARK, SSIWS1_MARK, SSISCK1_MARK, | ||
260 | SSIDATA0_MARK, SSIWS0_MARK, SSISCK0_MARK, | ||
261 | FCE_MARK, FRB_MARK, | ||
262 | NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, | ||
263 | NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, | ||
264 | FSC_MARK, FOE_MARK, FCDE_MARK, FWE_MARK, | ||
265 | LCD_VEPWC_MARK, LCD_VCPWC_MARK, LCD_CLK_MARK, LCD_FLM_MARK, | ||
266 | LCD_M_DISP_MARK, LCD_CL2_MARK, LCD_CL1_MARK, LCD_DON_MARK, | ||
267 | LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK, | ||
268 | LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK, | ||
269 | LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK, | ||
270 | LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK, | ||
271 | PINMUX_MARK_END, | ||
272 | }; | ||
273 | |||
274 | static pinmux_enum_t pinmux_data[] = { | ||
275 | |||
276 | /* PA */ | ||
277 | PINMUX_DATA(PA7_DATA, PA7_IN), | ||
278 | PINMUX_DATA(PA6_DATA, PA6_IN), | ||
279 | PINMUX_DATA(PA5_DATA, PA5_IN), | ||
280 | PINMUX_DATA(PA4_DATA, PA4_IN), | ||
281 | PINMUX_DATA(PA3_DATA, PA3_IN), | ||
282 | PINMUX_DATA(PA2_DATA, PA2_IN), | ||
283 | PINMUX_DATA(PA1_DATA, PA1_IN), | ||
284 | PINMUX_DATA(PA0_DATA, PA0_IN), | ||
285 | |||
286 | /* PB */ | ||
287 | PINMUX_DATA(PB12_DATA, PB12MD_00, FORCE_OUT), | ||
288 | PINMUX_DATA(WDTOVF_MARK, PB12MD_01), | ||
289 | PINMUX_DATA(IRQOUT_MARK, PB12MD_10, PB12IRQ_00), | ||
290 | PINMUX_DATA(REFOUT_MARK, PB12MD_10, PB12IRQ_01), | ||
291 | PINMUX_DATA(IRQOUT_REFOUT_MARK, PB12MD_10, PB12IRQ_10), | ||
292 | PINMUX_DATA(UBCTRG_MARK, PB12MD_11), | ||
293 | |||
294 | PINMUX_DATA(PB11_DATA, PB11MD_0, PB11_IN, PB11_OUT), | ||
295 | PINMUX_DATA(CTX1_MARK, PB11MD_1), | ||
296 | |||
297 | PINMUX_DATA(PB10_DATA, PB10MD_0, PB10_IN, PB10_OUT), | ||
298 | PINMUX_DATA(CRX1_MARK, PB10MD_1), | ||
299 | |||
300 | PINMUX_DATA(PB9_DATA, PB9MD_00, PB9_IN, PB9_OUT), | ||
301 | PINMUX_DATA(CTX0_MARK, PB9MD_01), | ||
302 | PINMUX_DATA(CTX0_CTX1_MARK, PB9MD_10), | ||
303 | |||
304 | PINMUX_DATA(PB8_DATA, PB8MD_00, PB8_IN, PB8_OUT), | ||
305 | PINMUX_DATA(CRX0_MARK, PB8MD_01), | ||
306 | PINMUX_DATA(CRX0_CRX1_MARK, PB8MD_10), | ||
307 | |||
308 | PINMUX_DATA(PB7_DATA, PB7MD_00, FORCE_IN), | ||
309 | PINMUX_DATA(SDA3_MARK, PB7MD_01), | ||
310 | PINMUX_DATA(PINT7_PB_MARK, PB7MD_10), | ||
311 | PINMUX_DATA(IRQ7_PB_MARK, PB7MD_11), | ||
312 | |||
313 | PINMUX_DATA(PB6_DATA, PB6MD_00, FORCE_IN), | ||
314 | PINMUX_DATA(SCL3_MARK, PB6MD_01), | ||
315 | PINMUX_DATA(PINT6_PB_MARK, PB6MD_10), | ||
316 | PINMUX_DATA(IRQ6_PB_MARK, PB6MD_11), | ||
317 | |||
318 | PINMUX_DATA(PB5_DATA, PB5MD_00, FORCE_IN), | ||
319 | PINMUX_DATA(SDA2_MARK, PB6MD_01), | ||
320 | PINMUX_DATA(PINT5_PB_MARK, PB6MD_10), | ||
321 | PINMUX_DATA(IRQ5_PB_MARK, PB6MD_11), | ||
322 | |||
323 | PINMUX_DATA(PB4_DATA, PB4MD_00, FORCE_IN), | ||
324 | PINMUX_DATA(SCL2_MARK, PB4MD_01), | ||
325 | PINMUX_DATA(PINT4_PB_MARK, PB4MD_10), | ||
326 | PINMUX_DATA(IRQ4_PB_MARK, PB4MD_11), | ||
327 | |||
328 | PINMUX_DATA(PB3_DATA, PB3MD_00, FORCE_IN), | ||
329 | PINMUX_DATA(SDA1_MARK, PB3MD_01), | ||
330 | PINMUX_DATA(PINT3_PB_MARK, PB3MD_10), | ||
331 | PINMUX_DATA(IRQ3_PB_MARK, PB3MD_11), | ||
332 | |||
333 | PINMUX_DATA(PB2_DATA, PB2MD_00, FORCE_IN), | ||
334 | PINMUX_DATA(SCL1_MARK, PB2MD_01), | ||
335 | PINMUX_DATA(PINT2_PB_MARK, PB2MD_10), | ||
336 | PINMUX_DATA(IRQ2_PB_MARK, PB2MD_11), | ||
337 | |||
338 | PINMUX_DATA(PB1_DATA, PB1MD_00, FORCE_IN), | ||
339 | PINMUX_DATA(SDA0_MARK, PB1MD_01), | ||
340 | PINMUX_DATA(PINT1_PB_MARK, PB1MD_10), | ||
341 | PINMUX_DATA(IRQ1_PB_MARK, PB1MD_11), | ||
342 | |||
343 | PINMUX_DATA(PB0_DATA, PB0MD_00, FORCE_IN), | ||
344 | PINMUX_DATA(SCL0_MARK, PB0MD_01), | ||
345 | PINMUX_DATA(PINT0_PB_MARK, PB0MD_10), | ||
346 | PINMUX_DATA(IRQ0_PB_MARK, PB0MD_11), | ||
347 | |||
348 | /* PC */ | ||
349 | PINMUX_DATA(PC14_DATA, PC14MD_0, PC14_IN, PC14_OUT), | ||
350 | PINMUX_DATA(WAIT_MARK, PC14MD_1), | ||
351 | |||
352 | PINMUX_DATA(PC13_DATA, PC13MD_0, PC13_IN, PC13_OUT), | ||
353 | PINMUX_DATA(RDWR_MARK, PC13MD_1), | ||
354 | |||
355 | PINMUX_DATA(PC12_DATA, PC12MD_0, PC12_IN, PC12_OUT), | ||
356 | PINMUX_DATA(CKE_MARK, PC12MD_1), | ||
357 | |||
358 | PINMUX_DATA(PC11_DATA, PC11MD_00, PC11_IN, PC11_OUT), | ||
359 | PINMUX_DATA(CASU_MARK, PC11MD_01), | ||
360 | PINMUX_DATA(BREQ_MARK, PC11MD_10), | ||
361 | |||
362 | PINMUX_DATA(PC10_DATA, PC10MD_00, PC10_IN, PC10_OUT), | ||
363 | PINMUX_DATA(RASU_MARK, PC10MD_01), | ||
364 | PINMUX_DATA(BACK_MARK, PC10MD_10), | ||
365 | |||
366 | PINMUX_DATA(PC9_DATA, PC9MD_0, PC9_IN, PC9_OUT), | ||
367 | PINMUX_DATA(CASL_MARK, PC9MD_1), | ||
368 | |||
369 | PINMUX_DATA(PC8_DATA, PC8MD_0, PC8_IN, PC8_OUT), | ||
370 | PINMUX_DATA(RASL_MARK, PC8MD_1), | ||
371 | |||
372 | PINMUX_DATA(PC7_DATA, PC7MD_0, PC7_IN, PC7_OUT), | ||
373 | PINMUX_DATA(WE3_DQMUU_AH_ICIO_WR_MARK, PC7MD_1), | ||
374 | |||
375 | PINMUX_DATA(PC6_DATA, PC6MD_0, PC6_IN, PC6_OUT), | ||
376 | PINMUX_DATA(WE2_DQMUL_ICIORD_MARK, PC6MD_1), | ||
377 | |||
378 | PINMUX_DATA(PC5_DATA, PC5MD_0, PC5_IN, PC5_OUT), | ||
379 | PINMUX_DATA(WE1_DQMLU_WE_MARK, PC5MD_1), | ||
380 | |||
381 | PINMUX_DATA(PC4_DATA, PC4MD_0, PC4_IN, PC4_OUT), | ||
382 | PINMUX_DATA(WE0_DQMLL_MARK, PC4MD_1), | ||
383 | |||
384 | PINMUX_DATA(PC3_DATA, PC3MD_0, PC3_IN, PC3_OUT), | ||
385 | PINMUX_DATA(CS3_MARK, PC3MD_1), | ||
386 | |||
387 | PINMUX_DATA(PC2_DATA, PC2MD_0, PC2_IN, PC2_OUT), | ||
388 | PINMUX_DATA(CS2_MARK, PC2MD_1), | ||
389 | |||
390 | PINMUX_DATA(PC1_DATA, PC1MD_0, PC1_IN, PC1_OUT), | ||
391 | PINMUX_DATA(A1_MARK, PC1MD_1), | ||
392 | |||
393 | PINMUX_DATA(PC0_DATA, PC0MD_00, PC0_IN, PC0_OUT), | ||
394 | PINMUX_DATA(A0_MARK, PC0MD_01), | ||
395 | PINMUX_DATA(CS7_MARK, PC0MD_10), | ||
396 | |||
397 | /* PD */ | ||
398 | PINMUX_DATA(PD15_DATA, PD15MD_000, PD15_IN, PD15_OUT), | ||
399 | PINMUX_DATA(D31_MARK, PD15MD_001), | ||
400 | PINMUX_DATA(PINT7_PD_MARK, PD15MD_010), | ||
401 | PINMUX_DATA(ADTRG_PD_MARK, PD15MD_100), | ||
402 | PINMUX_DATA(TIOC4D_MARK, PD15MD_101), | ||
403 | |||
404 | PINMUX_DATA(PD14_DATA, PD14MD_000, PD14_IN, PD14_OUT), | ||
405 | PINMUX_DATA(D30_MARK, PD14MD_001), | ||
406 | PINMUX_DATA(PINT6_PD_MARK, PD14MD_010), | ||
407 | PINMUX_DATA(TIOC4C_MARK, PD14MD_101), | ||
408 | |||
409 | PINMUX_DATA(PD13_DATA, PD13MD_000, PD13_IN, PD13_OUT), | ||
410 | PINMUX_DATA(D29_MARK, PD13MD_001), | ||
411 | PINMUX_DATA(PINT5_PD_MARK, PD13MD_010), | ||
412 | PINMUX_DATA(TEND1_PD_MARK, PD13MD_100), | ||
413 | PINMUX_DATA(TIOC4B_MARK, PD13MD_101), | ||
414 | |||
415 | PINMUX_DATA(PD12_DATA, PD12MD_000, PD12_IN, PD12_OUT), | ||
416 | PINMUX_DATA(D28_MARK, PD12MD_001), | ||
417 | PINMUX_DATA(PINT4_PD_MARK, PD12MD_010), | ||
418 | PINMUX_DATA(DACK1_PD_MARK, PD12MD_100), | ||
419 | PINMUX_DATA(TIOC4A_MARK, PD12MD_101), | ||
420 | |||
421 | PINMUX_DATA(PD11_DATA, PD11MD_000, PD11_IN, PD11_OUT), | ||
422 | PINMUX_DATA(D27_MARK, PD11MD_001), | ||
423 | PINMUX_DATA(PINT3_PD_MARK, PD11MD_010), | ||
424 | PINMUX_DATA(DREQ1_PD_MARK, PD11MD_100), | ||
425 | PINMUX_DATA(TIOC3D_MARK, PD11MD_101), | ||
426 | |||
427 | PINMUX_DATA(PD10_DATA, PD10MD_000, PD10_IN, PD10_OUT), | ||
428 | PINMUX_DATA(D26_MARK, PD10MD_001), | ||
429 | PINMUX_DATA(PINT2_PD_MARK, PD10MD_010), | ||
430 | PINMUX_DATA(TEND0_PD_MARK, PD10MD_100), | ||
431 | PINMUX_DATA(TIOC3C_MARK, PD10MD_101), | ||
432 | |||
433 | PINMUX_DATA(PD9_DATA, PD9MD_000, PD9_IN, PD9_OUT), | ||
434 | PINMUX_DATA(D25_MARK, PD9MD_001), | ||
435 | PINMUX_DATA(PINT1_PD_MARK, PD9MD_010), | ||
436 | PINMUX_DATA(DACK0_PD_MARK, PD9MD_100), | ||
437 | PINMUX_DATA(TIOC3B_MARK, PD9MD_101), | ||
438 | |||
439 | PINMUX_DATA(PD8_DATA, PD8MD_000, PD8_IN, PD8_OUT), | ||
440 | PINMUX_DATA(D24_MARK, PD8MD_001), | ||
441 | PINMUX_DATA(PINT0_PD_MARK, PD8MD_010), | ||
442 | PINMUX_DATA(DREQ0_PD_MARK, PD8MD_100), | ||
443 | PINMUX_DATA(TIOC3A_MARK, PD8MD_101), | ||
444 | |||
445 | PINMUX_DATA(PD7_DATA, PD7MD_000, PD7_IN, PD7_OUT), | ||
446 | PINMUX_DATA(D23_MARK, PD7MD_001), | ||
447 | PINMUX_DATA(IRQ7_PD_MARK, PD7MD_010), | ||
448 | PINMUX_DATA(SCS1_PD_MARK, PD7MD_011), | ||
449 | PINMUX_DATA(TCLKD_PD_MARK, PD7MD_100), | ||
450 | PINMUX_DATA(TIOC2B_MARK, PD7MD_101), | ||
451 | |||
452 | PINMUX_DATA(PD6_DATA, PD6MD_000, PD6_IN, PD6_OUT), | ||
453 | PINMUX_DATA(D22_MARK, PD6MD_001), | ||
454 | PINMUX_DATA(IRQ6_PD_MARK, PD6MD_010), | ||
455 | PINMUX_DATA(SSO1_PD_MARK, PD6MD_011), | ||
456 | PINMUX_DATA(TCLKC_PD_MARK, PD6MD_100), | ||
457 | PINMUX_DATA(TIOC2A_MARK, PD6MD_101), | ||
458 | |||
459 | PINMUX_DATA(PD5_DATA, PD5MD_000, PD5_IN, PD5_OUT), | ||
460 | PINMUX_DATA(D21_MARK, PD5MD_001), | ||
461 | PINMUX_DATA(IRQ5_PD_MARK, PD5MD_010), | ||
462 | PINMUX_DATA(SSI1_PD_MARK, PD5MD_011), | ||
463 | PINMUX_DATA(TCLKB_PD_MARK, PD5MD_100), | ||
464 | PINMUX_DATA(TIOC1B_MARK, PD5MD_101), | ||
465 | |||
466 | PINMUX_DATA(PD4_DATA, PD4MD_000, PD4_IN, PD4_OUT), | ||
467 | PINMUX_DATA(D20_MARK, PD4MD_001), | ||
468 | PINMUX_DATA(IRQ4_PD_MARK, PD4MD_010), | ||
469 | PINMUX_DATA(SSCK1_PD_MARK, PD4MD_011), | ||
470 | PINMUX_DATA(TCLKA_PD_MARK, PD4MD_100), | ||
471 | PINMUX_DATA(TIOC1A_MARK, PD4MD_101), | ||
472 | |||
473 | PINMUX_DATA(PD3_DATA, PD3MD_000, PD3_IN, PD3_OUT), | ||
474 | PINMUX_DATA(D19_MARK, PD3MD_001), | ||
475 | PINMUX_DATA(IRQ3_PD_MARK, PD3MD_010), | ||
476 | PINMUX_DATA(SCS0_PD_MARK, PD3MD_011), | ||
477 | PINMUX_DATA(DACK3_MARK, PD3MD_100), | ||
478 | PINMUX_DATA(TIOC0D_MARK, PD3MD_101), | ||
479 | |||
480 | PINMUX_DATA(PD2_DATA, PD2MD_000, PD2_IN, PD2_OUT), | ||
481 | PINMUX_DATA(D18_MARK, PD2MD_001), | ||
482 | PINMUX_DATA(IRQ2_PD_MARK, PD2MD_010), | ||
483 | PINMUX_DATA(SSO0_PD_MARK, PD2MD_011), | ||
484 | PINMUX_DATA(DREQ3_MARK, PD2MD_100), | ||
485 | PINMUX_DATA(TIOC0C_MARK, PD2MD_101), | ||
486 | |||
487 | PINMUX_DATA(PD1_DATA, PD1MD_000, PD1_IN, PD1_OUT), | ||
488 | PINMUX_DATA(D17_MARK, PD1MD_001), | ||
489 | PINMUX_DATA(IRQ1_PD_MARK, PD1MD_010), | ||
490 | PINMUX_DATA(SSI0_PD_MARK, PD1MD_011), | ||
491 | PINMUX_DATA(DACK2_MARK, PD1MD_100), | ||
492 | PINMUX_DATA(TIOC0B_MARK, PD1MD_101), | ||
493 | |||
494 | PINMUX_DATA(PD0_DATA, PD0MD_000, PD0_IN, PD0_OUT), | ||
495 | PINMUX_DATA(D16_MARK, PD0MD_001), | ||
496 | PINMUX_DATA(IRQ0_PD_MARK, PD0MD_010), | ||
497 | PINMUX_DATA(SSCK0_PD_MARK, PD0MD_011), | ||
498 | PINMUX_DATA(DREQ2_MARK, PD0MD_100), | ||
499 | PINMUX_DATA(TIOC0A_MARK, PD0MD_101), | ||
500 | |||
501 | /* PE */ | ||
502 | PINMUX_DATA(PE15_DATA, PE15MD_00, PE15_IN, PE15_OUT), | ||
503 | PINMUX_DATA(IOIS16_MARK, PE15MD_01), | ||
504 | PINMUX_DATA(RTS3_MARK, PE15MD_11), | ||
505 | |||
506 | PINMUX_DATA(PE14_DATA, PE14MD_00, PE14_IN, PE14_OUT), | ||
507 | PINMUX_DATA(CS1_MARK, PE14MD_01), | ||
508 | PINMUX_DATA(CTS3_MARK, PE14MD_11), | ||
509 | |||
510 | PINMUX_DATA(PE13_DATA, PE13MD_00, PE13_IN, PE13_OUT), | ||
511 | PINMUX_DATA(TXD3_MARK, PE13MD_11), | ||
512 | |||
513 | PINMUX_DATA(PE12_DATA, PE12MD_00, PE12_IN, PE12_OUT), | ||
514 | PINMUX_DATA(RXD3_MARK, PE12MD_11), | ||
515 | |||
516 | PINMUX_DATA(PE11_DATA, PE11MD_000, PE11_IN, PE11_OUT), | ||
517 | PINMUX_DATA(CS6_CE1B_MARK, PE11MD_001), | ||
518 | PINMUX_DATA(IRQ7_PE_MARK, PE11MD_010), | ||
519 | PINMUX_DATA(TEND1_PE_MARK, PE11MD_100), | ||
520 | |||
521 | PINMUX_DATA(PE10_DATA, PE10MD_000, PE10_IN, PE10_OUT), | ||
522 | PINMUX_DATA(CE2B_MARK, PE10MD_001), | ||
523 | PINMUX_DATA(IRQ6_PE_MARK, PE10MD_010), | ||
524 | PINMUX_DATA(TEND0_PE_MARK, PE10MD_100), | ||
525 | |||
526 | PINMUX_DATA(PE9_DATA, PE9MD_00, PE9_IN, PE9_OUT), | ||
527 | PINMUX_DATA(CS5_CE1A_MARK, PE9MD_01), | ||
528 | PINMUX_DATA(IRQ5_PE_MARK, PE9MD_10), | ||
529 | PINMUX_DATA(SCK3_MARK, PE9MD_11), | ||
530 | |||
531 | PINMUX_DATA(PE8_DATA, PE8MD_00, PE8_IN, PE8_OUT), | ||
532 | PINMUX_DATA(CE2A_MARK, PE8MD_01), | ||
533 | PINMUX_DATA(IRQ4_PE_MARK, PE8MD_10), | ||
534 | PINMUX_DATA(SCK2_MARK, PE8MD_11), | ||
535 | |||
536 | PINMUX_DATA(PE7_DATA, PE7MD_000, PE7_IN, PE7_OUT), | ||
537 | PINMUX_DATA(FRAME_MARK, PE7MD_001), | ||
538 | PINMUX_DATA(IRQ3_PE_MARK, PE7MD_010), | ||
539 | PINMUX_DATA(TXD2_MARK, PE7MD_011), | ||
540 | PINMUX_DATA(DACK1_PE_MARK, PE7MD_100), | ||
541 | |||
542 | PINMUX_DATA(PE6_DATA, PE6MD_000, PE6_IN, PE6_OUT), | ||
543 | PINMUX_DATA(A25_MARK, PE6MD_001), | ||
544 | PINMUX_DATA(IRQ2_PE_MARK, PE6MD_010), | ||
545 | PINMUX_DATA(RXD2_MARK, PE6MD_011), | ||
546 | PINMUX_DATA(DREQ1_PE_MARK, PE6MD_100), | ||
547 | |||
548 | PINMUX_DATA(PE5_DATA, PE5MD_000, PE5_IN, PE5_OUT), | ||
549 | PINMUX_DATA(A24_MARK, PE5MD_001), | ||
550 | PINMUX_DATA(IRQ1_PE_MARK, PE5MD_010), | ||
551 | PINMUX_DATA(TXD1_MARK, PE5MD_011), | ||
552 | PINMUX_DATA(DACK0_PE_MARK, PE5MD_100), | ||
553 | |||
554 | PINMUX_DATA(PE4_DATA, PE4MD_000, PE4_IN, PE4_OUT), | ||
555 | PINMUX_DATA(A23_MARK, PE4MD_001), | ||
556 | PINMUX_DATA(IRQ0_PE_MARK, PE4MD_010), | ||
557 | PINMUX_DATA(RXD1_MARK, PE4MD_011), | ||
558 | PINMUX_DATA(DREQ0_PE_MARK, PE4MD_100), | ||
559 | |||
560 | PINMUX_DATA(PE3_DATA, PE3MD_00, PE3_IN, PE3_OUT), | ||
561 | PINMUX_DATA(A22_MARK, PE3MD_01), | ||
562 | PINMUX_DATA(SCK1_MARK, PE3MD_11), | ||
563 | |||
564 | PINMUX_DATA(PE2_DATA, PE2MD_00, PE2_IN, PE2_OUT), | ||
565 | PINMUX_DATA(A21_MARK, PE2MD_01), | ||
566 | PINMUX_DATA(SCK0_MARK, PE2MD_11), | ||
567 | |||
568 | PINMUX_DATA(PE1_DATA, PE1MD_00, PE1_IN, PE1_OUT), | ||
569 | PINMUX_DATA(CS4_MARK, PE1MD_01), | ||
570 | PINMUX_DATA(MRES_MARK, PE1MD_10), | ||
571 | PINMUX_DATA(TXD0_MARK, PE1MD_11), | ||
572 | |||
573 | PINMUX_DATA(PE0_DATA, PE0MD_000, PE0_IN, PE0_OUT), | ||
574 | PINMUX_DATA(BS_MARK, PE0MD_001), | ||
575 | PINMUX_DATA(RXD0_MARK, PE0MD_011), | ||
576 | PINMUX_DATA(ADTRG_PE_MARK, PE0MD_100), | ||
577 | |||
578 | /* PF */ | ||
579 | PINMUX_DATA(PF30_DATA, PF30MD_0, PF30_IN, PF30_OUT), | ||
580 | PINMUX_DATA(AUDIO_CLK_MARK, PF30MD_1), | ||
581 | |||
582 | PINMUX_DATA(PF29_DATA, PF29MD_0, PF29_IN, PF29_OUT), | ||
583 | PINMUX_DATA(SSIDATA3_MARK, PF29MD_1), | ||
584 | |||
585 | PINMUX_DATA(PF28_DATA, PF28MD_0, PF28_IN, PF28_OUT), | ||
586 | PINMUX_DATA(SSIWS3_MARK, PF28MD_1), | ||
587 | |||
588 | PINMUX_DATA(PF27_DATA, PF27MD_0, PF27_IN, PF27_OUT), | ||
589 | PINMUX_DATA(SSISCK3_MARK, PF27MD_1), | ||
590 | |||
591 | PINMUX_DATA(PF26_DATA, PF26MD_0, PF26_IN, PF26_OUT), | ||
592 | PINMUX_DATA(SSIDATA2_MARK, PF26MD_1), | ||
593 | |||
594 | PINMUX_DATA(PF25_DATA, PF25MD_0, PF25_IN, PF25_OUT), | ||
595 | PINMUX_DATA(SSIWS2_MARK, PF25MD_1), | ||
596 | |||
597 | PINMUX_DATA(PF24_DATA, PF24MD_0, PF24_IN, PF24_OUT), | ||
598 | PINMUX_DATA(SSISCK2_MARK, PF24MD_1), | ||
599 | |||
600 | PINMUX_DATA(PF23_DATA, PF23MD_00, PF23_IN, PF23_OUT), | ||
601 | PINMUX_DATA(SSIDATA1_MARK, PF23MD_01), | ||
602 | PINMUX_DATA(LCD_VEPWC_MARK, PF23MD_10), | ||
603 | |||
604 | PINMUX_DATA(PF22_DATA, PF22MD_00, PF22_IN, PF22_OUT), | ||
605 | PINMUX_DATA(SSIWS1_MARK, PF22MD_01), | ||
606 | PINMUX_DATA(LCD_VCPWC_MARK, PF22MD_10), | ||
607 | |||
608 | PINMUX_DATA(PF21_DATA, PF21MD_00, PF21_IN, PF21_OUT), | ||
609 | PINMUX_DATA(SSISCK1_MARK, PF21MD_01), | ||
610 | PINMUX_DATA(LCD_CLK_MARK, PF21MD_10), | ||
611 | |||
612 | PINMUX_DATA(PF20_DATA, PF20MD_00, PF20_IN, PF20_OUT), | ||
613 | PINMUX_DATA(SSIDATA0_MARK, PF20MD_01), | ||
614 | PINMUX_DATA(LCD_FLM_MARK, PF20MD_10), | ||
615 | |||
616 | PINMUX_DATA(PF19_DATA, PF19MD_00, PF19_IN, PF19_OUT), | ||
617 | PINMUX_DATA(SSIWS0_MARK, PF19MD_01), | ||
618 | PINMUX_DATA(LCD_M_DISP_MARK, PF19MD_10), | ||
619 | |||
620 | PINMUX_DATA(PF18_DATA, PF18MD_00, PF18_IN, PF18_OUT), | ||
621 | PINMUX_DATA(SSISCK0_MARK, PF18MD_01), | ||
622 | PINMUX_DATA(LCD_CL2_MARK, PF18MD_10), | ||
623 | |||
624 | PINMUX_DATA(PF17_DATA, PF17MD_00, PF17_IN, PF17_OUT), | ||
625 | PINMUX_DATA(FCE_MARK, PF17MD_01), | ||
626 | PINMUX_DATA(LCD_CL1_MARK, PF17MD_10), | ||
627 | |||
628 | PINMUX_DATA(PF16_DATA, PF16MD_00, PF16_IN, PF16_OUT), | ||
629 | PINMUX_DATA(FRB_MARK, PF16MD_01), | ||
630 | PINMUX_DATA(LCD_DON_MARK, PF16MD_10), | ||
631 | |||
632 | PINMUX_DATA(PF15_DATA, PF15MD_00, PF15_IN, PF15_OUT), | ||
633 | PINMUX_DATA(NAF7_MARK, PF15MD_01), | ||
634 | PINMUX_DATA(LCD_DATA15_MARK, PF15MD_10), | ||
635 | |||
636 | PINMUX_DATA(PF14_DATA, PF14MD_00, PF14_IN, PF14_OUT), | ||
637 | PINMUX_DATA(NAF6_MARK, PF14MD_01), | ||
638 | PINMUX_DATA(LCD_DATA14_MARK, PF14MD_10), | ||
639 | |||
640 | PINMUX_DATA(PF13_DATA, PF13MD_00, PF13_IN, PF13_OUT), | ||
641 | PINMUX_DATA(NAF5_MARK, PF13MD_01), | ||
642 | PINMUX_DATA(LCD_DATA13_MARK, PF13MD_10), | ||
643 | |||
644 | PINMUX_DATA(PF12_DATA, PF12MD_00, PF12_IN, PF12_OUT), | ||
645 | PINMUX_DATA(NAF4_MARK, PF12MD_01), | ||
646 | PINMUX_DATA(LCD_DATA12_MARK, PF12MD_10), | ||
647 | |||
648 | PINMUX_DATA(PF11_DATA, PF11MD_00, PF11_IN, PF11_OUT), | ||
649 | PINMUX_DATA(NAF3_MARK, PF11MD_01), | ||
650 | PINMUX_DATA(LCD_DATA11_MARK, PF11MD_10), | ||
651 | |||
652 | PINMUX_DATA(PF10_DATA, PF10MD_00, PF10_IN, PF10_OUT), | ||
653 | PINMUX_DATA(NAF2_MARK, PF10MD_01), | ||
654 | PINMUX_DATA(LCD_DATA10_MARK, PF10MD_10), | ||
655 | |||
656 | PINMUX_DATA(PF9_DATA, PF9MD_00, PF9_IN, PF9_OUT), | ||
657 | PINMUX_DATA(NAF1_MARK, PF9MD_01), | ||
658 | PINMUX_DATA(LCD_DATA9_MARK, PF9MD_10), | ||
659 | |||
660 | PINMUX_DATA(PF8_DATA, PF8MD_00, PF8_IN, PF8_OUT), | ||
661 | PINMUX_DATA(NAF0_MARK, PF8MD_01), | ||
662 | PINMUX_DATA(LCD_DATA8_MARK, PF8MD_10), | ||
663 | |||
664 | PINMUX_DATA(PF7_DATA, PF7MD_00, PF7_IN, PF7_OUT), | ||
665 | PINMUX_DATA(FSC_MARK, PF7MD_01), | ||
666 | PINMUX_DATA(LCD_DATA7_MARK, PF7MD_10), | ||
667 | PINMUX_DATA(SCS1_PF_MARK, PF7MD_11), | ||
668 | |||
669 | PINMUX_DATA(PF6_DATA, PF6MD_00, PF6_IN, PF6_OUT), | ||
670 | PINMUX_DATA(FOE_MARK, PF6MD_01), | ||
671 | PINMUX_DATA(LCD_DATA6_MARK, PF6MD_10), | ||
672 | PINMUX_DATA(SSO1_PF_MARK, PF6MD_11), | ||
673 | |||
674 | PINMUX_DATA(PF5_DATA, PF5MD_00, PF5_IN, PF5_OUT), | ||
675 | PINMUX_DATA(FCDE_MARK, PF5MD_01), | ||
676 | PINMUX_DATA(LCD_DATA5_MARK, PF5MD_10), | ||
677 | PINMUX_DATA(SSI1_PF_MARK, PF5MD_11), | ||
678 | |||
679 | PINMUX_DATA(PF4_DATA, PF4MD_00, PF4_IN, PF4_OUT), | ||
680 | PINMUX_DATA(FWE_MARK, PF4MD_01), | ||
681 | PINMUX_DATA(LCD_DATA4_MARK, PF4MD_10), | ||
682 | PINMUX_DATA(SSCK1_PF_MARK, PF4MD_11), | ||
683 | |||
684 | PINMUX_DATA(PF3_DATA, PF3MD_00, PF3_IN, PF3_OUT), | ||
685 | PINMUX_DATA(TCLKD_PF_MARK, PF3MD_01), | ||
686 | PINMUX_DATA(LCD_DATA3_MARK, PF3MD_10), | ||
687 | PINMUX_DATA(SCS0_PF_MARK, PF3MD_11), | ||
688 | |||
689 | PINMUX_DATA(PF2_DATA, PF2MD_00, PF2_IN, PF2_OUT), | ||
690 | PINMUX_DATA(TCLKC_PF_MARK, PF2MD_01), | ||
691 | PINMUX_DATA(LCD_DATA2_MARK, PF2MD_10), | ||
692 | PINMUX_DATA(SSO0_PF_MARK, PF2MD_11), | ||
693 | |||
694 | PINMUX_DATA(PF1_DATA, PF1MD_00, PF1_IN, PF1_OUT), | ||
695 | PINMUX_DATA(TCLKB_PF_MARK, PF1MD_01), | ||
696 | PINMUX_DATA(LCD_DATA1_MARK, PF1MD_10), | ||
697 | PINMUX_DATA(SSI0_PF_MARK, PF1MD_11), | ||
698 | |||
699 | PINMUX_DATA(PF0_DATA, PF0MD_00, PF0_IN, PF0_OUT), | ||
700 | PINMUX_DATA(TCLKA_PF_MARK, PF0MD_01), | ||
701 | PINMUX_DATA(LCD_DATA0_MARK, PF0MD_10), | ||
702 | PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), | ||
703 | }; | ||
704 | |||
705 | static struct pinmux_gpio pinmux_gpios[] = { | ||
706 | |||
707 | /* PA */ | ||
708 | PINMUX_GPIO(GPIO_PA7, PA7_DATA), | ||
709 | PINMUX_GPIO(GPIO_PA6, PA6_DATA), | ||
710 | PINMUX_GPIO(GPIO_PA5, PA5_DATA), | ||
711 | PINMUX_GPIO(GPIO_PA4, PA4_DATA), | ||
712 | PINMUX_GPIO(GPIO_PA3, PA3_DATA), | ||
713 | PINMUX_GPIO(GPIO_PA2, PA2_DATA), | ||
714 | PINMUX_GPIO(GPIO_PA1, PA1_DATA), | ||
715 | PINMUX_GPIO(GPIO_PA0, PA0_DATA), | ||
716 | |||
717 | /* PB */ | ||
718 | PINMUX_GPIO(GPIO_PB12, PB12_DATA), | ||
719 | PINMUX_GPIO(GPIO_PB11, PB11_DATA), | ||
720 | PINMUX_GPIO(GPIO_PB10, PB10_DATA), | ||
721 | PINMUX_GPIO(GPIO_PB9, PB9_DATA), | ||
722 | PINMUX_GPIO(GPIO_PB8, PB8_DATA), | ||
723 | PINMUX_GPIO(GPIO_PB7, PB7_DATA), | ||
724 | PINMUX_GPIO(GPIO_PB6, PB6_DATA), | ||
725 | PINMUX_GPIO(GPIO_PB5, PB5_DATA), | ||
726 | PINMUX_GPIO(GPIO_PB4, PB4_DATA), | ||
727 | PINMUX_GPIO(GPIO_PB3, PB3_DATA), | ||
728 | PINMUX_GPIO(GPIO_PB2, PB2_DATA), | ||
729 | PINMUX_GPIO(GPIO_PB1, PB1_DATA), | ||
730 | PINMUX_GPIO(GPIO_PB0, PB0_DATA), | ||
731 | |||
732 | /* PC */ | ||
733 | PINMUX_GPIO(GPIO_PC14, PC14_DATA), | ||
734 | PINMUX_GPIO(GPIO_PC13, PC13_DATA), | ||
735 | PINMUX_GPIO(GPIO_PC12, PC12_DATA), | ||
736 | PINMUX_GPIO(GPIO_PC11, PC11_DATA), | ||
737 | PINMUX_GPIO(GPIO_PC10, PC10_DATA), | ||
738 | PINMUX_GPIO(GPIO_PC9, PC9_DATA), | ||
739 | PINMUX_GPIO(GPIO_PC8, PC8_DATA), | ||
740 | PINMUX_GPIO(GPIO_PC7, PC7_DATA), | ||
741 | PINMUX_GPIO(GPIO_PC6, PC6_DATA), | ||
742 | PINMUX_GPIO(GPIO_PC5, PC5_DATA), | ||
743 | PINMUX_GPIO(GPIO_PC4, PC4_DATA), | ||
744 | PINMUX_GPIO(GPIO_PC3, PC3_DATA), | ||
745 | PINMUX_GPIO(GPIO_PC2, PC2_DATA), | ||
746 | PINMUX_GPIO(GPIO_PC1, PC1_DATA), | ||
747 | PINMUX_GPIO(GPIO_PC0, PC0_DATA), | ||
748 | |||
749 | /* PD */ | ||
750 | PINMUX_GPIO(GPIO_PD15, PD15_DATA), | ||
751 | PINMUX_GPIO(GPIO_PD14, PD14_DATA), | ||
752 | PINMUX_GPIO(GPIO_PD13, PD13_DATA), | ||
753 | PINMUX_GPIO(GPIO_PD12, PD12_DATA), | ||
754 | PINMUX_GPIO(GPIO_PD11, PD11_DATA), | ||
755 | PINMUX_GPIO(GPIO_PD10, PD10_DATA), | ||
756 | PINMUX_GPIO(GPIO_PD9, PD9_DATA), | ||
757 | PINMUX_GPIO(GPIO_PD8, PD8_DATA), | ||
758 | PINMUX_GPIO(GPIO_PD7, PD7_DATA), | ||
759 | PINMUX_GPIO(GPIO_PD6, PD6_DATA), | ||
760 | PINMUX_GPIO(GPIO_PD5, PD5_DATA), | ||
761 | PINMUX_GPIO(GPIO_PD4, PD4_DATA), | ||
762 | PINMUX_GPIO(GPIO_PD3, PD3_DATA), | ||
763 | PINMUX_GPIO(GPIO_PD2, PD2_DATA), | ||
764 | PINMUX_GPIO(GPIO_PD1, PD1_DATA), | ||
765 | PINMUX_GPIO(GPIO_PD0, PD0_DATA), | ||
766 | |||
767 | /* PE */ | ||
768 | PINMUX_GPIO(GPIO_PE15, PE15_DATA), | ||
769 | PINMUX_GPIO(GPIO_PE14, PE14_DATA), | ||
770 | PINMUX_GPIO(GPIO_PE13, PE13_DATA), | ||
771 | PINMUX_GPIO(GPIO_PE12, PE12_DATA), | ||
772 | PINMUX_GPIO(GPIO_PE11, PE11_DATA), | ||
773 | PINMUX_GPIO(GPIO_PE10, PE10_DATA), | ||
774 | PINMUX_GPIO(GPIO_PE9, PE9_DATA), | ||
775 | PINMUX_GPIO(GPIO_PE8, PE8_DATA), | ||
776 | PINMUX_GPIO(GPIO_PE7, PE7_DATA), | ||
777 | PINMUX_GPIO(GPIO_PE6, PE6_DATA), | ||
778 | PINMUX_GPIO(GPIO_PE5, PE5_DATA), | ||
779 | PINMUX_GPIO(GPIO_PE4, PE4_DATA), | ||
780 | PINMUX_GPIO(GPIO_PE3, PE3_DATA), | ||
781 | PINMUX_GPIO(GPIO_PE2, PE2_DATA), | ||
782 | PINMUX_GPIO(GPIO_PE1, PE1_DATA), | ||
783 | PINMUX_GPIO(GPIO_PE0, PE0_DATA), | ||
784 | |||
785 | /* PF */ | ||
786 | PINMUX_GPIO(GPIO_PF30, PF30_DATA), | ||
787 | PINMUX_GPIO(GPIO_PF29, PF29_DATA), | ||
788 | PINMUX_GPIO(GPIO_PF28, PF28_DATA), | ||
789 | PINMUX_GPIO(GPIO_PF27, PF27_DATA), | ||
790 | PINMUX_GPIO(GPIO_PF26, PF26_DATA), | ||
791 | PINMUX_GPIO(GPIO_PF25, PF25_DATA), | ||
792 | PINMUX_GPIO(GPIO_PF24, PF24_DATA), | ||
793 | PINMUX_GPIO(GPIO_PF23, PF23_DATA), | ||
794 | PINMUX_GPIO(GPIO_PF22, PF22_DATA), | ||
795 | PINMUX_GPIO(GPIO_PF21, PF21_DATA), | ||
796 | PINMUX_GPIO(GPIO_PF20, PF20_DATA), | ||
797 | PINMUX_GPIO(GPIO_PF19, PF19_DATA), | ||
798 | PINMUX_GPIO(GPIO_PF18, PF18_DATA), | ||
799 | PINMUX_GPIO(GPIO_PF17, PF17_DATA), | ||
800 | PINMUX_GPIO(GPIO_PF16, PF16_DATA), | ||
801 | PINMUX_GPIO(GPIO_PF15, PF15_DATA), | ||
802 | PINMUX_GPIO(GPIO_PF14, PF14_DATA), | ||
803 | PINMUX_GPIO(GPIO_PF13, PF13_DATA), | ||
804 | PINMUX_GPIO(GPIO_PF12, PF12_DATA), | ||
805 | PINMUX_GPIO(GPIO_PF11, PF11_DATA), | ||
806 | PINMUX_GPIO(GPIO_PF10, PF10_DATA), | ||
807 | PINMUX_GPIO(GPIO_PF9, PF9_DATA), | ||
808 | PINMUX_GPIO(GPIO_PF8, PF8_DATA), | ||
809 | PINMUX_GPIO(GPIO_PF7, PF7_DATA), | ||
810 | PINMUX_GPIO(GPIO_PF6, PF6_DATA), | ||
811 | PINMUX_GPIO(GPIO_PF5, PF5_DATA), | ||
812 | PINMUX_GPIO(GPIO_PF4, PF4_DATA), | ||
813 | PINMUX_GPIO(GPIO_PF3, PF3_DATA), | ||
814 | PINMUX_GPIO(GPIO_PF2, PF2_DATA), | ||
815 | PINMUX_GPIO(GPIO_PF1, PF1_DATA), | ||
816 | PINMUX_GPIO(GPIO_PF0, PF0_DATA), | ||
817 | |||
818 | /* INTC */ | ||
819 | PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), | ||
820 | PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), | ||
821 | PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), | ||
822 | PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), | ||
823 | PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), | ||
824 | PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), | ||
825 | PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), | ||
826 | PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), | ||
827 | PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), | ||
828 | PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), | ||
829 | PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), | ||
830 | PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), | ||
831 | PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), | ||
832 | PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), | ||
833 | PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), | ||
834 | PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), | ||
835 | PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), | ||
836 | PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), | ||
837 | PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), | ||
838 | PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), | ||
839 | PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), | ||
840 | PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), | ||
841 | PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), | ||
842 | PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), | ||
843 | PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), | ||
844 | PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), | ||
845 | PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), | ||
846 | PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), | ||
847 | PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), | ||
848 | PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), | ||
849 | PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), | ||
850 | PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), | ||
851 | PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), | ||
852 | PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), | ||
853 | PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), | ||
854 | PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), | ||
855 | PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), | ||
856 | PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), | ||
857 | PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), | ||
858 | PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), | ||
859 | |||
860 | PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), | ||
861 | PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), | ||
862 | PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), | ||
863 | PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), | ||
864 | PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), | ||
865 | |||
866 | /* CAN */ | ||
867 | PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), | ||
868 | PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), | ||
869 | PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), | ||
870 | PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), | ||
871 | PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), | ||
872 | PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), | ||
873 | |||
874 | /* IIC3 */ | ||
875 | PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), | ||
876 | PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), | ||
877 | PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), | ||
878 | PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), | ||
879 | PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), | ||
880 | PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), | ||
881 | PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), | ||
882 | PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), | ||
883 | |||
884 | /* DMAC */ | ||
885 | PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), | ||
886 | PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), | ||
887 | PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), | ||
888 | PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), | ||
889 | PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), | ||
890 | PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), | ||
891 | PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), | ||
892 | PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), | ||
893 | PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), | ||
894 | PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), | ||
895 | PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), | ||
896 | PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), | ||
897 | PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), | ||
898 | PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), | ||
899 | PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), | ||
900 | PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), | ||
901 | |||
902 | /* ADC */ | ||
903 | PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), | ||
904 | PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), | ||
905 | |||
906 | /* BSC */ | ||
907 | PINMUX_GPIO(GPIO_FN_D31, D31_MARK), | ||
908 | PINMUX_GPIO(GPIO_FN_D30, D30_MARK), | ||
909 | PINMUX_GPIO(GPIO_FN_D29, D29_MARK), | ||
910 | PINMUX_GPIO(GPIO_FN_D28, D28_MARK), | ||
911 | PINMUX_GPIO(GPIO_FN_D27, D27_MARK), | ||
912 | PINMUX_GPIO(GPIO_FN_D26, D26_MARK), | ||
913 | PINMUX_GPIO(GPIO_FN_D25, D25_MARK), | ||
914 | PINMUX_GPIO(GPIO_FN_D24, D24_MARK), | ||
915 | PINMUX_GPIO(GPIO_FN_D23, D23_MARK), | ||
916 | PINMUX_GPIO(GPIO_FN_D22, D22_MARK), | ||
917 | PINMUX_GPIO(GPIO_FN_D21, D21_MARK), | ||
918 | PINMUX_GPIO(GPIO_FN_D20, D20_MARK), | ||
919 | PINMUX_GPIO(GPIO_FN_D19, D19_MARK), | ||
920 | PINMUX_GPIO(GPIO_FN_D18, D18_MARK), | ||
921 | PINMUX_GPIO(GPIO_FN_D17, D17_MARK), | ||
922 | PINMUX_GPIO(GPIO_FN_D16, D16_MARK), | ||
923 | PINMUX_GPIO(GPIO_FN_A25, A25_MARK), | ||
924 | PINMUX_GPIO(GPIO_FN_A24, A24_MARK), | ||
925 | PINMUX_GPIO(GPIO_FN_A23, A23_MARK), | ||
926 | PINMUX_GPIO(GPIO_FN_A22, A22_MARK), | ||
927 | PINMUX_GPIO(GPIO_FN_A21, A21_MARK), | ||
928 | PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), | ||
929 | PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), | ||
930 | PINMUX_GPIO(GPIO_FN_BS, BS_MARK), | ||
931 | PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), | ||
932 | PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), | ||
933 | PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), | ||
934 | PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), | ||
935 | PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), | ||
936 | PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), | ||
937 | PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), | ||
938 | PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), | ||
939 | PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), | ||
940 | PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), | ||
941 | PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), | ||
942 | PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), | ||
943 | PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), | ||
944 | PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), | ||
945 | PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), | ||
946 | PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), | ||
947 | PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), | ||
948 | PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), | ||
949 | PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), | ||
950 | PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), | ||
951 | PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), | ||
952 | PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), | ||
953 | PINMUX_GPIO(GPIO_FN_A1, A1_MARK), | ||
954 | PINMUX_GPIO(GPIO_FN_A0, A0_MARK), | ||
955 | PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), | ||
956 | |||
957 | /* TMU */ | ||
958 | PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), | ||
959 | PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), | ||
960 | PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), | ||
961 | PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), | ||
962 | PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), | ||
963 | PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), | ||
964 | PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), | ||
965 | PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), | ||
966 | PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), | ||
967 | PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), | ||
968 | PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), | ||
969 | PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), | ||
970 | PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), | ||
971 | PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), | ||
972 | PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), | ||
973 | PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), | ||
974 | PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), | ||
975 | PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), | ||
976 | PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), | ||
977 | PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), | ||
978 | PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), | ||
979 | PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), | ||
980 | PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), | ||
981 | PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), | ||
982 | |||
983 | /* SSU */ | ||
984 | PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), | ||
985 | PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), | ||
986 | PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), | ||
987 | PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), | ||
988 | PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), | ||
989 | PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), | ||
990 | PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), | ||
991 | PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), | ||
992 | PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), | ||
993 | PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), | ||
994 | PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), | ||
995 | PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), | ||
996 | PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), | ||
997 | PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), | ||
998 | PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), | ||
999 | PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), | ||
1000 | |||
1001 | /* SCIF */ | ||
1002 | PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), | ||
1003 | PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), | ||
1004 | PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), | ||
1005 | PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), | ||
1006 | PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), | ||
1007 | PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), | ||
1008 | PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), | ||
1009 | PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), | ||
1010 | PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), | ||
1011 | PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), | ||
1012 | PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), | ||
1013 | PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), | ||
1014 | PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), | ||
1015 | PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), | ||
1016 | |||
1017 | /* SSI */ | ||
1018 | PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), | ||
1019 | PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), | ||
1020 | PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), | ||
1021 | PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), | ||
1022 | PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), | ||
1023 | PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), | ||
1024 | PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), | ||
1025 | PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), | ||
1026 | PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), | ||
1027 | PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), | ||
1028 | PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), | ||
1029 | PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), | ||
1030 | PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), | ||
1031 | |||
1032 | /* FLCTL */ | ||
1033 | PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), | ||
1034 | PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), | ||
1035 | PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), | ||
1036 | PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), | ||
1037 | PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), | ||
1038 | PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), | ||
1039 | PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), | ||
1040 | PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), | ||
1041 | PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), | ||
1042 | PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), | ||
1043 | PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), | ||
1044 | PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), | ||
1045 | PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), | ||
1046 | PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), | ||
1047 | |||
1048 | /* LCDC */ | ||
1049 | PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), | ||
1050 | PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), | ||
1051 | PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), | ||
1052 | PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), | ||
1053 | PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), | ||
1054 | PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), | ||
1055 | PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), | ||
1056 | PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), | ||
1057 | PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), | ||
1058 | PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), | ||
1059 | PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), | ||
1060 | PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), | ||
1061 | PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), | ||
1062 | PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), | ||
1063 | PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), | ||
1064 | PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), | ||
1065 | PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), | ||
1066 | PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), | ||
1067 | PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), | ||
1068 | PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), | ||
1069 | PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), | ||
1070 | PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), | ||
1071 | PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), | ||
1072 | PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), | ||
1073 | }; | ||
1074 | |||
1075 | static struct pinmux_cfg_reg pinmux_config_regs[] = { | ||
1076 | { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { | ||
1077 | 0, 0, | ||
1078 | 0, 0, | ||
1079 | 0, 0, | ||
1080 | 0, 0, | ||
1081 | PB11_IN, PB11_OUT, | ||
1082 | PB10_IN, PB10_OUT, | ||
1083 | PB9_IN, PB9_OUT, | ||
1084 | PB8_IN, PB8_OUT, | ||
1085 | 0, 0, | ||
1086 | 0, 0, | ||
1087 | 0, 0, | ||
1088 | 0, 0, | ||
1089 | 0, 0, | ||
1090 | 0, 0, | ||
1091 | 0, 0, | ||
1092 | 0, 0 } | ||
1093 | }, | ||
1094 | { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) { | ||
1095 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1096 | |||
1097 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1098 | |||
1099 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1100 | |||
1101 | PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, | ||
1102 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1103 | }, | ||
1104 | { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) { | ||
1105 | PB11MD_0, PB11MD_1, | ||
1106 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1107 | |||
1108 | PB10MD_0, PB10MD_1, | ||
1109 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1110 | |||
1111 | PB9MD_00, PB9MD_01, PB9MD_10, 0, | ||
1112 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1113 | |||
1114 | PB8MD_00, PB8MD_01, PB8MD_10, 0, | ||
1115 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1116 | }, | ||
1117 | { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) { | ||
1118 | PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, | ||
1119 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1120 | |||
1121 | PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, | ||
1122 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1123 | |||
1124 | PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, | ||
1125 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1126 | |||
1127 | PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, | ||
1128 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1129 | }, | ||
1130 | { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) { | ||
1131 | PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, | ||
1132 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1133 | |||
1134 | PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, | ||
1135 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1136 | |||
1137 | PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, | ||
1138 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1139 | |||
1140 | PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11, | ||
1141 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1142 | }, | ||
1143 | { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) { | ||
1144 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1145 | |||
1146 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1147 | |||
1148 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1149 | |||
1150 | PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0, | ||
1151 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1152 | }, | ||
1153 | { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) { | ||
1154 | 0, 0, | ||
1155 | PC14_IN, PC14_OUT, | ||
1156 | PC13_IN, PC13_OUT, | ||
1157 | PC12_IN, PC12_OUT, | ||
1158 | PC11_IN, PC11_OUT, | ||
1159 | PC10_IN, PC10_OUT, | ||
1160 | PC9_IN, PC9_OUT, | ||
1161 | PC8_IN, PC8_OUT, | ||
1162 | PC7_IN, PC7_OUT, | ||
1163 | PC6_IN, PC6_OUT, | ||
1164 | PC5_IN, PC5_OUT, | ||
1165 | PC4_IN, PC4_OUT, | ||
1166 | PC3_IN, PC3_OUT, | ||
1167 | PC2_IN, PC2_OUT, | ||
1168 | PC1_IN, PC1_OUT, | ||
1169 | PC0_IN, PC0_OUT } | ||
1170 | }, | ||
1171 | { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) { | ||
1172 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1173 | |||
1174 | PC14MD_0, PC14MD_1, | ||
1175 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1176 | |||
1177 | PC13MD_0, PC13MD_1, | ||
1178 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1179 | |||
1180 | PC12MD_0, PC12MD_1, | ||
1181 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1182 | }, | ||
1183 | { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) { | ||
1184 | PC11MD_00, PC11MD_01, PC11MD_10, 0, | ||
1185 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1186 | |||
1187 | PC10MD_00, PC10MD_01, PC10MD_10, 0, | ||
1188 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1189 | |||
1190 | PC9MD_0, PC9MD_1, | ||
1191 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1192 | |||
1193 | PC8MD_0, PC8MD_1, | ||
1194 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1195 | }, | ||
1196 | { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) { | ||
1197 | PC7MD_0, PC7MD_1, | ||
1198 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1199 | |||
1200 | PC6MD_0, PC6MD_1, | ||
1201 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1202 | |||
1203 | PC5MD_0, PC5MD_1, | ||
1204 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1205 | |||
1206 | PC4MD_0, PC4MD_1, | ||
1207 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1208 | }, | ||
1209 | { PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4) { | ||
1210 | PC3MD_0, PC3MD_1, | ||
1211 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1212 | |||
1213 | PC2MD_0, PC2MD_1, | ||
1214 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1215 | |||
1216 | PC1MD_0, PC1MD_1, | ||
1217 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1218 | |||
1219 | PC0MD_00, PC0MD_01, PC0MD_10, 0, | ||
1220 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1221 | }, | ||
1222 | { PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1) { | ||
1223 | PD15_IN, PD15_OUT, | ||
1224 | PD14_IN, PD14_OUT, | ||
1225 | PD13_IN, PD13_OUT, | ||
1226 | PD12_IN, PD12_OUT, | ||
1227 | PD11_IN, PD11_OUT, | ||
1228 | PD10_IN, PD10_OUT, | ||
1229 | PD9_IN, PD9_OUT, | ||
1230 | PD8_IN, PD8_OUT, | ||
1231 | PD7_IN, PD7_OUT, | ||
1232 | PD6_IN, PD6_OUT, | ||
1233 | PD5_IN, PD5_OUT, | ||
1234 | PD4_IN, PD4_OUT, | ||
1235 | PD3_IN, PD3_OUT, | ||
1236 | PD2_IN, PD2_OUT, | ||
1237 | PD1_IN, PD1_OUT, | ||
1238 | PD0_IN, PD0_OUT } | ||
1239 | }, | ||
1240 | { PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4) { | ||
1241 | PD15MD_000, PD15MD_001, PD15MD_010, 0, | ||
1242 | PD15MD_100, PD15MD_101, 0, 0, | ||
1243 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1244 | |||
1245 | PD14MD_000, PD14MD_001, PD14MD_010, 0, | ||
1246 | 0, PD14MD_101, 0, 0, | ||
1247 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1248 | |||
1249 | PD13MD_000, PD13MD_001, PD13MD_010, 0, | ||
1250 | PD13MD_100, PD13MD_101, 0, 0, | ||
1251 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1252 | |||
1253 | PD12MD_000, PD12MD_001, PD12MD_010, 0, | ||
1254 | PD12MD_100, PD12MD_101, 0, 0, | ||
1255 | 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1256 | }, | ||
1257 | { PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4) { | ||
1258 | PD11MD_000, PD11MD_001, PD11MD_010, 0, | ||
1259 | PD11MD_100, PD11MD_101, 0, 0, | ||
1260 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1261 | |||
1262 | PD10MD_000, PD10MD_001, PD10MD_010, 0, | ||
1263 | PD10MD_100, PD10MD_101, 0, 0, | ||
1264 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1265 | |||
1266 | PD9MD_000, PD9MD_001, PD9MD_010, 0, | ||
1267 | PD9MD_100, PD9MD_101, 0, 0, | ||
1268 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1269 | |||
1270 | PD8MD_000, PD8MD_001, PD8MD_010, 0, | ||
1271 | PD8MD_100, PD8MD_101, 0, 0, | ||
1272 | 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1273 | }, | ||
1274 | { PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4) { | ||
1275 | PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, | ||
1276 | PD7MD_100, PD7MD_101, 0, 0, | ||
1277 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1278 | |||
1279 | PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, | ||
1280 | PD6MD_100, PD6MD_101, 0, 0, | ||
1281 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1282 | |||
1283 | PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, | ||
1284 | PD5MD_100, PD5MD_101, 0, 0, | ||
1285 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1286 | |||
1287 | PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, | ||
1288 | PD4MD_100, PD4MD_101, 0, 0, | ||
1289 | 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1290 | }, | ||
1291 | { PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4) { | ||
1292 | PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, | ||
1293 | PD3MD_100, PD3MD_101, 0, 0, | ||
1294 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1295 | |||
1296 | PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, | ||
1297 | PD2MD_100, PD2MD_101, 0, 0, | ||
1298 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1299 | |||
1300 | PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, | ||
1301 | PD1MD_100, PD1MD_101, 0, 0, | ||
1302 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1303 | |||
1304 | PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, | ||
1305 | PD0MD_100, PD0MD_101, 0, 0, | ||
1306 | 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1307 | }, | ||
1308 | { PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1) { | ||
1309 | PE15_IN, PE15_OUT, | ||
1310 | PE14_IN, PE14_OUT, | ||
1311 | PE13_IN, PE13_OUT, | ||
1312 | PE12_IN, PE12_OUT, | ||
1313 | PE11_IN, PE11_OUT, | ||
1314 | PE10_IN, PE10_OUT, | ||
1315 | PE9_IN, PE9_OUT, | ||
1316 | PE8_IN, PE8_OUT, | ||
1317 | PE7_IN, PE7_OUT, | ||
1318 | PE6_IN, PE6_OUT, | ||
1319 | PE5_IN, PE5_OUT, | ||
1320 | PE4_IN, PE4_OUT, | ||
1321 | PE3_IN, PE3_OUT, | ||
1322 | PE2_IN, PE2_OUT, | ||
1323 | PE1_IN, PE1_OUT, | ||
1324 | PE0_IN, PE0_OUT } | ||
1325 | }, | ||
1326 | { PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4) { | ||
1327 | PE15MD_00, PE15MD_01, 0, PE15MD_11, | ||
1328 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1329 | |||
1330 | PE14MD_00, PE14MD_01, 0, PE14MD_11, | ||
1331 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1332 | |||
1333 | PE13MD_00, 0, 0, PE13MD_11, | ||
1334 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1335 | |||
1336 | PE12MD_00, 0, 0, PE12MD_11, | ||
1337 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1338 | }, | ||
1339 | { PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4) { | ||
1340 | PE11MD_000, PE11MD_001, PE11MD_010, 0, | ||
1341 | PE11MD_100, 0, 0, 0, | ||
1342 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1343 | |||
1344 | PE10MD_000, PE10MD_001, PE10MD_010, 0, | ||
1345 | PE10MD_100, 0, 0, 0, | ||
1346 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1347 | |||
1348 | PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11, | ||
1349 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1350 | |||
1351 | PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11, | ||
1352 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1353 | }, | ||
1354 | { PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4) { | ||
1355 | PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, | ||
1356 | PE7MD_100, 0, 0, 0, | ||
1357 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1358 | |||
1359 | PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, | ||
1360 | PE6MD_100, 0, 0, 0, | ||
1361 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1362 | |||
1363 | PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, | ||
1364 | PE5MD_100, 0, 0, 0, | ||
1365 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
1366 | |||
1367 | PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, | ||
1368 | PE4MD_100, 0, 0, 0, | ||
1369 | 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1370 | }, | ||
1371 | { PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4) { | ||
1372 | PE3MD_00, PE3MD_01, 0, PE3MD_11, | ||
1373 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1374 | |||
1375 | PE2MD_00, PE2MD_01, 0, PE2MD_11, | ||
1376 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1377 | |||
1378 | PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11, | ||
1379 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1380 | |||
1381 | PE0MD_000, PE0MD_001, 0, PE0MD_011, | ||
1382 | PE0MD_100, 0, 0, 0, | ||
1383 | 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1384 | }, | ||
1385 | { PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1) { | ||
1386 | 0, 0, | ||
1387 | PF30_IN, PF30_OUT, | ||
1388 | PF29_IN, PF29_OUT, | ||
1389 | PF28_IN, PF28_OUT, | ||
1390 | PF27_IN, PF27_OUT, | ||
1391 | PF26_IN, PF26_OUT, | ||
1392 | PF25_IN, PF25_OUT, | ||
1393 | PF24_IN, PF24_OUT, | ||
1394 | PF23_IN, PF23_OUT, | ||
1395 | PF22_IN, PF22_OUT, | ||
1396 | PF21_IN, PF21_OUT, | ||
1397 | PF20_IN, PF20_OUT, | ||
1398 | PF19_IN, PF19_OUT, | ||
1399 | PF18_IN, PF18_OUT, | ||
1400 | PF17_IN, PF17_OUT, | ||
1401 | PF16_IN, PF16_OUT } | ||
1402 | }, | ||
1403 | { PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1) { | ||
1404 | PF15_IN, PF15_OUT, | ||
1405 | PF14_IN, PF14_OUT, | ||
1406 | PF13_IN, PF13_OUT, | ||
1407 | PF12_IN, PF12_OUT, | ||
1408 | PF11_IN, PF11_OUT, | ||
1409 | PF10_IN, PF10_OUT, | ||
1410 | PF9_IN, PF9_OUT, | ||
1411 | PF8_IN, PF8_OUT, | ||
1412 | PF7_IN, PF7_OUT, | ||
1413 | PF6_IN, PF6_OUT, | ||
1414 | PF5_IN, PF5_OUT, | ||
1415 | PF4_IN, PF4_OUT, | ||
1416 | PF3_IN, PF3_OUT, | ||
1417 | PF2_IN, PF2_OUT, | ||
1418 | PF1_IN, PF1_OUT, | ||
1419 | PF0_IN, PF0_OUT } | ||
1420 | }, | ||
1421 | { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4) { | ||
1422 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1423 | |||
1424 | PF30MD_0, PF30MD_1, | ||
1425 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1426 | |||
1427 | PF29MD_0, PF29MD_1, | ||
1428 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1429 | |||
1430 | PF28MD_0, PF28MD_1, | ||
1431 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1432 | }, | ||
1433 | { PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4) { | ||
1434 | PF27MD_0, PF27MD_1, | ||
1435 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1436 | |||
1437 | PF26MD_0, PF26MD_1, | ||
1438 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1439 | |||
1440 | PF25MD_0, PF25MD_1, | ||
1441 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1442 | |||
1443 | PF24MD_0, PF24MD_1, | ||
1444 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1445 | }, | ||
1446 | { PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4) { | ||
1447 | PF23MD_00, PF23MD_01, PF23MD_10, 0, | ||
1448 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1449 | |||
1450 | PF22MD_00, PF22MD_01, PF22MD_10, 0, | ||
1451 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1452 | |||
1453 | PF21MD_00, PF21MD_01, PF21MD_10, 0, | ||
1454 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1455 | |||
1456 | PF20MD_00, PF20MD_01, PF20MD_10, 0, | ||
1457 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1458 | }, | ||
1459 | { PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4) { | ||
1460 | PF19MD_00, PF19MD_01, PF19MD_10, 0, | ||
1461 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1462 | |||
1463 | PF18MD_00, PF18MD_01, PF18MD_10, 0, | ||
1464 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1465 | |||
1466 | PF17MD_00, PF17MD_01, PF17MD_10, 0, | ||
1467 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1468 | |||
1469 | PF16MD_00, PF16MD_01, PF16MD_10, 0, | ||
1470 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1471 | }, | ||
1472 | { PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4) { | ||
1473 | PF15MD_00, PF15MD_01, PF15MD_10, 0, | ||
1474 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1475 | |||
1476 | PF14MD_00, PF14MD_01, PF14MD_10, 0, | ||
1477 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1478 | |||
1479 | PF13MD_00, PF13MD_01, PF13MD_10, 0, | ||
1480 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1481 | |||
1482 | PF12MD_00, PF12MD_01, PF12MD_10, 0, | ||
1483 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1484 | }, | ||
1485 | { PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4) { | ||
1486 | PF11MD_00, PF11MD_01, PF11MD_10, 0, | ||
1487 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1488 | |||
1489 | PF10MD_00, PF10MD_01, PF10MD_10, 0, | ||
1490 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1491 | |||
1492 | PF9MD_00, PF9MD_01, PF9MD_10, 0, | ||
1493 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1494 | |||
1495 | PF8MD_00, PF8MD_01, PF8MD_10, 0, | ||
1496 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1497 | }, | ||
1498 | { PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4) { | ||
1499 | PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11, | ||
1500 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1501 | |||
1502 | PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11, | ||
1503 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1504 | |||
1505 | PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11, | ||
1506 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1507 | |||
1508 | PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11, | ||
1509 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1510 | }, | ||
1511 | { PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4) { | ||
1512 | PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11, | ||
1513 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1514 | |||
1515 | PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11, | ||
1516 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1517 | |||
1518 | PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11, | ||
1519 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1520 | |||
1521 | PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11, | ||
1522 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1523 | }, | ||
1524 | {} | ||
1525 | }; | ||
1526 | |||
1527 | static struct pinmux_data_reg pinmux_data_regs[] = { | ||
1528 | { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { | ||
1529 | 0, 0, 0, 0, | ||
1530 | 0, 0, 0, 0, | ||
1531 | PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, | ||
1532 | PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } | ||
1533 | }, | ||
1534 | { PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) { | ||
1535 | 0, 0, 0, PB12_DATA, | ||
1536 | PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, | ||
1537 | PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, | ||
1538 | PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } | ||
1539 | }, | ||
1540 | { PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) { | ||
1541 | 0, PC14_DATA, PC13_DATA, PC12_DATA, | ||
1542 | PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA, | ||
1543 | PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, | ||
1544 | PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } | ||
1545 | }, | ||
1546 | { PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) { | ||
1547 | PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, | ||
1548 | PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, | ||
1549 | PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, | ||
1550 | PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } | ||
1551 | }, | ||
1552 | { PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) { | ||
1553 | PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA, | ||
1554 | PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA, | ||
1555 | PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, | ||
1556 | PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } | ||
1557 | }, | ||
1558 | { PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) { | ||
1559 | 0, PF30_DATA, PF29_DATA, PF28_DATA, | ||
1560 | PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA, | ||
1561 | PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, | ||
1562 | PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA } | ||
1563 | }, | ||
1564 | { PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) { | ||
1565 | PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, | ||
1566 | PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, | ||
1567 | PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, | ||
1568 | PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } | ||
1569 | }, | ||
1570 | { }, | ||
1571 | }; | ||
1572 | |||
1573 | struct sh_pfc_soc_info sh7203_pinmux_info = { | ||
1574 | .name = "sh7203_pfc", | ||
1575 | .reserved_id = PINMUX_RESERVED, | ||
1576 | .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, | ||
1577 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, | ||
1578 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, | ||
1579 | .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, | ||
1580 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | ||
1581 | |||
1582 | .first_gpio = GPIO_PA7, | ||
1583 | .last_gpio = GPIO_FN_LCD_DATA0, | ||
1584 | |||
1585 | .gpios = pinmux_gpios, | ||
1586 | .cfg_regs = pinmux_config_regs, | ||
1587 | .data_regs = pinmux_data_regs, | ||
1588 | |||
1589 | .gpio_data = pinmux_data, | ||
1590 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | ||
1591 | }; | ||