diff options
author | Stephen Warren <swarren@nvidia.com> | 2012-04-11 17:42:56 -0400 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2012-04-18 16:35:18 -0400 |
commit | b5badbaad16b44f1d5508701295fa682308da701 (patch) | |
tree | 75764dbb2f856b30b15cc0df1285153808317b9e /drivers/pinctrl | |
parent | 52f48fe00fcad83cd5fc4c961d851a3530fe032b (diff) |
pinctrl: tegra: debugfs enhancements
* Only provide debugfs-relates ops when CONFIG_DEBUG_FS is enabled.
* Implement pin_config_group_dbg_show op.
* Implement pin_config_config_dbg_show op.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/pinctrl-tegra.c | 75 |
1 files changed, 69 insertions, 6 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 3ac8ad3829e4..df52d75c0db0 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c | |||
@@ -83,12 +83,14 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |||
83 | return 0; | 83 | return 0; |
84 | } | 84 | } |
85 | 85 | ||
86 | #ifdef CONFIG_DEBUG_FS | ||
86 | static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, | 87 | static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, |
87 | struct seq_file *s, | 88 | struct seq_file *s, |
88 | unsigned offset) | 89 | unsigned offset) |
89 | { | 90 | { |
90 | seq_printf(s, " %s", dev_name(pctldev->dev)); | 91 | seq_printf(s, " %s", dev_name(pctldev->dev)); |
91 | } | 92 | } |
93 | #endif | ||
92 | 94 | ||
93 | static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, | 95 | static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, |
94 | unsigned *num_maps, unsigned reserve) | 96 | unsigned *num_maps, unsigned reserve) |
@@ -295,7 +297,9 @@ static struct pinctrl_ops tegra_pinctrl_ops = { | |||
295 | .get_groups_count = tegra_pinctrl_get_groups_count, | 297 | .get_groups_count = tegra_pinctrl_get_groups_count, |
296 | .get_group_name = tegra_pinctrl_get_group_name, | 298 | .get_group_name = tegra_pinctrl_get_group_name, |
297 | .get_group_pins = tegra_pinctrl_get_group_pins, | 299 | .get_group_pins = tegra_pinctrl_get_group_pins, |
300 | #ifdef CONFIG_DEBUG_FS | ||
298 | .pin_dbg_show = tegra_pinctrl_pin_dbg_show, | 301 | .pin_dbg_show = tegra_pinctrl_pin_dbg_show, |
302 | #endif | ||
299 | .dt_node_to_map = tegra_pinctrl_dt_node_to_map, | 303 | .dt_node_to_map = tegra_pinctrl_dt_node_to_map, |
300 | .dt_free_map = tegra_pinctrl_dt_free_map, | 304 | .dt_free_map = tegra_pinctrl_dt_free_map, |
301 | }; | 305 | }; |
@@ -385,6 +389,7 @@ static struct pinmux_ops tegra_pinmux_ops = { | |||
385 | static int tegra_pinconf_reg(struct tegra_pmx *pmx, | 389 | static int tegra_pinconf_reg(struct tegra_pmx *pmx, |
386 | const struct tegra_pingroup *g, | 390 | const struct tegra_pingroup *g, |
387 | enum tegra_pinconf_param param, | 391 | enum tegra_pinconf_param param, |
392 | bool report_err, | ||
388 | s8 *bank, s16 *reg, s8 *bit, s8 *width) | 393 | s8 *bank, s16 *reg, s8 *bit, s8 *width) |
389 | { | 394 | { |
390 | switch (param) { | 395 | switch (param) { |
@@ -472,9 +477,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, | |||
472 | } | 477 | } |
473 | 478 | ||
474 | if (*reg < 0) { | 479 | if (*reg < 0) { |
475 | dev_err(pmx->dev, | 480 | if (report_err) |
476 | "Config param %04x not supported on group %s\n", | 481 | dev_err(pmx->dev, |
477 | param, g->name); | 482 | "Config param %04x not supported on group %s\n", |
483 | param, g->name); | ||
478 | return -ENOTSUPP; | 484 | return -ENOTSUPP; |
479 | } | 485 | } |
480 | 486 | ||
@@ -507,7 +513,8 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, | |||
507 | 513 | ||
508 | g = &pmx->soc->groups[group]; | 514 | g = &pmx->soc->groups[group]; |
509 | 515 | ||
510 | ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); | 516 | ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
517 | &width); | ||
511 | if (ret < 0) | 518 | if (ret < 0) |
512 | return ret; | 519 | return ret; |
513 | 520 | ||
@@ -534,7 +541,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |||
534 | 541 | ||
535 | g = &pmx->soc->groups[group]; | 542 | g = &pmx->soc->groups[group]; |
536 | 543 | ||
537 | ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); | 544 | ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
545 | &width); | ||
538 | if (ret < 0) | 546 | if (ret < 0) |
539 | return ret; | 547 | return ret; |
540 | 548 | ||
@@ -563,23 +571,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |||
563 | return 0; | 571 | return 0; |
564 | } | 572 | } |
565 | 573 | ||
574 | #ifdef CONFIG_DEBUG_FS | ||
566 | static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, | 575 | static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
567 | struct seq_file *s, unsigned offset) | 576 | struct seq_file *s, unsigned offset) |
568 | { | 577 | { |
569 | } | 578 | } |
570 | 579 | ||
580 | static const char *strip_prefix(const char *s) | ||
581 | { | ||
582 | const char *comma = strchr(s, ','); | ||
583 | if (!comma) | ||
584 | return s; | ||
585 | |||
586 | return comma + 1; | ||
587 | } | ||
588 | |||
571 | static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | 589 | static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
572 | struct seq_file *s, unsigned selector) | 590 | struct seq_file *s, unsigned group) |
591 | { | ||
592 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
593 | const struct tegra_pingroup *g; | ||
594 | int i, ret; | ||
595 | s8 bank, bit, width; | ||
596 | s16 reg; | ||
597 | u32 val; | ||
598 | |||
599 | g = &pmx->soc->groups[group]; | ||
600 | |||
601 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | ||
602 | ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, | ||
603 | &bank, ®, &bit, &width); | ||
604 | if (ret < 0) | ||
605 | continue; | ||
606 | |||
607 | val = pmx_readl(pmx, bank, reg); | ||
608 | val >>= bit; | ||
609 | val &= (1 << width) - 1; | ||
610 | |||
611 | seq_printf(s, "\n\t%s=%u", | ||
612 | strip_prefix(cfg_params[i].property), val); | ||
613 | } | ||
614 | } | ||
615 | |||
616 | static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, | ||
617 | struct seq_file *s, | ||
618 | unsigned long config) | ||
573 | { | 619 | { |
620 | enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); | ||
621 | u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); | ||
622 | const char *pname = "unknown"; | ||
623 | int i; | ||
624 | |||
625 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | ||
626 | if (cfg_params[i].param == param) { | ||
627 | pname = cfg_params[i].property; | ||
628 | break; | ||
629 | } | ||
630 | } | ||
631 | |||
632 | seq_printf(s, "%s=%d", strip_prefix(pname), arg); | ||
574 | } | 633 | } |
634 | #endif | ||
575 | 635 | ||
576 | struct pinconf_ops tegra_pinconf_ops = { | 636 | struct pinconf_ops tegra_pinconf_ops = { |
577 | .pin_config_get = tegra_pinconf_get, | 637 | .pin_config_get = tegra_pinconf_get, |
578 | .pin_config_set = tegra_pinconf_set, | 638 | .pin_config_set = tegra_pinconf_set, |
579 | .pin_config_group_get = tegra_pinconf_group_get, | 639 | .pin_config_group_get = tegra_pinconf_group_get, |
580 | .pin_config_group_set = tegra_pinconf_group_set, | 640 | .pin_config_group_set = tegra_pinconf_group_set, |
641 | #ifdef CONFIG_DEBUG_FS | ||
581 | .pin_config_dbg_show = tegra_pinconf_dbg_show, | 642 | .pin_config_dbg_show = tegra_pinconf_dbg_show, |
582 | .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, | 643 | .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, |
644 | .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, | ||
645 | #endif | ||
583 | }; | 646 | }; |
584 | 647 | ||
585 | static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { | 648 | static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { |