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authorJean-Nicolas Graux <jean-nicolas.graux@stericsson.com>2012-09-27 09:38:50 -0400
committerLinus Walleij <linus.walleij@linaro.org>2012-10-10 02:36:59 -0400
commitc22df08c7ffbfb281b0e5dff3fff4e192d1a7863 (patch)
tree0cd3f0a19be0391c4ed14d45f47c6aca34c1a055 /drivers/pinctrl
parent547b1e81afe3119f7daf702cc03b158495535a25 (diff)
pinctrl/nomadik: support other alternate-C functions
Upgrade nomadik pinctrl driver to enable selection of other alternate-C[1-4] functions on some specific ux500 SoC pins. Handling of those functions is done thanks to PRCM GPIOCR registers. This was previously managed in PRCMU driver and it was not really convenient. Idea is to provide a common way to control all alternate functions. Note that this improvement does not support the old-fashioned way used to control nomadik pins, namely the "nmk_config_pin()" function and its derivatives. Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@stericsson.com> Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c289
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8540.c344
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c101
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h78
4 files changed, 765 insertions, 47 deletions
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index ec6209dd7c39..debaa75b0552 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -725,10 +725,10 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
725 DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), 725 DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
726 DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C), 726 DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
727 DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C), 727 DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
728 /* Other alt C1 column, these are still configured as alt C */ 728 /* Other alt C1 column */
729 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C), 729 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
730 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C), 730 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C1),
731 DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C), 731 DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C1),
732}; 732};
733 733
734/* We use this macro to define the groups applicable to a function */ 734/* We use this macro to define the groups applicable to a function */
@@ -860,6 +860,284 @@ static const struct nmk_function nmk_db8500_functions[] = {
860 FUNCTION(spi2), 860 FUNCTION(spi2),
861}; 861};
862 862
863static const struct prcm_gpiocr_altcx_pin_desc db8500_altcx_pins[] = {
864 PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */
865 true, PRCM_IDX_GPIOCR1, 7, /* SBAG_CLK_a */
866 false, 0, 0,
867 false, 0, 0
868 ),
869 PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE or U2_RXD ??? */
870 true, PRCM_IDX_GPIOCR1, 7, /* SBAG_VAL_a */
871 true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
872 false, 0, 0
873 ),
874 PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */
875 true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[0] */
876 false, 0, 0,
877 false, 0, 0
878 ),
879 PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */
880 true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[1] */
881 false, 0, 0,
882 false, 0, 0
883 ),
884 PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */
885 true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[2] */
886 false, 0, 0,
887 false, 0, 0
888 ),
889 PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */
890 true, PRCM_IDX_GPIOCR1, 7, /* SBAG_D_a[3] */
891 false, 0, 0,
892 false, 0, 0
893 ),
894 PRCM_GPIOCR_ALTCX(29, false, 0, 0,
895 false, 0, 0,
896 true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
897 false, 0, 0
898 ),
899 PRCM_GPIOCR_ALTCX(30, false, 0, 0,
900 false, 0, 0,
901 true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
902 false, 0, 0
903 ),
904 PRCM_GPIOCR_ALTCX(31, false, 0, 0,
905 false, 0, 0,
906 true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
907 false, 0, 0
908 ),
909 PRCM_GPIOCR_ALTCX(32, false, 0, 0,
910 false, 0, 0,
911 true, PRCM_IDX_GPIOCR1, 10, /* STM_MOD_CMD0 */
912 false, 0, 0
913 ),
914 PRCM_GPIOCR_ALTCX(68, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */
915 false, 0, 0,
916 false, 0, 0,
917 false, 0, 0
918 ),
919 PRCM_GPIOCR_ALTCX(69, true, PRCM_IDX_GPIOCR1, 18, /* REMAP_SELECT_ON */
920 false, 0, 0,
921 false, 0, 0,
922 false, 0, 0
923 ),
924 PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D23 */
925 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
926 true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
927 true, PRCM_IDX_GPIOCR1, 8 /* SBAG_CLK */
928 ),
929 PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D22 */
930 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
931 true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
932 true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D3 */
933 ),
934 PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D21 */
935 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
936 true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
937 true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D2 */
938 ),
939 PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D20 */
940 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
941 true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
942 true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D1 */
943 ),
944 PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D19 */
945 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
946 true, PRCM_IDX_GPIOCR1, 11, /* STM_MOD_CMD1 */
947 true, PRCM_IDX_GPIOCR1, 8 /* SBAG_D0 */
948 ),
949 PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D18 */
950 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
951 true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */
952 false, 0, 0
953 ),
954 PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D17 */
955 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
956 true, PRCM_IDX_GPIOCR1, 0, /* DBG_UARTMOD_CMD0 */
957 false, 0, 0
958 ),
959 PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR1, 5, /* PTM_A9_D16 */
960 true, PRCM_IDX_GPIOCR2, 2, /* DBG_ETM_R4_CMD0 */
961 false, 0, 0,
962 true, PRCM_IDX_GPIOCR1, 8 /* SBAG_VAL */
963 ),
964 PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR1, 12, /* KP_O3 */
965 false, 0, 0,
966 false, 0, 0,
967 false, 0, 0
968 ),
969 PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR1, 12, /* KP_O2 */
970 false, 0, 0,
971 false, 0, 0,
972 false, 0, 0
973 ),
974 PRCM_GPIOCR_ALTCX(88, true, PRCM_IDX_GPIOCR1, 12, /* KP_I3 */
975 false, 0, 0,
976 false, 0, 0,
977 false, 0, 0
978 ),
979 PRCM_GPIOCR_ALTCX(89, true, PRCM_IDX_GPIOCR1, 12, /* KP_I2 */
980 false, 0, 0,
981 false, 0, 0,
982 false, 0, 0
983 ),
984 PRCM_GPIOCR_ALTCX(90, true, PRCM_IDX_GPIOCR1, 12, /* KP_O1 */
985 false, 0, 0,
986 false, 0, 0,
987 false, 0, 0
988 ),
989 PRCM_GPIOCR_ALTCX(91, true, PRCM_IDX_GPIOCR1, 12, /* KP_O0 */
990 false, 0, 0,
991 false, 0, 0,
992 false, 0, 0
993 ),
994 PRCM_GPIOCR_ALTCX(92, true, PRCM_IDX_GPIOCR1, 12, /* KP_I1 */
995 false, 0, 0,
996 false, 0, 0,
997 false, 0, 0
998 ),
999 PRCM_GPIOCR_ALTCX(93, true, PRCM_IDX_GPIOCR1, 12, /* KP_I0 */
1000 false, 0, 0,
1001 false, 0, 0,
1002 false, 0, 0
1003 ),
1004 PRCM_GPIOCR_ALTCX(96, true, PRCM_IDX_GPIOCR2, 3, /* RF_INT */
1005 false, 0, 0,
1006 false, 0, 0,
1007 false, 0, 0
1008 ),
1009 PRCM_GPIOCR_ALTCX(97, true, PRCM_IDX_GPIOCR2, 1, /* RF_CTRL */
1010 false, 0, 0,
1011 false, 0, 0,
1012 false, 0, 0
1013 ),
1014 PRCM_GPIOCR_ALTCX(151, false, 0, 0,
1015 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CTL */
1016 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1017 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS17 */
1018 ),
1019 PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 4, /* Hx_CLK */
1020 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_CLK */
1021 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1022 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS16 */
1023 ),
1024 PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */
1025 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D15 */
1026 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1027 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS15 */
1028 ),
1029 PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR1, 1, /* UARTMOD_CMD1 */
1030 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D14 */
1031 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1032 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS14 */
1033 ),
1034 PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
1035 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D13 */
1036 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1037 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS13 */
1038 ),
1039 PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
1040 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D12 */
1041 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1042 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS12 */
1043 ),
1044 PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
1045 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D11 */
1046 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1047 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS11 */
1048 ),
1049 PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
1050 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D10 */
1051 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1052 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS10 */
1053 ),
1054 PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR1, 13, /* STM_MOD_CMD2 */
1055 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D9 */
1056 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1057 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS9 */
1058 ),
1059 PRCM_GPIOCR_ALTCX(160, false, 0, 0,
1060 true, PRCM_IDX_GPIOCR1, 14, /* PTM_A9_D8 */
1061 true, PRCM_IDX_GPIOCR1, 19, /* DBG_ETM_R4_CMD2 */
1062 true, PRCM_IDX_GPIOCR1, 25 /* HW_OBS8 */
1063 ),
1064 PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO7 */
1065 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D7 */
1066 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1067 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS7 */
1068 ),
1069 PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO6 */
1070 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D6 */
1071 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1072 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS6 */
1073 ),
1074 PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO5 */
1075 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D5 */
1076 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1077 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS5 */
1078 ),
1079 PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO4 */
1080 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D4 */
1081 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1082 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS4 */
1083 ),
1084 PRCM_GPIOCR_ALTCX(165, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO3 */
1085 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D3 */
1086 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1087 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS3 */
1088 ),
1089 PRCM_GPIOCR_ALTCX(166, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO2 */
1090 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D2 */
1091 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1092 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS2 */
1093 ),
1094 PRCM_GPIOCR_ALTCX(167, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO1 */
1095 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D1 */
1096 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1097 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS1 */
1098 ),
1099 PRCM_GPIOCR_ALTCX(168, true, PRCM_IDX_GPIOCR1, 4, /* Hx_GPIO0 */
1100 true, PRCM_IDX_GPIOCR1, 6, /* PTM_A9_D0 */
1101 true, PRCM_IDX_GPIOCR1, 15, /* DBG_ETM_R4_CMD1*/
1102 true, PRCM_IDX_GPIOCR1, 24 /* HW_OBS0 */
1103 ),
1104 PRCM_GPIOCR_ALTCX(170, true, PRCM_IDX_GPIOCR2, 2, /* RF_INT */
1105 false, 0, 0,
1106 false, 0, 0,
1107 false, 0, 0
1108 ),
1109 PRCM_GPIOCR_ALTCX(171, true, PRCM_IDX_GPIOCR2, 0, /* RF_CTRL */
1110 false, 0, 0,
1111 false, 0, 0,
1112 false, 0, 0
1113 ),
1114 PRCM_GPIOCR_ALTCX(215, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_TXD */
1115 false, 0, 0,
1116 false, 0, 0,
1117 false, 0, 0
1118 ),
1119 PRCM_GPIOCR_ALTCX(216, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_FRM */
1120 false, 0, 0,
1121 false, 0, 0,
1122 false, 0, 0
1123 ),
1124 PRCM_GPIOCR_ALTCX(217, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_CLK */
1125 false, 0, 0,
1126 false, 0, 0,
1127 false, 0, 0
1128 ),
1129 PRCM_GPIOCR_ALTCX(218, true, PRCM_IDX_GPIOCR1, 23, /* SPI2_RXD */
1130 false, 0, 0,
1131 false, 0, 0,
1132 false, 0, 0
1133 ),
1134};
1135
1136static const u16 db8500_prcm_gpiocr_regs[] = {
1137 [PRCM_IDX_GPIOCR1] = 0x138,
1138 [PRCM_IDX_GPIOCR2] = 0x574,
1139};
1140
863static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { 1141static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
864 .gpio_ranges = nmk_db8500_ranges, 1142 .gpio_ranges = nmk_db8500_ranges,
865 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges), 1143 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
@@ -869,6 +1147,9 @@ static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
869 .nfunctions = ARRAY_SIZE(nmk_db8500_functions), 1147 .nfunctions = ARRAY_SIZE(nmk_db8500_functions),
870 .groups = nmk_db8500_groups, 1148 .groups = nmk_db8500_groups,
871 .ngroups = ARRAY_SIZE(nmk_db8500_groups), 1149 .ngroups = ARRAY_SIZE(nmk_db8500_groups),
1150 .altcx_pins = db8500_altcx_pins,
1151 .npins_altcx = ARRAY_SIZE(db8500_altcx_pins),
1152 .prcm_gpiocr_registers = db8500_prcm_gpiocr_regs,
872}; 1153};
873 1154
874void __devinit 1155void __devinit
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
index 3daf665c84c3..52fc30181f7e 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8540.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -778,50 +778,50 @@ static const struct nmk_pingroup nmk_db8540_groups[] = {
778 DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), 778 DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
779 DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), 779 DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
780 780
781 /* Other alt C1 column, these are still configured as alt C */ 781 /* Other alt C1 column */
782 DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C), 782 DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C1),
783 DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C), 783 DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1),
784 DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C), 784 DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C1),
785 DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C), 785 DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1),
786 DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C), 786 DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1),
787 DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C), 787 DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C1),
788 DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C), 788 DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C1),
789 DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C), 789 DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C1),
790 DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C), 790 DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C1),
791 DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C), 791 DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C1),
792 DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C), 792 DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C1),
793 DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C), 793 DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C1),
794 DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C), 794 DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
795 DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C), 795 DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C1),
796 DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C), 796 DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C1),
797 DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C), 797 DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C1),
798 DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C), 798 DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C1),
799 799
800 /* Other alt C2 column, these are still configured as alt C */ 800 /* Other alt C2 column */
801 DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C), 801 DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2),
802 DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C), 802 DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C2),
803 DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C), 803 DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C2),
804 DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C), 804 DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C2),
805 DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C), 805 DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C2),
806 DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C), 806 DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C2),
807 DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C), 807 DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C2),
808 DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C), 808 DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C2),
809 DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C), 809 DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C2),
810 DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C), 810 DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C2),
811 DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C), 811 DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C2),
812 DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C), 812 DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C2),
813 813
814 /* Other alt C3 column, these are still configured as alt C */ 814 /* Other alt C3 column */
815 DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C), 815 DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C3),
816 DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C), 816 DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C3),
817 817
818 /* Other alt C4 column, these are still configured as alt C */ 818 /* Other alt C4 column */
819 DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C), 819 DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4),
820 DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C), 820 DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C4),
821 DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C), 821 DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C4),
822 DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C), 822 DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C4),
823 DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C), 823 DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C4),
824 DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C), 824 DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C4),
825 825
826}; 826};
827 827
@@ -981,6 +981,265 @@ static const struct nmk_function nmk_db8540_functions[] = {
981 FUNCTION(usb) 981 FUNCTION(usb)
982}; 982};
983 983
984static const struct prcm_gpiocr_altcx_pin_desc db8540_altcx_pins[] = {
985 PRCM_GPIOCR_ALTCX(8, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_CLK */
986 false, 0, 0,
987 false, 0, 0,
988 false, 0, 0
989 ),
990 PRCM_GPIOCR_ALTCX(9, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_RXD */
991 false, 0, 0,
992 false, 0, 0,
993 false, 0, 0
994 ),
995 PRCM_GPIOCR_ALTCX(10, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_FRM */
996 false, 0, 0,
997 false, 0, 0,
998 false, 0, 0
999 ),
1000 PRCM_GPIOCR_ALTCX(11, true, PRCM_IDX_GPIOCR1, 20, /* SPI3_TXD */
1001 false, 0, 0,
1002 false, 0, 0,
1003 false, 0, 0
1004 ),
1005 PRCM_GPIOCR_ALTCX(23, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_CLK_a */
1006 true, PRCM_IDX_GPIOCR2, 10, /* SBAG_CLK_a */
1007 false, 0, 0,
1008 false, 0, 0
1009 ),
1010 PRCM_GPIOCR_ALTCX(24, true, PRCM_IDX_GPIOCR3, 30, /* U2_RXD_g */
1011 true, PRCM_IDX_GPIOCR2, 10, /* SBAG_VAL_a */
1012 false, 0, 0,
1013 false, 0, 0
1014 ),
1015 PRCM_GPIOCR_ALTCX(25, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[0] */
1016 true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[0] */
1017 false, 0, 0,
1018 false, 0, 0
1019 ),
1020 PRCM_GPIOCR_ALTCX(26, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[1] */
1021 true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[1] */
1022 false, 0, 0,
1023 false, 0, 0
1024 ),
1025 PRCM_GPIOCR_ALTCX(27, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[2] */
1026 true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[2] */
1027 false, 0, 0,
1028 false, 0, 0
1029 ),
1030 PRCM_GPIOCR_ALTCX(28, true, PRCM_IDX_GPIOCR1, 9, /* STMAPE_DAT_a[3] */
1031 true, PRCM_IDX_GPIOCR2, 10, /* SBAG_D_a[3] */
1032 false, 0, 0,
1033 false, 0, 0
1034 ),
1035 PRCM_GPIOCR_ALTCX(64, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_REFCLK_REQ */
1036 false, 0, 0,
1037 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CTL */
1038 true, PRCM_IDX_GPIOCR2, 23 /* HW_OBS_APE_PRCMU[17] */
1039 ),
1040 PRCM_GPIOCR_ALTCX(65, true, PRCM_IDX_GPIOCR1, 19, /* MODOBS_PWRCTRL0 */
1041 true, PRCM_IDX_GPIOCR1, 24, /* Hx_CLK */
1042 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_CLK */
1043 true, PRCM_IDX_GPIOCR2, 24 /* HW_OBS_APE_PRCMU[16] */
1044 ),
1045 PRCM_GPIOCR_ALTCX(66, true, PRCM_IDX_GPIOCR1, 15, /* MODOBS_CLKOUT1 */
1046 false, 0, 0,
1047 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[15] */
1048 true, PRCM_IDX_GPIOCR2, 25 /* HW_OBS_APE_PRCMU[15] */
1049 ),
1050 PRCM_GPIOCR_ALTCX(67, true, PRCM_IDX_GPIOCR1, 1, /* MODUART1_TXD_a */
1051 true, PRCM_IDX_GPIOCR1, 6, /* MODACCUART_TXD_a */
1052 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[14] */
1053 true, PRCM_IDX_GPIOCR2, 26 /* HW_OBS_APE_PRCMU[14] */
1054 ),
1055 PRCM_GPIOCR_ALTCX(70, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[17] */
1056 true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_CLK_b */
1057 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[13] */
1058 true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[13] */
1059 ),
1060 PRCM_GPIOCR_ALTCX(71, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[16] */
1061 true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[3] */
1062 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[12] */
1063 true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[12] */
1064 ),
1065 PRCM_GPIOCR_ALTCX(72, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[15] */
1066 true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[2] */
1067 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[11] */
1068 true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[11] */
1069 ),
1070 PRCM_GPIOCR_ALTCX(73, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[14] */
1071 true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[1] */
1072 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[10] */
1073 true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[10] */
1074 ),
1075 PRCM_GPIOCR_ALTCX(74, true, PRCM_IDX_GPIOCR3, 6, /* MOD_PRCMU_DEBUG[13] */
1076 true, PRCM_IDX_GPIOCR1, 10, /* STMMOD_DAT_b[0] */
1077 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[9] */
1078 true, PRCM_IDX_GPIOCR2, 27 /* HW_OBS_APE_PRCMU[9] */
1079 ),
1080 PRCM_GPIOCR_ALTCX(75, true, PRCM_IDX_GPIOCR1, 12, /* MODOBS_RESOUT0_N */
1081 true, PRCM_IDX_GPIOCR2, 1, /* MODUART_STMMUX_RXD_b */
1082 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[8] */
1083 true, PRCM_IDX_GPIOCR2, 28 /* HW_OBS_APE_PRCMU[8] */
1084 ),
1085 PRCM_GPIOCR_ALTCX(76, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[12] */
1086 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[7] */
1087 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[7] */
1088 true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[7] */
1089 ),
1090 PRCM_GPIOCR_ALTCX(77, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[11] */
1091 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[6] */
1092 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[6] */
1093 true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[6] */
1094 ),
1095 PRCM_GPIOCR_ALTCX(78, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[10] */
1096 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[5] */
1097 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[5] */
1098 true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[5] */
1099 ),
1100 PRCM_GPIOCR_ALTCX(79, true, PRCM_IDX_GPIOCR3, 7, /* MOD_PRCMU_DEBUG[9] */
1101 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[4] */
1102 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[4] */
1103 true, PRCM_IDX_GPIOCR2, 29 /* HW_OBS_APE_PRCMU[4] */
1104 ),
1105 PRCM_GPIOCR_ALTCX(80, true, PRCM_IDX_GPIOCR1, 26, /* MODACC_GPO[0] */
1106 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[3] */
1107 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[3] */
1108 true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[3] */
1109 ),
1110 PRCM_GPIOCR_ALTCX(81, true, PRCM_IDX_GPIOCR2, 17, /* MODACC_GPO[1] */
1111 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[2] */
1112 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[2] */
1113 true, PRCM_IDX_GPIOCR2, 30 /* HW_OBS_APE_PRCMU[2] */
1114 ),
1115 PRCM_GPIOCR_ALTCX(82, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[8] */
1116 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[1] */
1117 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[1] */
1118 true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[1] */
1119 ),
1120 PRCM_GPIOCR_ALTCX(83, true, PRCM_IDX_GPIOCR3, 8, /* MOD_PRCMU_DEBUG[7] */
1121 true, PRCM_IDX_GPIOCR1, 25, /* Hx_GPIO[0] */
1122 true, PRCM_IDX_GPIOCR1, 2, /* TPIU_D[0] */
1123 true, PRCM_IDX_GPIOCR2, 31 /* HW_OBS_APE_PRCMU[0] */
1124 ),
1125 PRCM_GPIOCR_ALTCX(84, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[6] */
1126 true, PRCM_IDX_GPIOCR1, 8, /* SBAG_CLK_b */
1127 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[23] */
1128 true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_RXD_b */
1129 ),
1130 PRCM_GPIOCR_ALTCX(85, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[5] */
1131 true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[3] */
1132 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[22] */
1133 true, PRCM_IDX_GPIOCR1, 16 /* MODUART1_TXD_b */
1134 ),
1135 PRCM_GPIOCR_ALTCX(86, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[0] */
1136 true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[0] */
1137 true, PRCM_IDX_GPIOCR1, 14, /* TPIU_D[25] */
1138 true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[0] */
1139 ),
1140 PRCM_GPIOCR_ALTCX(87, true, PRCM_IDX_GPIOCR3, 0, /* MODACC_GPO_a[5] */
1141 true, PRCM_IDX_GPIOCR2, 3, /* U2_RXD_c */
1142 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[24] */
1143 true, PRCM_IDX_GPIOCR1, 21 /* MODUART_STMMUX_RXD_c */
1144 ),
1145 PRCM_GPIOCR_ALTCX(151, true, PRCM_IDX_GPIOCR1, 18, /* REMAP0 */
1146 false, 0, 0,
1147 false, 0, 0,
1148 false, 0, 0
1149 ),
1150 PRCM_GPIOCR_ALTCX(152, true, PRCM_IDX_GPIOCR1, 18, /* REMAP1 */
1151 false, 0, 0,
1152 false, 0, 0,
1153 false, 0, 0
1154 ),
1155 PRCM_GPIOCR_ALTCX(153, true, PRCM_IDX_GPIOCR3, 2, /* KP_O_b[6] */
1156 true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[2] */
1157 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[21] */
1158 true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_RTS */
1159 ),
1160 PRCM_GPIOCR_ALTCX(154, true, PRCM_IDX_GPIOCR3, 2, /* KP_I_b[6] */
1161 true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[1] */
1162 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[20] */
1163 true, PRCM_IDX_GPIOCR1, 0 /* MODUART1_CTS */
1164 ),
1165 PRCM_GPIOCR_ALTCX(155, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[5] */
1166 true, PRCM_IDX_GPIOCR1, 8, /* SBAG_D_b[0] */
1167 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[19] */
1168 true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_RXD_c */
1169 ),
1170 PRCM_GPIOCR_ALTCX(156, true, PRCM_IDX_GPIOCR3, 3, /* KP_O_b[4] */
1171 true, PRCM_IDX_GPIOCR1, 8, /* SBAG_VAL_b */
1172 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[18] */
1173 true, PRCM_IDX_GPIOCR1, 5 /* MODACCUART_TXD_b */
1174 ),
1175 PRCM_GPIOCR_ALTCX(157, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[5] */
1176 true, PRCM_IDX_GPIOCR1, 23, /* MODOBS_SERVICE_N */
1177 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[17] */
1178 true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_RTS */
1179 ),
1180 PRCM_GPIOCR_ALTCX(158, true, PRCM_IDX_GPIOCR3, 4, /* KP_I_b[4] */
1181 true, PRCM_IDX_GPIOCR2, 0, /* U2_TXD_c */
1182 true, PRCM_IDX_GPIOCR1, 3, /* TPIU_D[16] */
1183 true, PRCM_IDX_GPIOCR1, 14 /* MODACCUART_CTS */
1184 ),
1185 PRCM_GPIOCR_ALTCX(159, true, PRCM_IDX_GPIOCR3, 5, /* KP_O_b[3] */
1186 true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_RXD */
1187 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[31] */
1188 false, 0, 0
1189 ),
1190 PRCM_GPIOCR_ALTCX(160, true, PRCM_IDX_GPIOCR3, 5, /* KP_I_b[3] */
1191 true, PRCM_IDX_GPIOCR3, 10, /* MODUART0_TXD */
1192 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[30] */
1193 false, 0, 0
1194 ),
1195 PRCM_GPIOCR_ALTCX(161, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[4] */
1196 true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_CLK_b */
1197 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[29] */
1198 true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_CLK_c */
1199 ),
1200 PRCM_GPIOCR_ALTCX(162, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[3] */
1201 true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[3] */
1202 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[28] */
1203 true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[3] */
1204 ),
1205 PRCM_GPIOCR_ALTCX(163, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[2] */
1206 true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[2] */
1207 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[27] */
1208 true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[2] */
1209 ),
1210 PRCM_GPIOCR_ALTCX(164, true, PRCM_IDX_GPIOCR3, 9, /* MOD_PRCMU_DEBUG[1] */
1211 true, PRCM_IDX_GPIOCR2, 18, /* STMAPE_DAT_b[1] */
1212 true, PRCM_IDX_GPIOCR1, 4, /* TPIU_D[26] */
1213 true, PRCM_IDX_GPIOCR1, 11 /* STMMOD_DAT_c[1] */
1214 ),
1215 PRCM_GPIOCR_ALTCX(204, true, PRCM_IDX_GPIOCR2, 2, /* U2_RXD_f */
1216 false, 0, 0,
1217 false, 0, 0,
1218 false, 0, 0
1219 ),
1220 PRCM_GPIOCR_ALTCX(205, true, PRCM_IDX_GPIOCR2, 2, /* U2_TXD_f */
1221 false, 0, 0,
1222 false, 0, 0,
1223 false, 0, 0
1224 ),
1225 PRCM_GPIOCR_ALTCX(206, true, PRCM_IDX_GPIOCR2, 2, /* U2_CTSn_b */
1226 false, 0, 0,
1227 false, 0, 0,
1228 false, 0, 0
1229 ),
1230 PRCM_GPIOCR_ALTCX(207, true, PRCM_IDX_GPIOCR2, 2, /* U2_RTSn_b */
1231 false, 0, 0,
1232 false, 0, 0,
1233 false, 0, 0
1234 ),
1235};
1236
1237static const u16 db8540_prcm_gpiocr_regs[] = {
1238 [PRCM_IDX_GPIOCR1] = 0x138,
1239 [PRCM_IDX_GPIOCR2] = 0x574,
1240 [PRCM_IDX_GPIOCR3] = 0x2bc,
1241};
1242
984static const struct nmk_pinctrl_soc_data nmk_db8540_soc = { 1243static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
985 .gpio_ranges = nmk_db8540_ranges, 1244 .gpio_ranges = nmk_db8540_ranges,
986 .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges), 1245 .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
@@ -990,6 +1249,9 @@ static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
990 .nfunctions = ARRAY_SIZE(nmk_db8540_functions), 1249 .nfunctions = ARRAY_SIZE(nmk_db8540_functions),
991 .groups = nmk_db8540_groups, 1250 .groups = nmk_db8540_groups,
992 .ngroups = ARRAY_SIZE(nmk_db8540_groups), 1251 .ngroups = ARRAY_SIZE(nmk_db8540_groups),
1252 .altcx_pins = db8540_altcx_pins,
1253 .npins_altcx = ARRAY_SIZE(db8540_altcx_pins),
1254 .prcm_gpiocr_registers = db8540_prcm_gpiocr_regs,
993}; 1255};
994 1256
995void __devinit 1257void __devinit
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 6030a513f3c4..67a5ef637ea7 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -30,6 +30,7 @@
30#include <linux/pinctrl/pinconf.h> 30#include <linux/pinctrl/pinconf.h>
31/* Since we request GPIOs from ourself */ 31/* Since we request GPIOs from ourself */
32#include <linux/pinctrl/consumer.h> 32#include <linux/pinctrl/consumer.h>
33#include <linux/mfd/dbx500-prcmu.h>
33 34
34#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
35 36
@@ -237,6 +238,89 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
237 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); 238 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
238} 239}
239 240
241static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
242 unsigned offset, unsigned alt_num)
243{
244 int i;
245 u16 reg;
246 u8 bit;
247 u8 alt_index;
248 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
249 const u16 *gpiocr_regs;
250
251 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
252 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
253 alt_num);
254 return;
255 }
256
257 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
258 if (npct->soc->altcx_pins[i].pin == offset)
259 break;
260 }
261 if (i == npct->soc->npins_altcx) {
262 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
263 offset);
264 return;
265 }
266
267 pin_desc = npct->soc->altcx_pins + i;
268 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
269
270 /*
271 * If alt_num is NULL, just clear current ALTCx selection
272 * to make sure we come back to a pure ALTC selection
273 */
274 if (!alt_num) {
275 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
276 if (pin_desc->altcx[i].used == true) {
277 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
278 bit = pin_desc->altcx[i].control_bit;
279 if (prcmu_read(reg) & BIT(bit)) {
280 prcmu_write_masked(reg, BIT(bit), 0);
281 dev_dbg(npct->dev,
282 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
283 offset, i+1);
284 }
285 }
286 }
287 return;
288 }
289
290 alt_index = alt_num - 1;
291 if (pin_desc->altcx[alt_index].used == false) {
292 dev_warn(npct->dev,
293 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
294 offset, alt_num);
295 return;
296 }
297
298 /*
299 * Check if any other ALTCx functions are activated on this pin
300 * and disable it first.
301 */
302 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
303 if (i == alt_index)
304 continue;
305 if (pin_desc->altcx[i].used == true) {
306 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
307 bit = pin_desc->altcx[i].control_bit;
308 if (prcmu_read(reg) & BIT(bit)) {
309 prcmu_write_masked(reg, BIT(bit), 0);
310 dev_dbg(npct->dev,
311 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
312 offset, i+1);
313 }
314 }
315 }
316
317 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
318 bit = pin_desc->altcx[alt_index].control_bit;
319 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
320 offset, alt_index+1);
321 prcmu_write_masked(reg, BIT(bit), BIT(bit));
322}
323
240static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, 324static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
241 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) 325 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
242{ 326{
@@ -1441,7 +1525,7 @@ static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1441 * IOFORCE will switch *all* ports to their sleepmode setting to as 1525 * IOFORCE will switch *all* ports to their sleepmode setting to as
1442 * to avoid glitches. (Not just one port!) 1526 * to avoid glitches. (Not just one port!)
1443 */ 1527 */
1444 glitch = (g->altsetting == NMK_GPIO_ALT_C); 1528 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1445 1529
1446 if (glitch) { 1530 if (glitch) {
1447 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1531 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
@@ -1491,8 +1575,21 @@ static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1491 */ 1575 */
1492 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1576 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1493 1577
1494 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch); 1578 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1579 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1495 clk_disable(nmk_chip->clk); 1580 clk_disable(nmk_chip->clk);
1581
1582 /*
1583 * Call PRCM GPIOCR config function in case ALTC
1584 * has been selected:
1585 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1586 * must be set.
1587 * - If selection is pure ALTC and previous selection was ALTCx,
1588 * then some bits in PRCM GPIOCR registers must be cleared.
1589 */
1590 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1591 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1592 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1496 } 1593 }
1497 1594
1498 /* When all pins are successfully reconfigured we get here */ 1595 /* When all pins are successfully reconfigured we get here */
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index 5c99f1c62dfd..eef316e979a0 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -8,6 +8,78 @@
8#define PINCTRL_NMK_DB8500 1 8#define PINCTRL_NMK_DB8500 1
9#define PINCTRL_NMK_DB8540 2 9#define PINCTRL_NMK_DB8540 2
10 10
11#define PRCM_GPIOCR_ALTCX(pin_num,\
12 altc1_used, altc1_ri, altc1_cb,\
13 altc2_used, altc2_ri, altc2_cb,\
14 altc3_used, altc3_ri, altc3_cb,\
15 altc4_used, altc4_ri, altc4_cb)\
16{\
17 .pin = pin_num,\
18 .altcx[PRCM_IDX_GPIOCR_ALTC1] = {\
19 .used = altc1_used,\
20 .reg_index = altc1_ri,\
21 .control_bit = altc1_cb\
22 },\
23 .altcx[PRCM_IDX_GPIOCR_ALTC2] = {\
24 .used = altc2_used,\
25 .reg_index = altc2_ri,\
26 .control_bit = altc2_cb\
27 },\
28 .altcx[PRCM_IDX_GPIOCR_ALTC3] = {\
29 .used = altc3_used,\
30 .reg_index = altc3_ri,\
31 .control_bit = altc3_cb\
32 },\
33 .altcx[PRCM_IDX_GPIOCR_ALTC4] = {\
34 .used = altc4_used,\
35 .reg_index = altc4_ri,\
36 .control_bit = altc4_cb\
37 },\
38}
39
40/**
41 * enum prcm_gpiocr_reg_index
42 * Used to reference an PRCM GPIOCR register address.
43 */
44enum prcm_gpiocr_reg_index {
45 PRCM_IDX_GPIOCR1,
46 PRCM_IDX_GPIOCR2,
47 PRCM_IDX_GPIOCR3
48};
49/**
50 * enum prcm_gpiocr_altcx_index
51 * Used to reference an Other alternate-C function.
52 */
53enum prcm_gpiocr_altcx_index {
54 PRCM_IDX_GPIOCR_ALTC1,
55 PRCM_IDX_GPIOCR_ALTC2,
56 PRCM_IDX_GPIOCR_ALTC3,
57 PRCM_IDX_GPIOCR_ALTC4,
58 PRCM_IDX_GPIOCR_ALTC_MAX,
59};
60
61/**
62 * struct prcm_gpio_altcx - Other alternate-C function
63 * @used: other alternate-C function availability
64 * @reg_index: PRCM GPIOCR register index used to control the function
65 * @control_bit: PRCM GPIOCR bit used to control the function
66 */
67struct prcm_gpiocr_altcx {
68 bool used:1;
69 u8 reg_index:2;
70 u8 control_bit:5;
71} __packed;
72
73/**
74 * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
75 * @pin: The pin number
76 * @altcx: array of other alternate-C[1-4] functions
77 */
78struct prcm_gpiocr_altcx_pin_desc {
79 unsigned short pin;
80 struct prcm_gpiocr_altcx altcx[PRCM_IDX_GPIOCR_ALTC_MAX];
81};
82
11/** 83/**
12 * struct nmk_function - Nomadik pinctrl mux function 84 * struct nmk_function - Nomadik pinctrl mux function
13 * @name: The name of the function, exported to pinctrl core. 85 * @name: The name of the function, exported to pinctrl core.
@@ -50,6 +122,9 @@ struct nmk_pingroup {
50 * @nfunction: The number of entries in @functions. 122 * @nfunction: The number of entries in @functions.
51 * @groups: An array describing all pin groups the pin SoC supports. 123 * @groups: An array describing all pin groups the pin SoC supports.
52 * @ngroups: The number of entries in @groups. 124 * @ngroups: The number of entries in @groups.
125 * @altcx_pins: The pins that support Other alternate-C function on this SoC
126 * @npins_altcx: The number of Other alternate-C pins
127 * @prcm_gpiocr_registers: The array of PRCM GPIOCR registers on this SoC
53 */ 128 */
54struct nmk_pinctrl_soc_data { 129struct nmk_pinctrl_soc_data {
55 struct pinctrl_gpio_range *gpio_ranges; 130 struct pinctrl_gpio_range *gpio_ranges;
@@ -60,6 +135,9 @@ struct nmk_pinctrl_soc_data {
60 unsigned nfunctions; 135 unsigned nfunctions;
61 const struct nmk_pingroup *groups; 136 const struct nmk_pingroup *groups;
62 unsigned ngroups; 137 unsigned ngroups;
138 const struct prcm_gpiocr_altcx_pin_desc *altcx_pins;
139 unsigned npins_altcx;
140 const u16 *prcm_gpiocr_registers;
63}; 141};
64 142
65#ifdef CONFIG_PINCTRL_STN8815 143#ifdef CONFIG_PINCTRL_STN8815
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 17:59:22 -0500