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authorMagnus Damm <damm@opensource.se>2013-03-26 09:50:27 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-04-02 21:30:39 -0400
commit57ef73b469e7e6f7d15e5467649c787bc7070819 (patch)
treeeb6f05af744340187a6ead03ddf4a79440818289 /drivers/pinctrl
parentc96931ca88b583a2d7c8bb02a33871c982bd5b68 (diff)
sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
Implement pull-up/down support for r8a73a4 similar to the implementation for sh73a0. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c197
1 files changed, 196 insertions, 1 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 01773291ea91..86a5fd33a479 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -17,10 +17,13 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20#include <linux/io.h>
20#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/pinctrl/pinconf-generic.h>
21#include <mach/irqs.h> 23#include <mach/irqs.h>
22#include <mach/r8a73a4.h> 24#include <mach/r8a73a4.h>
23 25
26#include "core.h"
24#include "sh_pfc.h" 27#include "sh_pfc.h"
25 28
26#define CPU_ALL_PORT(fn, pfx, sfx) \ 29#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -1420,8 +1423,143 @@ static const pinmux_enum_t pinmux_data[] = {
1420 PINMUX_DATA(IRQ57_MARK, PORT329_FN0), 1423 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1421}; 1424};
1422 1425
1426#define R8A73A4_PIN(pin, cfgs) \
1427 { \
1428 .name = __stringify(PORT##pin), \
1429 .enum_id = PORT##pin##_DATA, \
1430 .configs = cfgs, \
1431 }
1432
1433#define __O (SH_PFC_PIN_CFG_OUTPUT)
1434#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1435#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1436
1437#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1438#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1439
1423static struct sh_pfc_pin pinmux_pins[] = { 1440static struct sh_pfc_pin pinmux_pins[] = {
1424 GPIO_PORT_ALL(), 1441 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1442 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1443 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1444 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1445 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1446 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1447 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1448 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1449 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1450 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1451 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1452 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1453 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1454 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1455 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1456 R8A73A4_PIN_IO_PU_PD(30),
1457 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1458 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1459 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1460 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1461 R8A73A4_PIN_IO_PU_PD(40),
1462 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1463 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1464 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1465 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1466 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1467 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1468 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1469 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1470 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1471 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1472 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1473 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1474 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1475 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1476 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1477 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1478 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1479 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1480 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1481 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1482 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1483 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1484 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1485 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1486 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1487 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1488 R8A73A4_PIN_IO_PU_PD(126),
1489 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1490 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1491 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1492 R8A73A4_PIN_IO_PU_PD(134),
1493 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1494 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1495 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1496 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1497 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1498 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1499 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1500 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1501 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1502 R8A73A4_PIN_IO_PU_PD(178),
1503 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1504 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1505 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1506 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1507 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1508 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1509 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1510 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1511 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1512 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1513 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1514 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1515 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1516 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1517 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1518 R8A73A4_PIN_IO_PU_PD(222),
1519 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1520 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1521 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1522 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1523 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1524 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1525 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1526 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1527 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1528 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1529 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1530 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1531 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1532 R8A73A4_PIN_IO_PU_PD(250),
1533 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1534 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1535 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1536 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1537 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1538 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1539 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1540 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1541 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1542 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1543 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1544 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1545 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1546 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1547 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1548 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1549 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1550 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1551 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1552 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1553 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1554 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1555 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1556 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1557 R8A73A4_PIN_IO_PU_PD(308),
1558 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1559 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1560 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1561 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1562 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1425}; 1563};
1426 1564
1427static const struct pinmux_range pinmux_ranges[] = { 1565static const struct pinmux_range pinmux_ranges[] = {
@@ -2878,8 +3016,65 @@ static const struct pinmux_irq pinmux_irqs[] = {
2878 PINMUX_IRQ(irq_pin(56), 328), 3016 PINMUX_IRQ(irq_pin(56), 328),
2879 PINMUX_IRQ(irq_pin(57), 329), 3017 PINMUX_IRQ(irq_pin(57), 329),
2880}; 3018};
3019
3020#define PORTCR_PULMD_OFF (0 << 6)
3021#define PORTCR_PULMD_DOWN (2 << 6)
3022#define PORTCR_PULMD_UP (3 << 6)
3023#define PORTCR_PULMD_MASK (3 << 6)
3024
3025static const unsigned int r8a73a4_portcr_offsets[] = {
3026 0x00000000, 0x00001000, 0x00000000, 0x00001000,
3027 0x00001000, 0x00002000, 0x00002000, 0x00002000,
3028 0x00002000, 0x00003000, 0x00003000,
3029};
3030
3031static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
3032 unsigned int pin)
3033{
3034 void __iomem *addr;
3035
3036 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
3037
3038 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
3039 case PORTCR_PULMD_UP:
3040 return PIN_CONFIG_BIAS_PULL_UP;
3041 case PORTCR_PULMD_DOWN:
3042 return PIN_CONFIG_BIAS_PULL_DOWN;
3043 case PORTCR_PULMD_OFF:
3044 default:
3045 return PIN_CONFIG_BIAS_DISABLE;
3046 }
3047}
3048
3049static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3050 unsigned int bias)
3051{
3052 void __iomem *addr;
3053 u32 value;
3054
3055 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
3056 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
3057
3058 switch (bias) {
3059 case PIN_CONFIG_BIAS_PULL_UP:
3060 value |= PORTCR_PULMD_UP;
3061 break;
3062 case PIN_CONFIG_BIAS_PULL_DOWN:
3063 value |= PORTCR_PULMD_DOWN;
3064 break;
3065 }
3066
3067 iowrite8(value, addr);
3068}
3069
3070static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
3071 .get_bias = r8a73a4_pinmux_get_bias,
3072 .set_bias = r8a73a4_pinmux_set_bias,
3073};
3074
2881const struct sh_pfc_soc_info r8a73a4_pinmux_info = { 3075const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2882 .name = "r8a73a4_pfc", 3076 .name = "r8a73a4_pfc",
3077 .ops = &r8a73a4_pinmux_ops,
2883 3078
2884 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 3079 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2885 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 3080 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 23:16:18 -0500