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authorShawn Guo <shawn.guo@linaro.org>2012-04-28 01:00:50 -0400
committerLinus Walleij <linus.walleij@linaro.org>2012-05-01 19:18:27 -0400
commit17723111e64fbcc327846ff0b33532bcf1d40f56 (patch)
tree08b6f0609a59dab9f47a59ee339c54b4170405b2 /drivers/pinctrl
parentd8fe35727a3c7e0f2c4ff0a579aab1d7ce252df8 (diff)
pinctrl: add pinctrl-mxs support
Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28. The driver supports device tree probe only. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig15
-rw-r--r--drivers/pinctrl/Makefile3
-rw-r--r--drivers/pinctrl/pinctrl-imx23.c305
-rw-r--r--drivers/pinctrl/pinctrl-imx28.c421
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c508
-rw-r--r--drivers/pinctrl/pinctrl-mxs.h91
6 files changed, 1343 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 40d78aa5bca2..73f2fd66d658 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -49,6 +49,21 @@ config PINCTRL_MMP2
49 select PINCTRL_PXA3xx 49 select PINCTRL_PXA3xx
50 select PINCONF 50 select PINCONF
51 51
52config PINCTRL_MXS
53 bool
54
55config PINCTRL_IMX23
56 bool
57 select PINMUX
58 select PINCONF
59 select PINCTRL_MXS
60
61config PINCTRL_IMX28
62 bool
63 select PINMUX
64 select PINCONF
65 select PINCTRL_MXS
66
52config PINCTRL_PXA168 67config PINCTRL_PXA168
53 bool "PXA168 pin controller driver" 68 bool "PXA168 pin controller driver"
54 depends on ARCH_MMP 69 depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 133261d821a3..5f5a0a6414a5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -13,6 +13,9 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
13obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 13obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
14obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o 14obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
15obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o 15obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
16obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 19obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
17obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 20obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
18obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 21obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
new file mode 100644
index 000000000000..75d3eff94296
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -0,0 +1,305 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx23_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_D08 = PINID(0, 8),
28 GPMI_D09 = PINID(0, 9),
29 GPMI_D10 = PINID(0, 10),
30 GPMI_D11 = PINID(0, 11),
31 GPMI_D12 = PINID(0, 12),
32 GPMI_D13 = PINID(0, 13),
33 GPMI_D14 = PINID(0, 14),
34 GPMI_D15 = PINID(0, 15),
35 GPMI_CLE = PINID(0, 16),
36 GPMI_ALE = PINID(0, 17),
37 GPMI_CE2N = PINID(0, 18),
38 GPMI_RDY0 = PINID(0, 19),
39 GPMI_RDY1 = PINID(0, 20),
40 GPMI_RDY2 = PINID(0, 21),
41 GPMI_RDY3 = PINID(0, 22),
42 GPMI_WPN = PINID(0, 23),
43 GPMI_WRN = PINID(0, 24),
44 GPMI_RDN = PINID(0, 25),
45 AUART1_CTS = PINID(0, 26),
46 AUART1_RTS = PINID(0, 27),
47 AUART1_RX = PINID(0, 28),
48 AUART1_TX = PINID(0, 29),
49 I2C_SCL = PINID(0, 30),
50 I2C_SDA = PINID(0, 31),
51 LCD_D00 = PINID(1, 0),
52 LCD_D01 = PINID(1, 1),
53 LCD_D02 = PINID(1, 2),
54 LCD_D03 = PINID(1, 3),
55 LCD_D04 = PINID(1, 4),
56 LCD_D05 = PINID(1, 5),
57 LCD_D06 = PINID(1, 6),
58 LCD_D07 = PINID(1, 7),
59 LCD_D08 = PINID(1, 8),
60 LCD_D09 = PINID(1, 9),
61 LCD_D10 = PINID(1, 10),
62 LCD_D11 = PINID(1, 11),
63 LCD_D12 = PINID(1, 12),
64 LCD_D13 = PINID(1, 13),
65 LCD_D14 = PINID(1, 14),
66 LCD_D15 = PINID(1, 15),
67 LCD_D16 = PINID(1, 16),
68 LCD_D17 = PINID(1, 17),
69 LCD_RESET = PINID(1, 18),
70 LCD_RS = PINID(1, 19),
71 LCD_WR = PINID(1, 20),
72 LCD_CS = PINID(1, 21),
73 LCD_DOTCK = PINID(1, 22),
74 LCD_ENABLE = PINID(1, 23),
75 LCD_HSYNC = PINID(1, 24),
76 LCD_VSYNC = PINID(1, 25),
77 PWM0 = PINID(1, 26),
78 PWM1 = PINID(1, 27),
79 PWM2 = PINID(1, 28),
80 PWM3 = PINID(1, 29),
81 PWM4 = PINID(1, 30),
82 SSP1_CMD = PINID(2, 0),
83 SSP1_DETECT = PINID(2, 1),
84 SSP1_DATA0 = PINID(2, 2),
85 SSP1_DATA1 = PINID(2, 3),
86 SSP1_DATA2 = PINID(2, 4),
87 SSP1_DATA3 = PINID(2, 5),
88 SSP1_SCK = PINID(2, 6),
89 ROTARYA = PINID(2, 7),
90 ROTARYB = PINID(2, 8),
91 EMI_A00 = PINID(2, 9),
92 EMI_A01 = PINID(2, 10),
93 EMI_A02 = PINID(2, 11),
94 EMI_A03 = PINID(2, 12),
95 EMI_A04 = PINID(2, 13),
96 EMI_A05 = PINID(2, 14),
97 EMI_A06 = PINID(2, 15),
98 EMI_A07 = PINID(2, 16),
99 EMI_A08 = PINID(2, 17),
100 EMI_A09 = PINID(2, 18),
101 EMI_A10 = PINID(2, 19),
102 EMI_A11 = PINID(2, 20),
103 EMI_A12 = PINID(2, 21),
104 EMI_BA0 = PINID(2, 22),
105 EMI_BA1 = PINID(2, 23),
106 EMI_CASN = PINID(2, 24),
107 EMI_CE0N = PINID(2, 25),
108 EMI_CE1N = PINID(2, 26),
109 GPMI_CE1N = PINID(2, 27),
110 GPMI_CE0N = PINID(2, 28),
111 EMI_CKE = PINID(2, 29),
112 EMI_RASN = PINID(2, 30),
113 EMI_WEN = PINID(2, 31),
114 EMI_D00 = PINID(3, 0),
115 EMI_D01 = PINID(3, 1),
116 EMI_D02 = PINID(3, 2),
117 EMI_D03 = PINID(3, 3),
118 EMI_D04 = PINID(3, 4),
119 EMI_D05 = PINID(3, 5),
120 EMI_D06 = PINID(3, 6),
121 EMI_D07 = PINID(3, 7),
122 EMI_D08 = PINID(3, 8),
123 EMI_D09 = PINID(3, 9),
124 EMI_D10 = PINID(3, 10),
125 EMI_D11 = PINID(3, 11),
126 EMI_D12 = PINID(3, 12),
127 EMI_D13 = PINID(3, 13),
128 EMI_D14 = PINID(3, 14),
129 EMI_D15 = PINID(3, 15),
130 EMI_DQM0 = PINID(3, 16),
131 EMI_DQM1 = PINID(3, 17),
132 EMI_DQS0 = PINID(3, 18),
133 EMI_DQS1 = PINID(3, 19),
134 EMI_CLK = PINID(3, 20),
135 EMI_CLKN = PINID(3, 21),
136};
137
138static const struct pinctrl_pin_desc imx23_pins[] = {
139 MXS_PINCTRL_PIN(GPMI_D00),
140 MXS_PINCTRL_PIN(GPMI_D01),
141 MXS_PINCTRL_PIN(GPMI_D02),
142 MXS_PINCTRL_PIN(GPMI_D03),
143 MXS_PINCTRL_PIN(GPMI_D04),
144 MXS_PINCTRL_PIN(GPMI_D05),
145 MXS_PINCTRL_PIN(GPMI_D06),
146 MXS_PINCTRL_PIN(GPMI_D07),
147 MXS_PINCTRL_PIN(GPMI_D08),
148 MXS_PINCTRL_PIN(GPMI_D09),
149 MXS_PINCTRL_PIN(GPMI_D10),
150 MXS_PINCTRL_PIN(GPMI_D11),
151 MXS_PINCTRL_PIN(GPMI_D12),
152 MXS_PINCTRL_PIN(GPMI_D13),
153 MXS_PINCTRL_PIN(GPMI_D14),
154 MXS_PINCTRL_PIN(GPMI_D15),
155 MXS_PINCTRL_PIN(GPMI_CLE),
156 MXS_PINCTRL_PIN(GPMI_ALE),
157 MXS_PINCTRL_PIN(GPMI_CE2N),
158 MXS_PINCTRL_PIN(GPMI_RDY0),
159 MXS_PINCTRL_PIN(GPMI_RDY1),
160 MXS_PINCTRL_PIN(GPMI_RDY2),
161 MXS_PINCTRL_PIN(GPMI_RDY3),
162 MXS_PINCTRL_PIN(GPMI_WPN),
163 MXS_PINCTRL_PIN(GPMI_WRN),
164 MXS_PINCTRL_PIN(GPMI_RDN),
165 MXS_PINCTRL_PIN(AUART1_CTS),
166 MXS_PINCTRL_PIN(AUART1_RTS),
167 MXS_PINCTRL_PIN(AUART1_RX),
168 MXS_PINCTRL_PIN(AUART1_TX),
169 MXS_PINCTRL_PIN(I2C_SCL),
170 MXS_PINCTRL_PIN(I2C_SDA),
171 MXS_PINCTRL_PIN(LCD_D00),
172 MXS_PINCTRL_PIN(LCD_D01),
173 MXS_PINCTRL_PIN(LCD_D02),
174 MXS_PINCTRL_PIN(LCD_D03),
175 MXS_PINCTRL_PIN(LCD_D04),
176 MXS_PINCTRL_PIN(LCD_D05),
177 MXS_PINCTRL_PIN(LCD_D06),
178 MXS_PINCTRL_PIN(LCD_D07),
179 MXS_PINCTRL_PIN(LCD_D08),
180 MXS_PINCTRL_PIN(LCD_D09),
181 MXS_PINCTRL_PIN(LCD_D10),
182 MXS_PINCTRL_PIN(LCD_D11),
183 MXS_PINCTRL_PIN(LCD_D12),
184 MXS_PINCTRL_PIN(LCD_D13),
185 MXS_PINCTRL_PIN(LCD_D14),
186 MXS_PINCTRL_PIN(LCD_D15),
187 MXS_PINCTRL_PIN(LCD_D16),
188 MXS_PINCTRL_PIN(LCD_D17),
189 MXS_PINCTRL_PIN(LCD_RESET),
190 MXS_PINCTRL_PIN(LCD_RS),
191 MXS_PINCTRL_PIN(LCD_WR),
192 MXS_PINCTRL_PIN(LCD_CS),
193 MXS_PINCTRL_PIN(LCD_DOTCK),
194 MXS_PINCTRL_PIN(LCD_ENABLE),
195 MXS_PINCTRL_PIN(LCD_HSYNC),
196 MXS_PINCTRL_PIN(LCD_VSYNC),
197 MXS_PINCTRL_PIN(PWM0),
198 MXS_PINCTRL_PIN(PWM1),
199 MXS_PINCTRL_PIN(PWM2),
200 MXS_PINCTRL_PIN(PWM3),
201 MXS_PINCTRL_PIN(PWM4),
202 MXS_PINCTRL_PIN(SSP1_CMD),
203 MXS_PINCTRL_PIN(SSP1_DETECT),
204 MXS_PINCTRL_PIN(SSP1_DATA0),
205 MXS_PINCTRL_PIN(SSP1_DATA1),
206 MXS_PINCTRL_PIN(SSP1_DATA2),
207 MXS_PINCTRL_PIN(SSP1_DATA3),
208 MXS_PINCTRL_PIN(SSP1_SCK),
209 MXS_PINCTRL_PIN(ROTARYA),
210 MXS_PINCTRL_PIN(ROTARYB),
211 MXS_PINCTRL_PIN(EMI_A00),
212 MXS_PINCTRL_PIN(EMI_A01),
213 MXS_PINCTRL_PIN(EMI_A02),
214 MXS_PINCTRL_PIN(EMI_A03),
215 MXS_PINCTRL_PIN(EMI_A04),
216 MXS_PINCTRL_PIN(EMI_A05),
217 MXS_PINCTRL_PIN(EMI_A06),
218 MXS_PINCTRL_PIN(EMI_A07),
219 MXS_PINCTRL_PIN(EMI_A08),
220 MXS_PINCTRL_PIN(EMI_A09),
221 MXS_PINCTRL_PIN(EMI_A10),
222 MXS_PINCTRL_PIN(EMI_A11),
223 MXS_PINCTRL_PIN(EMI_A12),
224 MXS_PINCTRL_PIN(EMI_BA0),
225 MXS_PINCTRL_PIN(EMI_BA1),
226 MXS_PINCTRL_PIN(EMI_CASN),
227 MXS_PINCTRL_PIN(EMI_CE0N),
228 MXS_PINCTRL_PIN(EMI_CE1N),
229 MXS_PINCTRL_PIN(GPMI_CE1N),
230 MXS_PINCTRL_PIN(GPMI_CE0N),
231 MXS_PINCTRL_PIN(EMI_CKE),
232 MXS_PINCTRL_PIN(EMI_RASN),
233 MXS_PINCTRL_PIN(EMI_WEN),
234 MXS_PINCTRL_PIN(EMI_D00),
235 MXS_PINCTRL_PIN(EMI_D01),
236 MXS_PINCTRL_PIN(EMI_D02),
237 MXS_PINCTRL_PIN(EMI_D03),
238 MXS_PINCTRL_PIN(EMI_D04),
239 MXS_PINCTRL_PIN(EMI_D05),
240 MXS_PINCTRL_PIN(EMI_D06),
241 MXS_PINCTRL_PIN(EMI_D07),
242 MXS_PINCTRL_PIN(EMI_D08),
243 MXS_PINCTRL_PIN(EMI_D09),
244 MXS_PINCTRL_PIN(EMI_D10),
245 MXS_PINCTRL_PIN(EMI_D11),
246 MXS_PINCTRL_PIN(EMI_D12),
247 MXS_PINCTRL_PIN(EMI_D13),
248 MXS_PINCTRL_PIN(EMI_D14),
249 MXS_PINCTRL_PIN(EMI_D15),
250 MXS_PINCTRL_PIN(EMI_DQM0),
251 MXS_PINCTRL_PIN(EMI_DQM1),
252 MXS_PINCTRL_PIN(EMI_DQS0),
253 MXS_PINCTRL_PIN(EMI_DQS1),
254 MXS_PINCTRL_PIN(EMI_CLK),
255 MXS_PINCTRL_PIN(EMI_CLKN),
256};
257
258static struct mxs_regs imx23_regs = {
259 .muxsel = 0x100,
260 .drive = 0x200,
261 .pull = 0x400,
262};
263
264static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
265 .regs = &imx23_regs,
266 .pins = imx23_pins,
267 .npins = ARRAY_SIZE(imx23_pins),
268};
269
270static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
271{
272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273}
274
275static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
276 { .compatible = "fsl,imx23-pinctrl", },
277 { /* sentinel */ }
278};
279MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
280
281static struct platform_driver imx23_pinctrl_driver = {
282 .driver = {
283 .name = "imx23-pinctrl",
284 .owner = THIS_MODULE,
285 .of_match_table = imx23_pinctrl_of_match,
286 },
287 .probe = imx23_pinctrl_probe,
288 .remove = __devexit_p(mxs_pinctrl_remove),
289};
290
291static int __init imx23_pinctrl_init(void)
292{
293 return platform_driver_register(&imx23_pinctrl_driver);
294}
295arch_initcall(imx23_pinctrl_init);
296
297static void __exit imx23_pinctrl_exit(void)
298{
299 platform_driver_unregister(&imx23_pinctrl_driver);
300}
301module_exit(imx23_pinctrl_exit);
302
303MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
304MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
305MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
new file mode 100644
index 000000000000..b973026811a2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -0,0 +1,421 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx28_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_CE0N = PINID(0, 16),
28 GPMI_CE1N = PINID(0, 17),
29 GPMI_CE2N = PINID(0, 18),
30 GPMI_CE3N = PINID(0, 19),
31 GPMI_RDY0 = PINID(0, 20),
32 GPMI_RDY1 = PINID(0, 21),
33 GPMI_RDY2 = PINID(0, 22),
34 GPMI_RDY3 = PINID(0, 23),
35 GPMI_RDN = PINID(0, 24),
36 GPMI_WRN = PINID(0, 25),
37 GPMI_ALE = PINID(0, 26),
38 GPMI_CLE = PINID(0, 27),
39 GPMI_RESETN = PINID(0, 28),
40 LCD_D00 = PINID(1, 0),
41 LCD_D01 = PINID(1, 1),
42 LCD_D02 = PINID(1, 2),
43 LCD_D03 = PINID(1, 3),
44 LCD_D04 = PINID(1, 4),
45 LCD_D05 = PINID(1, 5),
46 LCD_D06 = PINID(1, 6),
47 LCD_D07 = PINID(1, 7),
48 LCD_D08 = PINID(1, 8),
49 LCD_D09 = PINID(1, 9),
50 LCD_D10 = PINID(1, 10),
51 LCD_D11 = PINID(1, 11),
52 LCD_D12 = PINID(1, 12),
53 LCD_D13 = PINID(1, 13),
54 LCD_D14 = PINID(1, 14),
55 LCD_D15 = PINID(1, 15),
56 LCD_D16 = PINID(1, 16),
57 LCD_D17 = PINID(1, 17),
58 LCD_D18 = PINID(1, 18),
59 LCD_D19 = PINID(1, 19),
60 LCD_D20 = PINID(1, 20),
61 LCD_D21 = PINID(1, 21),
62 LCD_D22 = PINID(1, 22),
63 LCD_D23 = PINID(1, 23),
64 LCD_RD_E = PINID(1, 24),
65 LCD_WR_RWN = PINID(1, 25),
66 LCD_RS = PINID(1, 26),
67 LCD_CS = PINID(1, 27),
68 LCD_VSYNC = PINID(1, 28),
69 LCD_HSYNC = PINID(1, 29),
70 LCD_DOTCLK = PINID(1, 30),
71 LCD_ENABLE = PINID(1, 31),
72 SSP0_DATA0 = PINID(2, 0),
73 SSP0_DATA1 = PINID(2, 1),
74 SSP0_DATA2 = PINID(2, 2),
75 SSP0_DATA3 = PINID(2, 3),
76 SSP0_DATA4 = PINID(2, 4),
77 SSP0_DATA5 = PINID(2, 5),
78 SSP0_DATA6 = PINID(2, 6),
79 SSP0_DATA7 = PINID(2, 7),
80 SSP0_CMD = PINID(2, 8),
81 SSP0_DETECT = PINID(2, 9),
82 SSP0_SCK = PINID(2, 10),
83 SSP1_SCK = PINID(2, 12),
84 SSP1_CMD = PINID(2, 13),
85 SSP1_DATA0 = PINID(2, 14),
86 SSP1_DATA3 = PINID(2, 15),
87 SSP2_SCK = PINID(2, 16),
88 SSP2_MOSI = PINID(2, 17),
89 SSP2_MISO = PINID(2, 18),
90 SSP2_SS0 = PINID(2, 19),
91 SSP2_SS1 = PINID(2, 20),
92 SSP2_SS2 = PINID(2, 21),
93 SSP3_SCK = PINID(2, 24),
94 SSP3_MOSI = PINID(2, 25),
95 SSP3_MISO = PINID(2, 26),
96 SSP3_SS0 = PINID(2, 27),
97 AUART0_RX = PINID(3, 0),
98 AUART0_TX = PINID(3, 1),
99 AUART0_CTS = PINID(3, 2),
100 AUART0_RTS = PINID(3, 3),
101 AUART1_RX = PINID(3, 4),
102 AUART1_TX = PINID(3, 5),
103 AUART1_CTS = PINID(3, 6),
104 AUART1_RTS = PINID(3, 7),
105 AUART2_RX = PINID(3, 8),
106 AUART2_TX = PINID(3, 9),
107 AUART2_CTS = PINID(3, 10),
108 AUART2_RTS = PINID(3, 11),
109 AUART3_RX = PINID(3, 12),
110 AUART3_TX = PINID(3, 13),
111 AUART3_CTS = PINID(3, 14),
112 AUART3_RTS = PINID(3, 15),
113 PWM0 = PINID(3, 16),
114 PWM1 = PINID(3, 17),
115 PWM2 = PINID(3, 18),
116 SAIF0_MCLK = PINID(3, 20),
117 SAIF0_LRCLK = PINID(3, 21),
118 SAIF0_BITCLK = PINID(3, 22),
119 SAIF0_SDATA0 = PINID(3, 23),
120 I2C0_SCL = PINID(3, 24),
121 I2C0_SDA = PINID(3, 25),
122 SAIF1_SDATA0 = PINID(3, 26),
123 SPDIF = PINID(3, 27),
124 PWM3 = PINID(3, 28),
125 PWM4 = PINID(3, 29),
126 LCD_RESET = PINID(3, 30),
127 ENET0_MDC = PINID(4, 0),
128 ENET0_MDIO = PINID(4, 1),
129 ENET0_RX_EN = PINID(4, 2),
130 ENET0_RXD0 = PINID(4, 3),
131 ENET0_RXD1 = PINID(4, 4),
132 ENET0_TX_CLK = PINID(4, 5),
133 ENET0_TX_EN = PINID(4, 6),
134 ENET0_TXD0 = PINID(4, 7),
135 ENET0_TXD1 = PINID(4, 8),
136 ENET0_RXD2 = PINID(4, 9),
137 ENET0_RXD3 = PINID(4, 10),
138 ENET0_TXD2 = PINID(4, 11),
139 ENET0_TXD3 = PINID(4, 12),
140 ENET0_RX_CLK = PINID(4, 13),
141 ENET0_COL = PINID(4, 14),
142 ENET0_CRS = PINID(4, 15),
143 ENET_CLK = PINID(4, 16),
144 JTAG_RTCK = PINID(4, 20),
145 EMI_D00 = PINID(5, 0),
146 EMI_D01 = PINID(5, 1),
147 EMI_D02 = PINID(5, 2),
148 EMI_D03 = PINID(5, 3),
149 EMI_D04 = PINID(5, 4),
150 EMI_D05 = PINID(5, 5),
151 EMI_D06 = PINID(5, 6),
152 EMI_D07 = PINID(5, 7),
153 EMI_D08 = PINID(5, 8),
154 EMI_D09 = PINID(5, 9),
155 EMI_D10 = PINID(5, 10),
156 EMI_D11 = PINID(5, 11),
157 EMI_D12 = PINID(5, 12),
158 EMI_D13 = PINID(5, 13),
159 EMI_D14 = PINID(5, 14),
160 EMI_D15 = PINID(5, 15),
161 EMI_ODT0 = PINID(5, 16),
162 EMI_DQM0 = PINID(5, 17),
163 EMI_ODT1 = PINID(5, 18),
164 EMI_DQM1 = PINID(5, 19),
165 EMI_DDR_OPEN_FB = PINID(5, 20),
166 EMI_CLK = PINID(5, 21),
167 EMI_DQS0 = PINID(5, 22),
168 EMI_DQS1 = PINID(5, 23),
169 EMI_DDR_OPEN = PINID(5, 26),
170 EMI_A00 = PINID(6, 0),
171 EMI_A01 = PINID(6, 1),
172 EMI_A02 = PINID(6, 2),
173 EMI_A03 = PINID(6, 3),
174 EMI_A04 = PINID(6, 4),
175 EMI_A05 = PINID(6, 5),
176 EMI_A06 = PINID(6, 6),
177 EMI_A07 = PINID(6, 7),
178 EMI_A08 = PINID(6, 8),
179 EMI_A09 = PINID(6, 9),
180 EMI_A10 = PINID(6, 10),
181 EMI_A11 = PINID(6, 11),
182 EMI_A12 = PINID(6, 12),
183 EMI_A13 = PINID(6, 13),
184 EMI_A14 = PINID(6, 14),
185 EMI_BA0 = PINID(6, 16),
186 EMI_BA1 = PINID(6, 17),
187 EMI_BA2 = PINID(6, 18),
188 EMI_CASN = PINID(6, 19),
189 EMI_RASN = PINID(6, 20),
190 EMI_WEN = PINID(6, 21),
191 EMI_CE0N = PINID(6, 22),
192 EMI_CE1N = PINID(6, 23),
193 EMI_CKE = PINID(6, 24),
194};
195
196static const struct pinctrl_pin_desc imx28_pins[] = {
197 MXS_PINCTRL_PIN(GPMI_D00),
198 MXS_PINCTRL_PIN(GPMI_D01),
199 MXS_PINCTRL_PIN(GPMI_D02),
200 MXS_PINCTRL_PIN(GPMI_D03),
201 MXS_PINCTRL_PIN(GPMI_D04),
202 MXS_PINCTRL_PIN(GPMI_D05),
203 MXS_PINCTRL_PIN(GPMI_D06),
204 MXS_PINCTRL_PIN(GPMI_D07),
205 MXS_PINCTRL_PIN(GPMI_CE0N),
206 MXS_PINCTRL_PIN(GPMI_CE1N),
207 MXS_PINCTRL_PIN(GPMI_CE2N),
208 MXS_PINCTRL_PIN(GPMI_CE3N),
209 MXS_PINCTRL_PIN(GPMI_RDY0),
210 MXS_PINCTRL_PIN(GPMI_RDY1),
211 MXS_PINCTRL_PIN(GPMI_RDY2),
212 MXS_PINCTRL_PIN(GPMI_RDY3),
213 MXS_PINCTRL_PIN(GPMI_RDN),
214 MXS_PINCTRL_PIN(GPMI_WRN),
215 MXS_PINCTRL_PIN(GPMI_ALE),
216 MXS_PINCTRL_PIN(GPMI_CLE),
217 MXS_PINCTRL_PIN(GPMI_RESETN),
218 MXS_PINCTRL_PIN(LCD_D00),
219 MXS_PINCTRL_PIN(LCD_D01),
220 MXS_PINCTRL_PIN(LCD_D02),
221 MXS_PINCTRL_PIN(LCD_D03),
222 MXS_PINCTRL_PIN(LCD_D04),
223 MXS_PINCTRL_PIN(LCD_D05),
224 MXS_PINCTRL_PIN(LCD_D06),
225 MXS_PINCTRL_PIN(LCD_D07),
226 MXS_PINCTRL_PIN(LCD_D08),
227 MXS_PINCTRL_PIN(LCD_D09),
228 MXS_PINCTRL_PIN(LCD_D10),
229 MXS_PINCTRL_PIN(LCD_D11),
230 MXS_PINCTRL_PIN(LCD_D12),
231 MXS_PINCTRL_PIN(LCD_D13),
232 MXS_PINCTRL_PIN(LCD_D14),
233 MXS_PINCTRL_PIN(LCD_D15),
234 MXS_PINCTRL_PIN(LCD_D16),
235 MXS_PINCTRL_PIN(LCD_D17),
236 MXS_PINCTRL_PIN(LCD_D18),
237 MXS_PINCTRL_PIN(LCD_D19),
238 MXS_PINCTRL_PIN(LCD_D20),
239 MXS_PINCTRL_PIN(LCD_D21),
240 MXS_PINCTRL_PIN(LCD_D22),
241 MXS_PINCTRL_PIN(LCD_D23),
242 MXS_PINCTRL_PIN(LCD_RD_E),
243 MXS_PINCTRL_PIN(LCD_WR_RWN),
244 MXS_PINCTRL_PIN(LCD_RS),
245 MXS_PINCTRL_PIN(LCD_CS),
246 MXS_PINCTRL_PIN(LCD_VSYNC),
247 MXS_PINCTRL_PIN(LCD_HSYNC),
248 MXS_PINCTRL_PIN(LCD_DOTCLK),
249 MXS_PINCTRL_PIN(LCD_ENABLE),
250 MXS_PINCTRL_PIN(SSP0_DATA0),
251 MXS_PINCTRL_PIN(SSP0_DATA1),
252 MXS_PINCTRL_PIN(SSP0_DATA2),
253 MXS_PINCTRL_PIN(SSP0_DATA3),
254 MXS_PINCTRL_PIN(SSP0_DATA4),
255 MXS_PINCTRL_PIN(SSP0_DATA5),
256 MXS_PINCTRL_PIN(SSP0_DATA6),
257 MXS_PINCTRL_PIN(SSP0_DATA7),
258 MXS_PINCTRL_PIN(SSP0_CMD),
259 MXS_PINCTRL_PIN(SSP0_DETECT),
260 MXS_PINCTRL_PIN(SSP0_SCK),
261 MXS_PINCTRL_PIN(SSP1_SCK),
262 MXS_PINCTRL_PIN(SSP1_CMD),
263 MXS_PINCTRL_PIN(SSP1_DATA0),
264 MXS_PINCTRL_PIN(SSP1_DATA3),
265 MXS_PINCTRL_PIN(SSP2_SCK),
266 MXS_PINCTRL_PIN(SSP2_MOSI),
267 MXS_PINCTRL_PIN(SSP2_MISO),
268 MXS_PINCTRL_PIN(SSP2_SS0),
269 MXS_PINCTRL_PIN(SSP2_SS1),
270 MXS_PINCTRL_PIN(SSP2_SS2),
271 MXS_PINCTRL_PIN(SSP3_SCK),
272 MXS_PINCTRL_PIN(SSP3_MOSI),
273 MXS_PINCTRL_PIN(SSP3_MISO),
274 MXS_PINCTRL_PIN(SSP3_SS0),
275 MXS_PINCTRL_PIN(AUART0_RX),
276 MXS_PINCTRL_PIN(AUART0_TX),
277 MXS_PINCTRL_PIN(AUART0_CTS),
278 MXS_PINCTRL_PIN(AUART0_RTS),
279 MXS_PINCTRL_PIN(AUART1_RX),
280 MXS_PINCTRL_PIN(AUART1_TX),
281 MXS_PINCTRL_PIN(AUART1_CTS),
282 MXS_PINCTRL_PIN(AUART1_RTS),
283 MXS_PINCTRL_PIN(AUART2_RX),
284 MXS_PINCTRL_PIN(AUART2_TX),
285 MXS_PINCTRL_PIN(AUART2_CTS),
286 MXS_PINCTRL_PIN(AUART2_RTS),
287 MXS_PINCTRL_PIN(AUART3_RX),
288 MXS_PINCTRL_PIN(AUART3_TX),
289 MXS_PINCTRL_PIN(AUART3_CTS),
290 MXS_PINCTRL_PIN(AUART3_RTS),
291 MXS_PINCTRL_PIN(PWM0),
292 MXS_PINCTRL_PIN(PWM1),
293 MXS_PINCTRL_PIN(PWM2),
294 MXS_PINCTRL_PIN(SAIF0_MCLK),
295 MXS_PINCTRL_PIN(SAIF0_LRCLK),
296 MXS_PINCTRL_PIN(SAIF0_BITCLK),
297 MXS_PINCTRL_PIN(SAIF0_SDATA0),
298 MXS_PINCTRL_PIN(I2C0_SCL),
299 MXS_PINCTRL_PIN(I2C0_SDA),
300 MXS_PINCTRL_PIN(SAIF1_SDATA0),
301 MXS_PINCTRL_PIN(SPDIF),
302 MXS_PINCTRL_PIN(PWM3),
303 MXS_PINCTRL_PIN(PWM4),
304 MXS_PINCTRL_PIN(LCD_RESET),
305 MXS_PINCTRL_PIN(ENET0_MDC),
306 MXS_PINCTRL_PIN(ENET0_MDIO),
307 MXS_PINCTRL_PIN(ENET0_RX_EN),
308 MXS_PINCTRL_PIN(ENET0_RXD0),
309 MXS_PINCTRL_PIN(ENET0_RXD1),
310 MXS_PINCTRL_PIN(ENET0_TX_CLK),
311 MXS_PINCTRL_PIN(ENET0_TX_EN),
312 MXS_PINCTRL_PIN(ENET0_TXD0),
313 MXS_PINCTRL_PIN(ENET0_TXD1),
314 MXS_PINCTRL_PIN(ENET0_RXD2),
315 MXS_PINCTRL_PIN(ENET0_RXD3),
316 MXS_PINCTRL_PIN(ENET0_TXD2),
317 MXS_PINCTRL_PIN(ENET0_TXD3),
318 MXS_PINCTRL_PIN(ENET0_RX_CLK),
319 MXS_PINCTRL_PIN(ENET0_COL),
320 MXS_PINCTRL_PIN(ENET0_CRS),
321 MXS_PINCTRL_PIN(ENET_CLK),
322 MXS_PINCTRL_PIN(JTAG_RTCK),
323 MXS_PINCTRL_PIN(EMI_D00),
324 MXS_PINCTRL_PIN(EMI_D01),
325 MXS_PINCTRL_PIN(EMI_D02),
326 MXS_PINCTRL_PIN(EMI_D03),
327 MXS_PINCTRL_PIN(EMI_D04),
328 MXS_PINCTRL_PIN(EMI_D05),
329 MXS_PINCTRL_PIN(EMI_D06),
330 MXS_PINCTRL_PIN(EMI_D07),
331 MXS_PINCTRL_PIN(EMI_D08),
332 MXS_PINCTRL_PIN(EMI_D09),
333 MXS_PINCTRL_PIN(EMI_D10),
334 MXS_PINCTRL_PIN(EMI_D11),
335 MXS_PINCTRL_PIN(EMI_D12),
336 MXS_PINCTRL_PIN(EMI_D13),
337 MXS_PINCTRL_PIN(EMI_D14),
338 MXS_PINCTRL_PIN(EMI_D15),
339 MXS_PINCTRL_PIN(EMI_ODT0),
340 MXS_PINCTRL_PIN(EMI_DQM0),
341 MXS_PINCTRL_PIN(EMI_ODT1),
342 MXS_PINCTRL_PIN(EMI_DQM1),
343 MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
344 MXS_PINCTRL_PIN(EMI_CLK),
345 MXS_PINCTRL_PIN(EMI_DQS0),
346 MXS_PINCTRL_PIN(EMI_DQS1),
347 MXS_PINCTRL_PIN(EMI_DDR_OPEN),
348 MXS_PINCTRL_PIN(EMI_A00),
349 MXS_PINCTRL_PIN(EMI_A01),
350 MXS_PINCTRL_PIN(EMI_A02),
351 MXS_PINCTRL_PIN(EMI_A03),
352 MXS_PINCTRL_PIN(EMI_A04),
353 MXS_PINCTRL_PIN(EMI_A05),
354 MXS_PINCTRL_PIN(EMI_A06),
355 MXS_PINCTRL_PIN(EMI_A07),
356 MXS_PINCTRL_PIN(EMI_A08),
357 MXS_PINCTRL_PIN(EMI_A09),
358 MXS_PINCTRL_PIN(EMI_A10),
359 MXS_PINCTRL_PIN(EMI_A11),
360 MXS_PINCTRL_PIN(EMI_A12),
361 MXS_PINCTRL_PIN(EMI_A13),
362 MXS_PINCTRL_PIN(EMI_A14),
363 MXS_PINCTRL_PIN(EMI_BA0),
364 MXS_PINCTRL_PIN(EMI_BA1),
365 MXS_PINCTRL_PIN(EMI_BA2),
366 MXS_PINCTRL_PIN(EMI_CASN),
367 MXS_PINCTRL_PIN(EMI_RASN),
368 MXS_PINCTRL_PIN(EMI_WEN),
369 MXS_PINCTRL_PIN(EMI_CE0N),
370 MXS_PINCTRL_PIN(EMI_CE1N),
371 MXS_PINCTRL_PIN(EMI_CKE),
372};
373
374static struct mxs_regs imx28_regs = {
375 .muxsel = 0x100,
376 .drive = 0x300,
377 .pull = 0x600,
378};
379
380static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
381 .regs = &imx28_regs,
382 .pins = imx28_pins,
383 .npins = ARRAY_SIZE(imx28_pins),
384};
385
386static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
387{
388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389}
390
391static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
392 { .compatible = "fsl,imx28-pinctrl", },
393 { /* sentinel */ }
394};
395MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
396
397static struct platform_driver imx28_pinctrl_driver = {
398 .driver = {
399 .name = "imx28-pinctrl",
400 .owner = THIS_MODULE,
401 .of_match_table = imx28_pinctrl_of_match,
402 },
403 .probe = imx28_pinctrl_probe,
404 .remove = __devexit_p(mxs_pinctrl_remove),
405};
406
407static int __init imx28_pinctrl_init(void)
408{
409 return platform_driver_register(&imx28_pinctrl_driver);
410}
411arch_initcall(imx28_pinctrl_init);
412
413static void __exit imx28_pinctrl_exit(void)
414{
415 platform_driver_unregister(&imx28_pinctrl_driver);
416}
417module_exit(imx28_pinctrl_exit);
418
419MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
420MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
421MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
new file mode 100644
index 000000000000..93cd959971c5
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -0,0 +1,508 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/pinctrl/machine.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include "core.h"
25#include "pinctrl-mxs.h"
26
27#define SUFFIX_LEN 4
28
29struct mxs_pinctrl_data {
30 struct device *dev;
31 struct pinctrl_dev *pctl;
32 void __iomem *base;
33 struct mxs_pinctrl_soc_data *soc;
34};
35
36static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37{
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
40 return d->soc->ngroups;
41}
42
43static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44 unsigned group)
45{
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
48 return d->soc->groups[group].name;
49}
50
51static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52 const unsigned **pins, unsigned *num_pins)
53{
54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
56 *pins = d->soc->groups[group].pins;
57 *num_pins = d->soc->groups[group].npins;
58
59 return 0;
60}
61
62static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63 unsigned offset)
64{
65 seq_printf(s, " %s", dev_name(pctldev->dev));
66}
67
68static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69 struct device_node *np,
70 struct pinctrl_map **map, unsigned *num_maps)
71{
72 struct pinctrl_map *new_map;
73 char *group;
74 unsigned new_num;
75 unsigned long config = 0;
76 unsigned long *pconfig;
77 int length = strlen(np->name) + SUFFIX_LEN;
78 u32 val;
79 int ret;
80
81 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
82 if (!ret)
83 config = val | MA_PRESENT;
84 ret = of_property_read_u32(np, "fsl,voltage", &val);
85 if (!ret)
86 config |= val << VOL_SHIFT | VOL_PRESENT;
87 ret = of_property_read_u32(np, "fsl,pull-up", &val);
88 if (!ret)
89 config |= val << PULL_SHIFT | PULL_PRESENT;
90
91 new_num = config ? 2 : 1;
92 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
93 if (!new_map)
94 return -ENOMEM;
95
96 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
97 new_map[0].data.mux.function = np->name;
98
99 /* Compose group name */
100 group = kzalloc(length, GFP_KERNEL);
101 if (!group)
102 return -ENOMEM;
103 of_property_read_u32(np, "reg", &val);
104 snprintf(group, length, "%s.%d", np->name, val);
105 new_map[0].data.mux.group = group;
106
107 if (config) {
108 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
109 if (!pconfig) {
110 ret = -ENOMEM;
111 goto free;
112 }
113
114 new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
115 new_map[1].data.configs.group_or_pin = group;
116 new_map[1].data.configs.configs = pconfig;
117 new_map[1].data.configs.num_configs = 1;
118 }
119
120 *map = new_map;
121 *num_maps = new_num;
122
123 return 0;
124
125free:
126 kfree(new_map);
127 return ret;
128}
129
130static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
131 struct pinctrl_map *map, unsigned num_maps)
132{
133 int i;
134
135 for (i = 0; i < num_maps; i++) {
136 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
137 kfree(map[i].data.mux.group);
138 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
139 kfree(map[i].data.configs.configs);
140 }
141
142 kfree(map);
143}
144
145static struct pinctrl_ops mxs_pinctrl_ops = {
146 .get_groups_count = mxs_get_groups_count,
147 .get_group_name = mxs_get_group_name,
148 .get_group_pins = mxs_get_group_pins,
149 .pin_dbg_show = mxs_pin_dbg_show,
150 .dt_node_to_map = mxs_dt_node_to_map,
151 .dt_free_map = mxs_dt_free_map,
152};
153
154static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
155{
156 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
157
158 return d->soc->nfunctions;
159}
160
161static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
162 unsigned function)
163{
164 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
165
166 return d->soc->functions[function].name;
167}
168
169static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
170 unsigned group,
171 const char * const **groups,
172 unsigned * const num_groups)
173{
174 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
175
176 *groups = d->soc->functions[group].groups;
177 *num_groups = d->soc->functions[group].ngroups;
178
179 return 0;
180}
181
182static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
183 unsigned group)
184{
185 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
186 struct mxs_group *g = &d->soc->groups[group];
187 void __iomem *reg;
188 u8 bank, shift;
189 u16 pin;
190 int i;
191
192 for (i = 0; i < g->npins; i++) {
193 bank = PINID_TO_BANK(g->pins[i]);
194 pin = PINID_TO_PIN(g->pins[i]);
195 reg = d->base + d->soc->regs->muxsel;
196 reg += bank * 0x20 + pin / 16 * 0x10;
197 shift = pin % 16 * 2;
198
199 writel(0x3 << shift, reg + CLR);
200 writel(g->muxsel[i] << shift, reg + SET);
201 }
202
203 return 0;
204}
205
206static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
207 unsigned function, unsigned group)
208{
209 /* Nothing to do here */
210}
211
212static struct pinmux_ops mxs_pinmux_ops = {
213 .get_functions_count = mxs_pinctrl_get_funcs_count,
214 .get_function_name = mxs_pinctrl_get_func_name,
215 .get_function_groups = mxs_pinctrl_get_func_groups,
216 .enable = mxs_pinctrl_enable,
217 .disable = mxs_pinctrl_disable,
218};
219
220static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
221 unsigned pin, unsigned long *config)
222{
223 return -ENOTSUPP;
224}
225
226static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
227 unsigned pin, unsigned long config)
228{
229 return -ENOTSUPP;
230}
231
232static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
233 unsigned group, unsigned long *config)
234{
235 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
236
237 *config = d->soc->groups[group].config;
238
239 return 0;
240}
241
242static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
243 unsigned group, unsigned long config)
244{
245 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
246 struct mxs_group *g = &d->soc->groups[group];
247 void __iomem *reg;
248 u8 ma, vol, pull, bank, shift;
249 u16 pin;
250 int i;
251
252 ma = CONFIG_TO_MA(config);
253 vol = CONFIG_TO_VOL(config);
254 pull = CONFIG_TO_PULL(config);
255
256 for (i = 0; i < g->npins; i++) {
257 bank = PINID_TO_BANK(g->pins[i]);
258 pin = PINID_TO_PIN(g->pins[i]);
259
260 /* drive */
261 reg = d->base + d->soc->regs->drive;
262 reg += bank * 0x40 + pin / 8 * 0x10;
263
264 /* mA */
265 if (config & MA_PRESENT) {
266 shift = pin % 8 * 4;
267 writel(0x3 << shift, reg + CLR);
268 writel(ma << shift, reg + SET);
269 }
270
271 /* vol */
272 if (config & VOL_PRESENT) {
273 shift = pin % 8 * 4 + 2;
274 if (vol)
275 writel(1 << shift, reg + SET);
276 else
277 writel(1 << shift, reg + CLR);
278 }
279
280 /* pull */
281 if (config & PULL_PRESENT) {
282 reg = d->base + d->soc->regs->pull;
283 reg += bank * 0x10;
284 shift = pin;
285 if (pull)
286 writel(1 << shift, reg + SET);
287 else
288 writel(1 << shift, reg + CLR);
289 }
290 }
291
292 /* cache the config value for mxs_pinconf_group_get() */
293 g->config = config;
294
295 return 0;
296}
297
298static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
299 struct seq_file *s, unsigned pin)
300{
301 /* Not support */
302}
303
304static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
305 struct seq_file *s, unsigned group)
306{
307 unsigned long config;
308
309 if (!mxs_pinconf_group_get(pctldev, group, &config))
310 seq_printf(s, "0x%lx", config);
311}
312
313struct pinconf_ops mxs_pinconf_ops = {
314 .pin_config_get = mxs_pinconf_get,
315 .pin_config_set = mxs_pinconf_set,
316 .pin_config_group_get = mxs_pinconf_group_get,
317 .pin_config_group_set = mxs_pinconf_group_set,
318 .pin_config_dbg_show = mxs_pinconf_dbg_show,
319 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
320};
321
322static struct pinctrl_desc mxs_pinctrl_desc = {
323 .pctlops = &mxs_pinctrl_ops,
324 .pmxops = &mxs_pinmux_ops,
325 .confops = &mxs_pinconf_ops,
326 .owner = THIS_MODULE,
327};
328
329static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
330 struct device_node *np, int idx,
331 const char **out_name)
332{
333 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
334 struct mxs_group *g = &d->soc->groups[idx];
335 struct property *prop;
336 const char *propname = "fsl,pinmux-ids";
337 char *group;
338 int length = strlen(np->name) + SUFFIX_LEN;
339 int i;
340 u32 val;
341
342 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
343 if (!group)
344 return -ENOMEM;
345 of_property_read_u32(np, "reg", &val);
346 snprintf(group, length, "%s.%d", np->name, val);
347 g->name = group;
348
349 prop = of_find_property(np, propname, &length);
350 if (!prop)
351 return -EINVAL;
352 g->npins = length / sizeof(u32);
353
354 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
355 GFP_KERNEL);
356 if (!g->pins)
357 return -ENOMEM;
358
359 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
360 GFP_KERNEL);
361 if (!g->muxsel)
362 return -ENOMEM;
363
364 of_property_read_u32_array(np, propname, g->pins, g->npins);
365 for (i = 0; i < g->npins; i++) {
366 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
367 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
368 }
369
370 *out_name = g->name;
371
372 return 0;
373}
374
375static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
376 struct mxs_pinctrl_data *d)
377{
378 struct mxs_pinctrl_soc_data *soc = d->soc;
379 struct device_node *np = pdev->dev.of_node;
380 struct device_node *child;
381 struct mxs_function *f;
382 const char *fn, *fnull = "";
383 int i = 0, idxf = 0, idxg = 0;
384 int ret;
385 u32 val;
386
387 child = of_get_next_child(np, NULL);
388 if (!child) {
389 dev_err(&pdev->dev, "no group is defined\n");
390 return -ENOENT;
391 }
392
393 /* Count total functions and groups */
394 fn = fnull;
395 for_each_child_of_node(np, child) {
396 /* Skip pure pinconf node */
397 if (of_property_read_u32(child, "reg", &val))
398 continue;
399 if (strcmp(fn, child->name)) {
400 fn = child->name;
401 soc->nfunctions++;
402 }
403 soc->ngroups++;
404 }
405
406 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
407 sizeof(*soc->functions), GFP_KERNEL);
408 if (!soc->functions)
409 return -ENOMEM;
410
411 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
412 sizeof(*soc->groups), GFP_KERNEL);
413 if (!soc->groups)
414 return -ENOMEM;
415
416 /* Count groups for each function */
417 fn = fnull;
418 f = &soc->functions[idxf];
419 for_each_child_of_node(np, child) {
420 if (of_property_read_u32(child, "reg", &val))
421 continue;
422 if (strcmp(fn, child->name)) {
423 f = &soc->functions[idxf++];
424 f->name = fn = child->name;
425 }
426 f->ngroups++;
427 };
428
429 /* Get groups for each function */
430 idxf = 0;
431 fn = fnull;
432 for_each_child_of_node(np, child) {
433 if (of_property_read_u32(child, "reg", &val))
434 continue;
435 if (strcmp(fn, child->name)) {
436 f = &soc->functions[idxf++];
437 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
438 sizeof(*f->groups),
439 GFP_KERNEL);
440 if (!f->groups)
441 return -ENOMEM;
442 fn = child->name;
443 i = 0;
444 }
445 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
446 &f->groups[i++]);
447 if (ret)
448 return ret;
449 }
450
451 return 0;
452}
453
454int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
455 struct mxs_pinctrl_soc_data *soc)
456{
457 struct device_node *np = pdev->dev.of_node;
458 struct mxs_pinctrl_data *d;
459 int ret;
460
461 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
462 if (!d)
463 return -ENOMEM;
464
465 d->dev = &pdev->dev;
466 d->soc = soc;
467
468 d->base = of_iomap(np, 0);
469 if (!d->base)
470 return -EADDRNOTAVAIL;
471
472 mxs_pinctrl_desc.pins = d->soc->pins;
473 mxs_pinctrl_desc.npins = d->soc->npins;
474 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
475
476 platform_set_drvdata(pdev, d);
477
478 ret = mxs_pinctrl_probe_dt(pdev, d);
479 if (ret) {
480 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
481 goto err;
482 }
483
484 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
485 if (!d->pctl) {
486 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
487 ret = -EINVAL;
488 goto err;
489 }
490
491 return 0;
492
493err:
494 iounmap(d->base);
495 return ret;
496}
497EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
498
499int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
500{
501 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
502
503 pinctrl_unregister(d->pctl);
504 iounmap(d->base);
505
506 return 0;
507}
508EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h
new file mode 100644
index 000000000000..fdd88d0bae22
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __PINCTRL_MXS_H
13#define __PINCTRL_MXS_H
14
15#include <linux/platform_device.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#define SET 0x4
19#define CLR 0x8
20#define TOG 0xc
21
22#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23#define PINID(bank, pin) ((bank) * 32 + (pin))
24
25/*
26 * pinmux-id bit field definitions
27 *
28 * bank: 15..12 (4)
29 * pin: 11..4 (8)
30 * muxsel: 3..0 (4)
31 */
32#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
33#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
34
35#define PINID_TO_BANK(p) ((p) >> 5)
36#define PINID_TO_PIN(p) ((p) % 32)
37
38/*
39 * pin config bit field definitions
40 *
41 * pull-up: 6..5 (2)
42 * voltage: 4..3 (2)
43 * mA: 2..0 (3)
44 *
45 * MSB of each field is presence bit for the config.
46 */
47#define PULL_PRESENT (1 << 6)
48#define PULL_SHIFT 5
49#define VOL_PRESENT (1 << 4)
50#define VOL_SHIFT 3
51#define MA_PRESENT (1 << 2)
52#define MA_SHIFT 0
53#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
54#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
55#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
56
57struct mxs_function {
58 const char *name;
59 const char **groups;
60 unsigned ngroups;
61};
62
63struct mxs_group {
64 const char *name;
65 unsigned int *pins;
66 unsigned npins;
67 u8 *muxsel;
68 u8 config;
69};
70
71struct mxs_regs {
72 u16 muxsel;
73 u16 drive;
74 u16 pull;
75};
76
77struct mxs_pinctrl_soc_data {
78 const struct mxs_regs *regs;
79 const struct pinctrl_pin_desc *pins;
80 unsigned npins;
81 struct mxs_function *functions;
82 unsigned nfunctions;
83 struct mxs_group *groups;
84 unsigned ngroups;
85};
86
87int mxs_pinctrl_probe(struct platform_device *pdev,
88 struct mxs_pinctrl_soc_data *soc);
89int mxs_pinctrl_remove(struct platform_device *pdev);
90
91#endif /* __PINCTRL_MXS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-07 18:49:17 -0400