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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-04-18 14:12:50 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-05-04 03:03:29 -0400
commit342cefb2128b098035d324e448d42253c9c44699 (patch)
tree170798af257843d0e4a9593c2331aa9c08e07c3c /drivers/pinctrl/sunxi
parent0a127c1c395a06c2e23b13fc8f6753f9e1aaba43 (diff)
pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/pinctrl/sunxi')
-rw-r--r--drivers/pinctrl/sunxi/Makefile1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c411
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h366
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c1
4 files changed, 412 insertions, 367 deletions
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 9e437266f50f..0cb72fed6ee3 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
4# SoC Drivers 4# SoC Drivers
5obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sun4i-a10.o 5obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sun4i-a10.o
6obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sun5i-a10s.o 6obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sun5i-a10s.o
7obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sun5i-a13.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
new file mode 100644
index 000000000000..1188a2b7b988
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -0,0 +1,411 @@
1/*
2 * Allwinner A13 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun5i_a13_pins[] = {
22 /* Hole */
23 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
24 SUNXI_FUNCTION(0x0, "gpio_in"),
25 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
27 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
28 SUNXI_FUNCTION(0x0, "gpio_in"),
29 SUNXI_FUNCTION(0x1, "gpio_out"),
30 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "pwm"),
35 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
40 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
45 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
46 /* Hole */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
51 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
52 /* Hole */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
57 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
58 SUNXI_FUNCTION(0x0, "gpio_in"),
59 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
69 /* Hole */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
74 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
79 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
84 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
89 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
91 SUNXI_FUNCTION(0x0, "gpio_in"),
92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
95 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out"),
97 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
102 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
107 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
108 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
109 SUNXI_FUNCTION(0x0, "gpio_in"),
110 SUNXI_FUNCTION(0x1, "gpio_out"),
111 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
112 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
117 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
119 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out"),
121 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
122 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
123 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
124 SUNXI_FUNCTION(0x0, "gpio_in"),
125 SUNXI_FUNCTION(0x1, "gpio_out"),
126 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
127 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
132 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out"),
136 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
137 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
142 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
147 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
148 /* Hole */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
153 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
154 /* Hole */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
179 /* Hole */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
188 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
189 SUNXI_FUNCTION(0x0, "gpio_in"),
190 SUNXI_FUNCTION(0x1, "gpio_out"),
191 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
201 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
204 /* Hole */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
245 /* Hole */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
249 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
250 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
254 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
255 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
256 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
257 SUNXI_FUNCTION(0x0, "gpio_in"),
258 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
259 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
264 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
269 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
274 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
279 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
284 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
289 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
291 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out"),
293 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
294 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
295 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
296 SUNXI_FUNCTION(0x0, "gpio_in"),
297 SUNXI_FUNCTION(0x1, "gpio_out"),
298 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
299 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
304 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
305 /* Hole */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
310 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
311 SUNXI_FUNCTION(0x0, "gpio_in"),
312 SUNXI_FUNCTION(0x1, "gpio_out"),
313 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
330 /* Hole */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
336 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
347 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
348 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
353 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
354 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
355 /* Hole */
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
360 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
361 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
366 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
367 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
368 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
369 SUNXI_FUNCTION(0x0, "gpio_in"),
370 SUNXI_FUNCTION(0x1, "gpio_out"),
371 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
372 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
373 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
378 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
379 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
380};
381
382static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
383 .pins = sun5i_a13_pins,
384 .npins = ARRAY_SIZE(sun5i_a13_pins),
385};
386
387static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
388{
389 return sunxi_pinctrl_init(pdev,
390 &sun5i_a13_pinctrl_data);
391}
392
393static struct of_device_id sun5i_a13_pinctrl_match[] = {
394 { .compatible = "allwinner,sun5i-a13-pinctrl", },
395 {}
396};
397MODULE_DEVICE_TABLE(of, sun5i_a13_pinctrl_match);
398
399static struct platform_driver sun5i_a13_pinctrl_driver = {
400 .probe = sun5i_a13_pinctrl_probe,
401 .driver = {
402 .name = "sun5i-a13-pinctrl",
403 .owner = THIS_MODULE,
404 .of_match_table = sun5i_a13_pinctrl_match,
405 },
406};
407module_platform_driver(sun5i_a13_pinctrl_driver);
408
409MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
410MODULE_DESCRIPTION("Allwinner A13 pinctrl driver");
411MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h b/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
index 50f63e6b623f..6ed6f4c3c262 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
@@ -15,367 +15,6 @@
15 15
16#include "pinctrl-sunxi.h" 16#include "pinctrl-sunxi.h"
17 17
18static const struct sunxi_desc_pin sun5i_a13_pins[] = {
19 /* Hole */
20 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
21 SUNXI_FUNCTION(0x0, "gpio_in"),
22 SUNXI_FUNCTION(0x1, "gpio_out"),
23 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
24 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
25 SUNXI_FUNCTION(0x0, "gpio_in"),
26 SUNXI_FUNCTION(0x1, "gpio_out"),
27 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "pwm"),
32 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
33 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
34 SUNXI_FUNCTION(0x0, "gpio_in"),
35 SUNXI_FUNCTION(0x1, "gpio_out"),
36 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
37 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
42 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
43 /* Hole */
44 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
45 SUNXI_FUNCTION(0x0, "gpio_in"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
48 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
49 /* Hole */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
54 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
55 SUNXI_FUNCTION(0x0, "gpio_in"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
57 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
62 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
63 SUNXI_FUNCTION(0x0, "gpio_in"),
64 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
66 /* Hole */
67 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
68 SUNXI_FUNCTION(0x0, "gpio_in"),
69 SUNXI_FUNCTION(0x1, "gpio_out"),
70 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
71 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
72 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
73 SUNXI_FUNCTION(0x0, "gpio_in"),
74 SUNXI_FUNCTION(0x1, "gpio_out"),
75 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
76 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
81 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
83 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
86 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
87 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
88 SUNXI_FUNCTION(0x0, "gpio_in"),
89 SUNXI_FUNCTION(0x1, "gpio_out"),
90 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
99 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
104 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
106 SUNXI_FUNCTION(0x0, "gpio_in"),
107 SUNXI_FUNCTION(0x1, "gpio_out"),
108 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
109 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
114 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
115 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
116 SUNXI_FUNCTION(0x0, "gpio_in"),
117 SUNXI_FUNCTION(0x1, "gpio_out"),
118 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
119 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
124 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
125 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
126 SUNXI_FUNCTION(0x0, "gpio_in"),
127 SUNXI_FUNCTION(0x1, "gpio_out"),
128 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
129 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
130 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
131 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out"),
133 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
134 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
136 SUNXI_FUNCTION(0x0, "gpio_in"),
137 SUNXI_FUNCTION(0x1, "gpio_out"),
138 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
139 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
144 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
145 /* Hole */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
150 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
151 /* Hole */
152 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
153 SUNXI_FUNCTION(0x0, "gpio_in"),
154 SUNXI_FUNCTION(0x1, "gpio_out"),
155 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
156 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
157 SUNXI_FUNCTION(0x0, "gpio_in"),
158 SUNXI_FUNCTION(0x1, "gpio_out"),
159 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
176 /* Hole */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
193 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
194 SUNXI_FUNCTION(0x0, "gpio_in"),
195 SUNXI_FUNCTION(0x1, "gpio_out"),
196 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
197 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
198 SUNXI_FUNCTION(0x0, "gpio_in"),
199 SUNXI_FUNCTION(0x1, "gpio_out"),
200 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
201 /* Hole */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
206 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
207 SUNXI_FUNCTION(0x0, "gpio_in"),
208 SUNXI_FUNCTION(0x1, "gpio_out"),
209 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
210 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
211 SUNXI_FUNCTION(0x0, "gpio_in"),
212 SUNXI_FUNCTION(0x1, "gpio_out"),
213 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
214 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
215 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out"),
217 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
218 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
219 SUNXI_FUNCTION(0x0, "gpio_in"),
220 SUNXI_FUNCTION(0x1, "gpio_out"),
221 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
226 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
227 SUNXI_FUNCTION(0x0, "gpio_in"),
228 SUNXI_FUNCTION(0x1, "gpio_out"),
229 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
242 /* Hole */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
246 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
247 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
251 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
252 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
256 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
261 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
266 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
271 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
276 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
281 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
282 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
283 SUNXI_FUNCTION(0x0, "gpio_in"),
284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
286 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
291 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
296 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
301 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
302 /* Hole */
303 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
304 SUNXI_FUNCTION(0x0, "gpio_in"),
305 SUNXI_FUNCTION(0x1, "gpio_out"),
306 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
307 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
308 SUNXI_FUNCTION(0x0, "gpio_in"),
309 SUNXI_FUNCTION(0x1, "gpio_out"),
310 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
315 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
316 SUNXI_FUNCTION(0x0, "gpio_in"),
317 SUNXI_FUNCTION(0x1, "gpio_out"),
318 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
319 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
320 SUNXI_FUNCTION(0x0, "gpio_in"),
321 SUNXI_FUNCTION(0x1, "gpio_out"),
322 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
327 /* Hole */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out"),
339 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
340 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
341 SUNXI_FUNCTION(0x0, "gpio_in"),
342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
344 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
345 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
346 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
347 SUNXI_FUNCTION(0x0, "gpio_in"),
348 SUNXI_FUNCTION(0x1, "gpio_out"),
349 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
350 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
351 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
352 /* Hole */
353 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
354 SUNXI_FUNCTION(0x0, "gpio_in"),
355 SUNXI_FUNCTION(0x1, "gpio_out"),
356 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
357 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
358 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
363 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
364 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
365 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
366 SUNXI_FUNCTION(0x0, "gpio_in"),
367 SUNXI_FUNCTION(0x1, "gpio_out"),
368 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
369 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
370 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
375 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
376 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
377};
378
379static const struct sunxi_desc_pin sun6i_a31_pins[] = { 18static const struct sunxi_desc_pin sun6i_a31_pins[] = {
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), 19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
381 SUNXI_FUNCTION(0x0, "gpio_in"), 20 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -2274,11 +1913,6 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2274 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ 1913 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
2275}; 1914};
2276 1915
2277static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
2278 .pins = sun5i_a13_pins,
2279 .npins = ARRAY_SIZE(sun5i_a13_pins),
2280};
2281
2282static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { 1916static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
2283 .pins = sun6i_a31_pins, 1917 .pins = sun6i_a31_pins,
2284 .npins = ARRAY_SIZE(sun6i_a31_pins), 1918 .npins = ARRAY_SIZE(sun6i_a31_pins),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 1cfcd6e5cf76..a339482655fe 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -674,7 +674,6 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
674} 674}
675 675
676static struct of_device_id sunxi_pinctrl_match[] = { 676static struct of_device_id sunxi_pinctrl_match[] = {
677 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
678 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data }, 677 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
679 { .compatible = "allwinner,sun6i-a31-r-pinctrl", .data = (void *)&sun6i_a31_r_pinctrl_data }, 678 { .compatible = "allwinner,sun6i-a31-r-pinctrl", .data = (void *)&sun6i_a31_r_pinctrl_data },
680 { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data }, 679 { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 16:12:16 -0500