diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2013-07-23 19:47:29 -0400 |
---|---|---|
committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2013-07-29 09:52:12 -0400 |
commit | 457c11d3e89f7c874d793b05a1c808f64d5f896f (patch) | |
tree | db7c2a3870b49dfd416287269e16ef14d34201fe /drivers/pinctrl/sh-pfc | |
parent | 0a664e3d7978f54af72277a969245ac5e6418cd9 (diff) |
sh-pfc: r8a7790: Sort pin groups and functions alphabetically
Navigating through the source code is hard enough without having to
manually search for groups and functions.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/pinctrl/sh-pfc')
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 530 |
1 files changed, 265 insertions, 265 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 62ac0d20c2df..7f7b2bde62f3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c | |||
@@ -1814,128 +1814,6 @@ static const unsigned int eth_rmii_mux[] = { | |||
1814 | ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, | 1814 | ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, |
1815 | ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, | 1815 | ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, |
1816 | }; | 1816 | }; |
1817 | /* - INTC ------------------------------------------------------------------- */ | ||
1818 | static const unsigned int intc_irq0_pins[] = { | ||
1819 | /* IRQ */ | ||
1820 | RCAR_GP_PIN(1, 25), | ||
1821 | }; | ||
1822 | static const unsigned int intc_irq0_mux[] = { | ||
1823 | IRQ0_MARK, | ||
1824 | }; | ||
1825 | static const unsigned int intc_irq1_pins[] = { | ||
1826 | /* IRQ */ | ||
1827 | RCAR_GP_PIN(1, 27), | ||
1828 | }; | ||
1829 | static const unsigned int intc_irq1_mux[] = { | ||
1830 | IRQ1_MARK, | ||
1831 | }; | ||
1832 | static const unsigned int intc_irq2_pins[] = { | ||
1833 | /* IRQ */ | ||
1834 | RCAR_GP_PIN(1, 29), | ||
1835 | }; | ||
1836 | static const unsigned int intc_irq2_mux[] = { | ||
1837 | IRQ2_MARK, | ||
1838 | }; | ||
1839 | static const unsigned int intc_irq3_pins[] = { | ||
1840 | /* IRQ */ | ||
1841 | RCAR_GP_PIN(1, 23), | ||
1842 | }; | ||
1843 | static const unsigned int intc_irq3_mux[] = { | ||
1844 | IRQ3_MARK, | ||
1845 | }; | ||
1846 | /* - SCIF0 ----------------------------------------------------------------- */ | ||
1847 | static const unsigned int scif0_data_pins[] = { | ||
1848 | /* RX, TX */ | ||
1849 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | ||
1850 | }; | ||
1851 | static const unsigned int scif0_data_mux[] = { | ||
1852 | RX0_MARK, TX0_MARK, | ||
1853 | }; | ||
1854 | static const unsigned int scif0_clk_pins[] = { | ||
1855 | /* SCK */ | ||
1856 | RCAR_GP_PIN(4, 27), | ||
1857 | }; | ||
1858 | static const unsigned int scif0_clk_mux[] = { | ||
1859 | SCK0_MARK, | ||
1860 | }; | ||
1861 | static const unsigned int scif0_ctrl_pins[] = { | ||
1862 | /* RTS, CTS */ | ||
1863 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | ||
1864 | }; | ||
1865 | static const unsigned int scif0_ctrl_mux[] = { | ||
1866 | RTS0_N_MARK, CTS0_N_MARK, | ||
1867 | }; | ||
1868 | static const unsigned int scif0_data_b_pins[] = { | ||
1869 | /* RX, TX */ | ||
1870 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
1871 | }; | ||
1872 | static const unsigned int scif0_data_b_mux[] = { | ||
1873 | RX0_B_MARK, TX0_B_MARK, | ||
1874 | }; | ||
1875 | /* - SCIF1 ----------------------------------------------------------------- */ | ||
1876 | static const unsigned int scif1_data_pins[] = { | ||
1877 | /* RX, TX */ | ||
1878 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), | ||
1879 | }; | ||
1880 | static const unsigned int scif1_data_mux[] = { | ||
1881 | RX1_MARK, TX1_MARK, | ||
1882 | }; | ||
1883 | static const unsigned int scif1_clk_pins[] = { | ||
1884 | /* SCK */ | ||
1885 | RCAR_GP_PIN(4, 20), | ||
1886 | }; | ||
1887 | static const unsigned int scif1_clk_mux[] = { | ||
1888 | SCK1_MARK, | ||
1889 | }; | ||
1890 | static const unsigned int scif1_ctrl_pins[] = { | ||
1891 | /* RTS, CTS */ | ||
1892 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), | ||
1893 | }; | ||
1894 | static const unsigned int scif1_ctrl_mux[] = { | ||
1895 | RTS1_N_MARK, CTS1_N_MARK, | ||
1896 | }; | ||
1897 | static const unsigned int scif1_data_b_pins[] = { | ||
1898 | /* RX, TX */ | ||
1899 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
1900 | }; | ||
1901 | static const unsigned int scif1_data_b_mux[] = { | ||
1902 | RX1_B_MARK, TX1_B_MARK, | ||
1903 | }; | ||
1904 | static const unsigned int scif1_data_c_pins[] = { | ||
1905 | /* RX, TX */ | ||
1906 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | ||
1907 | }; | ||
1908 | static const unsigned int scif1_data_c_mux[] = { | ||
1909 | RX1_C_MARK, TX1_C_MARK, | ||
1910 | }; | ||
1911 | static const unsigned int scif1_data_d_pins[] = { | ||
1912 | /* RX, TX */ | ||
1913 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | ||
1914 | }; | ||
1915 | static const unsigned int scif1_data_d_mux[] = { | ||
1916 | RX1_D_MARK, TX1_D_MARK, | ||
1917 | }; | ||
1918 | static const unsigned int scif1_clk_d_pins[] = { | ||
1919 | /* SCK */ | ||
1920 | RCAR_GP_PIN(3, 17), | ||
1921 | }; | ||
1922 | static const unsigned int scif1_clk_d_mux[] = { | ||
1923 | SCK1_D_MARK, | ||
1924 | }; | ||
1925 | static const unsigned int scif1_data_e_pins[] = { | ||
1926 | /* RX, TX */ | ||
1927 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | ||
1928 | }; | ||
1929 | static const unsigned int scif1_data_e_mux[] = { | ||
1930 | RX1_E_MARK, TX1_E_MARK, | ||
1931 | }; | ||
1932 | static const unsigned int scif1_clk_e_pins[] = { | ||
1933 | /* SCK */ | ||
1934 | RCAR_GP_PIN(2, 20), | ||
1935 | }; | ||
1936 | static const unsigned int scif1_clk_e_mux[] = { | ||
1937 | SCK1_E_MARK, | ||
1938 | }; | ||
1939 | /* - HSCIF0 ----------------------------------------------------------------- */ | 1817 | /* - HSCIF0 ----------------------------------------------------------------- */ |
1940 | static const unsigned int hscif0_data_pins[] = { | 1818 | static const unsigned int hscif0_data_pins[] = { |
1941 | /* RX, TX */ | 1819 | /* RX, TX */ |
@@ -2071,6 +1949,196 @@ static const unsigned int hscif1_ctrl_b_pins[] = { | |||
2071 | static const unsigned int hscif1_ctrl_b_mux[] = { | 1949 | static const unsigned int hscif1_ctrl_b_mux[] = { |
2072 | HRTS1_N_B_MARK, HCTS1_N_B_MARK, | 1950 | HRTS1_N_B_MARK, HCTS1_N_B_MARK, |
2073 | }; | 1951 | }; |
1952 | /* - INTC ------------------------------------------------------------------- */ | ||
1953 | static const unsigned int intc_irq0_pins[] = { | ||
1954 | /* IRQ */ | ||
1955 | RCAR_GP_PIN(1, 25), | ||
1956 | }; | ||
1957 | static const unsigned int intc_irq0_mux[] = { | ||
1958 | IRQ0_MARK, | ||
1959 | }; | ||
1960 | static const unsigned int intc_irq1_pins[] = { | ||
1961 | /* IRQ */ | ||
1962 | RCAR_GP_PIN(1, 27), | ||
1963 | }; | ||
1964 | static const unsigned int intc_irq1_mux[] = { | ||
1965 | IRQ1_MARK, | ||
1966 | }; | ||
1967 | static const unsigned int intc_irq2_pins[] = { | ||
1968 | /* IRQ */ | ||
1969 | RCAR_GP_PIN(1, 29), | ||
1970 | }; | ||
1971 | static const unsigned int intc_irq2_mux[] = { | ||
1972 | IRQ2_MARK, | ||
1973 | }; | ||
1974 | static const unsigned int intc_irq3_pins[] = { | ||
1975 | /* IRQ */ | ||
1976 | RCAR_GP_PIN(1, 23), | ||
1977 | }; | ||
1978 | static const unsigned int intc_irq3_mux[] = { | ||
1979 | IRQ3_MARK, | ||
1980 | }; | ||
1981 | /* - MMCIF0 ----------------------------------------------------------------- */ | ||
1982 | static const unsigned int mmc0_data1_pins[] = { | ||
1983 | /* D[0] */ | ||
1984 | RCAR_GP_PIN(3, 18), | ||
1985 | }; | ||
1986 | static const unsigned int mmc0_data1_mux[] = { | ||
1987 | MMC0_D0_MARK, | ||
1988 | }; | ||
1989 | static const unsigned int mmc0_data4_pins[] = { | ||
1990 | /* D[0:3] */ | ||
1991 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | ||
1992 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | ||
1993 | }; | ||
1994 | static const unsigned int mmc0_data4_mux[] = { | ||
1995 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | ||
1996 | }; | ||
1997 | static const unsigned int mmc0_data8_pins[] = { | ||
1998 | /* D[0:7] */ | ||
1999 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | ||
2000 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | ||
2001 | RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), | ||
2002 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | ||
2003 | }; | ||
2004 | static const unsigned int mmc0_data8_mux[] = { | ||
2005 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | ||
2006 | MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, | ||
2007 | }; | ||
2008 | static const unsigned int mmc0_ctrl_pins[] = { | ||
2009 | /* CLK, CMD */ | ||
2010 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), | ||
2011 | }; | ||
2012 | static const unsigned int mmc0_ctrl_mux[] = { | ||
2013 | MMC0_CLK_MARK, MMC0_CMD_MARK, | ||
2014 | }; | ||
2015 | /* - MMCIF1 ----------------------------------------------------------------- */ | ||
2016 | static const unsigned int mmc1_data1_pins[] = { | ||
2017 | /* D[0] */ | ||
2018 | RCAR_GP_PIN(3, 26), | ||
2019 | }; | ||
2020 | static const unsigned int mmc1_data1_mux[] = { | ||
2021 | MMC1_D0_MARK, | ||
2022 | }; | ||
2023 | static const unsigned int mmc1_data4_pins[] = { | ||
2024 | /* D[0:3] */ | ||
2025 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | ||
2026 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | ||
2027 | }; | ||
2028 | static const unsigned int mmc1_data4_mux[] = { | ||
2029 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | ||
2030 | }; | ||
2031 | static const unsigned int mmc1_data8_pins[] = { | ||
2032 | /* D[0:7] */ | ||
2033 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | ||
2034 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | ||
2035 | RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), | ||
2036 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | ||
2037 | }; | ||
2038 | static const unsigned int mmc1_data8_mux[] = { | ||
2039 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | ||
2040 | MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, | ||
2041 | }; | ||
2042 | static const unsigned int mmc1_ctrl_pins[] = { | ||
2043 | /* CLK, CMD */ | ||
2044 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), | ||
2045 | }; | ||
2046 | static const unsigned int mmc1_ctrl_mux[] = { | ||
2047 | MMC1_CLK_MARK, MMC1_CMD_MARK, | ||
2048 | }; | ||
2049 | /* - SCIF0 ------------------------------------------------------------------ */ | ||
2050 | static const unsigned int scif0_data_pins[] = { | ||
2051 | /* RX, TX */ | ||
2052 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | ||
2053 | }; | ||
2054 | static const unsigned int scif0_data_mux[] = { | ||
2055 | RX0_MARK, TX0_MARK, | ||
2056 | }; | ||
2057 | static const unsigned int scif0_clk_pins[] = { | ||
2058 | /* SCK */ | ||
2059 | RCAR_GP_PIN(4, 27), | ||
2060 | }; | ||
2061 | static const unsigned int scif0_clk_mux[] = { | ||
2062 | SCK0_MARK, | ||
2063 | }; | ||
2064 | static const unsigned int scif0_ctrl_pins[] = { | ||
2065 | /* RTS, CTS */ | ||
2066 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | ||
2067 | }; | ||
2068 | static const unsigned int scif0_ctrl_mux[] = { | ||
2069 | RTS0_N_MARK, CTS0_N_MARK, | ||
2070 | }; | ||
2071 | static const unsigned int scif0_data_b_pins[] = { | ||
2072 | /* RX, TX */ | ||
2073 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
2074 | }; | ||
2075 | static const unsigned int scif0_data_b_mux[] = { | ||
2076 | RX0_B_MARK, TX0_B_MARK, | ||
2077 | }; | ||
2078 | /* - SCIF1 ------------------------------------------------------------------ */ | ||
2079 | static const unsigned int scif1_data_pins[] = { | ||
2080 | /* RX, TX */ | ||
2081 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), | ||
2082 | }; | ||
2083 | static const unsigned int scif1_data_mux[] = { | ||
2084 | RX1_MARK, TX1_MARK, | ||
2085 | }; | ||
2086 | static const unsigned int scif1_clk_pins[] = { | ||
2087 | /* SCK */ | ||
2088 | RCAR_GP_PIN(4, 20), | ||
2089 | }; | ||
2090 | static const unsigned int scif1_clk_mux[] = { | ||
2091 | SCK1_MARK, | ||
2092 | }; | ||
2093 | static const unsigned int scif1_ctrl_pins[] = { | ||
2094 | /* RTS, CTS */ | ||
2095 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), | ||
2096 | }; | ||
2097 | static const unsigned int scif1_ctrl_mux[] = { | ||
2098 | RTS1_N_MARK, CTS1_N_MARK, | ||
2099 | }; | ||
2100 | static const unsigned int scif1_data_b_pins[] = { | ||
2101 | /* RX, TX */ | ||
2102 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
2103 | }; | ||
2104 | static const unsigned int scif1_data_b_mux[] = { | ||
2105 | RX1_B_MARK, TX1_B_MARK, | ||
2106 | }; | ||
2107 | static const unsigned int scif1_data_c_pins[] = { | ||
2108 | /* RX, TX */ | ||
2109 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | ||
2110 | }; | ||
2111 | static const unsigned int scif1_data_c_mux[] = { | ||
2112 | RX1_C_MARK, TX1_C_MARK, | ||
2113 | }; | ||
2114 | static const unsigned int scif1_data_d_pins[] = { | ||
2115 | /* RX, TX */ | ||
2116 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | ||
2117 | }; | ||
2118 | static const unsigned int scif1_data_d_mux[] = { | ||
2119 | RX1_D_MARK, TX1_D_MARK, | ||
2120 | }; | ||
2121 | static const unsigned int scif1_clk_d_pins[] = { | ||
2122 | /* SCK */ | ||
2123 | RCAR_GP_PIN(3, 17), | ||
2124 | }; | ||
2125 | static const unsigned int scif1_clk_d_mux[] = { | ||
2126 | SCK1_D_MARK, | ||
2127 | }; | ||
2128 | static const unsigned int scif1_data_e_pins[] = { | ||
2129 | /* RX, TX */ | ||
2130 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | ||
2131 | }; | ||
2132 | static const unsigned int scif1_data_e_mux[] = { | ||
2133 | RX1_E_MARK, TX1_E_MARK, | ||
2134 | }; | ||
2135 | static const unsigned int scif1_clk_e_pins[] = { | ||
2136 | /* SCK */ | ||
2137 | RCAR_GP_PIN(2, 20), | ||
2138 | }; | ||
2139 | static const unsigned int scif1_clk_e_mux[] = { | ||
2140 | SCK1_E_MARK, | ||
2141 | }; | ||
2074 | /* - SCIFA0 ----------------------------------------------------------------- */ | 2142 | /* - SCIFA0 ----------------------------------------------------------------- */ |
2075 | static const unsigned int scifa0_data_pins[] = { | 2143 | static const unsigned int scifa0_data_pins[] = { |
2076 | /* RXD, TXD */ | 2144 | /* RXD, TXD */ |
@@ -2434,103 +2502,6 @@ static const unsigned int scifb2_data_c_pins[] = { | |||
2434 | static const unsigned int scifb2_data_c_mux[] = { | 2502 | static const unsigned int scifb2_data_c_mux[] = { |
2435 | SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, | 2503 | SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, |
2436 | }; | 2504 | }; |
2437 | /* - TPU0 ------------------------------------------------------------------- */ | ||
2438 | static const unsigned int tpu0_to0_pins[] = { | ||
2439 | /* TO */ | ||
2440 | RCAR_GP_PIN(0, 20), | ||
2441 | }; | ||
2442 | static const unsigned int tpu0_to0_mux[] = { | ||
2443 | TPU0TO0_MARK, | ||
2444 | }; | ||
2445 | static const unsigned int tpu0_to1_pins[] = { | ||
2446 | /* TO */ | ||
2447 | RCAR_GP_PIN(0, 21), | ||
2448 | }; | ||
2449 | static const unsigned int tpu0_to1_mux[] = { | ||
2450 | TPU0TO1_MARK, | ||
2451 | }; | ||
2452 | static const unsigned int tpu0_to2_pins[] = { | ||
2453 | /* TO */ | ||
2454 | RCAR_GP_PIN(0, 22), | ||
2455 | }; | ||
2456 | static const unsigned int tpu0_to2_mux[] = { | ||
2457 | TPU0TO2_MARK, | ||
2458 | }; | ||
2459 | static const unsigned int tpu0_to3_pins[] = { | ||
2460 | /* TO */ | ||
2461 | RCAR_GP_PIN(0, 23), | ||
2462 | }; | ||
2463 | static const unsigned int tpu0_to3_mux[] = { | ||
2464 | TPU0TO3_MARK, | ||
2465 | }; | ||
2466 | /* - MMCIF0 ----------------------------------------------------------------- */ | ||
2467 | static const unsigned int mmc0_data1_pins[] = { | ||
2468 | /* D[0] */ | ||
2469 | RCAR_GP_PIN(3, 18), | ||
2470 | }; | ||
2471 | static const unsigned int mmc0_data1_mux[] = { | ||
2472 | MMC0_D0_MARK, | ||
2473 | }; | ||
2474 | static const unsigned int mmc0_data4_pins[] = { | ||
2475 | /* D[0:3] */ | ||
2476 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | ||
2477 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | ||
2478 | }; | ||
2479 | static const unsigned int mmc0_data4_mux[] = { | ||
2480 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | ||
2481 | }; | ||
2482 | static const unsigned int mmc0_data8_pins[] = { | ||
2483 | /* D[0:7] */ | ||
2484 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | ||
2485 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | ||
2486 | RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), | ||
2487 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | ||
2488 | }; | ||
2489 | static const unsigned int mmc0_data8_mux[] = { | ||
2490 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | ||
2491 | MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, | ||
2492 | }; | ||
2493 | static const unsigned int mmc0_ctrl_pins[] = { | ||
2494 | /* CLK, CMD */ | ||
2495 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), | ||
2496 | }; | ||
2497 | static const unsigned int mmc0_ctrl_mux[] = { | ||
2498 | MMC0_CLK_MARK, MMC0_CMD_MARK, | ||
2499 | }; | ||
2500 | /* - MMCIF1 ----------------------------------------------------------------- */ | ||
2501 | static const unsigned int mmc1_data1_pins[] = { | ||
2502 | /* D[0] */ | ||
2503 | RCAR_GP_PIN(3, 26), | ||
2504 | }; | ||
2505 | static const unsigned int mmc1_data1_mux[] = { | ||
2506 | MMC1_D0_MARK, | ||
2507 | }; | ||
2508 | static const unsigned int mmc1_data4_pins[] = { | ||
2509 | /* D[0:3] */ | ||
2510 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | ||
2511 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | ||
2512 | }; | ||
2513 | static const unsigned int mmc1_data4_mux[] = { | ||
2514 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | ||
2515 | }; | ||
2516 | static const unsigned int mmc1_data8_pins[] = { | ||
2517 | /* D[0:7] */ | ||
2518 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | ||
2519 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | ||
2520 | RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), | ||
2521 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | ||
2522 | }; | ||
2523 | static const unsigned int mmc1_data8_mux[] = { | ||
2524 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | ||
2525 | MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, | ||
2526 | }; | ||
2527 | static const unsigned int mmc1_ctrl_pins[] = { | ||
2528 | /* CLK, CMD */ | ||
2529 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), | ||
2530 | }; | ||
2531 | static const unsigned int mmc1_ctrl_mux[] = { | ||
2532 | MMC1_CLK_MARK, MMC1_CMD_MARK, | ||
2533 | }; | ||
2534 | /* - SDHI0 ------------------------------------------------------------------ */ | 2505 | /* - SDHI0 ------------------------------------------------------------------ */ |
2535 | static const unsigned int sdhi0_data1_pins[] = { | 2506 | static const unsigned int sdhi0_data1_pins[] = { |
2536 | /* D0 */ | 2507 | /* D0 */ |
@@ -2675,6 +2646,35 @@ static const unsigned int sdhi3_wp_pins[] = { | |||
2675 | static const unsigned int sdhi3_wp_mux[] = { | 2646 | static const unsigned int sdhi3_wp_mux[] = { |
2676 | SD3_WP_MARK, | 2647 | SD3_WP_MARK, |
2677 | }; | 2648 | }; |
2649 | /* - TPU0 ------------------------------------------------------------------- */ | ||
2650 | static const unsigned int tpu0_to0_pins[] = { | ||
2651 | /* TO */ | ||
2652 | RCAR_GP_PIN(0, 20), | ||
2653 | }; | ||
2654 | static const unsigned int tpu0_to0_mux[] = { | ||
2655 | TPU0TO0_MARK, | ||
2656 | }; | ||
2657 | static const unsigned int tpu0_to1_pins[] = { | ||
2658 | /* TO */ | ||
2659 | RCAR_GP_PIN(0, 21), | ||
2660 | }; | ||
2661 | static const unsigned int tpu0_to1_mux[] = { | ||
2662 | TPU0TO1_MARK, | ||
2663 | }; | ||
2664 | static const unsigned int tpu0_to2_pins[] = { | ||
2665 | /* TO */ | ||
2666 | RCAR_GP_PIN(0, 22), | ||
2667 | }; | ||
2668 | static const unsigned int tpu0_to2_mux[] = { | ||
2669 | TPU0TO2_MARK, | ||
2670 | }; | ||
2671 | static const unsigned int tpu0_to3_pins[] = { | ||
2672 | /* TO */ | ||
2673 | RCAR_GP_PIN(0, 23), | ||
2674 | }; | ||
2675 | static const unsigned int tpu0_to3_mux[] = { | ||
2676 | TPU0TO3_MARK, | ||
2677 | }; | ||
2678 | 2678 | ||
2679 | static const struct sh_pfc_pin_group pinmux_groups[] = { | 2679 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
2680 | SH_PFC_PIN_GROUP(eth_link), | 2680 | SH_PFC_PIN_GROUP(eth_link), |
@@ -2809,6 +2809,31 @@ static const char * const eth_groups[] = { | |||
2809 | "eth_rmii", | 2809 | "eth_rmii", |
2810 | }; | 2810 | }; |
2811 | 2811 | ||
2812 | static const char * const hscif0_groups[] = { | ||
2813 | "hscif0_data", | ||
2814 | "hscif0_clk", | ||
2815 | "hscif0_ctrl", | ||
2816 | "hscif0_data_b", | ||
2817 | "hscif0_ctrl_b", | ||
2818 | "hscif0_data_c", | ||
2819 | "hscif0_ctrl_c", | ||
2820 | "hscif0_data_d", | ||
2821 | "hscif0_ctrl_d", | ||
2822 | "hscif0_data_e", | ||
2823 | "hscif0_ctrl_e", | ||
2824 | "hscif0_data_f", | ||
2825 | "hscif0_ctrl_f", | ||
2826 | }; | ||
2827 | |||
2828 | static const char * const hscif1_groups[] = { | ||
2829 | "hscif1_data", | ||
2830 | "hscif1_clk", | ||
2831 | "hscif1_ctrl", | ||
2832 | "hscif1_data_b", | ||
2833 | "hscif1_clk_b", | ||
2834 | "hscif1_ctrl_b", | ||
2835 | }; | ||
2836 | |||
2812 | static const char * const intc_groups[] = { | 2837 | static const char * const intc_groups[] = { |
2813 | "intc_irq0", | 2838 | "intc_irq0", |
2814 | "intc_irq1", | 2839 | "intc_irq1", |
@@ -2816,6 +2841,20 @@ static const char * const intc_groups[] = { | |||
2816 | "intc_irq3", | 2841 | "intc_irq3", |
2817 | }; | 2842 | }; |
2818 | 2843 | ||
2844 | static const char * const mmc0_groups[] = { | ||
2845 | "mmc0_data1", | ||
2846 | "mmc0_data4", | ||
2847 | "mmc0_data8", | ||
2848 | "mmc0_ctrl", | ||
2849 | }; | ||
2850 | |||
2851 | static const char * const mmc1_groups[] = { | ||
2852 | "mmc1_data1", | ||
2853 | "mmc1_data4", | ||
2854 | "mmc1_data8", | ||
2855 | "mmc1_ctrl", | ||
2856 | }; | ||
2857 | |||
2819 | static const char * const scif0_groups[] = { | 2858 | static const char * const scif0_groups[] = { |
2820 | "scif0_data", | 2859 | "scif0_data", |
2821 | "scif0_clk", | 2860 | "scif0_clk", |
@@ -2835,31 +2874,6 @@ static const char * const scif1_groups[] = { | |||
2835 | "scif1_clk_e", | 2874 | "scif1_clk_e", |
2836 | }; | 2875 | }; |
2837 | 2876 | ||
2838 | static const char * const hscif0_groups[] = { | ||
2839 | "hscif0_data", | ||
2840 | "hscif0_clk", | ||
2841 | "hscif0_ctrl", | ||
2842 | "hscif0_data_b", | ||
2843 | "hscif0_ctrl_b", | ||
2844 | "hscif0_data_c", | ||
2845 | "hscif0_ctrl_c", | ||
2846 | "hscif0_data_d", | ||
2847 | "hscif0_ctrl_d", | ||
2848 | "hscif0_data_e", | ||
2849 | "hscif0_ctrl_e", | ||
2850 | "hscif0_data_f", | ||
2851 | "hscif0_ctrl_f", | ||
2852 | }; | ||
2853 | |||
2854 | static const char * const hscif1_groups[] = { | ||
2855 | "hscif1_data", | ||
2856 | "hscif1_clk", | ||
2857 | "hscif1_ctrl", | ||
2858 | "hscif1_data_b", | ||
2859 | "hscif1_clk_b", | ||
2860 | "hscif1_ctrl_b", | ||
2861 | }; | ||
2862 | |||
2863 | static const char * const scifa0_groups[] = { | 2877 | static const char * const scifa0_groups[] = { |
2864 | "scifa0_data", | 2878 | "scifa0_data", |
2865 | "scifa0_clk", | 2879 | "scifa0_clk", |
@@ -2929,27 +2943,6 @@ static const char * const scifb2_groups[] = { | |||
2929 | "scifb2_data_c", | 2943 | "scifb2_data_c", |
2930 | }; | 2944 | }; |
2931 | 2945 | ||
2932 | static const char * const tpu0_groups[] = { | ||
2933 | "tpu0_to0", | ||
2934 | "tpu0_to1", | ||
2935 | "tpu0_to2", | ||
2936 | "tpu0_to3", | ||
2937 | }; | ||
2938 | |||
2939 | static const char * const mmc0_groups[] = { | ||
2940 | "mmc0_data1", | ||
2941 | "mmc0_data4", | ||
2942 | "mmc0_data8", | ||
2943 | "mmc0_ctrl", | ||
2944 | }; | ||
2945 | |||
2946 | static const char * const mmc1_groups[] = { | ||
2947 | "mmc1_data1", | ||
2948 | "mmc1_data4", | ||
2949 | "mmc1_data8", | ||
2950 | "mmc1_ctrl", | ||
2951 | }; | ||
2952 | |||
2953 | static const char * const sdhi0_groups[] = { | 2946 | static const char * const sdhi0_groups[] = { |
2954 | "sdhi0_data1", | 2947 | "sdhi0_data1", |
2955 | "sdhi0_data4", | 2948 | "sdhi0_data4", |
@@ -2982,6 +2975,13 @@ static const char * const sdhi3_groups[] = { | |||
2982 | "sdhi3_wp", | 2975 | "sdhi3_wp", |
2983 | }; | 2976 | }; |
2984 | 2977 | ||
2978 | static const char * const tpu0_groups[] = { | ||
2979 | "tpu0_to0", | ||
2980 | "tpu0_to1", | ||
2981 | "tpu0_to2", | ||
2982 | "tpu0_to3", | ||
2983 | }; | ||
2984 | |||
2985 | static const struct sh_pfc_function pinmux_functions[] = { | 2985 | static const struct sh_pfc_function pinmux_functions[] = { |
2986 | SH_PFC_FUNCTION(eth), | 2986 | SH_PFC_FUNCTION(eth), |
2987 | SH_PFC_FUNCTION(hscif0), | 2987 | SH_PFC_FUNCTION(hscif0), |