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authorLinus Walleij <linus.walleij@linaro.org>2013-07-29 10:33:57 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-07-29 10:33:57 -0400
commitf7a3427f3eec669f5d7ff15d081433dc5621e7c9 (patch)
treee45241a56fb2b9dd88fb9a7295789686f722e331 /drivers/pinctrl/sh-pfc
parentda52faa5715d1d3596b2b05030022f3d4bc56087 (diff)
parente120cacfaac24d4de31b181371daaef6a5773ee3 (diff)
Merge branch 'pinmux/next/fixes' of git://linuxtv.org/pinchartl/fbdev into devel
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sh-pfc')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c105
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c1543
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c68
6 files changed, 1093 insertions, 629 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 05d96ae36fca..d25fd4ea0a1d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -21,7 +21,6 @@
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/pinctrl/pinconf-generic.h> 22#include <linux/pinctrl/pinconf-generic.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/r8a73a4.h>
25 24
26#include "core.h" 25#include "core.h"
27#include "sh_pfc.h" 26#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 2c745368afa3..009174d07767 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -22,7 +22,6 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinconf-generic.h>
24 24
25#include <mach/r8a7740.h>
26#include <mach/irqs.h> 25#include <mach/irqs.h>
27 26
28#include "core.h" 27#include "core.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index be832dcd8c03..d3e94e307d7f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1674,6 +1674,79 @@ static const unsigned int hspi2_b_pins[] = {
1674static const unsigned int hspi2_b_mux[] = { 1674static const unsigned int hspi2_b_mux[] = {
1675 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, 1675 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1676}; 1676};
1677/* - I2C1 ------------------------------------------------------------------ */
1678static const unsigned int i2c1_pins[] = {
1679 /* SCL, SDA, */
1680 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1681};
1682static const unsigned int i2c1_mux[] = {
1683 SCL1_MARK, SDA1_MARK,
1684};
1685static const unsigned int i2c1_b_pins[] = {
1686 /* SCL, SDA, */
1687 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1688};
1689static const unsigned int i2c1_b_mux[] = {
1690 SCL1_B_MARK, SDA1_B_MARK,
1691};
1692static const unsigned int i2c1_c_pins[] = {
1693 /* SCL, SDA, */
1694 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1695};
1696static const unsigned int i2c1_c_mux[] = {
1697 SCL1_C_MARK, SDA1_C_MARK,
1698};
1699static const unsigned int i2c1_d_pins[] = {
1700 /* SCL, SDA, */
1701 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1702};
1703static const unsigned int i2c1_d_mux[] = {
1704 SCL1_D_MARK, SDA1_D_MARK,
1705};
1706/* - I2C2 ------------------------------------------------------------------ */
1707static const unsigned int i2c2_pins[] = {
1708 /* SCL, SDA, */
1709 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
1710};
1711static const unsigned int i2c2_mux[] = {
1712 SCL2_MARK, SDA2_MARK,
1713};
1714static const unsigned int i2c2_b_pins[] = {
1715 /* SCL, SDA, */
1716 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1717};
1718static const unsigned int i2c2_b_mux[] = {
1719 SCL2_B_MARK, SDA2_B_MARK,
1720};
1721static const unsigned int i2c2_c_pins[] = {
1722 /* SCL, SDA */
1723 RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
1724};
1725static const unsigned int i2c2_c_mux[] = {
1726 SCL2_C_MARK, SDA2_C_MARK,
1727};
1728static const unsigned int i2c2_d_pins[] = {
1729 /* SCL, SDA */
1730 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
1731};
1732static const unsigned int i2c2_d_mux[] = {
1733 SCL2_D_MARK, SDA2_D_MARK,
1734};
1735/* - I2C3 ------------------------------------------------------------------ */
1736static const unsigned int i2c3_pins[] = {
1737 /* SCL, SDA, */
1738 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
1739};
1740static const unsigned int i2c3_mux[] = {
1741 SCL3_MARK, SDA3_MARK,
1742};
1743static const unsigned int i2c3_b_pins[] = {
1744 /* SCL, SDA, */
1745 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
1746};
1747static const unsigned int i2c3_b_mux[] = {
1748 SCL3_B_MARK, SDA3_B_MARK,
1749};
1677/* - INTC ------------------------------------------------------------------- */ 1750/* - INTC ------------------------------------------------------------------- */
1678static const unsigned int intc_irq0_pins[] = { 1751static const unsigned int intc_irq0_pins[] = {
1679 /* IRQ */ 1752 /* IRQ */
@@ -2543,6 +2616,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2543 SH_PFC_PIN_GROUP(hspi1_d), 2616 SH_PFC_PIN_GROUP(hspi1_d),
2544 SH_PFC_PIN_GROUP(hspi2), 2617 SH_PFC_PIN_GROUP(hspi2),
2545 SH_PFC_PIN_GROUP(hspi2_b), 2618 SH_PFC_PIN_GROUP(hspi2_b),
2619 SH_PFC_PIN_GROUP(i2c1),
2620 SH_PFC_PIN_GROUP(i2c1_b),
2621 SH_PFC_PIN_GROUP(i2c1_c),
2622 SH_PFC_PIN_GROUP(i2c1_d),
2623 SH_PFC_PIN_GROUP(i2c2),
2624 SH_PFC_PIN_GROUP(i2c2_b),
2625 SH_PFC_PIN_GROUP(i2c2_c),
2626 SH_PFC_PIN_GROUP(i2c2_d),
2627 SH_PFC_PIN_GROUP(i2c3),
2628 SH_PFC_PIN_GROUP(i2c3_b),
2546 SH_PFC_PIN_GROUP(intc_irq0), 2629 SH_PFC_PIN_GROUP(intc_irq0),
2547 SH_PFC_PIN_GROUP(intc_irq0_b), 2630 SH_PFC_PIN_GROUP(intc_irq0_b),
2548 SH_PFC_PIN_GROUP(intc_irq1), 2631 SH_PFC_PIN_GROUP(intc_irq1),
@@ -2703,6 +2786,25 @@ static const char * const hspi2_groups[] = {
2703 "hspi2_b", 2786 "hspi2_b",
2704}; 2787};
2705 2788
2789static const char * const i2c1_groups[] = {
2790 "i2c1",
2791 "i2c1_b",
2792 "i2c1_c",
2793 "i2c1_d",
2794};
2795
2796static const char * const i2c2_groups[] = {
2797 "i2c2",
2798 "i2c2_b",
2799 "i2c2_c",
2800 "i2c2_d",
2801};
2802
2803static const char * const i2c3_groups[] = {
2804 "i2c3",
2805 "i2c3_b",
2806};
2807
2706static const char * const intc_groups[] = { 2808static const char * const intc_groups[] = {
2707 "intc_irq0", 2809 "intc_irq0",
2708 "intc_irq0_b", 2810 "intc_irq0_b",
@@ -2886,6 +2988,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
2886 SH_PFC_FUNCTION(hspi0), 2988 SH_PFC_FUNCTION(hspi0),
2887 SH_PFC_FUNCTION(hspi1), 2989 SH_PFC_FUNCTION(hspi1),
2888 SH_PFC_FUNCTION(hspi2), 2990 SH_PFC_FUNCTION(hspi2),
2991 SH_PFC_FUNCTION(i2c1),
2992 SH_PFC_FUNCTION(i2c2),
2993 SH_PFC_FUNCTION(i2c3),
2889 SH_PFC_FUNCTION(intc), 2994 SH_PFC_FUNCTION(intc),
2890 SH_PFC_FUNCTION(lbsc), 2995 SH_PFC_FUNCTION(lbsc),
2891 SH_PFC_FUNCTION(mmc0), 2996 SH_PFC_FUNCTION(mmc0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 95b38fafe449..763c031e818a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -111,18 +111,18 @@ enum {
111 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, 111 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
112 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 112 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
113 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, 113 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
114 FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 114 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
115 FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, 115 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
116 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, 116 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
117 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, 117 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
118 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 118 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
119 119
120 /* IPSR1 */ 120 /* IPSR1 */
121 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, 121 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
122 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, 122 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
123 FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, 123 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
124 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, 124 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
125 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, 125 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
126 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 126 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
127 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 127 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
128 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 128 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
@@ -141,9 +141,9 @@ enum {
141 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, 141 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
142 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 142 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
143 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 143 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
144 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, 144 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
145 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 145 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
146 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, 146 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
147 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 147 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
148 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 148 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
149 149
@@ -182,11 +182,11 @@ enum {
182 /* IPSR5 */ 182 /* IPSR5 */
183 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 183 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
184 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 184 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
185 FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, 185 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
186 FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, 186 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
187 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, 187 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
188 FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, 188 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
189 FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, 189 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
190 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, 190 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
191 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, 191 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
192 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 192 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
@@ -209,29 +209,29 @@ enum {
209 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, 209 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
210 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 210 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
211 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 211 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
212 FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, 212 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
213 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, 213 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
214 FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, 214 FN_I2C2_SCL_E, FN_ETH_RX_ER,
215 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, 215 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
216 FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, 216 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
217 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, 217 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
218 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, 218 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
219 FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, 219 FN_HRX0_E, FN_STP_ISSYNC_0_B,
220 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, 220 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
221 FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, 221 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
222 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 222 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
223 FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, 223 FN_ETH_REF_CLK, FN_HCTS0_N_E,
224 FN_STP_IVCXO27_1_B, FN_HRX0_F, 224 FN_STP_IVCXO27_1_B, FN_HRX0_F,
225 225
226 /* IPSR7 */ 226 /* IPSR7 */
227 FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, 227 FN_ETH_MDIO, FN_HRTS0_N_E,
228 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, 228 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
229 FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, 229 FN_HTX0_F, FN_BPFCLK_G,
230 FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, 230 FN_ETH_TX_EN, FN_SIM0_CLK_C,
231 FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, 231 FN_HRTS0_N_F, FN_ETH_MAGIC,
232 FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, 232 FN_SIM0_RST_C, FN_ETH_TXD0,
233 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, 233 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
234 FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, 234 FN_ETH_MDC, FN_STP_ISD_1_B,
235 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, 235 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
236 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 236 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
237 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, 237 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
@@ -239,26 +239,25 @@ enum {
239 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, 239 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
240 FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, 240 FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
241 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, 241 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
242 FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, 242 FN_ATACS00_N, FN_AVB_RXD1,
243 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 243 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
244 FN_MII_RXD2,
245 244
246 /* IPSR8 */ 245 /* IPSR8 */
247 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 246 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
248 FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, 247 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
249 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, 248 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
250 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, 249 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
251 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, 250 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
252 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 251 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
253 FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 252 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
254 FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, 253 FN_VI1_CLK, FN_AVB_RX_DV,
255 FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, 254 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
256 FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, 255 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
257 FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, 256 FN_SCIFA1_RXD_D, FN_AVB_MDC,
258 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 257 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
259 FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, 258 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
260 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 259 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
261 FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, 260 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
262 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 261 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
263 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, 262 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
264 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 263 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
@@ -269,26 +268,26 @@ enum {
269 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 268 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
270 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 269 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
271 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 270 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
272 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, 271 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
273 FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, 272 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
274 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 273 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
275 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, 274 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
276 FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, 275 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
277 FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, 276 FN_AVB_TX_EN, FN_SD1_CMD,
278 FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, 277 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
279 FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, 278 FN_SD1_DAT0, FN_AVB_TX_CLK,
280 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, 279 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
281 FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, 280 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
282 FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, 281 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
283 FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, 282 FN_SD1_DAT3, FN_AVB_RXD0,
284 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, 283 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
285 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, 284 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
286 FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, 285 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
287 FN_VI3_CLK_B, 286 FN_VI3_CLK_B,
288 287
289 /* IPSR10 */ 288 /* IPSR10 */
290 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 289 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
291 FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, 290 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
292 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 291 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
293 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 292 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
294 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 293 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
@@ -297,10 +296,10 @@ enum {
297 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 296 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
298 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 297 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
299 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 298 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
300 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, 299 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
301 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 300 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
302 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 301 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
303 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, 302 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
304 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 303 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
305 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, 304 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
306 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 305 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
@@ -321,12 +320,12 @@ enum {
321 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 320 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
322 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, 321 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
323 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 322 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
324 FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, 323 FN_FMIN_E, FN_FMIN_F,
325 FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 324 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
326 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, 325 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
327 FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, 326 FN_I2C2_SDA_B, FN_MLB_DAT,
328 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 327 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
329 FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, 328 FN_SSI_SCK0129, FN_CAN_CLK_B,
330 FN_MOUT0, 329 FN_MOUT0,
331 330
332 /* IPSR12 */ 331 /* IPSR12 */
@@ -353,12 +352,12 @@ enum {
353 /* IPSR13 */ 352 /* IPSR13 */
354 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 353 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
355 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, 354 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
356 FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, 355 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
357 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 356 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
358 FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6, 357 FN_BPFCLK_F, FN_SSI_WS6,
359 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 358 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
360 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, 359 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
361 FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, 360 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
362 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, 361 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
363 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, 362 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
364 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, 363 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
@@ -366,8 +365,8 @@ enum {
366 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, 365 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
367 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 366 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
368 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, 367 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
369 FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B, 368 FN_BPFCLK_E, FN_SSI_SDATA7_B,
370 FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8, 369 FN_FMIN_G, FN_SSI_SDATA8,
371 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 370 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
372 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, 371 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
373 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 372 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
@@ -378,29 +377,29 @@ enum {
378 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 377 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
379 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 378 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
380 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, 379 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
381 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, 380 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
382 FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, 381 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
383 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, 382 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
384 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, 383 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
385 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, 384 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
386 FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, 385 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
387 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, 386 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
388 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 387 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
389 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 388 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
390 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 389 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
391 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 390 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
392 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, 391 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
393 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, 392 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
394 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, 393 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
395 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 394 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
396 FN_HRTS0_N_C, 395 FN_HRTS0_N_C,
397 396
398 /* IPSR15 */ 397 /* IPSR15 */
399 FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, 398 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
400 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, 399 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
401 FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, 400 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
402 FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, 401 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
403 FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, 402 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
404 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, 403 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
405 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, 404 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
406 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, 405 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
@@ -408,7 +407,7 @@ enum {
408 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 407 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
409 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, 408 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
410 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, 409 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
411 FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0, 410 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
412 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, 411 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
413 FN_DU2_DG6, FN_LCDOUT14, 412 FN_DU2_DG6, FN_LCDOUT14,
414 413
@@ -416,7 +415,7 @@ enum {
416 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 415 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
417 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 416 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
418 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 417 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
419 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 418 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
420 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, 419 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
421 FN_TCLK1_B, 420 FN_TCLK1_B,
422 421
@@ -451,6 +450,7 @@ enum {
451 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 450 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
452 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 451 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
453 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 452 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
453 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
454 FN_SEL_ADI_0, FN_SEL_ADI_1, 454 FN_SEL_ADI_0, FN_SEL_ADI_1,
455 FN_SEL_SSP_0, FN_SEL_SSP_1, 455 FN_SEL_SSP_0, FN_SEL_SSP_1,
456 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 456 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
@@ -458,8 +458,6 @@ enum {
458 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, 458 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
459 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 459 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
460 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 460 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
461 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
462 FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
463 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 461 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
464 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 462 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
465 463
@@ -491,17 +489,17 @@ enum {
491 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, 489 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
492 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, 490 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
493 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, 491 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
494 SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, 492 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
495 SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, 493 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
496 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, 494 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
497 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, 495 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
498 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, 496 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
499 497
500 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, 498 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
501 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, 499 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
502 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, 500 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
503 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, 501 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
504 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, 502 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
505 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, 503 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
506 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, 504 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
507 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, 505 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
@@ -519,9 +517,9 @@ enum {
519 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, 517 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
520 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, 518 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
521 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, 519 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
522 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, 520 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
523 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, 521 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
524 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, 522 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
525 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, 523 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
526 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, 524 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
527 525
@@ -558,11 +556,11 @@ enum {
558 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, 556 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
559 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, 557 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
560 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, 558 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
561 VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, 559 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
562 INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, 560 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
563 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, 561 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
564 VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, 562 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
565 SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, 563 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
566 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, 564 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
567 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, 565 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
568 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, 566 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
@@ -584,28 +582,28 @@ enum {
584 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, 582 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
585 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, 583 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
586 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, 584 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
587 ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, 585 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
588 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, 586 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
589 SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, 587 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
590 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, 588 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
591 SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, 589 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
592 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, 590 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
593 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, 591 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
594 RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, 592 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
595 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, 593 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
596 RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, 594 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
597 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, 595 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
598 ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, 596 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
599 STP_IVCXO27_1_B_MARK, HRX0_F_MARK, 597 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
600 598
601 ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, 599 ETH_MDIO_MARK, HRTS0_N_E_MARK,
602 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, 600 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
603 RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, 601 HTX0_F_MARK, BPFCLK_G_MARK,
604 ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, 602 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
605 HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, 603 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
606 SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, 604 SIM0_RST_C_MARK, ETH_TXD0_MARK,
607 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, 605 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
608 ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, 606 ETH_MDC_MARK, STP_ISD_1_B_MARK,
609 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, 607 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
610 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, 608 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
611 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, 609 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
@@ -613,25 +611,24 @@ enum {
613 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, 611 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
614 PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, 612 PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
615 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, 613 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
616 ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, 614 ATACS00_N_MARK, AVB_RXD1_MARK,
617 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, 615 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
618 MII_RXD2_MARK,
619 616
620 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, 617 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
621 MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, 618 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
622 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, 619 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
623 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, 620 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
624 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, 621 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
625 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, 622 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
626 MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, 623 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
627 MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, 624 VI1_CLK_MARK, AVB_RX_DV_MARK,
628 MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, 625 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
629 AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, 626 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
630 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, 627 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
631 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, 628 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
632 MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, 629 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
633 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, 630 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
634 AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, 631 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
635 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, 632 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
636 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, 633 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
637 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 634 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
@@ -641,25 +638,25 @@ enum {
641 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, 638 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
642 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 639 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
643 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, 640 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
644 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, 641 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
645 SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, 642 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
646 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, 643 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
647 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, 644 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
648 SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, 645 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
649 AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, 646 AVB_TX_EN_MARK, SD1_CMD_MARK,
650 AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, 647 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
651 SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, 648 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
652 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, 649 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
653 MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, 650 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
654 AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, 651 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
655 SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, 652 SD1_DAT3_MARK, AVB_RXD0_MARK,
656 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, 653 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
657 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, 654 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
658 SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, 655 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
659 VI3_CLK_B_MARK, 656 VI3_CLK_B_MARK,
660 657
661 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, 658 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
662 GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, 659 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
663 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, 660 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
664 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, 661 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
665 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, 662 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
@@ -668,10 +665,10 @@ enum {
668 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, 665 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
669 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, 666 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
670 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, 667 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
671 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, 668 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
672 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, 669 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
673 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, 670 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
674 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, 671 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
675 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, 672 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
676 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, 673 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
677 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, 674 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
@@ -691,12 +688,12 @@ enum {
691 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, 688 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
692 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, 689 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
693 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, 690 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
694 RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, 691 FMIN_E_MARK, FMIN_F_MARK,
695 RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, 692 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
696 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, 693 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
697 SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, 694 I2C2_SDA_B_MARK, MLB_DAT_MARK,
698 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, 695 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
699 RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, 696 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
700 MOUT0_MARK, 697 MOUT0_MARK,
701 698
702 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, 699 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
@@ -721,12 +718,12 @@ enum {
721 718
722 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, 719 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
723 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, 720 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
724 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, 721 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
725 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, 722 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
726 BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, 723 BPFCLK_F_MARK, SSI_WS6_MARK,
727 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, 724 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
728 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, 725 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
729 FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, 726 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
730 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, 727 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
731 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, 728 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
732 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, 729 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
@@ -734,8 +731,8 @@ enum {
734 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, 731 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
735 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, 732 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
736 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, 733 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
737 BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, 734 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
738 FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, 735 FMIN_G_MARK, SSI_SDATA8_MARK,
739 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, 736 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
740 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, 737 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
741 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, 738 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
@@ -745,28 +742,28 @@ enum {
745 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, 742 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
746 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, 743 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
747 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, 744 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
748 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, 745 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
749 SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, 746 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
750 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, 747 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
751 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, 748 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
752 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, 749 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
753 LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, 750 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
754 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, 751 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
755 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, 752 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
756 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, 753 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
757 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 754 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
758 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, 755 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
759 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, 756 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
760 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, 757 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
761 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, 758 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
762 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, 759 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
763 HRTS0_N_C_MARK, 760 HRTS0_N_C_MARK,
764 761
765 SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, 762 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
766 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, 763 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
767 DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, 764 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
768 SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, 765 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
769 SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, 766 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
770 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, 767 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
771 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, 768 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
772 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, 769 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
@@ -774,14 +771,14 @@ enum {
774 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, 771 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
775 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, 772 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
776 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, 773 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
777 SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, 774 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
778 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, 775 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
779 DU2_DG6_MARK, LCDOUT14_MARK, 776 DU2_DG6_MARK, LCDOUT14_MARK,
780 777
781 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, 778 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
782 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, 779 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
783 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, 780 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
784 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, 781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
785 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
786 TCLK1_B_MARK, 783 TCLK1_B_MARK,
787 PINMUX_MARK_END, 784 PINMUX_MARK_END,
@@ -835,22 +832,22 @@ static const u16 pinmux_data[] = {
835 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), 832 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
836 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), 833 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
837 PINMUX_IPSR_DATA(IP0_22_20, D6), 834 PINMUX_IPSR_DATA(IP0_22_20, D6),
838 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), 835 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
839 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), 836 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
840 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), 837 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
841 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), 838 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
842 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), 839 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
843 PINMUX_IPSR_DATA(IP0_26_23, D7), 840 PINMUX_IPSR_DATA(IP0_26_23, D7),
844 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), 841 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
845 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), 842 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
846 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), 843 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
847 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), 844 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
848 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), 845 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
849 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), 846 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
847 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
850 PINMUX_IPSR_DATA(IP0_30_27, D8), 848 PINMUX_IPSR_DATA(IP0_30_27, D8),
851 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 849 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
852 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), 850 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
853 PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
854 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), 851 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
855 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), 852 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
856 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 853 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
@@ -858,21 +855,18 @@ static const u16 pinmux_data[] = {
858 PINMUX_IPSR_DATA(IP1_3_0, D9), 855 PINMUX_IPSR_DATA(IP1_3_0, D9),
859 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 856 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
860 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), 857 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
861 PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
862 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), 858 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
863 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), 859 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
864 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 860 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
865 PINMUX_IPSR_DATA(IP1_7_4, D10), 861 PINMUX_IPSR_DATA(IP1_7_4, D10),
866 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 862 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
867 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), 863 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
868 PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
869 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), 864 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
870 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), 865 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
871 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 866 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
872 PINMUX_IPSR_DATA(IP1_11_8, D11), 867 PINMUX_IPSR_DATA(IP1_11_8, D11),
873 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 868 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
874 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), 869 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
875 PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
876 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), 870 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
877 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), 871 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
878 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 872 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
@@ -883,7 +877,7 @@ static const u16 pinmux_data[] = {
883 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 877 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
884 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 878 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
885 PINMUX_IPSR_DATA(IP1_17_15, D13), 879 PINMUX_IPSR_DATA(IP1_17_15, D13),
886 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2), 880 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
887 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 881 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
888 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 882 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
889 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 883 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
@@ -931,6 +925,7 @@ static const u16 pinmux_data[] = {
931 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), 925 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
932 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), 926 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
933 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 927 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
928 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
934 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 929 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
935 PINMUX_IPSR_DATA(IP2_25_22, A9), 930 PINMUX_IPSR_DATA(IP2_25_22, A9),
936 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 931 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
@@ -938,6 +933,7 @@ static const u16 pinmux_data[] = {
938 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), 933 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
939 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), 934 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
940 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 935 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
936 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
941 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 937 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
942 PINMUX_IPSR_DATA(IP2_28_26, A10), 938 PINMUX_IPSR_DATA(IP2_28_26, A10),
943 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 939 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
@@ -952,14 +948,14 @@ static const u16 pinmux_data[] = {
952 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), 948 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
953 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), 949 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
954 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), 950 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
955 PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B), 951 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
956 PINMUX_IPSR_DATA(IP3_7_4, A12), 952 PINMUX_IPSR_DATA(IP3_7_4, A12),
957 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 953 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
958 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), 954 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
959 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), 955 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
960 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), 956 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
961 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), 957 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
962 PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B), 958 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
963 PINMUX_IPSR_DATA(IP3_11_8, A13), 959 PINMUX_IPSR_DATA(IP3_11_8, A13),
964 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 960 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
965 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), 961 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
@@ -967,7 +963,7 @@ static const u16 pinmux_data[] = {
967 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), 963 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
968 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), 964 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
969 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), 965 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
970 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0), 966 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
971 PINMUX_IPSR_DATA(IP3_14_12, A14), 967 PINMUX_IPSR_DATA(IP3_14_12, A14),
972 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 968 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
973 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), 969 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
@@ -1059,14 +1055,14 @@ static const u16 pinmux_data[] = {
1059 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), 1055 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1060 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1056 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1061 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), 1057 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1062 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0), 1058 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1059 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1064 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), 1060 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1061 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1066 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), 1062 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1067 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1063 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1068 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), 1064 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), 1065 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1070 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), 1066 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1071 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1067 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1068 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
@@ -1074,9 +1070,9 @@ static const u16 pinmux_data[] = {
1074 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), 1070 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1071 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1076 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), 1072 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1077 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), 1073 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1078 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), 1074 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), 1075 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1080 PINMUX_IPSR_DATA(IP5_12_10, BS_N), 1076 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), 1077 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1082 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1078 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
@@ -1106,7 +1102,7 @@ static const u16 pinmux_data[] = {
1106 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), 1102 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1107 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1103 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1108 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), 1104 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1109 PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0), 1105 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1110 PINMUX_IPSR_DATA(IP5_26_24, IRQ3), 1106 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1111 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), 1107 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1112 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), 1108 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
@@ -1148,28 +1144,24 @@ static const u16 pinmux_data[] = {
1148 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1144 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1149 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1145 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1150 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), 1146 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1151 PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
1152 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1147 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1153 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1148 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1154 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1149 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1155 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), 1150 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1156 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), 1151 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1157 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), 1152 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1158 PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
1159 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1153 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1160 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1154 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1161 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1155 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1162 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), 1156 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1163 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), 1157 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1164 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), 1158 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1165 PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
1166 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1159 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1167 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1160 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1168 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1161 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1169 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1162 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1170 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1163 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1171 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), 1164 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1172 PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
1173 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1165 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1174 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1166 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1175 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1167 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
@@ -1177,41 +1169,32 @@ static const u16 pinmux_data[] = {
1177 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1169 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1178 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), 1170 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1179 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), 1171 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1180 PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
1181 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1172 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1182 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1173 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1183 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1174 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1184 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), 1175 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1185 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), 1176 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1186 PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
1187 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1177 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1188 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1178 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1189 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1179 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1190 1180
1191 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), 1181 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1192 PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
1193 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1182 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1194 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1183 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1195 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1184 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1196 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), 1185 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1197 PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), 1186 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1198 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), 1187 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
1199 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
1200 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
1201 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), 1188 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1202 PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
1203 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1189 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1204 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1190 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1205 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), 1191 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1206 PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
1207 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1192 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1208 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), 1193 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1209 PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
1210 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1194 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1195 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1196 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1213 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), 1197 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1214 PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
1215 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1198 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1216 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1199 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1217 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1200 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
@@ -1237,16 +1220,13 @@ static const u16 pinmux_data[] = {
1237 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), 1220 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1238 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), 1221 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1239 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), 1222 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1240 PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
1241 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1223 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1242 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), 1224 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1243 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), 1225 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1244 PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
1245 1226
1246 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1227 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1247 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), 1228 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1248 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), 1229 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1249 PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
1250 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1230 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1251 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), 1231 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1252 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), 1232 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
@@ -1261,34 +1241,27 @@ static const u16 pinmux_data[] = {
1261 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), 1241 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1262 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1242 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1263 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), 1243 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1264 PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
1265 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1244 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1266 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), 1245 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1267 PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
1268 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), 1246 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1269 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), 1247 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1270 PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
1271 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1248 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1272 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1249 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1273 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), 1250 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1274 PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
1275 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1251 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1276 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1252 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1277 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), 1253 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1278 PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
1279 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1254 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1280 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1255 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1281 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), 1256 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1282 PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
1283 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1257 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1284 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1258 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1285 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), 1259 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1286 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1260 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1287 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1261 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1288 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), 1262 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1289 PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
1290 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1263 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1291 PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), 1264 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
1292 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1265 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1293 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), 1266 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1294 PINMUX_IPSR_DATA(IP8_28, SD0_CLK), 1267 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
@@ -1315,8 +1288,8 @@ static const u16 pinmux_data[] = {
1315 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), 1288 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1316 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1289 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1317 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1290 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1318 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), 1291 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1319 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), 1292 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1320 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1293 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1321 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), 1294 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1322 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), 1295 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
@@ -1324,31 +1297,25 @@ static const u16 pinmux_data[] = {
1324 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), 1297 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1325 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1298 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1326 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1299 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1327 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), 1300 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1328 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), 1301 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1329 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1302 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1330 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), 1303 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1331 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), 1304 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1332 PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
1333 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), 1305 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1334 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), 1306 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1335 PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
1336 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1307 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1337 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), 1308 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1338 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), 1309 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1339 PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
1340 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1310 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1341 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), 1311 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1342 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), 1312 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1343 PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
1344 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1313 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1345 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), 1314 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1346 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), 1315 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1347 PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
1348 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1316 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1349 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), 1317 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1350 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), 1318 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1351 PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
1352 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1319 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1353 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), 1320 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1354 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), 1321 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
@@ -1356,8 +1323,8 @@ static const u16 pinmux_data[] = {
1356 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), 1323 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1357 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), 1324 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1358 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1325 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1359 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), 1326 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1360 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), 1327 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1361 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1328 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1362 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1329 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1363 1330
@@ -1367,8 +1334,8 @@ static const u16 pinmux_data[] = {
1367 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), 1334 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1368 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), 1335 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1336 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), 1337 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), 1338 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1372 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1339 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1373 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), 1340 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1374 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), 1341 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
@@ -1398,7 +1365,6 @@ static const u16 pinmux_data[] = {
1398 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), 1365 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1399 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), 1366 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1400 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), 1367 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
1402 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1368 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1403 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1369 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1404 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), 1370 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
@@ -1408,7 +1374,6 @@ static const u16 pinmux_data[] = {
1408 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), 1374 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1409 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), 1375 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1410 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), 1376 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1411 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
1412 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1377 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1413 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1378 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1414 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1379 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
@@ -1471,25 +1436,20 @@ static const u16 pinmux_data[] = {
1471 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1436 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1472 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), 1437 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1473 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), 1438 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1474 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
1475 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), 1439 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1476 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
1477 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), 1440 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1478 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
1479 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), 1441 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1480 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), 1442 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1481 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), 1443 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1482 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), 1444 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1483 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1445 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1484 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), 1446 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1485 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), 1447 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1486 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), 1448 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1487 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), 1449 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1488 PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
1489 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1450 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1490 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), 1451 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1491 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), 1452 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1492 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
1493 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), 1453 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1494 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1454 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1495 PINMUX_IPSR_DATA(IP11_31_30, MOUT0), 1455 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
@@ -1505,7 +1465,7 @@ static const u16 pinmux_data[] = {
1505 PINMUX_IPSR_DATA(IP12_5_4, MOUT5), 1465 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1506 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), 1466 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1507 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1467 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1508 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1), 1468 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
1509 PINMUX_IPSR_DATA(IP12_7_6, MOUT6), 1469 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1510 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), 1470 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1511 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), 1471 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
@@ -1560,12 +1520,10 @@ static const u16 pinmux_data[] = {
1560 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1520 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1561 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1521 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1562 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), 1522 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1563 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
1564 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), 1523 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1565 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), 1524 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1566 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), 1525 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1567 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), 1526 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1568 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
1569 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1527 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1570 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1528 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1571 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1529 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
@@ -1574,7 +1532,6 @@ static const u16 pinmux_data[] = {
1574 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), 1532 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1575 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1533 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1576 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), 1534 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1577 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
1578 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), 1535 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1579 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), 1536 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1580 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), 1537 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
@@ -1600,10 +1557,8 @@ static const u16 pinmux_data[] = {
1600 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), 1557 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1601 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), 1558 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1602 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), 1559 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1603 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
1604 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1560 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1605 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), 1561 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1606 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
1607 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1562 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1608 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1563 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1609 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1564 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
@@ -1633,8 +1588,8 @@ static const u16 pinmux_data[] = {
1633 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), 1588 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1634 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), 1589 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1635 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), 1590 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1636 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), 1591 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1637 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), 1592 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1638 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1593 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1639 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), 1594 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1640 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), 1595 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
@@ -1647,16 +1602,16 @@ static const u16 pinmux_data[] = {
1647 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), 1602 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1648 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1603 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1649 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1604 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1650 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0), 1605 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
1651 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1606 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1652 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), 1607 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1653 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), 1608 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1654 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), 1609 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
1655 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), 1610 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1656 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), 1611 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1657 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1612 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1658 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1613 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1659 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), 1614 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1660 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), 1615 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1661 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), 1616 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1662 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), 1617 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
@@ -1679,7 +1634,7 @@ static const u16 pinmux_data[] = {
1679 PINMUX_IPSR_DATA(IP14_27_25, QCLK), 1634 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1680 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1635 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1681 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1636 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1682 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), 1637 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1683 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1638 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1684 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), 1639 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1685 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), 1640 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
@@ -1687,28 +1642,30 @@ static const u16 pinmux_data[] = {
1687 1642
1688 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1643 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1689 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), 1644 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1645 PINMUX_IPSR_DATA(IP15_2_0, SCK2),
1690 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1646 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1691 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), 1647 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1692 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), 1648 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1693 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), 1649 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1694 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1650 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1695 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), 1651 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1652 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
1696 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), 1653 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1697 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), 1654 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1698 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), 1655 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1699 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), 1656 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1700 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1657 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1701 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), 1658 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1659 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
1702 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), 1660 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1703 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), 1661 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1704 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), 1662 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1705 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), 1663 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1706 PINMUX_IPSR_DATA(IP15_11_9, HSCK0), 1664 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1707 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1665 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1708 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), 1666 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1709 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), 1667 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1710 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), 1668 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1711 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
1712 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), 1669 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1713 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), 1670 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1714 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), 1671 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
@@ -1734,7 +1691,7 @@ static const u16 pinmux_data[] = {
1734 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), 1691 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1735 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), 1692 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1736 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), 1693 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1737 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1), 1694 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1738 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1695 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1739 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), 1696 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1740 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), 1697 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
@@ -1757,7 +1714,7 @@ static const u16 pinmux_data[] = {
1757 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), 1714 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1758 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), 1715 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1759 PINMUX_IPSR_DATA(IP16_5_3, QPOLB), 1716 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1760 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2), 1717 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1761 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), 1718 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1762 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), 1719 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1763 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1720 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
@@ -1800,128 +1757,6 @@ static const unsigned int eth_rmii_mux[] = {
1800 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1757 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1801 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 1758 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1802}; 1759};
1803/* - INTC ------------------------------------------------------------------- */
1804static const unsigned int intc_irq0_pins[] = {
1805 /* IRQ */
1806 RCAR_GP_PIN(1, 25),
1807};
1808static const unsigned int intc_irq0_mux[] = {
1809 IRQ0_MARK,
1810};
1811static const unsigned int intc_irq1_pins[] = {
1812 /* IRQ */
1813 RCAR_GP_PIN(1, 27),
1814};
1815static const unsigned int intc_irq1_mux[] = {
1816 IRQ1_MARK,
1817};
1818static const unsigned int intc_irq2_pins[] = {
1819 /* IRQ */
1820 RCAR_GP_PIN(1, 29),
1821};
1822static const unsigned int intc_irq2_mux[] = {
1823 IRQ2_MARK,
1824};
1825static const unsigned int intc_irq3_pins[] = {
1826 /* IRQ */
1827 RCAR_GP_PIN(1, 23),
1828};
1829static const unsigned int intc_irq3_mux[] = {
1830 IRQ3_MARK,
1831};
1832/* - SCIF0 ----------------------------------------------------------------- */
1833static const unsigned int scif0_data_pins[] = {
1834 /* RX, TX */
1835 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1836};
1837static const unsigned int scif0_data_mux[] = {
1838 RX0_MARK, TX0_MARK,
1839};
1840static const unsigned int scif0_clk_pins[] = {
1841 /* SCK */
1842 RCAR_GP_PIN(4, 27),
1843};
1844static const unsigned int scif0_clk_mux[] = {
1845 SCK0_MARK,
1846};
1847static const unsigned int scif0_ctrl_pins[] = {
1848 /* RTS, CTS */
1849 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
1850};
1851static const unsigned int scif0_ctrl_mux[] = {
1852 RTS0_N_TANS_MARK, CTS0_N_MARK,
1853};
1854static const unsigned int scif0_data_b_pins[] = {
1855 /* RX, TX */
1856 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1857};
1858static const unsigned int scif0_data_b_mux[] = {
1859 RX0_B_MARK, TX0_B_MARK,
1860};
1861/* - SCIF1 ----------------------------------------------------------------- */
1862static const unsigned int scif1_data_pins[] = {
1863 /* RX, TX */
1864 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1865};
1866static const unsigned int scif1_data_mux[] = {
1867 RX1_MARK, TX1_MARK,
1868};
1869static const unsigned int scif1_clk_pins[] = {
1870 /* SCK */
1871 RCAR_GP_PIN(4, 20),
1872};
1873static const unsigned int scif1_clk_mux[] = {
1874 SCK1_MARK,
1875};
1876static const unsigned int scif1_ctrl_pins[] = {
1877 /* RTS, CTS */
1878 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
1879};
1880static const unsigned int scif1_ctrl_mux[] = {
1881 RTS1_N_TANS_MARK, CTS1_N_MARK,
1882};
1883static const unsigned int scif1_data_b_pins[] = {
1884 /* RX, TX */
1885 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1886};
1887static const unsigned int scif1_data_b_mux[] = {
1888 RX1_B_MARK, TX1_B_MARK,
1889};
1890static const unsigned int scif1_data_c_pins[] = {
1891 /* RX, TX */
1892 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
1893};
1894static const unsigned int scif1_data_c_mux[] = {
1895 RX1_C_MARK, TX1_C_MARK,
1896};
1897static const unsigned int scif1_data_d_pins[] = {
1898 /* RX, TX */
1899 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1900};
1901static const unsigned int scif1_data_d_mux[] = {
1902 RX1_D_MARK, TX1_D_MARK,
1903};
1904static const unsigned int scif1_clk_d_pins[] = {
1905 /* SCK */
1906 RCAR_GP_PIN(3, 17),
1907};
1908static const unsigned int scif1_clk_d_mux[] = {
1909 SCK1_D_MARK,
1910};
1911static const unsigned int scif1_data_e_pins[] = {
1912 /* RX, TX */
1913 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1914};
1915static const unsigned int scif1_data_e_mux[] = {
1916 RX1_E_MARK, TX1_E_MARK,
1917};
1918static const unsigned int scif1_clk_e_pins[] = {
1919 /* SCK */
1920 RCAR_GP_PIN(2, 20),
1921};
1922static const unsigned int scif1_clk_e_mux[] = {
1923 SCK1_E_MARK,
1924};
1925/* - HSCIF0 ----------------------------------------------------------------- */ 1760/* - HSCIF0 ----------------------------------------------------------------- */
1926static const unsigned int hscif0_data_pins[] = { 1761static const unsigned int hscif0_data_pins[] = {
1927 /* RX, TX */ 1762 /* RX, TX */
@@ -2057,6 +1892,390 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
2057static const unsigned int hscif1_ctrl_b_mux[] = { 1892static const unsigned int hscif1_ctrl_b_mux[] = {
2058 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 1893 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2059}; 1894};
1895/* - INTC ------------------------------------------------------------------- */
1896static const unsigned int intc_irq0_pins[] = {
1897 /* IRQ */
1898 RCAR_GP_PIN(1, 25),
1899};
1900static const unsigned int intc_irq0_mux[] = {
1901 IRQ0_MARK,
1902};
1903static const unsigned int intc_irq1_pins[] = {
1904 /* IRQ */
1905 RCAR_GP_PIN(1, 27),
1906};
1907static const unsigned int intc_irq1_mux[] = {
1908 IRQ1_MARK,
1909};
1910static const unsigned int intc_irq2_pins[] = {
1911 /* IRQ */
1912 RCAR_GP_PIN(1, 29),
1913};
1914static const unsigned int intc_irq2_mux[] = {
1915 IRQ2_MARK,
1916};
1917static const unsigned int intc_irq3_pins[] = {
1918 /* IRQ */
1919 RCAR_GP_PIN(1, 23),
1920};
1921static const unsigned int intc_irq3_mux[] = {
1922 IRQ3_MARK,
1923};
1924/* - MMCIF0 ----------------------------------------------------------------- */
1925static const unsigned int mmc0_data1_pins[] = {
1926 /* D[0] */
1927 RCAR_GP_PIN(3, 18),
1928};
1929static const unsigned int mmc0_data1_mux[] = {
1930 MMC0_D0_MARK,
1931};
1932static const unsigned int mmc0_data4_pins[] = {
1933 /* D[0:3] */
1934 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1935 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1936};
1937static const unsigned int mmc0_data4_mux[] = {
1938 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1939};
1940static const unsigned int mmc0_data8_pins[] = {
1941 /* D[0:7] */
1942 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1943 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1944 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1945 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1946};
1947static const unsigned int mmc0_data8_mux[] = {
1948 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1949 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1950};
1951static const unsigned int mmc0_ctrl_pins[] = {
1952 /* CLK, CMD */
1953 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
1954};
1955static const unsigned int mmc0_ctrl_mux[] = {
1956 MMC0_CLK_MARK, MMC0_CMD_MARK,
1957};
1958/* - MMCIF1 ----------------------------------------------------------------- */
1959static const unsigned int mmc1_data1_pins[] = {
1960 /* D[0] */
1961 RCAR_GP_PIN(3, 26),
1962};
1963static const unsigned int mmc1_data1_mux[] = {
1964 MMC1_D0_MARK,
1965};
1966static const unsigned int mmc1_data4_pins[] = {
1967 /* D[0:3] */
1968 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
1969 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
1970};
1971static const unsigned int mmc1_data4_mux[] = {
1972 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1973};
1974static const unsigned int mmc1_data8_pins[] = {
1975 /* D[0:7] */
1976 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
1977 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
1978 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1979 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1980};
1981static const unsigned int mmc1_data8_mux[] = {
1982 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1983 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1984};
1985static const unsigned int mmc1_ctrl_pins[] = {
1986 /* CLK, CMD */
1987 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1988};
1989static const unsigned int mmc1_ctrl_mux[] = {
1990 MMC1_CLK_MARK, MMC1_CMD_MARK,
1991};
1992/* - MSIOF0 ----------------------------------------------------------------- */
1993static const unsigned int msiof0_clk_pins[] = {
1994 /* SCK */
1995 RCAR_GP_PIN(5, 12),
1996};
1997static const unsigned int msiof0_clk_mux[] = {
1998 MSIOF0_SCK_MARK,
1999};
2000static const unsigned int msiof0_sync_pins[] = {
2001 /* SYNC */
2002 RCAR_GP_PIN(5, 13),
2003};
2004static const unsigned int msiof0_sync_mux[] = {
2005 MSIOF0_SYNC_MARK,
2006};
2007static const unsigned int msiof0_ss1_pins[] = {
2008 /* SS1 */
2009 RCAR_GP_PIN(5, 14),
2010};
2011static const unsigned int msiof0_ss1_mux[] = {
2012 MSIOF0_SS1_MARK,
2013};
2014static const unsigned int msiof0_ss2_pins[] = {
2015 /* SS2 */
2016 RCAR_GP_PIN(5, 16),
2017};
2018static const unsigned int msiof0_ss2_mux[] = {
2019 MSIOF0_SS2_MARK,
2020};
2021static const unsigned int msiof0_rx_pins[] = {
2022 /* RXD */
2023 RCAR_GP_PIN(5, 17),
2024};
2025static const unsigned int msiof0_rx_mux[] = {
2026 MSIOF0_RXD_MARK,
2027};
2028static const unsigned int msiof0_tx_pins[] = {
2029 /* TXD */
2030 RCAR_GP_PIN(5, 15),
2031};
2032static const unsigned int msiof0_tx_mux[] = {
2033 MSIOF0_TXD_MARK,
2034};
2035/* - MSIOF1 ----------------------------------------------------------------- */
2036static const unsigned int msiof1_clk_pins[] = {
2037 /* SCK */
2038 RCAR_GP_PIN(4, 8),
2039};
2040static const unsigned int msiof1_clk_mux[] = {
2041 MSIOF1_SCK_MARK,
2042};
2043static const unsigned int msiof1_sync_pins[] = {
2044 /* SYNC */
2045 RCAR_GP_PIN(4, 9),
2046};
2047static const unsigned int msiof1_sync_mux[] = {
2048 MSIOF1_SYNC_MARK,
2049};
2050static const unsigned int msiof1_ss1_pins[] = {
2051 /* SS1 */
2052 RCAR_GP_PIN(4, 10),
2053};
2054static const unsigned int msiof1_ss1_mux[] = {
2055 MSIOF1_SS1_MARK,
2056};
2057static const unsigned int msiof1_ss2_pins[] = {
2058 /* SS2 */
2059 RCAR_GP_PIN(4, 11),
2060};
2061static const unsigned int msiof1_ss2_mux[] = {
2062 MSIOF1_SS2_MARK,
2063};
2064static const unsigned int msiof1_rx_pins[] = {
2065 /* RXD */
2066 RCAR_GP_PIN(4, 13),
2067};
2068static const unsigned int msiof1_rx_mux[] = {
2069 MSIOF1_RXD_MARK,
2070};
2071static const unsigned int msiof1_tx_pins[] = {
2072 /* TXD */
2073 RCAR_GP_PIN(4, 12),
2074};
2075static const unsigned int msiof1_tx_mux[] = {
2076 MSIOF1_TXD_MARK,
2077};
2078/* - MSIOF2 ----------------------------------------------------------------- */
2079static const unsigned int msiof2_clk_pins[] = {
2080 /* SCK */
2081 RCAR_GP_PIN(0, 27),
2082};
2083static const unsigned int msiof2_clk_mux[] = {
2084 MSIOF2_SCK_MARK,
2085};
2086static const unsigned int msiof2_sync_pins[] = {
2087 /* SYNC */
2088 RCAR_GP_PIN(0, 26),
2089};
2090static const unsigned int msiof2_sync_mux[] = {
2091 MSIOF2_SYNC_MARK,
2092};
2093static const unsigned int msiof2_ss1_pins[] = {
2094 /* SS1 */
2095 RCAR_GP_PIN(0, 30),
2096};
2097static const unsigned int msiof2_ss1_mux[] = {
2098 MSIOF2_SS1_MARK,
2099};
2100static const unsigned int msiof2_ss2_pins[] = {
2101 /* SS2 */
2102 RCAR_GP_PIN(0, 31),
2103};
2104static const unsigned int msiof2_ss2_mux[] = {
2105 MSIOF2_SS2_MARK,
2106};
2107static const unsigned int msiof2_rx_pins[] = {
2108 /* RXD */
2109 RCAR_GP_PIN(0, 29),
2110};
2111static const unsigned int msiof2_rx_mux[] = {
2112 MSIOF2_RXD_MARK,
2113};
2114static const unsigned int msiof2_tx_pins[] = {
2115 /* TXD */
2116 RCAR_GP_PIN(0, 28),
2117};
2118static const unsigned int msiof2_tx_mux[] = {
2119 MSIOF2_TXD_MARK,
2120};
2121/* - MSIOF3 ----------------------------------------------------------------- */
2122static const unsigned int msiof3_clk_pins[] = {
2123 /* SCK */
2124 RCAR_GP_PIN(5, 4),
2125};
2126static const unsigned int msiof3_clk_mux[] = {
2127 MSIOF3_SCK_MARK,
2128};
2129static const unsigned int msiof3_sync_pins[] = {
2130 /* SYNC */
2131 RCAR_GP_PIN(4, 30),
2132};
2133static const unsigned int msiof3_sync_mux[] = {
2134 MSIOF3_SYNC_MARK,
2135};
2136static const unsigned int msiof3_ss1_pins[] = {
2137 /* SS1 */
2138 RCAR_GP_PIN(4, 31),
2139};
2140static const unsigned int msiof3_ss1_mux[] = {
2141 MSIOF3_SS1_MARK,
2142};
2143static const unsigned int msiof3_ss2_pins[] = {
2144 /* SS2 */
2145 RCAR_GP_PIN(4, 27),
2146};
2147static const unsigned int msiof3_ss2_mux[] = {
2148 MSIOF3_SS2_MARK,
2149};
2150static const unsigned int msiof3_rx_pins[] = {
2151 /* RXD */
2152 RCAR_GP_PIN(5, 2),
2153};
2154static const unsigned int msiof3_rx_mux[] = {
2155 MSIOF3_RXD_MARK,
2156};
2157static const unsigned int msiof3_tx_pins[] = {
2158 /* TXD */
2159 RCAR_GP_PIN(5, 3),
2160};
2161static const unsigned int msiof3_tx_mux[] = {
2162 MSIOF3_TXD_MARK,
2163};
2164/* - SCIF0 ------------------------------------------------------------------ */
2165static const unsigned int scif0_data_pins[] = {
2166 /* RX, TX */
2167 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2168};
2169static const unsigned int scif0_data_mux[] = {
2170 RX0_MARK, TX0_MARK,
2171};
2172static const unsigned int scif0_clk_pins[] = {
2173 /* SCK */
2174 RCAR_GP_PIN(4, 27),
2175};
2176static const unsigned int scif0_clk_mux[] = {
2177 SCK0_MARK,
2178};
2179static const unsigned int scif0_ctrl_pins[] = {
2180 /* RTS, CTS */
2181 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2182};
2183static const unsigned int scif0_ctrl_mux[] = {
2184 RTS0_N_MARK, CTS0_N_MARK,
2185};
2186static const unsigned int scif0_data_b_pins[] = {
2187 /* RX, TX */
2188 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2189};
2190static const unsigned int scif0_data_b_mux[] = {
2191 RX0_B_MARK, TX0_B_MARK,
2192};
2193/* - SCIF1 ------------------------------------------------------------------ */
2194static const unsigned int scif1_data_pins[] = {
2195 /* RX, TX */
2196 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2197};
2198static const unsigned int scif1_data_mux[] = {
2199 RX1_MARK, TX1_MARK,
2200};
2201static const unsigned int scif1_clk_pins[] = {
2202 /* SCK */
2203 RCAR_GP_PIN(4, 20),
2204};
2205static const unsigned int scif1_clk_mux[] = {
2206 SCK1_MARK,
2207};
2208static const unsigned int scif1_ctrl_pins[] = {
2209 /* RTS, CTS */
2210 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2211};
2212static const unsigned int scif1_ctrl_mux[] = {
2213 RTS1_N_MARK, CTS1_N_MARK,
2214};
2215static const unsigned int scif1_data_b_pins[] = {
2216 /* RX, TX */
2217 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2218};
2219static const unsigned int scif1_data_b_mux[] = {
2220 RX1_B_MARK, TX1_B_MARK,
2221};
2222static const unsigned int scif1_data_c_pins[] = {
2223 /* RX, TX */
2224 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2225};
2226static const unsigned int scif1_data_c_mux[] = {
2227 RX1_C_MARK, TX1_C_MARK,
2228};
2229static const unsigned int scif1_data_d_pins[] = {
2230 /* RX, TX */
2231 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2232};
2233static const unsigned int scif1_data_d_mux[] = {
2234 RX1_D_MARK, TX1_D_MARK,
2235};
2236static const unsigned int scif1_clk_d_pins[] = {
2237 /* SCK */
2238 RCAR_GP_PIN(3, 17),
2239};
2240static const unsigned int scif1_clk_d_mux[] = {
2241 SCK1_D_MARK,
2242};
2243static const unsigned int scif1_data_e_pins[] = {
2244 /* RX, TX */
2245 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2246};
2247static const unsigned int scif1_data_e_mux[] = {
2248 RX1_E_MARK, TX1_E_MARK,
2249};
2250static const unsigned int scif1_clk_e_pins[] = {
2251 /* SCK */
2252 RCAR_GP_PIN(2, 20),
2253};
2254static const unsigned int scif1_clk_e_mux[] = {
2255 SCK1_E_MARK,
2256};
2257/* - SCIF2 ------------------------------------------------------------------ */
2258static const unsigned int scif2_data_pins[] = {
2259 /* RX, TX */
2260 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2261};
2262static const unsigned int scif2_data_mux[] = {
2263 RX2_MARK, TX2_MARK,
2264};
2265static const unsigned int scif2_clk_pins[] = {
2266 /* SCK */
2267 RCAR_GP_PIN(5, 4),
2268};
2269static const unsigned int scif2_clk_mux[] = {
2270 SCK2_MARK,
2271};
2272static const unsigned int scif2_data_b_pins[] = {
2273 /* RX, TX */
2274 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2275};
2276static const unsigned int scif2_data_b_mux[] = {
2277 RX2_B_MARK, TX2_B_MARK,
2278};
2060/* - SCIFA0 ----------------------------------------------------------------- */ 2279/* - SCIFA0 ----------------------------------------------------------------- */
2061static const unsigned int scifa0_data_pins[] = { 2280static const unsigned int scifa0_data_pins[] = {
2062 /* RXD, TXD */ 2281 /* RXD, TXD */
@@ -2420,103 +2639,6 @@ static const unsigned int scifb2_data_c_pins[] = {
2420static const unsigned int scifb2_data_c_mux[] = { 2639static const unsigned int scifb2_data_c_mux[] = {
2421 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 2640 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2422}; 2641};
2423/* - TPU0 ------------------------------------------------------------------- */
2424static const unsigned int tpu0_to0_pins[] = {
2425 /* TO */
2426 RCAR_GP_PIN(0, 20),
2427};
2428static const unsigned int tpu0_to0_mux[] = {
2429 TPU0TO0_MARK,
2430};
2431static const unsigned int tpu0_to1_pins[] = {
2432 /* TO */
2433 RCAR_GP_PIN(0, 21),
2434};
2435static const unsigned int tpu0_to1_mux[] = {
2436 TPU0TO1_MARK,
2437};
2438static const unsigned int tpu0_to2_pins[] = {
2439 /* TO */
2440 RCAR_GP_PIN(0, 22),
2441};
2442static const unsigned int tpu0_to2_mux[] = {
2443 TPU0TO2_MARK,
2444};
2445static const unsigned int tpu0_to3_pins[] = {
2446 /* TO */
2447 RCAR_GP_PIN(0, 23),
2448};
2449static const unsigned int tpu0_to3_mux[] = {
2450 TPU0TO3_MARK,
2451};
2452/* - MMCIF0 ----------------------------------------------------------------- */
2453static const unsigned int mmc0_data1_pins[] = {
2454 /* D[0] */
2455 RCAR_GP_PIN(3, 18),
2456};
2457static const unsigned int mmc0_data1_mux[] = {
2458 MMC0_D0_MARK,
2459};
2460static const unsigned int mmc0_data4_pins[] = {
2461 /* D[0:3] */
2462 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2463 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2464};
2465static const unsigned int mmc0_data4_mux[] = {
2466 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2467};
2468static const unsigned int mmc0_data8_pins[] = {
2469 /* D[0:7] */
2470 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2471 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2472 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2473 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2474};
2475static const unsigned int mmc0_data8_mux[] = {
2476 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2477 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2478};
2479static const unsigned int mmc0_ctrl_pins[] = {
2480 /* CLK, CMD */
2481 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2482};
2483static const unsigned int mmc0_ctrl_mux[] = {
2484 MMC0_CLK_MARK, MMC0_CMD_MARK,
2485};
2486/* - MMCIF1 ----------------------------------------------------------------- */
2487static const unsigned int mmc1_data1_pins[] = {
2488 /* D[0] */
2489 RCAR_GP_PIN(3, 26),
2490};
2491static const unsigned int mmc1_data1_mux[] = {
2492 MMC1_D0_MARK,
2493};
2494static const unsigned int mmc1_data4_pins[] = {
2495 /* D[0:3] */
2496 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2497 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2498};
2499static const unsigned int mmc1_data4_mux[] = {
2500 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2501};
2502static const unsigned int mmc1_data8_pins[] = {
2503 /* D[0:7] */
2504 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2505 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2506 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2507 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2508};
2509static const unsigned int mmc1_data8_mux[] = {
2510 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2511 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2512};
2513static const unsigned int mmc1_ctrl_pins[] = {
2514 /* CLK, CMD */
2515 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2516};
2517static const unsigned int mmc1_ctrl_mux[] = {
2518 MMC1_CLK_MARK, MMC1_CMD_MARK,
2519};
2520/* - SDHI0 ------------------------------------------------------------------ */ 2642/* - SDHI0 ------------------------------------------------------------------ */
2521static const unsigned int sdhi0_data1_pins[] = { 2643static const unsigned int sdhi0_data1_pins[] = {
2522 /* D0 */ 2644 /* D0 */
@@ -2661,6 +2783,137 @@ static const unsigned int sdhi3_wp_pins[] = {
2661static const unsigned int sdhi3_wp_mux[] = { 2783static const unsigned int sdhi3_wp_mux[] = {
2662 SD3_WP_MARK, 2784 SD3_WP_MARK,
2663}; 2785};
2786/* - TPU0 ------------------------------------------------------------------- */
2787static const unsigned int tpu0_to0_pins[] = {
2788 /* TO */
2789 RCAR_GP_PIN(0, 20),
2790};
2791static const unsigned int tpu0_to0_mux[] = {
2792 TPU0TO0_MARK,
2793};
2794static const unsigned int tpu0_to1_pins[] = {
2795 /* TO */
2796 RCAR_GP_PIN(0, 21),
2797};
2798static const unsigned int tpu0_to1_mux[] = {
2799 TPU0TO1_MARK,
2800};
2801static const unsigned int tpu0_to2_pins[] = {
2802 /* TO */
2803 RCAR_GP_PIN(0, 22),
2804};
2805static const unsigned int tpu0_to2_mux[] = {
2806 TPU0TO2_MARK,
2807};
2808static const unsigned int tpu0_to3_pins[] = {
2809 /* TO */
2810 RCAR_GP_PIN(0, 23),
2811};
2812static const unsigned int tpu0_to3_mux[] = {
2813 TPU0TO3_MARK,
2814};
2815/* - USB0 ------------------------------------------------------------------- */
2816static const unsigned int usb0_pins[] = {
2817 /* PWEN, OVC/VBUS */
2818 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2819};
2820static const unsigned int usb0_mux[] = {
2821 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
2822};
2823/* - USB1 ------------------------------------------------------------------- */
2824static const unsigned int usb1_pins[] = {
2825 /* PWEN, OVC */
2826 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2827};
2828static const unsigned int usb1_mux[] = {
2829 USB1_PWEN_MARK, USB1_OVC_MARK,
2830};
2831/* - USB2 ------------------------------------------------------------------- */
2832static const unsigned int usb2_pins[] = {
2833 /* PWEN, OVC */
2834 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2835};
2836static const unsigned int usb2_mux[] = {
2837 USB2_PWEN_MARK, USB2_OVC_MARK,
2838};
2839/* - VIN0 ------------------------------------------------------------------- */
2840static const unsigned int vin0_data_g_pins[] = {
2841 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2842 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
2843 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
2844};
2845static const unsigned int vin0_data_g_mux[] = {
2846 VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK,
2847 VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK,
2848 VI0_G6_MARK, VI0_G7_MARK,
2849};
2850static const unsigned int vin0_data_r_pins[] = {
2851 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2852 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2853 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
2854};
2855static const unsigned int vin0_data_r_mux[] = {
2856 VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK,
2857 VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK,
2858 VI0_R6_MARK, VI0_R7_MARK,
2859};
2860static const unsigned int vin0_data_b_pins[] = {
2861 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2862 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
2863 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2864};
2865static const unsigned int vin0_data_b_mux[] = {
2866 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2867 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2868 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2869};
2870static const unsigned int vin0_hsync_signal_pins[] = {
2871 RCAR_GP_PIN(0, 12),
2872};
2873static const unsigned int vin0_hsync_signal_mux[] = {
2874 VI0_HSYNC_N_MARK,
2875};
2876static const unsigned int vin0_vsync_signal_pins[] = {
2877 RCAR_GP_PIN(0, 13),
2878};
2879static const unsigned int vin0_vsync_signal_mux[] = {
2880 VI0_VSYNC_N_MARK,
2881};
2882static const unsigned int vin0_field_signal_pins[] = {
2883 RCAR_GP_PIN(0, 15),
2884};
2885static const unsigned int vin0_field_signal_mux[] = {
2886 VI0_FIELD_MARK,
2887};
2888static const unsigned int vin0_data_enable_pins[] = {
2889 RCAR_GP_PIN(0, 14),
2890};
2891static const unsigned int vin0_data_enable_mux[] = {
2892 VI0_CLKENB_MARK,
2893};
2894static const unsigned int vin0_clk_pins[] = {
2895 RCAR_GP_PIN(2, 0),
2896};
2897static const unsigned int vin0_clk_mux[] = {
2898 VI0_CLK_MARK,
2899};
2900/* - VIN1 ------------------------------------------------------------------- */
2901static const unsigned int vin1_data_pins[] = {
2902 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2903 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
2904 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2905};
2906static const unsigned int vin1_data_mux[] = {
2907 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2908 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2909 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2910};
2911static const unsigned int vin1_clk_pins[] = {
2912 RCAR_GP_PIN(2, 9),
2913};
2914static const unsigned int vin1_clk_mux[] = {
2915 VI1_CLK_MARK,
2916};
2664 2917
2665static const struct sh_pfc_pin_group pinmux_groups[] = { 2918static const struct sh_pfc_pin_group pinmux_groups[] = {
2666 SH_PFC_PIN_GROUP(eth_link), 2919 SH_PFC_PIN_GROUP(eth_link),
@@ -2698,6 +2951,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2698 SH_PFC_PIN_GROUP(mmc1_data4), 2951 SH_PFC_PIN_GROUP(mmc1_data4),
2699 SH_PFC_PIN_GROUP(mmc1_data8), 2952 SH_PFC_PIN_GROUP(mmc1_data8),
2700 SH_PFC_PIN_GROUP(mmc1_ctrl), 2953 SH_PFC_PIN_GROUP(mmc1_ctrl),
2954 SH_PFC_PIN_GROUP(msiof0_clk),
2955 SH_PFC_PIN_GROUP(msiof0_sync),
2956 SH_PFC_PIN_GROUP(msiof0_ss1),
2957 SH_PFC_PIN_GROUP(msiof0_ss2),
2958 SH_PFC_PIN_GROUP(msiof0_rx),
2959 SH_PFC_PIN_GROUP(msiof0_tx),
2960 SH_PFC_PIN_GROUP(msiof1_clk),
2961 SH_PFC_PIN_GROUP(msiof1_sync),
2962 SH_PFC_PIN_GROUP(msiof1_ss1),
2963 SH_PFC_PIN_GROUP(msiof1_ss2),
2964 SH_PFC_PIN_GROUP(msiof1_rx),
2965 SH_PFC_PIN_GROUP(msiof1_tx),
2966 SH_PFC_PIN_GROUP(msiof2_clk),
2967 SH_PFC_PIN_GROUP(msiof2_sync),
2968 SH_PFC_PIN_GROUP(msiof2_ss1),
2969 SH_PFC_PIN_GROUP(msiof2_ss2),
2970 SH_PFC_PIN_GROUP(msiof2_rx),
2971 SH_PFC_PIN_GROUP(msiof2_tx),
2972 SH_PFC_PIN_GROUP(msiof3_clk),
2973 SH_PFC_PIN_GROUP(msiof3_sync),
2974 SH_PFC_PIN_GROUP(msiof3_ss1),
2975 SH_PFC_PIN_GROUP(msiof3_ss2),
2976 SH_PFC_PIN_GROUP(msiof3_rx),
2977 SH_PFC_PIN_GROUP(msiof3_tx),
2701 SH_PFC_PIN_GROUP(scif0_data), 2978 SH_PFC_PIN_GROUP(scif0_data),
2702 SH_PFC_PIN_GROUP(scif0_clk), 2979 SH_PFC_PIN_GROUP(scif0_clk),
2703 SH_PFC_PIN_GROUP(scif0_ctrl), 2980 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2711,6 +2988,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2711 SH_PFC_PIN_GROUP(scif1_clk_d), 2988 SH_PFC_PIN_GROUP(scif1_clk_d),
2712 SH_PFC_PIN_GROUP(scif1_data_e), 2989 SH_PFC_PIN_GROUP(scif1_data_e),
2713 SH_PFC_PIN_GROUP(scif1_clk_e), 2990 SH_PFC_PIN_GROUP(scif1_clk_e),
2991 SH_PFC_PIN_GROUP(scif2_data),
2992 SH_PFC_PIN_GROUP(scif2_clk),
2993 SH_PFC_PIN_GROUP(scif2_data_b),
2714 SH_PFC_PIN_GROUP(scifa0_data), 2994 SH_PFC_PIN_GROUP(scifa0_data),
2715 SH_PFC_PIN_GROUP(scifa0_clk), 2995 SH_PFC_PIN_GROUP(scifa0_clk),
2716 SH_PFC_PIN_GROUP(scifa0_ctrl), 2996 SH_PFC_PIN_GROUP(scifa0_ctrl),
@@ -2786,6 +3066,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2786 SH_PFC_PIN_GROUP(tpu0_to1), 3066 SH_PFC_PIN_GROUP(tpu0_to1),
2787 SH_PFC_PIN_GROUP(tpu0_to2), 3067 SH_PFC_PIN_GROUP(tpu0_to2),
2788 SH_PFC_PIN_GROUP(tpu0_to3), 3068 SH_PFC_PIN_GROUP(tpu0_to3),
3069 SH_PFC_PIN_GROUP(usb0),
3070 SH_PFC_PIN_GROUP(usb1),
3071 SH_PFC_PIN_GROUP(usb2),
3072 SH_PFC_PIN_GROUP(vin0_data_g),
3073 SH_PFC_PIN_GROUP(vin0_data_r),
3074 SH_PFC_PIN_GROUP(vin0_data_b),
3075 SH_PFC_PIN_GROUP(vin0_hsync_signal),
3076 SH_PFC_PIN_GROUP(vin0_vsync_signal),
3077 SH_PFC_PIN_GROUP(vin0_field_signal),
3078 SH_PFC_PIN_GROUP(vin0_data_enable),
3079 SH_PFC_PIN_GROUP(vin0_clk),
3080 SH_PFC_PIN_GROUP(vin1_data),
3081 SH_PFC_PIN_GROUP(vin1_clk),
2789}; 3082};
2790 3083
2791static const char * const eth_groups[] = { 3084static const char * const eth_groups[] = {
@@ -2795,6 +3088,31 @@ static const char * const eth_groups[] = {
2795 "eth_rmii", 3088 "eth_rmii",
2796}; 3089};
2797 3090
3091static const char * const hscif0_groups[] = {
3092 "hscif0_data",
3093 "hscif0_clk",
3094 "hscif0_ctrl",
3095 "hscif0_data_b",
3096 "hscif0_ctrl_b",
3097 "hscif0_data_c",
3098 "hscif0_ctrl_c",
3099 "hscif0_data_d",
3100 "hscif0_ctrl_d",
3101 "hscif0_data_e",
3102 "hscif0_ctrl_e",
3103 "hscif0_data_f",
3104 "hscif0_ctrl_f",
3105};
3106
3107static const char * const hscif1_groups[] = {
3108 "hscif1_data",
3109 "hscif1_clk",
3110 "hscif1_ctrl",
3111 "hscif1_data_b",
3112 "hscif1_clk_b",
3113 "hscif1_ctrl_b",
3114};
3115
2798static const char * const intc_groups[] = { 3116static const char * const intc_groups[] = {
2799 "intc_irq0", 3117 "intc_irq0",
2800 "intc_irq1", 3118 "intc_irq1",
@@ -2802,6 +3120,56 @@ static const char * const intc_groups[] = {
2802 "intc_irq3", 3120 "intc_irq3",
2803}; 3121};
2804 3122
3123static const char * const mmc0_groups[] = {
3124 "mmc0_data1",
3125 "mmc0_data4",
3126 "mmc0_data8",
3127 "mmc0_ctrl",
3128};
3129
3130static const char * const mmc1_groups[] = {
3131 "mmc1_data1",
3132 "mmc1_data4",
3133 "mmc1_data8",
3134 "mmc1_ctrl",
3135};
3136
3137static const char * const msiof0_groups[] = {
3138 "msiof0_clk",
3139 "msiof0_sync",
3140 "msiof0_ss1",
3141 "msiof0_ss2",
3142 "msiof0_rx",
3143 "msiof0_tx",
3144};
3145
3146static const char * const msiof1_groups[] = {
3147 "msiof1_clk",
3148 "msiof1_sync",
3149 "msiof1_ss1",
3150 "msiof1_ss2",
3151 "msiof1_rx",
3152 "msiof1_tx",
3153};
3154
3155static const char * const msiof2_groups[] = {
3156 "msiof2_clk",
3157 "msiof2_sync",
3158 "msiof2_ss1",
3159 "msiof2_ss2",
3160 "msiof2_rx",
3161 "msiof2_tx",
3162};
3163
3164static const char * const msiof3_groups[] = {
3165 "msiof3_clk",
3166 "msiof3_sync",
3167 "msiof3_ss1",
3168 "msiof3_ss2",
3169 "msiof3_rx",
3170 "msiof3_tx",
3171};
3172
2805static const char * const scif0_groups[] = { 3173static const char * const scif0_groups[] = {
2806 "scif0_data", 3174 "scif0_data",
2807 "scif0_clk", 3175 "scif0_clk",
@@ -2821,29 +3189,10 @@ static const char * const scif1_groups[] = {
2821 "scif1_clk_e", 3189 "scif1_clk_e",
2822}; 3190};
2823 3191
2824static const char * const hscif0_groups[] = { 3192static const char * const scif2_groups[] = {
2825 "hscif0_data", 3193 "scif2_data",
2826 "hscif0_clk", 3194 "scif2_clk",
2827 "hscif0_ctrl", 3195 "scif2_data_b",
2828 "hscif0_data_b",
2829 "hscif0_ctrl_b",
2830 "hscif0_data_c",
2831 "hscif0_ctrl_c",
2832 "hscif0_data_d",
2833 "hscif0_ctrl_d",
2834 "hscif0_data_e",
2835 "hscif0_ctrl_e",
2836 "hscif0_data_f",
2837 "hscif0_ctrl_f",
2838};
2839
2840static const char * const hscif1_groups[] = {
2841 "hscif1_data",
2842 "hscif1_clk",
2843 "hscif1_ctrl",
2844 "hscif1_data_b",
2845 "hscif1_clk_b",
2846 "hscif1_ctrl_b",
2847}; 3196};
2848 3197
2849static const char * const scifa0_groups[] = { 3198static const char * const scifa0_groups[] = {
@@ -2915,27 +3264,6 @@ static const char * const scifb2_groups[] = {
2915 "scifb2_data_c", 3264 "scifb2_data_c",
2916}; 3265};
2917 3266
2918static const char * const tpu0_groups[] = {
2919 "tpu0_to0",
2920 "tpu0_to1",
2921 "tpu0_to2",
2922 "tpu0_to3",
2923};
2924
2925static const char * const mmc0_groups[] = {
2926 "mmc0_data1",
2927 "mmc0_data4",
2928 "mmc0_data8",
2929 "mmc0_ctrl",
2930};
2931
2932static const char * const mmc1_groups[] = {
2933 "mmc1_data1",
2934 "mmc1_data4",
2935 "mmc1_data8",
2936 "mmc1_ctrl",
2937};
2938
2939static const char * const sdhi0_groups[] = { 3267static const char * const sdhi0_groups[] = {
2940 "sdhi0_data1", 3268 "sdhi0_data1",
2941 "sdhi0_data4", 3269 "sdhi0_data4",
@@ -2968,6 +3296,41 @@ static const char * const sdhi3_groups[] = {
2968 "sdhi3_wp", 3296 "sdhi3_wp",
2969}; 3297};
2970 3298
3299static const char * const tpu0_groups[] = {
3300 "tpu0_to0",
3301 "tpu0_to1",
3302 "tpu0_to2",
3303 "tpu0_to3",
3304};
3305
3306static const char * const usb0_groups[] = {
3307 "usb0",
3308};
3309
3310static const char * const usb1_groups[] = {
3311 "usb1",
3312};
3313
3314static const char * const usb2_groups[] = {
3315 "usb2",
3316};
3317
3318static const char * const vin0_groups[] = {
3319 "vin0_data_g",
3320 "vin0_data_r",
3321 "vin0_data_b",
3322 "vin0_hsync_signal",
3323 "vin0_vsync_signal",
3324 "vin0_field_signal",
3325 "vin0_data_enable",
3326 "vin0_clk",
3327};
3328
3329static const char * const vin1_groups[] = {
3330 "vin1_data",
3331 "vin1_clk",
3332};
3333
2971static const struct sh_pfc_function pinmux_functions[] = { 3334static const struct sh_pfc_function pinmux_functions[] = {
2972 SH_PFC_FUNCTION(eth), 3335 SH_PFC_FUNCTION(eth),
2973 SH_PFC_FUNCTION(hscif0), 3336 SH_PFC_FUNCTION(hscif0),
@@ -2975,8 +3338,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
2975 SH_PFC_FUNCTION(intc), 3338 SH_PFC_FUNCTION(intc),
2976 SH_PFC_FUNCTION(mmc0), 3339 SH_PFC_FUNCTION(mmc0),
2977 SH_PFC_FUNCTION(mmc1), 3340 SH_PFC_FUNCTION(mmc1),
3341 SH_PFC_FUNCTION(msiof0),
3342 SH_PFC_FUNCTION(msiof1),
3343 SH_PFC_FUNCTION(msiof2),
3344 SH_PFC_FUNCTION(msiof3),
2978 SH_PFC_FUNCTION(scif0), 3345 SH_PFC_FUNCTION(scif0),
2979 SH_PFC_FUNCTION(scif1), 3346 SH_PFC_FUNCTION(scif1),
3347 SH_PFC_FUNCTION(scif2),
2980 SH_PFC_FUNCTION(scifa0), 3348 SH_PFC_FUNCTION(scifa0),
2981 SH_PFC_FUNCTION(scifa1), 3349 SH_PFC_FUNCTION(scifa1),
2982 SH_PFC_FUNCTION(scifa2), 3350 SH_PFC_FUNCTION(scifa2),
@@ -2988,6 +3356,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
2988 SH_PFC_FUNCTION(sdhi2), 3356 SH_PFC_FUNCTION(sdhi2),
2989 SH_PFC_FUNCTION(sdhi3), 3357 SH_PFC_FUNCTION(sdhi3),
2990 SH_PFC_FUNCTION(tpu0), 3358 SH_PFC_FUNCTION(tpu0),
3359 SH_PFC_FUNCTION(usb0),
3360 SH_PFC_FUNCTION(usb1),
3361 SH_PFC_FUNCTION(usb2),
3362 SH_PFC_FUNCTION(vin0),
3363 SH_PFC_FUNCTION(vin1),
2991}; 3364};
2992 3365
2993static struct pinmux_cfg_reg pinmux_config_regs[] = { 3366static struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3200,16 +3573,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3200 /* IP0_31 [1] */ 3573 /* IP0_31 [1] */
3201 0, 0, 3574 0, 0,
3202 /* IP0_30_27 [4] */ 3575 /* IP0_30_27 [4] */
3203 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, 3576 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
3204 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 3577 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
3205 0, 0, 0, 0, 0, 0, 0, 0, 0, 3578 0, 0, 0, 0, 0, 0, 0, 0, 0,
3206 /* IP0_26_23 [4] */ 3579 /* IP0_26_23 [4] */
3207 FN_D7, FN_AD_DI_B, FN_SDA2_C, 3580 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
3208 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, 3581 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
3209 0, 0, 0, 0, 0, 0, 0, 0, 0, 3582 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
3210 /* IP0_22_20 [3] */ 3583 /* IP0_22_20 [3] */
3211 FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 3584 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
3212 FN_SCL2_CIS_C, 0, 0, 3585 FN_I2C2_SCL_C, 0, 0,
3213 /* IP0_19_16 [4] */ 3586 /* IP0_19_16 [4] */
3214 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 3587 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
3215 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, 3588 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
@@ -3256,15 +3629,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3256 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 3629 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
3257 0, 0, 3630 0, 0,
3258 /* IP1_11_8 [4] */ 3631 /* IP1_11_8 [4] */
3259 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, 3632 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
3260 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 3633 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
3261 0, 0, 0, 0, 0, 0, 0, 0, 0, 3634 0, 0, 0, 0, 0, 0, 0, 0, 0,
3262 /* IP1_7_4 [4] */ 3635 /* IP1_7_4 [4] */
3263 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, 3636 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
3264 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, 3637 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
3265 0, 0, 0, 0, 0, 0, 0, 0, 0, 3638 0, 0, 0, 0, 0, 0, 0, 0, 0,
3266 /* IP1_3_0 [4] */ 3639 /* IP1_3_0 [4] */
3267 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, 3640 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
3268 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 3641 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
3269 0, 0, 0, 0, 0, 0, 0, 0, 0, } 3642 0, 0, 0, 0, 0, 0, 0, 0, 0, }
3270 }, 3643 },
@@ -3277,11 +3650,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3277 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, 3650 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
3278 /* IP2_25_22 [4] */ 3651 /* IP2_25_22 [4] */
3279 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 3652 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
3280 FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, 3653 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
3281 0, 0, 0, 0, 0, 0, 0, 0, 3654 0, 0, 0, 0, 0, 0, 0, 0,
3282 /* IP2_21_18 [4] */ 3655 /* IP2_21_18 [4] */
3283 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 3656 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
3284 FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, 3657 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
3285 0, 0, 0, 0, 0, 0, 0, 0, 3658 0, 0, 0, 0, 0, 0, 0, 0,
3286 /* IP2_17_15 [3] */ 3659 /* IP2_17_15 [3] */
3287 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 3660 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
@@ -3391,12 +3764,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3391 0, 0, 3764 0, 0,
3392 /* IP5_9_6 [4] */ 3765 /* IP5_9_6 [4] */
3393 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, 3766 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
3394 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, 3767 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
3395 FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, 3768 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
3396 /* IP5_5_3 [3] */ 3769 /* IP5_5_3 [3] */
3397 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 3770 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
3398 FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, 3771 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
3399 FN_INTC_EN0_N, FN_SCL1_CIS, 3772 FN_INTC_EN0_N, FN_I2C1_SCL,
3400 /* IP5_2_0 [3] */ 3773 /* IP5_2_0 [3] */
3401 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 3774 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
3402 FN_VI2_R3, 0, 0, } 3775 FN_VI2_R3, 0, 0, }
@@ -3404,24 +3777,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3404 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 3777 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3405 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { 3778 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
3406 /* IP6_31_29 [3] */ 3779 /* IP6_31_29 [3] */
3407 FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, 3780 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
3408 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 3781 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
3409 /* IP6_28_26 [3] */ 3782 /* IP6_28_26 [3] */
3410 FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, 3783 FN_ETH_LINK, 0, FN_HTX0_E,
3411 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, 3784 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
3412 /* IP6_25_23 [3] */ 3785 /* IP6_25_23 [3] */
3413 FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, 3786 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
3414 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, 3787 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
3415 /* IP6_22_20 [3] */ 3788 /* IP6_22_20 [3] */
3416 FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, 3789 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
3417 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, 3790 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
3418 /* IP6_19_17 [3] */ 3791 /* IP6_19_17 [3] */
3419 FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, 3792 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
3420 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, 3793 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
3421 /* IP6_16_14 [3] */ 3794 /* IP6_16_14 [3] */
3422 FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, 3795 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
3423 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, 3796 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
3424 FN_SCL2_CIS_E, 0, 3797 FN_I2C2_SCL_E, 0,
3425 /* IP6_13_11 [3] */ 3798 /* IP6_13_11 [3] */
3426 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 3799 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
3427 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, 3800 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
@@ -3442,10 +3815,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3442 /* IP7_31 [1] */ 3815 /* IP7_31 [1] */
3443 0, 0, 3816 0, 0,
3444 /* IP7_30_29 [2] */ 3817 /* IP7_30_29 [2] */
3445 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 3818 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
3446 FN_MII_RXD2,
3447 /* IP7_28_27 [2] */ 3819 /* IP7_28_27 [2] */
3448 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, 3820 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
3449 /* IP7_26_25 [2] */ 3821 /* IP7_26_25 [2] */
3450 FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, 3822 FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
3451 /* IP7_24_22 [3] */ 3823 /* IP7_24_22 [3] */
@@ -3458,20 +3830,19 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3458 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 3830 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
3459 FN_GLO_SS_C, 0, 0, 0, 3831 FN_GLO_SS_C, 0, 0, 0,
3460 /* IP7_15_13 [3] */ 3832 /* IP7_15_13 [3] */
3461 FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, 3833 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
3462 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, 3834 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
3463 /* IP7_12_10 [3] */ 3835 /* IP7_12_10 [3] */
3464 FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, 3836 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
3465 FN_GLO_SCLK_C, 0, 0, 0, 3837 FN_GLO_SCLK_C, 0, 0, 0,
3466 /* IP7_9_8 [2] */ 3838 /* IP7_9_8 [2] */
3467 FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, 3839 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
3468 /* IP7_7_6 [2] */ 3840 /* IP7_7_6 [2] */
3469 FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, 3841 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
3470 /* IP7_5_3 [3] */ 3842 /* IP7_5_3 [3] */
3471 FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, 3843 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
3472 0, 0, 0,
3473 /* IP7_2_0 [3] */ 3844 /* IP7_2_0 [3] */
3474 FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, 3845 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
3475 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } 3846 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
3476 }, 3847 },
3477 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 3848 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
@@ -3489,22 +3860,21 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3489 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, 3860 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
3490 /* IP8_25_24 [2] */ 3861 /* IP8_25_24 [2] */
3491 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 3862 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
3492 FN_AVB_MAGIC, FN_MII_MAGIC, 3863 FN_AVB_MAGIC, 0,
3493 /* IP8_23_22 [2] */ 3864 /* IP8_23_22 [2] */
3494 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, 3865 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
3495 /* IP8_21_20 [2] */ 3866 /* IP8_21_20 [2] */
3496 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 3867 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
3497 FN_MII_MDIO,
3498 /* IP8_19_18 [2] */ 3868 /* IP8_19_18 [2] */
3499 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, 3869 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
3500 /* IP8_17_16 [2] */ 3870 /* IP8_17_16 [2] */
3501 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, 3871 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
3502 /* IP8_15_14 [2] */ 3872 /* IP8_15_14 [2] */
3503 FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, 3873 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
3504 /* IP8_13_12 [2] */ 3874 /* IP8_13_12 [2] */
3505 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, 3875 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
3506 /* IP8_11_10 [2] */ 3876 /* IP8_11_10 [2] */
3507 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, 3877 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
3508 /* IP8_9_8 [2] */ 3878 /* IP8_9_8 [2] */
3509 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, 3879 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
3510 /* IP8_7_6 [2] */ 3880 /* IP8_7_6 [2] */
@@ -3514,34 +3884,34 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3514 /* IP8_3_2 [2] */ 3884 /* IP8_3_2 [2] */
3515 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 3885 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
3516 /* IP8_1_0 [2] */ 3886 /* IP8_1_0 [2] */
3517 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } 3887 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
3518 }, 3888 },
3519 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 3889 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3520 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { 3890 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
3521 /* IP9_31_28 [4] */ 3891 /* IP9_31_28 [4] */
3522 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 3892 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
3523 FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, 3893 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
3524 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, 3894 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
3525 /* IP9_27_26 [2] */ 3895 /* IP9_27_26 [2] */
3526 FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, 3896 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
3527 /* IP9_25_24 [2] */ 3897 /* IP9_25_24 [2] */
3528 FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, 3898 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
3529 /* IP9_23_22 [2] */ 3899 /* IP9_23_22 [2] */
3530 FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, 3900 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
3531 /* IP9_21_20 [2] */ 3901 /* IP9_21_20 [2] */
3532 FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, 3902 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
3533 /* IP9_19_18 [2] */ 3903 /* IP9_19_18 [2] */
3534 FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, 3904 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
3535 /* IP9_17_16 [2] */ 3905 /* IP9_17_16 [2] */
3536 FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, 3906 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
3537 /* IP9_15_12 [4] */ 3907 /* IP9_15_12 [4] */
3538 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 3908 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
3539 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, 3909 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
3540 FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, 3910 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
3541 /* IP9_11_8 [4] */ 3911 /* IP9_11_8 [4] */
3542 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 3912 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
3543 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, 3913 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
3544 FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, 3914 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
3545 /* IP9_7_6 [2] */ 3915 /* IP9_7_6 [2] */
3546 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, 3916 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
3547 /* IP9_5_4 [2] */ 3917 /* IP9_5_4 [2] */
@@ -3563,11 +3933,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3563 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 3933 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
3564 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, 3934 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
3565 /* IP10_22_19 [4] */ 3935 /* IP10_22_19 [4] */
3566 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, 3936 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
3567 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 3937 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
3568 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, 3938 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
3569 /* IP10_18_15 [4] */ 3939 /* IP10_18_15 [4] */
3570 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, 3940 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
3571 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 3941 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
3572 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 3942 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
3573 0, 0, 0, 0, 0, 0, 3943 0, 0, 0, 0, 0, 0,
@@ -3587,7 +3957,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3587 FN_VI3_DATA0_B, 0, 3957 FN_VI3_DATA0_B, 0,
3588 /* IP10_3_0 [4] */ 3958 /* IP10_3_0 [4] */
3589 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 3959 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
3590 FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, 3960 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
3591 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } 3961 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
3592 }, 3962 },
3593 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 3963 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
@@ -3595,17 +3965,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3595 /* IP11_31_30 [2] */ 3965 /* IP11_31_30 [2] */
3596 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 3966 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
3597 /* IP11_29_27 [3] */ 3967 /* IP11_29_27 [3] */
3598 FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 3968 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
3599 FN_RDS_CLK_B, 0, 0, 3969 0, 0, 0,
3600 /* IP11_26_24 [3] */ 3970 /* IP11_26_24 [3] */
3601 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, 3971 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
3602 0, 0, 0, 3972 0, 0, 0,
3603 /* IP11_23_22 [2] */ 3973 /* IP11_23_22 [2] */
3604 FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, 3974 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
3605 /* IP11_21_18 [4] */ 3975 /* IP11_21_18 [4] */
3606 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 3976 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
3607 FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, 3977 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
3608 FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
3609 /* IP11_17_15 [3] */ 3978 /* IP11_17_15 [3] */
3610 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 3979 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
3611 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, 3980 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
@@ -3680,8 +4049,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3680 /* IP13_22_19 [4] */ 4049 /* IP13_22_19 [4] */
3681 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 4050 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
3682 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, 4051 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
3683 FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F, 4052 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
3684 0, 0, 0, 0,
3685 /* IP13_18_16 [3] */ 4053 /* IP13_18_16 [3] */
3686 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, 4054 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
3687 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, 4055 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
@@ -3689,15 +4057,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3689 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, 4057 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
3690 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, 4058 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
3691 /* IP13_12_10 [3] */ 4059 /* IP13_12_10 [3] */
3692 FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, 4060 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
3693 FN_CAN_DEBUGOUT8, 0, 0, 4061 FN_CAN_DEBUGOUT8, 0, 0,
3694 /* IP13_9_7 [3] */ 4062 /* IP13_9_7 [3] */
3695 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 4063 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
3696 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, 4064 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
3697 /* IP13_6_3 [4] */ 4065 /* IP13_6_3 [4] */
3698 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, 4066 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
3699 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 4067 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
3700 FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0, 4068 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
3701 /* IP13_2_0 [3] */ 4069 /* IP13_2_0 [3] */
3702 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 4070 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
3703 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } 4071 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
@@ -3707,7 +4075,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3707 /* IP14_30 [1] */ 4075 /* IP14_30 [1] */
3708 0, 0, 4076 0, 0,
3709 /* IP14_30_28 [3] */ 4077 /* IP14_30_28 [3] */
3710 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, 4078 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
3711 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 4079 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
3712 FN_HRTS0_N_C, 0, 4080 FN_HRTS0_N_C, 0,
3713 /* IP14_27_25 [3] */ 4081 /* IP14_27_25 [3] */
@@ -3720,11 +4088,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3720 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 4088 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
3721 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, 4089 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
3722 /* IP14_18_16 [3] */ 4090 /* IP14_18_16 [3] */
3723 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, 4091 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
3724 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, 4092 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
3725 /* IP14_15_12 [4] */ 4093 /* IP14_15_12 [4] */
3726 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, 4094 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
3727 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, 4095 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
3728 0, 0, 0, 0, 0, 0, 0, 4096 0, 0, 0, 0, 0, 0, 0,
3729 /* IP14_11_9 [3] */ 4097 /* IP14_11_9 [3] */
3730 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, 4098 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
@@ -3734,7 +4102,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3734 0, 0, 0, 4102 0, 0, 0,
3735 /* IP14_5_3 [3] */ 4103 /* IP14_5_3 [3] */
3736 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, 4104 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
3737 FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, 4105 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
3738 /* IP14_2_0 [3] */ 4106 /* IP14_2_0 [3] */
3739 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 4107 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
3740 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 4108 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
@@ -3750,7 +4118,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3750 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, 4118 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
3751 /* IP15_25_23 [3] */ 4119 /* IP15_25_23 [3] */
3752 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, 4120 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
3753 FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0, 4121 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
3754 /* IP15_22_20 [3] */ 4122 /* IP15_22_20 [3] */
3755 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 4123 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
3756 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, 4124 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
@@ -3766,13 +4134,13 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3766 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, 4134 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
3767 0, 0, 0, 4135 0, 0, 0,
3768 /* IP15_8_6 [3] */ 4136 /* IP15_8_6 [3] */
3769 FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, 4137 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
3770 FN_SDA2, FN_SDA2_CIS, 0, 4138 FN_IIC2_SDA, FN_I2C2_SDA, 0,
3771 /* IP15_5_3 [3] */ 4139 /* IP15_5_3 [3] */
3772 FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, 4140 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
3773 FN_SCL2, FN_SCL2_CIS, 0, 4141 FN_IIC2_SCL, FN_I2C2_SCL, 0,
3774 /* IP15_2_0 [3] */ 4142 /* IP15_2_0 [3] */
3775 FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, 4143 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
3776 FN_LCDOUT15, FN_SCIF_CLK_B, 0, } 4144 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
3777 }, 4145 },
3778 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 4146 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
@@ -3801,7 +4169,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3801 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, 4169 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
3802 /* IP16_5_3 [3] */ 4170 /* IP16_5_3 [3] */
3803 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 4171 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
3804 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0, 4172 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
3805 /* IP16_2_0 [3] */ 4173 /* IP16_2_0 [3] */
3806 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 4174 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
3807 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } 4175 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
@@ -3877,8 +4245,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3877 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 4245 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
3878 /* RESERVED [2] */ 4246 /* RESERVED [2] */
3879 0, 0, 0, 0, 4247 0, 0, 0, 0,
3880 /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ 4248 /* SEL_SCIF2 [1] */
3881 0, 0, 4249 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
3882 /* SEL_ADI [1] */ 4250 /* SEL_ADI [1] */
3883 FN_SEL_ADI_0, FN_SEL_ADI_1, 4251 FN_SEL_ADI_0, FN_SEL_ADI_1,
3884 /* SEL_SSP [1] */ 4252 /* SEL_SSP [1] */
@@ -3891,9 +4259,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
3891 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, 4259 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
3892 /* SEL_GPS [2] */ 4260 /* SEL_GPS [2] */
3893 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, 4261 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
3894 /* SEL_RDS [3] */ 4262 /* RESERVED [3] */
3895 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, 4263 0, 0, 0, 0, 0, 0, 0, 0,
3896 FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
3897 /* SEL_SIM [2] */ 4264 /* SEL_SIM [2] */
3898 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 4265 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
3899 /* SEL_SSI8 [2] */ 4266 /* SEL_SSI8 [2] */
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 02526df3ffef..70b522d34821 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -23,9 +23,7 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/pinctrl/pinconf-generic.h> 25#include <linux/pinctrl/pinconf-generic.h>
26 26#include <linux/sh_intc.h>
27#include <mach/irqs.h>
28#include <mach/sh7372.h>
29 27
30#include "core.h" 28#include "core.h"
31#include "sh_pfc.h" 29#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6417be5514e2..3e730386fced 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3660,43 +3660,39 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3660 { }, 3660 { },
3661}; 3661};
3662 3662
3663/* External IRQ pins mapped at IRQPIN_BASE */
3664#define EXT_IRQ16L(n) irq_pin(n)
3665#define EXT_IRQ16H(n) irq_pin(n)
3666
3667static const struct pinmux_irq pinmux_irqs[] = { 3663static const struct pinmux_irq pinmux_irqs[] = {
3668 PINMUX_IRQ(EXT_IRQ16H(19), 9), 3664 PINMUX_IRQ(irq_pin(19), 9),
3669 PINMUX_IRQ(EXT_IRQ16L(1), 10), 3665 PINMUX_IRQ(irq_pin(1), 10),
3670 PINMUX_IRQ(EXT_IRQ16L(0), 11), 3666 PINMUX_IRQ(irq_pin(0), 11),
3671 PINMUX_IRQ(EXT_IRQ16H(18), 13), 3667 PINMUX_IRQ(irq_pin(18), 13),
3672 PINMUX_IRQ(EXT_IRQ16H(20), 14), 3668 PINMUX_IRQ(irq_pin(20), 14),
3673 PINMUX_IRQ(EXT_IRQ16H(21), 15), 3669 PINMUX_IRQ(irq_pin(21), 15),
3674 PINMUX_IRQ(EXT_IRQ16H(31), 26), 3670 PINMUX_IRQ(irq_pin(31), 26),
3675 PINMUX_IRQ(EXT_IRQ16H(30), 27), 3671 PINMUX_IRQ(irq_pin(30), 27),
3676 PINMUX_IRQ(EXT_IRQ16H(29), 28), 3672 PINMUX_IRQ(irq_pin(29), 28),
3677 PINMUX_IRQ(EXT_IRQ16H(22), 40), 3673 PINMUX_IRQ(irq_pin(22), 40),
3678 PINMUX_IRQ(EXT_IRQ16H(23), 53), 3674 PINMUX_IRQ(irq_pin(23), 53),
3679 PINMUX_IRQ(EXT_IRQ16L(10), 54), 3675 PINMUX_IRQ(irq_pin(10), 54),
3680 PINMUX_IRQ(EXT_IRQ16L(9), 56), 3676 PINMUX_IRQ(irq_pin(9), 56),
3681 PINMUX_IRQ(EXT_IRQ16H(26), 115), 3677 PINMUX_IRQ(irq_pin(26), 115),
3682 PINMUX_IRQ(EXT_IRQ16H(27), 116), 3678 PINMUX_IRQ(irq_pin(27), 116),
3683 PINMUX_IRQ(EXT_IRQ16H(28), 117), 3679 PINMUX_IRQ(irq_pin(28), 117),
3684 PINMUX_IRQ(EXT_IRQ16H(24), 118), 3680 PINMUX_IRQ(irq_pin(24), 118),
3685 PINMUX_IRQ(EXT_IRQ16L(6), 147), 3681 PINMUX_IRQ(irq_pin(6), 147),
3686 PINMUX_IRQ(EXT_IRQ16L(2), 149), 3682 PINMUX_IRQ(irq_pin(2), 149),
3687 PINMUX_IRQ(EXT_IRQ16L(7), 150), 3683 PINMUX_IRQ(irq_pin(7), 150),
3688 PINMUX_IRQ(EXT_IRQ16L(12), 156), 3684 PINMUX_IRQ(irq_pin(12), 156),
3689 PINMUX_IRQ(EXT_IRQ16L(4), 159), 3685 PINMUX_IRQ(irq_pin(4), 159),
3690 PINMUX_IRQ(EXT_IRQ16H(25), 164), 3686 PINMUX_IRQ(irq_pin(25), 164),
3691 PINMUX_IRQ(EXT_IRQ16L(8), 223), 3687 PINMUX_IRQ(irq_pin(8), 223),
3692 PINMUX_IRQ(EXT_IRQ16L(3), 224), 3688 PINMUX_IRQ(irq_pin(3), 224),
3693 PINMUX_IRQ(EXT_IRQ16L(5), 227), 3689 PINMUX_IRQ(irq_pin(5), 227),
3694 PINMUX_IRQ(EXT_IRQ16H(17), 234), 3690 PINMUX_IRQ(irq_pin(17), 234),
3695 PINMUX_IRQ(EXT_IRQ16L(11), 238), 3691 PINMUX_IRQ(irq_pin(11), 238),
3696 PINMUX_IRQ(EXT_IRQ16L(13), 239), 3692 PINMUX_IRQ(irq_pin(13), 239),
3697 PINMUX_IRQ(EXT_IRQ16H(16), 249), 3693 PINMUX_IRQ(irq_pin(16), 249),
3698 PINMUX_IRQ(EXT_IRQ16L(14), 251), 3694 PINMUX_IRQ(irq_pin(14), 251),
3699 PINMUX_IRQ(EXT_IRQ16L(9), 308), 3695 PINMUX_IRQ(irq_pin(9), 308),
3700}; 3696};
3701 3697
3702/* ----------------------------------------------------------------------------- 3698/* -----------------------------------------------------------------------------
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 00:46:18 -0500