diff options
| author | Koji Matsuoka <koji.matsuoka.xm@rms.renesas.com> | 2013-04-07 22:08:53 -0400 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2013-06-04 08:03:58 -0400 |
| commit | 58c229e18b7754dfe505f3bc1688feb28c84f42a (patch) | |
| tree | 29be1154b136dbf33d48e573081d3e516d138221 /drivers/pinctrl/sh-pfc/pfc-r8a7790.c | |
| parent | 369b00bbe51e128a201af58a4daabb01253f126e (diff) | |
sh-pfc: Initial r8a7790 PFC support
Add initial PFC support for the r8a7790 SoC.
At this point only GPIO interface is supported, move to
newer interfaces planned as incremental changes.
Original authors is Koji Matsuoka-san, thanks for him
and his team for the heavy lifting. Adjusted by Magnus
to work together with updated code in drivers/pinctrl.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@rms.renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7790.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 3238 |
1 files changed, 3238 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c new file mode 100644 index 000000000000..42b0c5514f90 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c | |||
| @@ -0,0 +1,3238 @@ | |||
| 1 | /* | ||
| 2 | * R8A7790 processor support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Renesas Electronics Corporation | ||
| 5 | * Copyright (C) 2013 Magnus Damm | ||
| 6 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
| 7 | * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation; version 2 of the | ||
| 12 | * License. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | */ | ||
| 23 | #include <linux/kernel.h> | ||
| 24 | #include <mach/r8a7790.h> | ||
| 25 | |||
| 26 | #include "core.h" | ||
| 27 | #include "sh_pfc.h" | ||
| 28 | |||
| 29 | #define CPU_32_PORT(fn, pfx, sfx) \ | ||
| 30 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | ||
| 31 | PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ | ||
| 32 | PORT_1(fn, pfx##31, sfx) | ||
| 33 | |||
| 34 | #define CPU_32_PORT1(fn, pfx, sfx) \ | ||
| 35 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | ||
| 36 | PORT_10(fn, pfx##2, sfx) | ||
| 37 | |||
| 38 | #define CPU_32_PORT2(fn, pfx, sfx) \ | ||
| 39 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | ||
| 40 | PORT_10(fn, pfx##2, sfx) | ||
| 41 | |||
| 42 | /* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ | ||
| 43 | #define CPU_ALL_PORT(fn, pfx, sfx) \ | ||
| 44 | CPU_32_PORT(fn, pfx##_0_, sfx), \ | ||
| 45 | CPU_32_PORT1(fn, pfx##_1_, sfx), \ | ||
| 46 | CPU_32_PORT2(fn, pfx##_2_, sfx), \ | ||
| 47 | CPU_32_PORT(fn, pfx##_3_, sfx), \ | ||
| 48 | CPU_32_PORT(fn, pfx##_4_, sfx), \ | ||
| 49 | CPU_32_PORT(fn, pfx##_5_, sfx) \ | ||
| 50 | |||
| 51 | #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) | ||
| 52 | #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ | ||
| 53 | GP##pfx##_IN, GP##pfx##_OUT) | ||
| 54 | |||
| 55 | #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT | ||
| 56 | #define _GP_INDT(pfx, sfx) GP##pfx##_DATA | ||
| 57 | |||
| 58 | #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) | ||
| 59 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) | ||
| 60 | #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) | ||
| 61 | |||
| 62 | |||
| 63 | #define PORT_10_REV(fn, pfx, sfx) \ | ||
| 64 | PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ | ||
| 65 | PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ | ||
| 66 | PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ | ||
| 67 | PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ | ||
| 68 | PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) | ||
| 69 | |||
| 70 | #define CPU_32_PORT_REV(fn, pfx, sfx) \ | ||
| 71 | PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ | ||
| 72 | PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ | ||
| 73 | PORT_10_REV(fn, pfx, sfx) | ||
| 74 | |||
| 75 | #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) | ||
| 76 | #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) | ||
| 77 | |||
| 78 | #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) | ||
| 79 | #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ | ||
| 80 | FN_##ipsr, FN_##fn) | ||
| 81 | |||
| 82 | enum { | ||
| 83 | PINMUX_RESERVED = 0, | ||
| 84 | |||
| 85 | PINMUX_DATA_BEGIN, | ||
| 86 | GP_ALL(DATA), | ||
| 87 | PINMUX_DATA_END, | ||
| 88 | |||
| 89 | PINMUX_INPUT_BEGIN, | ||
| 90 | GP_ALL(IN), | ||
| 91 | PINMUX_INPUT_END, | ||
| 92 | |||
| 93 | PINMUX_OUTPUT_BEGIN, | ||
| 94 | GP_ALL(OUT), | ||
| 95 | PINMUX_OUTPUT_END, | ||
| 96 | |||
| 97 | PINMUX_FUNCTION_BEGIN, | ||
| 98 | GP_ALL(FN), | ||
| 99 | |||
| 100 | /* GPSR0 */ | ||
| 101 | FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, | ||
| 102 | FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, | ||
| 103 | FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, | ||
| 104 | FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, | ||
| 105 | FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, | ||
| 106 | FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, | ||
| 107 | FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, | ||
| 108 | FN_IP3_14_12, FN_IP3_17_15, | ||
| 109 | |||
| 110 | /* GPSR1 */ | ||
| 111 | FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, | ||
| 112 | FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, | ||
| 113 | FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, | ||
| 114 | FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, | ||
| 115 | FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, | ||
| 116 | FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, | ||
| 117 | FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, | ||
| 118 | |||
| 119 | /* GPSR2 */ | ||
| 120 | FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, | ||
| 121 | FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, | ||
| 122 | FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, | ||
| 123 | FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, | ||
| 124 | FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, | ||
| 125 | FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, | ||
| 126 | FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, | ||
| 127 | |||
| 128 | /* GPSR3 */ | ||
| 129 | FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, | ||
| 130 | FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, | ||
| 131 | FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, | ||
| 132 | FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, | ||
| 133 | FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, | ||
| 134 | FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, | ||
| 135 | FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, | ||
| 136 | |||
| 137 | /* GPSR4 */ | ||
| 138 | FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, | ||
| 139 | FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, | ||
| 140 | FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, | ||
| 141 | FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, | ||
| 142 | FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, | ||
| 143 | FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, | ||
| 144 | FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, | ||
| 145 | FN_IP14_15_12, FN_IP14_18_16, | ||
| 146 | |||
| 147 | /* GPSR5 */ | ||
| 148 | FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, | ||
| 149 | FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, | ||
| 150 | FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, | ||
| 151 | FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, | ||
| 152 | FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, | ||
| 153 | FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, | ||
| 154 | FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, | ||
| 155 | |||
| 156 | /* IPSR0 */ | ||
| 157 | FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, | ||
| 158 | FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, | ||
| 159 | FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, | ||
| 160 | FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, | ||
| 161 | FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, | ||
| 162 | FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, | ||
| 163 | FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, | ||
| 164 | FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, | ||
| 165 | FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, | ||
| 166 | FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, | ||
| 167 | FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, | ||
| 168 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, | ||
| 169 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, | ||
| 170 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, | ||
| 171 | |||
| 172 | /* IPSR1 */ | ||
| 173 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, | ||
| 174 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, | ||
| 175 | FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, | ||
| 176 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, | ||
| 177 | FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, | ||
| 178 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, | ||
| 179 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | ||
| 180 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | ||
| 181 | FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, | ||
| 182 | FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, | ||
| 183 | FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, | ||
| 184 | FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, | ||
| 185 | FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, | ||
| 186 | FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, | ||
| 187 | FN_A0, FN_PWM3, FN_A1, FN_PWM4, | ||
| 188 | |||
| 189 | /* IPSR2 */ | ||
| 190 | FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, | ||
| 191 | FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, | ||
| 192 | FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, | ||
| 193 | FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, | ||
| 194 | FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, | ||
| 195 | FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, | ||
| 196 | FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, | ||
| 197 | FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, | ||
| 198 | FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, | ||
| 199 | FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, | ||
| 200 | FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, | ||
| 201 | |||
| 202 | /* IPSR3 */ | ||
| 203 | FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, | ||
| 204 | FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, | ||
| 205 | FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, | ||
| 206 | FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, | ||
| 207 | FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, | ||
| 208 | FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, | ||
| 209 | FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, | ||
| 210 | FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, | ||
| 211 | FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, | ||
| 212 | FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, | ||
| 213 | FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, | ||
| 214 | FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, | ||
| 215 | FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, | ||
| 216 | |||
| 217 | /* IPSR4 */ | ||
| 218 | FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, | ||
| 219 | FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, | ||
| 220 | FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, | ||
| 221 | FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, | ||
| 222 | FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, | ||
| 223 | FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, | ||
| 224 | FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, | ||
| 225 | FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, | ||
| 226 | FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, | ||
| 227 | FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, | ||
| 228 | FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, | ||
| 229 | FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, | ||
| 230 | FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, | ||
| 231 | FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, | ||
| 232 | FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, | ||
| 233 | |||
| 234 | /* IPSR5 */ | ||
| 235 | FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, | ||
| 236 | FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, | ||
| 237 | FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, | ||
| 238 | FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, | ||
| 239 | FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, | ||
| 240 | FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, | ||
| 241 | FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, | ||
| 242 | FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, | ||
| 243 | FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, | ||
| 244 | FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, | ||
| 245 | FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, | ||
| 246 | FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, | ||
| 247 | FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, | ||
| 248 | FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, | ||
| 249 | FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, | ||
| 250 | FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, | ||
| 251 | FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, | ||
| 252 | FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, | ||
| 253 | FN_SSI_WS78_B, | ||
| 254 | |||
| 255 | /* IPSR6 */ | ||
| 256 | FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, | ||
| 257 | FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, | ||
| 258 | FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, | ||
| 259 | FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, | ||
| 260 | FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, | ||
| 261 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, | ||
| 262 | FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | ||
| 263 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, | ||
| 264 | FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, | ||
| 265 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, | ||
| 266 | FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, | ||
| 267 | FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, | ||
| 268 | FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, | ||
| 269 | FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, | ||
| 270 | FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, | ||
| 271 | FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, | ||
| 272 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, | ||
| 273 | FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, | ||
| 274 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, | ||
| 275 | FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, | ||
| 276 | FN_STP_IVCXO27_1_B, FN_HRX0_F, | ||
| 277 | |||
| 278 | /* IPSR7 */ | ||
| 279 | FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, | ||
| 280 | FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, | ||
| 281 | FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, | ||
| 282 | FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, | ||
| 283 | FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, | ||
| 284 | FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, | ||
| 285 | FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, | ||
| 286 | FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, | ||
| 287 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, | ||
| 288 | FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | ||
| 289 | FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, | ||
| 290 | FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, | ||
| 291 | FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, | ||
| 292 | FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, | ||
| 293 | FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, | ||
| 294 | FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, | ||
| 295 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, | ||
| 296 | FN_MII_RXD2, | ||
| 297 | |||
| 298 | /* IPSR8 */ | ||
| 299 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, | ||
| 300 | FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, | ||
| 301 | FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, | ||
| 302 | FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, | ||
| 303 | FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, | ||
| 304 | FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, | ||
| 305 | FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, | ||
| 306 | FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, | ||
| 307 | FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, | ||
| 308 | FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, | ||
| 309 | FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, | ||
| 310 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, | ||
| 311 | FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, | ||
| 312 | FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, | ||
| 313 | FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, | ||
| 314 | FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, | ||
| 315 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, | ||
| 316 | FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, | ||
| 317 | |||
| 318 | /* IPSR9 */ | ||
| 319 | FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, | ||
| 320 | FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, | ||
| 321 | FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, | ||
| 322 | FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, | ||
| 323 | FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, | ||
| 324 | FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, | ||
| 325 | FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, | ||
| 326 | FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, | ||
| 327 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, | ||
| 328 | FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, | ||
| 329 | FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, | ||
| 330 | FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, | ||
| 331 | FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, | ||
| 332 | FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, | ||
| 333 | FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, | ||
| 334 | FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, | ||
| 335 | FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, | ||
| 336 | FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, | ||
| 337 | FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, | ||
| 338 | FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, | ||
| 339 | FN_VI3_CLK_B, | ||
| 340 | |||
| 341 | /* IPSR10 */ | ||
| 342 | FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, | ||
| 343 | FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, | ||
| 344 | FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, | ||
| 345 | FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, | ||
| 346 | FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, | ||
| 347 | FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, | ||
| 348 | FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, | ||
| 349 | FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, | ||
| 350 | FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, | ||
| 351 | FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, | ||
| 352 | FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, | ||
| 353 | FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, | ||
| 354 | FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, | ||
| 355 | FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, | ||
| 356 | FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, | ||
| 357 | FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, | ||
| 358 | FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, | ||
| 359 | FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, | ||
| 360 | FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, | ||
| 361 | FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, | ||
| 362 | FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, | ||
| 363 | FN_GLO_I0_B, FN_VI3_DATA6_B, | ||
| 364 | |||
| 365 | /* IPSR11 */ | ||
| 366 | FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, | ||
| 367 | FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, | ||
| 368 | FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, | ||
| 369 | FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, | ||
| 370 | FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, | ||
| 371 | FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, | ||
| 372 | FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, | ||
| 373 | FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, | ||
| 374 | FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, | ||
| 375 | FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, | ||
| 376 | FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, | ||
| 377 | FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, | ||
| 378 | FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, | ||
| 379 | FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, | ||
| 380 | FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, | ||
| 381 | FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, | ||
| 382 | FN_MOUT0, | ||
| 383 | |||
| 384 | /* IPSR12 */ | ||
| 385 | FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, | ||
| 386 | FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, | ||
| 387 | FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, | ||
| 388 | FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, | ||
| 389 | FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, | ||
| 390 | FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, | ||
| 391 | FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, | ||
| 392 | FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, | ||
| 393 | FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, | ||
| 394 | FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, | ||
| 395 | FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, | ||
| 396 | FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, | ||
| 397 | FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, | ||
| 398 | FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, | ||
| 399 | FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, | ||
| 400 | FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, | ||
| 401 | FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, | ||
| 402 | FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, | ||
| 403 | FN_CAN_DEBUGOUT4, | ||
| 404 | |||
| 405 | /* IPSR13 */ | ||
| 406 | FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, | ||
| 407 | FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, | ||
| 408 | FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, | ||
| 409 | FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, | ||
| 410 | FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6, | ||
| 411 | FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, | ||
| 412 | FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, | ||
| 413 | FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, | ||
| 414 | FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, | ||
| 415 | FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, | ||
| 416 | FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, | ||
| 417 | FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, | ||
| 418 | FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, | ||
| 419 | FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, | ||
| 420 | FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, | ||
| 421 | FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B, | ||
| 422 | FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8, | ||
| 423 | FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, | ||
| 424 | FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, | ||
| 425 | FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, | ||
| 426 | FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, | ||
| 427 | FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, | ||
| 428 | |||
| 429 | /* IPSR14 */ | ||
| 430 | FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, | ||
| 431 | FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, | ||
| 432 | FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, | ||
| 433 | FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, | ||
| 434 | FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, | ||
| 435 | FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, | ||
| 436 | FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, | ||
| 437 | FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, | ||
| 438 | FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, | ||
| 439 | FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, | ||
| 440 | FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, | ||
| 441 | FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, | ||
| 442 | FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, | ||
| 443 | FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, | ||
| 444 | FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, | ||
| 445 | FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, | ||
| 446 | FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, | ||
| 447 | FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, | ||
| 448 | FN_HRTS0_N_C, | ||
| 449 | |||
| 450 | /* IPSR15 */ | ||
| 451 | FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, | ||
| 452 | FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, | ||
| 453 | FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, | ||
| 454 | FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, | ||
| 455 | FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, | ||
| 456 | FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, | ||
| 457 | FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, | ||
| 458 | FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, | ||
| 459 | FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, | ||
| 460 | FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, | ||
| 461 | FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, | ||
| 462 | FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, | ||
| 463 | FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0, | ||
| 464 | FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, | ||
| 465 | FN_DU2_DG6, FN_LCDOUT14, | ||
| 466 | |||
| 467 | /* IPSR16 */ | ||
| 468 | FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, | ||
| 469 | FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, | ||
| 470 | FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, | ||
| 471 | FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, | ||
| 472 | FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, | ||
| 473 | FN_TCLK1_B, | ||
| 474 | |||
| 475 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, | ||
| 476 | FN_SEL_SCIF1_4, | ||
| 477 | FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, | ||
| 478 | FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, | ||
| 479 | FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, | ||
| 480 | FN_SEL_SCIFB1_4, | ||
| 481 | FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, | ||
| 482 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, | ||
| 483 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, | ||
| 484 | FN_SEL_SCFA_0, FN_SEL_SCFA_1, | ||
| 485 | FN_SEL_SOF1_0, FN_SEL_SOF1_1, | ||
| 486 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, | ||
| 487 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | ||
| 488 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, | ||
| 489 | FN_SEL_VI3_0, FN_SEL_VI3_1, | ||
| 490 | FN_SEL_VI2_0, FN_SEL_VI2_1, | ||
| 491 | FN_SEL_VI1_0, FN_SEL_VI1_1, | ||
| 492 | FN_SEL_VI0_0, FN_SEL_VI0_1, | ||
| 493 | FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, | ||
| 494 | FN_SEL_LBS_0, FN_SEL_LBS_1, | ||
| 495 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | ||
| 496 | FN_SEL_SOF3_0, FN_SEL_SOF3_1, | ||
| 497 | FN_SEL_SOF0_0, FN_SEL_SOF0_1, | ||
| 498 | |||
| 499 | FN_SEL_TMU1_0, FN_SEL_TMU1_1, | ||
| 500 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | ||
| 501 | FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, | ||
| 502 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | ||
| 503 | FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, | ||
| 504 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, | ||
| 505 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, | ||
| 506 | FN_SEL_ADI_0, FN_SEL_ADI_1, | ||
| 507 | FN_SEL_SSP_0, FN_SEL_SSP_1, | ||
| 508 | FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, | ||
| 509 | FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, | ||
| 510 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, | ||
| 511 | FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, | ||
| 512 | FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, | ||
| 513 | FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, | ||
| 514 | FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, | ||
| 515 | FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, | ||
| 516 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, | ||
| 517 | |||
| 518 | FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, | ||
| 519 | FN_SEL_IIC0_0, FN_SEL_IIC0_1, | ||
| 520 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, | ||
| 521 | FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, | ||
| 522 | FN_SEL_IIC2_4, | ||
| 523 | FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, | ||
| 524 | FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, | ||
| 525 | FN_SEL_I2C2_4, | ||
| 526 | FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, | ||
| 527 | PINMUX_FUNCTION_END, | ||
| 528 | |||
| 529 | PINMUX_MARK_BEGIN, | ||
| 530 | |||
| 531 | VI1_DATA7_VI1_B7_MARK, | ||
| 532 | |||
| 533 | USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, | ||
| 534 | USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, | ||
| 535 | DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, | ||
| 536 | |||
| 537 | D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, | ||
| 538 | D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, | ||
| 539 | VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, | ||
| 540 | VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, | ||
| 541 | VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, | ||
| 542 | SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, | ||
| 543 | VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, | ||
| 544 | SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, | ||
| 545 | VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, | ||
| 546 | SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, | ||
| 547 | SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, | ||
| 548 | VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, | ||
| 549 | D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, | ||
| 550 | VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, | ||
| 551 | |||
| 552 | D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, | ||
| 553 | VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, | ||
| 554 | SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, | ||
| 555 | VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, | ||
| 556 | SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, | ||
| 557 | VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, | ||
| 558 | D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, | ||
| 559 | VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, | ||
| 560 | D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, | ||
| 561 | VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, | ||
| 562 | SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, | ||
| 563 | VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, | ||
| 564 | D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, | ||
| 565 | VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, | ||
| 566 | A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, | ||
| 567 | |||
| 568 | A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, | ||
| 569 | PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, | ||
| 570 | TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, | ||
| 571 | A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, | ||
| 572 | SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, | ||
| 573 | A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, | ||
| 574 | VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, | ||
| 575 | A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, | ||
| 576 | VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, | ||
| 577 | A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, | ||
| 578 | VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, | ||
| 579 | |||
| 580 | A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, | ||
| 581 | VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, | ||
| 582 | A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, | ||
| 583 | VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, | ||
| 584 | A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, | ||
| 585 | MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, | ||
| 586 | VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, | ||
| 587 | ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, | ||
| 588 | ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, | ||
| 589 | A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, | ||
| 590 | AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, | ||
| 591 | ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, | ||
| 592 | VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, | ||
| 593 | |||
| 594 | A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, | ||
| 595 | A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, | ||
| 596 | VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, | ||
| 597 | VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, | ||
| 598 | VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, | ||
| 599 | VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, | ||
| 600 | VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, | ||
| 601 | VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, | ||
| 602 | CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, | ||
| 603 | VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, | ||
| 604 | VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, | ||
| 605 | MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, | ||
| 606 | HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, | ||
| 607 | VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, | ||
| 608 | VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, | ||
| 609 | |||
| 610 | EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, | ||
| 611 | VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, | ||
| 612 | EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, | ||
| 613 | VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, | ||
| 614 | INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, | ||
| 615 | MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, | ||
| 616 | VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, | ||
| 617 | SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, | ||
| 618 | CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, | ||
| 619 | CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, | ||
| 620 | VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, | ||
| 621 | INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, | ||
| 622 | VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, | ||
| 623 | WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, | ||
| 624 | VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, | ||
| 625 | IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, | ||
| 626 | VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, | ||
| 627 | MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, | ||
| 628 | VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, | ||
| 629 | SSI_WS78_B_MARK, | ||
| 630 | |||
| 631 | DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, | ||
| 632 | VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, | ||
| 633 | DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, | ||
| 634 | SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, | ||
| 635 | INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, | ||
| 636 | DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, | ||
| 637 | MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, | ||
| 638 | SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, | ||
| 639 | ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, | ||
| 640 | TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, | ||
| 641 | SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, | ||
| 642 | STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, | ||
| 643 | SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, | ||
| 644 | STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, | ||
| 645 | SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, | ||
| 646 | RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, | ||
| 647 | TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, | ||
| 648 | RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, | ||
| 649 | STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, | ||
| 650 | ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, | ||
| 651 | STP_IVCXO27_1_B_MARK, HRX0_F_MARK, | ||
| 652 | |||
| 653 | ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, | ||
| 654 | SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, | ||
| 655 | RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, | ||
| 656 | ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, | ||
| 657 | HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, | ||
| 658 | SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, | ||
| 659 | STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, | ||
| 660 | ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, | ||
| 661 | TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, | ||
| 662 | SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, | ||
| 663 | GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, | ||
| 664 | STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, | ||
| 665 | PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, | ||
| 666 | PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, | ||
| 667 | AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, | ||
| 668 | ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, | ||
| 669 | VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, | ||
| 670 | MII_RXD2_MARK, | ||
| 671 | |||
| 672 | VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, | ||
| 673 | MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, | ||
| 674 | AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, | ||
| 675 | AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, | ||
| 676 | AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, | ||
| 677 | AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, | ||
| 678 | MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, | ||
| 679 | MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, | ||
| 680 | MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, | ||
| 681 | AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, | ||
| 682 | SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, | ||
| 683 | VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, | ||
| 684 | MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, | ||
| 685 | AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, | ||
| 686 | AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, | ||
| 687 | AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, | ||
| 688 | SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, | ||
| 689 | SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, | ||
| 690 | |||
| 691 | SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, | ||
| 692 | SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, | ||
| 693 | SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, | ||
| 694 | SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, | ||
| 695 | SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, | ||
| 696 | GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, | ||
| 697 | SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, | ||
| 698 | MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, | ||
| 699 | GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, | ||
| 700 | SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, | ||
| 701 | AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, | ||
| 702 | AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, | ||
| 703 | SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, | ||
| 704 | SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, | ||
| 705 | MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, | ||
| 706 | AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, | ||
| 707 | SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, | ||
| 708 | SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, | ||
| 709 | TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, | ||
| 710 | SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, | ||
| 711 | VI3_CLK_B_MARK, | ||
| 712 | |||
| 713 | SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, | ||
| 714 | GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, | ||
| 715 | SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, | ||
| 716 | VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, | ||
| 717 | VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, | ||
| 718 | VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, | ||
| 719 | TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, | ||
| 720 | SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, | ||
| 721 | VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, | ||
| 722 | TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, | ||
| 723 | SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, | ||
| 724 | VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, | ||
| 725 | TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, | ||
| 726 | SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, | ||
| 727 | VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, | ||
| 728 | GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, | ||
| 729 | MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, | ||
| 730 | HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, | ||
| 731 | VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, | ||
| 732 | TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, | ||
| 733 | VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, | ||
| 734 | GLO_I0_B_MARK, VI3_DATA6_B_MARK, | ||
| 735 | |||
| 736 | SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, | ||
| 737 | GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, | ||
| 738 | TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, | ||
| 739 | SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, | ||
| 740 | MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, | ||
| 741 | SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, | ||
| 742 | MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, | ||
| 743 | SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, | ||
| 744 | VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, | ||
| 745 | MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, | ||
| 746 | RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, | ||
| 747 | RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, | ||
| 748 | MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, | ||
| 749 | SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, | ||
| 750 | SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, | ||
| 751 | RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, | ||
| 752 | MOUT0_MARK, | ||
| 753 | |||
| 754 | SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, | ||
| 755 | SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, | ||
| 756 | SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, | ||
| 757 | SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, | ||
| 758 | SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, | ||
| 759 | MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, | ||
| 760 | STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, | ||
| 761 | CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, | ||
| 762 | SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, | ||
| 763 | SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, | ||
| 764 | MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, | ||
| 765 | SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, | ||
| 766 | MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, | ||
| 767 | SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, | ||
| 768 | CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, | ||
| 769 | IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, | ||
| 770 | CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, | ||
| 771 | IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, | ||
| 772 | CAN_DEBUGOUT4_MARK, | ||
| 773 | |||
| 774 | SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, | ||
| 775 | LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, | ||
| 776 | SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, | ||
| 777 | DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, | ||
| 778 | BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, | ||
| 779 | SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, | ||
| 780 | LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, | ||
| 781 | FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, | ||
| 782 | CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, | ||
| 783 | SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, | ||
| 784 | CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, | ||
| 785 | SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, | ||
| 786 | LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, | ||
| 787 | STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, | ||
| 788 | TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, | ||
| 789 | BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, | ||
| 790 | FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, | ||
| 791 | STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, | ||
| 792 | CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, | ||
| 793 | STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, | ||
| 794 | SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, | ||
| 795 | SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, | ||
| 796 | |||
| 797 | AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, | ||
| 798 | DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, | ||
| 799 | REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, | ||
| 800 | MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, | ||
| 801 | SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, | ||
| 802 | DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, | ||
| 803 | TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, | ||
| 804 | HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, | ||
| 805 | LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, | ||
| 806 | SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, | ||
| 807 | MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, | ||
| 808 | SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, | ||
| 809 | DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, | ||
| 810 | SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, | ||
| 811 | LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, | ||
| 812 | CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, | ||
| 813 | SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, | ||
| 814 | MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, | ||
| 815 | HRTS0_N_C_MARK, | ||
| 816 | |||
| 817 | SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, | ||
| 818 | LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, | ||
| 819 | DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, | ||
| 820 | SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, | ||
| 821 | SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, | ||
| 822 | DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, | ||
| 823 | DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, | ||
| 824 | LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, | ||
| 825 | LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, | ||
| 826 | LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, | ||
| 827 | DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, | ||
| 828 | SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, | ||
| 829 | SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, | ||
| 830 | DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, | ||
| 831 | DU2_DG6_MARK, LCDOUT14_MARK, | ||
| 832 | |||
| 833 | MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, | ||
| 834 | DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, | ||
| 835 | MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, | ||
| 836 | ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, | ||
| 837 | USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, | ||
| 838 | TCLK1_B_MARK, | ||
| 839 | PINMUX_MARK_END, | ||
| 840 | }; | ||
| 841 | |||
| 842 | static const pinmux_enum_t pinmux_data[] = { | ||
| 843 | PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ | ||
| 844 | |||
| 845 | PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), | ||
| 846 | PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), | ||
| 847 | PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), | ||
| 848 | PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), | ||
| 849 | PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), | ||
| 850 | PINMUX_DATA(AVS1_MARK, FN_AVS1), | ||
| 851 | PINMUX_DATA(AVS2_MARK, FN_AVS2), | ||
| 852 | PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), | ||
| 853 | PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), | ||
| 854 | |||
| 855 | PINMUX_IPSR_DATA(IP0_2_0, D0), | ||
| 856 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), | ||
| 857 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), | ||
| 858 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), | ||
| 859 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), | ||
| 860 | PINMUX_IPSR_DATA(IP0_5_3, D1), | ||
| 861 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), | ||
| 862 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), | ||
| 863 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), | ||
| 864 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), | ||
| 865 | PINMUX_IPSR_DATA(IP0_8_6, D2), | ||
| 866 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), | ||
| 867 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), | ||
| 868 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), | ||
| 869 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), | ||
| 870 | PINMUX_IPSR_DATA(IP0_11_9, D3), | ||
| 871 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), | ||
| 872 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), | ||
| 873 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), | ||
| 874 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), | ||
| 875 | PINMUX_IPSR_DATA(IP0_15_12, D4), | ||
| 876 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), | ||
| 877 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), | ||
| 878 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), | ||
| 879 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), | ||
| 880 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), | ||
| 881 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), | ||
| 882 | PINMUX_IPSR_DATA(IP0_19_16, D5), | ||
| 883 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), | ||
| 884 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), | ||
| 885 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), | ||
| 886 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), | ||
| 887 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), | ||
| 888 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), | ||
| 889 | PINMUX_IPSR_DATA(IP0_22_20, D6), | ||
| 890 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), | ||
| 891 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), | ||
| 892 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), | ||
| 893 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), | ||
| 894 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), | ||
| 895 | PINMUX_IPSR_DATA(IP0_26_23, D7), | ||
| 896 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), | ||
| 897 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), | ||
| 898 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), | ||
| 899 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), | ||
| 900 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), | ||
| 901 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), | ||
| 902 | PINMUX_IPSR_DATA(IP0_30_27, D8), | ||
| 903 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), | ||
| 904 | PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), | ||
| 905 | PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0), | ||
| 906 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), | ||
| 907 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), | ||
| 908 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), | ||
| 909 | |||
| 910 | PINMUX_IPSR_DATA(IP1_3_0, D9), | ||
| 911 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), | ||
| 912 | PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), | ||
| 913 | PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1), | ||
| 914 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), | ||
| 915 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), | ||
| 916 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), | ||
| 917 | PINMUX_IPSR_DATA(IP1_7_4, D10), | ||
| 918 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), | ||
| 919 | PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), | ||
| 920 | PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2), | ||
| 921 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), | ||
| 922 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), | ||
| 923 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), | ||
| 924 | PINMUX_IPSR_DATA(IP1_11_8, D11), | ||
| 925 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), | ||
| 926 | PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), | ||
| 927 | PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3), | ||
| 928 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), | ||
| 929 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), | ||
| 930 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), | ||
| 931 | PINMUX_IPSR_DATA(IP1_14_12, D12), | ||
| 932 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), | ||
| 933 | PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), | ||
| 934 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), | ||
| 935 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), | ||
| 936 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), | ||
| 937 | PINMUX_IPSR_DATA(IP1_17_15, D13), | ||
| 938 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2), | ||
| 939 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), | ||
| 940 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), | ||
| 941 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), | ||
| 942 | PINMUX_IPSR_DATA(IP1_21_18, D14), | ||
| 943 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), | ||
| 944 | PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), | ||
| 945 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), | ||
| 946 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), | ||
| 947 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), | ||
| 948 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), | ||
| 949 | PINMUX_IPSR_DATA(IP1_25_22, D15), | ||
| 950 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), | ||
| 951 | PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), | ||
| 952 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), | ||
| 953 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), | ||
| 954 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), | ||
| 955 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), | ||
| 956 | PINMUX_IPSR_DATA(IP1_27_26, A0), | ||
| 957 | PINMUX_IPSR_DATA(IP1_27_26, PWM3), | ||
| 958 | PINMUX_IPSR_DATA(IP1_29_28, A1), | ||
| 959 | PINMUX_IPSR_DATA(IP1_29_28, PWM4), | ||
| 960 | |||
| 961 | PINMUX_IPSR_DATA(IP2_2_0, A2), | ||
| 962 | PINMUX_IPSR_DATA(IP2_2_0, PWM5), | ||
| 963 | PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), | ||
| 964 | PINMUX_IPSR_DATA(IP2_5_3, A3), | ||
| 965 | PINMUX_IPSR_DATA(IP2_5_3, PWM6), | ||
| 966 | PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), | ||
| 967 | PINMUX_IPSR_DATA(IP2_8_6, A4), | ||
| 968 | PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), | ||
| 969 | PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), | ||
| 970 | PINMUX_IPSR_DATA(IP2_11_9, A5), | ||
| 971 | PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), | ||
| 972 | PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), | ||
| 973 | PINMUX_IPSR_DATA(IP2_14_12, A6), | ||
| 974 | PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), | ||
| 975 | PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), | ||
| 976 | PINMUX_IPSR_DATA(IP2_17_15, A7), | ||
| 977 | PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), | ||
| 978 | PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), | ||
| 979 | PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), | ||
| 980 | PINMUX_IPSR_DATA(IP2_21_18, A8), | ||
| 981 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), | ||
| 982 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), | ||
| 983 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), | ||
| 984 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), | ||
| 985 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), | ||
| 986 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), | ||
| 987 | PINMUX_IPSR_DATA(IP2_25_22, A9), | ||
| 988 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), | ||
| 989 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), | ||
| 990 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), | ||
| 991 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), | ||
| 992 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), | ||
| 993 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), | ||
| 994 | PINMUX_IPSR_DATA(IP2_28_26, A10), | ||
| 995 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), | ||
| 996 | PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), | ||
| 997 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), | ||
| 998 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), | ||
| 999 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), | ||
| 1000 | |||
| 1001 | PINMUX_IPSR_DATA(IP3_3_0, A11), | ||
| 1002 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), | ||
| 1003 | PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), | ||
| 1004 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), | ||
| 1005 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), | ||
| 1006 | PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), | ||
| 1007 | PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B), | ||
| 1008 | PINMUX_IPSR_DATA(IP3_7_4, A12), | ||
| 1009 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), | ||
| 1010 | PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), | ||
| 1011 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), | ||
| 1012 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), | ||
| 1013 | PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), | ||
| 1014 | PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B), | ||
| 1015 | PINMUX_IPSR_DATA(IP3_11_8, A13), | ||
| 1016 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), | ||
| 1017 | PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), | ||
| 1018 | PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), | ||
| 1019 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), | ||
| 1020 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), | ||
| 1021 | PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), | ||
| 1022 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0), | ||
| 1023 | PINMUX_IPSR_DATA(IP3_14_12, A14), | ||
| 1024 | PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), | ||
| 1025 | PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), | ||
| 1026 | PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), | ||
| 1027 | PINMUX_IPSR_DATA(IP3_17_15, A15), | ||
| 1028 | PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), | ||
| 1029 | PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), | ||
| 1030 | PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), | ||
| 1031 | PINMUX_IPSR_DATA(IP3_19_18, A16), | ||
| 1032 | PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), | ||
| 1033 | PINMUX_IPSR_DATA(IP3_22_20, A17), | ||
| 1034 | PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), | ||
| 1035 | PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), | ||
| 1036 | PINMUX_IPSR_DATA(IP3_25_23, A18), | ||
| 1037 | PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), | ||
| 1038 | PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), | ||
| 1039 | PINMUX_IPSR_DATA(IP3_28_26, A19), | ||
| 1040 | PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), | ||
| 1041 | PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), | ||
| 1042 | PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), | ||
| 1043 | PINMUX_IPSR_DATA(IP3_31_29, A20), | ||
| 1044 | PINMUX_IPSR_DATA(IP3_31_29, SPCLK), | ||
| 1045 | PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), | ||
| 1046 | PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), | ||
| 1047 | PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), | ||
| 1048 | |||
| 1049 | PINMUX_IPSR_DATA(IP4_2_0, A21), | ||
| 1050 | PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), | ||
| 1051 | PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), | ||
| 1052 | PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), | ||
| 1053 | PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), | ||
| 1054 | PINMUX_IPSR_DATA(IP4_5_3, A22), | ||
| 1055 | PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), | ||
| 1056 | PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), | ||
| 1057 | PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), | ||
| 1058 | PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), | ||
| 1059 | PINMUX_IPSR_DATA(IP4_8_6, A23), | ||
| 1060 | PINMUX_IPSR_DATA(IP4_8_6, IO2), | ||
| 1061 | PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), | ||
| 1062 | PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), | ||
| 1063 | PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), | ||
| 1064 | PINMUX_IPSR_DATA(IP4_11_9, A24), | ||
| 1065 | PINMUX_IPSR_DATA(IP4_11_9, IO3), | ||
| 1066 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), | ||
| 1067 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), | ||
| 1068 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), | ||
| 1069 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), | ||
| 1070 | PINMUX_IPSR_DATA(IP4_14_12, A25), | ||
| 1071 | PINMUX_IPSR_DATA(IP4_14_12, SSL), | ||
| 1072 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), | ||
| 1073 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), | ||
| 1074 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), | ||
| 1075 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), | ||
| 1076 | PINMUX_IPSR_DATA(IP4_17_15, CS0_N), | ||
| 1077 | PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), | ||
| 1078 | PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), | ||
| 1079 | PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), | ||
| 1080 | PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), | ||
| 1081 | PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), | ||
| 1082 | PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), | ||
| 1083 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), | ||
| 1084 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), | ||
| 1085 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), | ||
| 1086 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), | ||
| 1087 | PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), | ||
| 1088 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), | ||
| 1089 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), | ||
| 1090 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), | ||
| 1091 | PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), | ||
| 1092 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), | ||
| 1093 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), | ||
| 1094 | PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), | ||
| 1095 | PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), | ||
| 1096 | PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), | ||
| 1097 | PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), | ||
| 1098 | PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), | ||
| 1099 | PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), | ||
| 1100 | PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), | ||
| 1101 | PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), | ||
| 1102 | PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), | ||
| 1103 | PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), | ||
| 1104 | PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), | ||
| 1105 | PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), | ||
| 1106 | PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), | ||
| 1107 | |||
| 1108 | PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), | ||
| 1109 | PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), | ||
| 1110 | PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), | ||
| 1111 | PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), | ||
| 1112 | PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), | ||
| 1113 | PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), | ||
| 1114 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0), | ||
| 1115 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), | ||
| 1116 | PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), | ||
| 1117 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), | ||
| 1118 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), | ||
| 1119 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), | ||
| 1120 | PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), | ||
| 1121 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), | ||
| 1122 | PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), | ||
| 1123 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), | ||
| 1124 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), | ||
| 1125 | PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), | ||
| 1126 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), | ||
| 1127 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), | ||
| 1128 | PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), | ||
| 1129 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), | ||
| 1130 | PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), | ||
| 1131 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), | ||
| 1132 | PINMUX_IPSR_DATA(IP5_12_10, BS_N), | ||
| 1133 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), | ||
| 1134 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), | ||
| 1135 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), | ||
| 1136 | PINMUX_IPSR_DATA(IP5_12_10, DRACK0), | ||
| 1137 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), | ||
| 1138 | PINMUX_IPSR_DATA(IP5_14_13, RD_N), | ||
| 1139 | PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), | ||
| 1140 | PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), | ||
| 1141 | PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), | ||
| 1142 | PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), | ||
| 1143 | PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), | ||
| 1144 | PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), | ||
| 1145 | PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), | ||
| 1146 | PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), | ||
| 1147 | PINMUX_IPSR_DATA(IP5_20_18, WE0_N), | ||
| 1148 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), | ||
| 1149 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), | ||
| 1150 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), | ||
| 1151 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), | ||
| 1152 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), | ||
| 1153 | PINMUX_IPSR_DATA(IP5_23_21, WE1_N), | ||
| 1154 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), | ||
| 1155 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), | ||
| 1156 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), | ||
| 1157 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), | ||
| 1158 | PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), | ||
| 1159 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), | ||
| 1160 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), | ||
| 1161 | PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0), | ||
| 1162 | PINMUX_IPSR_DATA(IP5_26_24, IRQ3), | ||
| 1163 | PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), | ||
| 1164 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), | ||
| 1165 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), | ||
| 1166 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), | ||
| 1167 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), | ||
| 1168 | PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), | ||
| 1169 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), | ||
| 1170 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), | ||
| 1171 | PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), | ||
| 1172 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), | ||
| 1173 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), | ||
| 1174 | |||
| 1175 | PINMUX_IPSR_DATA(IP6_2_0, DACK0), | ||
| 1176 | PINMUX_IPSR_DATA(IP6_2_0, IRQ0), | ||
| 1177 | PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), | ||
| 1178 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), | ||
| 1179 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), | ||
| 1180 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), | ||
| 1181 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), | ||
| 1182 | PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), | ||
| 1183 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), | ||
| 1184 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), | ||
| 1185 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), | ||
| 1186 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), | ||
| 1187 | PINMUX_IPSR_DATA(IP6_8_6, DACK1), | ||
| 1188 | PINMUX_IPSR_DATA(IP6_8_6, IRQ1), | ||
| 1189 | PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), | ||
| 1190 | PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), | ||
| 1191 | PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), | ||
| 1192 | PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), | ||
| 1193 | PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), | ||
| 1194 | PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), | ||
| 1195 | PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), | ||
| 1196 | PINMUX_IPSR_DATA(IP6_13_11, DACK2), | ||
| 1197 | PINMUX_IPSR_DATA(IP6_13_11, IRQ2), | ||
| 1198 | PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), | ||
| 1199 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), | ||
| 1200 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), | ||
| 1201 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), | ||
| 1202 | PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), | ||
| 1203 | PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), | ||
| 1204 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), | ||
| 1205 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), | ||
| 1206 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), | ||
| 1207 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), | ||
| 1208 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), | ||
| 1209 | PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), | ||
| 1210 | PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), | ||
| 1211 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), | ||
| 1212 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), | ||
| 1213 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), | ||
| 1214 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), | ||
| 1215 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), | ||
| 1216 | PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), | ||
| 1217 | PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), | ||
| 1218 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), | ||
| 1219 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), | ||
| 1220 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), | ||
| 1221 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), | ||
| 1222 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), | ||
| 1223 | PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), | ||
| 1224 | PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), | ||
| 1225 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), | ||
| 1226 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), | ||
| 1227 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), | ||
| 1228 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), | ||
| 1229 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), | ||
| 1230 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), | ||
| 1231 | PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), | ||
| 1232 | PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), | ||
| 1233 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), | ||
| 1234 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), | ||
| 1235 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), | ||
| 1236 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), | ||
| 1237 | PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), | ||
| 1238 | PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), | ||
| 1239 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), | ||
| 1240 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), | ||
| 1241 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), | ||
| 1242 | |||
| 1243 | PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), | ||
| 1244 | PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), | ||
| 1245 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), | ||
| 1246 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), | ||
| 1247 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), | ||
| 1248 | PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), | ||
| 1249 | PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), | ||
| 1250 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), | ||
| 1251 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), | ||
| 1252 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), | ||
| 1253 | PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), | ||
| 1254 | PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), | ||
| 1255 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), | ||
| 1256 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), | ||
| 1257 | PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), | ||
| 1258 | PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), | ||
| 1259 | PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), | ||
| 1260 | PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), | ||
| 1261 | PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), | ||
| 1262 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), | ||
| 1263 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), | ||
| 1264 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), | ||
| 1265 | PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), | ||
| 1266 | PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), | ||
| 1267 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), | ||
| 1268 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), | ||
| 1269 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), | ||
| 1270 | PINMUX_IPSR_DATA(IP7_18_16, PWM0), | ||
| 1271 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), | ||
| 1272 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), | ||
| 1273 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), | ||
| 1274 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), | ||
| 1275 | PINMUX_IPSR_DATA(IP7_21_19, PWM1), | ||
| 1276 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), | ||
| 1277 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), | ||
| 1278 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), | ||
| 1279 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), | ||
| 1280 | PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), | ||
| 1281 | PINMUX_IPSR_DATA(IP7_24_22, PWM2), | ||
| 1282 | PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), | ||
| 1283 | PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), | ||
| 1284 | PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), | ||
| 1285 | PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), | ||
| 1286 | PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), | ||
| 1287 | PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), | ||
| 1288 | PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), | ||
| 1289 | PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), | ||
| 1290 | PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), | ||
| 1291 | PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), | ||
| 1292 | PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), | ||
| 1293 | PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), | ||
| 1294 | PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), | ||
| 1295 | PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), | ||
| 1296 | PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), | ||
| 1297 | |||
| 1298 | PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), | ||
| 1299 | PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), | ||
| 1300 | PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), | ||
| 1301 | PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), | ||
| 1302 | PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), | ||
| 1303 | PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), | ||
| 1304 | PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), | ||
| 1305 | PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), | ||
| 1306 | PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), | ||
| 1307 | PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), | ||
| 1308 | PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), | ||
| 1309 | PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), | ||
| 1310 | PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), | ||
| 1311 | PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), | ||
| 1312 | PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), | ||
| 1313 | PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), | ||
| 1314 | PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), | ||
| 1315 | PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), | ||
| 1316 | PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), | ||
| 1317 | PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), | ||
| 1318 | PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), | ||
| 1319 | PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), | ||
| 1320 | PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), | ||
| 1321 | PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), | ||
| 1322 | PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), | ||
| 1323 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), | ||
| 1324 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), | ||
| 1325 | PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), | ||
| 1326 | PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), | ||
| 1327 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), | ||
| 1328 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), | ||
| 1329 | PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), | ||
| 1330 | PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), | ||
| 1331 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), | ||
| 1332 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), | ||
| 1333 | PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), | ||
| 1334 | PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), | ||
| 1335 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), | ||
| 1336 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), | ||
| 1337 | PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), | ||
| 1338 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), | ||
| 1339 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), | ||
| 1340 | PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), | ||
| 1341 | PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), | ||
| 1342 | PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), | ||
| 1343 | PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), | ||
| 1344 | PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), | ||
| 1345 | PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), | ||
| 1346 | PINMUX_IPSR_DATA(IP8_28, SD0_CLK), | ||
| 1347 | PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), | ||
| 1348 | PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), | ||
| 1349 | PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), | ||
| 1350 | PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), | ||
| 1351 | |||
| 1352 | PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), | ||
| 1353 | PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), | ||
| 1354 | PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), | ||
| 1355 | PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), | ||
| 1356 | PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), | ||
| 1357 | PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), | ||
| 1358 | PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), | ||
| 1359 | PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), | ||
| 1360 | PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), | ||
| 1361 | PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), | ||
| 1362 | PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), | ||
| 1363 | PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), | ||
| 1364 | PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), | ||
| 1365 | PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), | ||
| 1366 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), | ||
| 1367 | PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), | ||
| 1368 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), | ||
| 1369 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), | ||
| 1370 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), | ||
| 1371 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), | ||
| 1372 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), | ||
| 1373 | PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), | ||
| 1374 | PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), | ||
| 1375 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), | ||
| 1376 | PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), | ||
| 1377 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), | ||
| 1378 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), | ||
| 1379 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), | ||
| 1380 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), | ||
| 1381 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), | ||
| 1382 | PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), | ||
| 1383 | PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), | ||
| 1384 | PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), | ||
| 1385 | PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), | ||
| 1386 | PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), | ||
| 1387 | PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), | ||
| 1388 | PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), | ||
| 1389 | PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), | ||
| 1390 | PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), | ||
| 1391 | PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), | ||
| 1392 | PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), | ||
| 1393 | PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), | ||
| 1394 | PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), | ||
| 1395 | PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), | ||
| 1396 | PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), | ||
| 1397 | PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), | ||
| 1398 | PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), | ||
| 1399 | PINMUX_IPSR_DATA(IP9_25_24, MII_COL), | ||
| 1400 | PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), | ||
| 1401 | PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), | ||
| 1402 | PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), | ||
| 1403 | PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), | ||
| 1404 | PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), | ||
| 1405 | PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), | ||
| 1406 | PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), | ||
| 1407 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), | ||
| 1408 | PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), | ||
| 1409 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), | ||
| 1410 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), | ||
| 1411 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), | ||
| 1412 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), | ||
| 1413 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), | ||
| 1414 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), | ||
| 1415 | |||
| 1416 | PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), | ||
| 1417 | PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), | ||
| 1418 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), | ||
| 1419 | PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), | ||
| 1420 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), | ||
| 1421 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), | ||
| 1422 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), | ||
| 1423 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), | ||
| 1424 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), | ||
| 1425 | PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), | ||
| 1426 | PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), | ||
| 1427 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), | ||
| 1428 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), | ||
| 1429 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), | ||
| 1430 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), | ||
| 1431 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), | ||
| 1432 | PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), | ||
| 1433 | PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), | ||
| 1434 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), | ||
| 1435 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), | ||
| 1436 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), | ||
| 1437 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), | ||
| 1438 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), | ||
| 1439 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), | ||
| 1440 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), | ||
| 1441 | PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), | ||
| 1442 | PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), | ||
| 1443 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), | ||
| 1444 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), | ||
| 1445 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), | ||
| 1446 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), | ||
| 1447 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), | ||
| 1448 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), | ||
| 1449 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), | ||
| 1450 | PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), | ||
| 1451 | PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), | ||
| 1452 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), | ||
| 1453 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0), | ||
| 1454 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), | ||
| 1455 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), | ||
| 1456 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), | ||
| 1457 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), | ||
| 1458 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), | ||
| 1459 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), | ||
| 1460 | PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), | ||
| 1461 | PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), | ||
| 1462 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), | ||
| 1463 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0), | ||
| 1464 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), | ||
| 1465 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), | ||
| 1466 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), | ||
| 1467 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), | ||
| 1468 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), | ||
| 1469 | PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), | ||
| 1470 | PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), | ||
| 1471 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), | ||
| 1472 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), | ||
| 1473 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), | ||
| 1474 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), | ||
| 1475 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), | ||
| 1476 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), | ||
| 1477 | PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), | ||
| 1478 | PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), | ||
| 1479 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), | ||
| 1480 | PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), | ||
| 1481 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), | ||
| 1482 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), | ||
| 1483 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), | ||
| 1484 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), | ||
| 1485 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), | ||
| 1486 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), | ||
| 1487 | |||
| 1488 | PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), | ||
| 1489 | PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), | ||
| 1490 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), | ||
| 1491 | PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), | ||
| 1492 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), | ||
| 1493 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), | ||
| 1494 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), | ||
| 1495 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), | ||
| 1496 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), | ||
| 1497 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), | ||
| 1498 | PINMUX_IPSR_DATA(IP11_4, SD3_CLK), | ||
| 1499 | PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), | ||
| 1500 | PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), | ||
| 1501 | PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), | ||
| 1502 | PINMUX_IPSR_DATA(IP11_6_5, MTS_N), | ||
| 1503 | PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), | ||
| 1504 | PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), | ||
| 1505 | PINMUX_IPSR_DATA(IP11_8_7, STM_N), | ||
| 1506 | PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), | ||
| 1507 | PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), | ||
| 1508 | PINMUX_IPSR_DATA(IP11_10_9, MDATA), | ||
| 1509 | PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), | ||
| 1510 | PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), | ||
| 1511 | PINMUX_IPSR_DATA(IP11_12_11, SDATA), | ||
| 1512 | PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), | ||
| 1513 | PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), | ||
| 1514 | PINMUX_IPSR_DATA(IP11_14_13, SCKZ), | ||
| 1515 | PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), | ||
| 1516 | PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), | ||
| 1517 | PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), | ||
| 1518 | PINMUX_IPSR_DATA(IP11_17_15, VSP), | ||
| 1519 | PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), | ||
| 1520 | PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), | ||
| 1521 | PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), | ||
| 1522 | PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), | ||
| 1523 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), | ||
| 1524 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), | ||
| 1525 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), | ||
| 1526 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1), | ||
| 1527 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), | ||
| 1528 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3), | ||
| 1529 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), | ||
| 1530 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), | ||
| 1531 | PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), | ||
| 1532 | PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), | ||
| 1533 | PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), | ||
| 1534 | PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), | ||
| 1535 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), | ||
| 1536 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), | ||
| 1537 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), | ||
| 1538 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), | ||
| 1539 | PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), | ||
| 1540 | PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), | ||
| 1541 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), | ||
| 1542 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), | ||
| 1543 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), | ||
| 1544 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1), | ||
| 1545 | PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), | ||
| 1546 | PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), | ||
| 1547 | PINMUX_IPSR_DATA(IP11_31_30, MOUT0), | ||
| 1548 | |||
| 1549 | PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), | ||
| 1550 | PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), | ||
| 1551 | PINMUX_IPSR_DATA(IP12_1_0, MOUT1), | ||
| 1552 | PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), | ||
| 1553 | PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), | ||
| 1554 | PINMUX_IPSR_DATA(IP12_3_2, MOUT2), | ||
| 1555 | PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), | ||
| 1556 | PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), | ||
| 1557 | PINMUX_IPSR_DATA(IP12_5_4, MOUT5), | ||
| 1558 | PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), | ||
| 1559 | PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), | ||
| 1560 | PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1), | ||
| 1561 | PINMUX_IPSR_DATA(IP12_7_6, MOUT6), | ||
| 1562 | PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), | ||
| 1563 | PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), | ||
| 1564 | PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), | ||
| 1565 | PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), | ||
| 1566 | PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), | ||
| 1567 | PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), | ||
| 1568 | PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), | ||
| 1569 | PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), | ||
| 1570 | PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), | ||
| 1571 | PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), | ||
| 1572 | PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), | ||
| 1573 | PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), | ||
| 1574 | PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), | ||
| 1575 | PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), | ||
| 1576 | PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), | ||
| 1577 | PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), | ||
| 1578 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), | ||
| 1579 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), | ||
| 1580 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), | ||
| 1581 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), | ||
| 1582 | PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), | ||
| 1583 | PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), | ||
| 1584 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), | ||
| 1585 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), | ||
| 1586 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), | ||
| 1587 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), | ||
| 1588 | PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), | ||
| 1589 | PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), | ||
| 1590 | PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), | ||
| 1591 | PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), | ||
| 1592 | PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), | ||
| 1593 | PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), | ||
| 1594 | PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), | ||
| 1595 | PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), | ||
| 1596 | PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), | ||
| 1597 | PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), | ||
| 1598 | PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), | ||
| 1599 | PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), | ||
| 1600 | PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), | ||
| 1601 | PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), | ||
| 1602 | PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), | ||
| 1603 | PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), | ||
| 1604 | PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), | ||
| 1605 | |||
| 1606 | PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), | ||
| 1607 | PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), | ||
| 1608 | PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), | ||
| 1609 | PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), | ||
| 1610 | PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), | ||
| 1611 | PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), | ||
| 1612 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), | ||
| 1613 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), | ||
| 1614 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), | ||
| 1615 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2), | ||
| 1616 | PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), | ||
| 1617 | PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), | ||
| 1618 | PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), | ||
| 1619 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), | ||
| 1620 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4), | ||
| 1621 | PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), | ||
| 1622 | PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), | ||
| 1623 | PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), | ||
| 1624 | PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), | ||
| 1625 | PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), | ||
| 1626 | PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), | ||
| 1627 | PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), | ||
| 1628 | PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), | ||
| 1629 | PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2), | ||
| 1630 | PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), | ||
| 1631 | PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), | ||
| 1632 | PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), | ||
| 1633 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), | ||
| 1634 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), | ||
| 1635 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), | ||
| 1636 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), | ||
| 1637 | PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), | ||
| 1638 | PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), | ||
| 1639 | PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), | ||
| 1640 | PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), | ||
| 1641 | PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), | ||
| 1642 | PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), | ||
| 1643 | PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), | ||
| 1644 | PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), | ||
| 1645 | PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), | ||
| 1646 | PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), | ||
| 1647 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), | ||
| 1648 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), | ||
| 1649 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), | ||
| 1650 | PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), | ||
| 1651 | PINMUX_IPSR_DATA(IP13_22_19, TCLK2), | ||
| 1652 | PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), | ||
| 1653 | PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), | ||
| 1654 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), | ||
| 1655 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3), | ||
| 1656 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), | ||
| 1657 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), | ||
| 1658 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5), | ||
| 1659 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), | ||
| 1660 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), | ||
| 1661 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), | ||
| 1662 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), | ||
| 1663 | PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), | ||
| 1664 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), | ||
| 1665 | PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), | ||
| 1666 | PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), | ||
| 1667 | PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), | ||
| 1668 | PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), | ||
| 1669 | PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), | ||
| 1670 | PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), | ||
| 1671 | PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), | ||
| 1672 | PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), | ||
| 1673 | PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), | ||
| 1674 | |||
| 1675 | PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), | ||
| 1676 | PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), | ||
| 1677 | PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), | ||
| 1678 | PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), | ||
| 1679 | PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), | ||
| 1680 | PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), | ||
| 1681 | PINMUX_IPSR_DATA(IP14_2_0, REMOCON), | ||
| 1682 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), | ||
| 1683 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), | ||
| 1684 | PINMUX_IPSR_DATA(IP14_5_3, SCK0), | ||
| 1685 | PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), | ||
| 1686 | PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), | ||
| 1687 | PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), | ||
| 1688 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), | ||
| 1689 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), | ||
| 1690 | PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), | ||
| 1691 | PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), | ||
| 1692 | PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), | ||
| 1693 | PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), | ||
| 1694 | PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), | ||
| 1695 | PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), | ||
| 1696 | PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), | ||
| 1697 | PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), | ||
| 1698 | PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), | ||
| 1699 | PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), | ||
| 1700 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), | ||
| 1701 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), | ||
| 1702 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0), | ||
| 1703 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), | ||
| 1704 | PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), | ||
| 1705 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), | ||
| 1706 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), | ||
| 1707 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), | ||
| 1708 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), | ||
| 1709 | PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), | ||
| 1710 | PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), | ||
| 1711 | PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), | ||
| 1712 | PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), | ||
| 1713 | PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), | ||
| 1714 | PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), | ||
| 1715 | PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), | ||
| 1716 | PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), | ||
| 1717 | PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), | ||
| 1718 | PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), | ||
| 1719 | PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), | ||
| 1720 | PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), | ||
| 1721 | PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), | ||
| 1722 | PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), | ||
| 1723 | PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), | ||
| 1724 | PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), | ||
| 1725 | PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), | ||
| 1726 | PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), | ||
| 1727 | PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), | ||
| 1728 | PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), | ||
| 1729 | PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), | ||
| 1730 | PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), | ||
| 1731 | PINMUX_IPSR_DATA(IP14_27_25, QCLK), | ||
| 1732 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), | ||
| 1733 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), | ||
| 1734 | PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), | ||
| 1735 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), | ||
| 1736 | PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), | ||
| 1737 | PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), | ||
| 1738 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), | ||
| 1739 | |||
| 1740 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), | ||
| 1741 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), | ||
| 1742 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), | ||
| 1743 | PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), | ||
| 1744 | PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), | ||
| 1745 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), | ||
| 1746 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), | ||
| 1747 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), | ||
| 1748 | PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), | ||
| 1749 | PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), | ||
| 1750 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), | ||
| 1751 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), | ||
| 1752 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), | ||
| 1753 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), | ||
| 1754 | PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), | ||
| 1755 | PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), | ||
| 1756 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), | ||
| 1757 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), | ||
| 1758 | PINMUX_IPSR_DATA(IP15_11_9, HSCK0), | ||
| 1759 | PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), | ||
| 1760 | PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), | ||
| 1761 | PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), | ||
| 1762 | PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), | ||
| 1763 | PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0), | ||
| 1764 | PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), | ||
| 1765 | PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), | ||
| 1766 | PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), | ||
| 1767 | PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), | ||
| 1768 | PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), | ||
| 1769 | PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), | ||
| 1770 | PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), | ||
| 1771 | PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), | ||
| 1772 | PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), | ||
| 1773 | PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), | ||
| 1774 | PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), | ||
| 1775 | PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), | ||
| 1776 | PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), | ||
| 1777 | PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), | ||
| 1778 | PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), | ||
| 1779 | PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), | ||
| 1780 | PINMUX_IPSR_DATA(IP15_22_20, ADICLK), | ||
| 1781 | PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), | ||
| 1782 | PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), | ||
| 1783 | PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), | ||
| 1784 | PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), | ||
| 1785 | PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), | ||
| 1786 | PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), | ||
| 1787 | PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), | ||
| 1788 | PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), | ||
| 1789 | PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1), | ||
| 1790 | PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), | ||
| 1791 | PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), | ||
| 1792 | PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), | ||
| 1793 | PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), | ||
| 1794 | PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), | ||
| 1795 | PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), | ||
| 1796 | PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), | ||
| 1797 | PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), | ||
| 1798 | |||
| 1799 | PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), | ||
| 1800 | PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), | ||
| 1801 | PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), | ||
| 1802 | PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), | ||
| 1803 | PINMUX_IPSR_DATA(IP16_2_0, QPOLA), | ||
| 1804 | PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), | ||
| 1805 | PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), | ||
| 1806 | PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), | ||
| 1807 | PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), | ||
| 1808 | PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), | ||
| 1809 | PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), | ||
| 1810 | PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), | ||
| 1811 | PINMUX_IPSR_DATA(IP16_5_3, QPOLB), | ||
| 1812 | PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2), | ||
| 1813 | PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), | ||
| 1814 | PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), | ||
| 1815 | PINMUX_IPSR_DATA(IP16_7, USB1_OVC), | ||
| 1816 | PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), | ||
| 1817 | }; | ||
| 1818 | |||
| 1819 | static struct sh_pfc_pin pinmux_pins[] = { | ||
| 1820 | PINMUX_GPIO_GP_ALL(), | ||
| 1821 | }; | ||
| 1822 | |||
| 1823 | #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) | ||
| 1824 | |||
| 1825 | static const struct pinmux_func pinmux_func_gpios[] = { | ||
| 1826 | GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS), | ||
| 1827 | GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2), | ||
| 1828 | GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2), | ||
| 1829 | |||
| 1830 | /*IPSR0*/ | ||
| 1831 | GPIO_FN(D1), GPIO_FN(MSIOF3_SYNC_B), GPIO_FN(VI3_DATA1), | ||
| 1832 | GPIO_FN(VI0_G5), GPIO_FN(VI0_G5_B), GPIO_FN(D2), GPIO_FN(MSIOF3_RXD_B), | ||
| 1833 | GPIO_FN(VI3_DATA2), GPIO_FN(VI0_G6), GPIO_FN(VI0_G6_B), GPIO_FN(D3), | ||
| 1834 | GPIO_FN(MSIOF3_TXD_B), GPIO_FN(VI3_DATA3), GPIO_FN(VI0_G7), | ||
| 1835 | GPIO_FN(VI0_G7_B), GPIO_FN(D4), GPIO_FN(SCIFB1_RXD_F), | ||
| 1836 | GPIO_FN(SCIFB0_RXD_C), GPIO_FN(VI3_DATA4), GPIO_FN(VI0_R0), | ||
| 1837 | GPIO_FN(VI0_R0_B), GPIO_FN(RX0_B), GPIO_FN(D5), GPIO_FN(SCIFB1_TXD_F), | ||
| 1838 | GPIO_FN(SCIFB0_TXD_C), GPIO_FN(VI3_DATA5), GPIO_FN(VI0_R1), | ||
| 1839 | GPIO_FN(VI0_R1_B), GPIO_FN(TX0_B), GPIO_FN(D6), GPIO_FN(SCL2_C), | ||
| 1840 | GPIO_FN(VI3_DATA6), GPIO_FN(VI0_R2), GPIO_FN(VI0_R2_B), | ||
| 1841 | GPIO_FN(SCL2_CIS_C), GPIO_FN(D7), GPIO_FN(AD_DI_B), GPIO_FN(SDA2_C), | ||
| 1842 | GPIO_FN(VI3_DATA7), GPIO_FN(VI0_R3), GPIO_FN(VI0_R3_B), | ||
| 1843 | GPIO_FN(SDA2_CIS_C), GPIO_FN(D8), GPIO_FN(SCIFA1_SCK_C), | ||
| 1844 | GPIO_FN(AVB_TXD0), GPIO_FN(MII_TXD0), GPIO_FN(VI0_G0), | ||
| 1845 | GPIO_FN(VI0_G0_B), GPIO_FN(VI2_DATA0_VI2_B0), | ||
| 1846 | |||
| 1847 | /*IPSR1*/ | ||
| 1848 | GPIO_FN(D9), GPIO_FN(SCIFA1_RXD_C), GPIO_FN(AVB_TXD1), | ||
| 1849 | GPIO_FN(MII_TXD1), GPIO_FN(VI0_G1), GPIO_FN(VI0_G1_B), | ||
| 1850 | GPIO_FN(VI2_DATA1_VI2_B1), GPIO_FN(D10), GPIO_FN(SCIFA1_TXD_C), | ||
| 1851 | GPIO_FN(AVB_TXD2), GPIO_FN(MII_TXD2), GPIO_FN(VI0_G2), | ||
| 1852 | GPIO_FN(VI0_G2_B), GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(D11), | ||
| 1853 | GPIO_FN(SCIFA1_CTS_N_C), GPIO_FN(AVB_TXD3), GPIO_FN(MII_TXD3), | ||
| 1854 | GPIO_FN(VI0_G3), GPIO_FN(VI0_G3_B), GPIO_FN(VI2_DATA3_VI2_B3), | ||
| 1855 | GPIO_FN(D12), GPIO_FN(SCIFA1_RTS_N_C), GPIO_FN(AVB_TXD4), | ||
| 1856 | GPIO_FN(VI0_HSYNC_N), GPIO_FN(VI0_HSYNC_N_B), GPIO_FN(VI2_DATA4_VI2_B4), | ||
| 1857 | GPIO_FN(D13), GPIO_FN(AVB_TXD5), GPIO_FN(VI0_VSYNC_N), | ||
| 1858 | GPIO_FN(VI0_VSYNC_N_B), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(D14), | ||
| 1859 | GPIO_FN(SCIFB1_RXD_C), GPIO_FN(AVB_TXD6), GPIO_FN(RX1_B), | ||
| 1860 | GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_CLKENB_B), GPIO_FN(VI2_DATA6_VI2_B6), | ||
| 1861 | GPIO_FN(D15), GPIO_FN(SCIFB1_TXD_C), GPIO_FN(AVB_TXD7), GPIO_FN(TX1_B), | ||
| 1862 | GPIO_FN(VI0_FIELD), GPIO_FN(VI0_FIELD_B), GPIO_FN(VI2_DATA7_VI2_B7), | ||
| 1863 | GPIO_FN(A0), GPIO_FN(PWM3), GPIO_FN(A1), GPIO_FN(PWM4), | ||
| 1864 | |||
| 1865 | /*IPSR2*/ | ||
| 1866 | GPIO_FN(A2), GPIO_FN(PWM5), GPIO_FN(MSIOF1_SS1_B), GPIO_FN(A3), | ||
| 1867 | GPIO_FN(PWM6), GPIO_FN(MSIOF1_SS2_B), GPIO_FN(A4), | ||
| 1868 | GPIO_FN(MSIOF1_TXD_B), GPIO_FN(TPU0TO0), GPIO_FN(A5), | ||
| 1869 | GPIO_FN(SCIFA1_TXD_B), GPIO_FN(TPU0TO1), GPIO_FN(A6), | ||
| 1870 | GPIO_FN(SCIFA1_RTS_N_B), GPIO_FN(TPU0TO2), GPIO_FN(A7), | ||
| 1871 | GPIO_FN(SCIFA1_SCK_B), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(TPU0TO3), | ||
| 1872 | GPIO_FN(A8), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(SSI_SCK5_B), | ||
| 1873 | GPIO_FN(VI0_R4), GPIO_FN(VI0_R4_B), GPIO_FN(SCIFB2_RXD_C), | ||
| 1874 | GPIO_FN(VI2_DATA0_VI2_B0_B), GPIO_FN(A9), GPIO_FN(SCIFA1_CTS_N_B), | ||
| 1875 | GPIO_FN(SSI_WS5_B), GPIO_FN(VI0_R5), GPIO_FN(VI0_R5_B), | ||
| 1876 | GPIO_FN(SCIFB2_TXD_C), GPIO_FN(VI2_DATA1_VI2_B1_B), GPIO_FN(A10), | ||
| 1877 | GPIO_FN(SSI_SDATA5_B), GPIO_FN(MSIOF2_SYNC), GPIO_FN(VI0_R6), | ||
| 1878 | GPIO_FN(VI0_R6_B), GPIO_FN(VI2_DATA2_VI2_B2_B), | ||
| 1879 | |||
| 1880 | /*IPSR3*/ | ||
| 1881 | GPIO_FN(A11), GPIO_FN(SCIFB2_CTS_N_B), GPIO_FN(MSIOF2_SCK), | ||
| 1882 | GPIO_FN(VI1_R0), GPIO_FN(VI1_R0_B), GPIO_FN(VI2_G0), | ||
| 1883 | GPIO_FN(VI2_DATA3_VI2_B3_B), GPIO_FN(A12), GPIO_FN(SCIFB2_RXD_B), | ||
| 1884 | GPIO_FN(MSIOF2_TXD), GPIO_FN(VI1_R1), GPIO_FN(VI1_R1_B), | ||
| 1885 | GPIO_FN(VI2_G1), GPIO_FN(VI2_DATA4_VI2_B4_B), GPIO_FN(A13), | ||
| 1886 | GPIO_FN(SCIFB2_RTS_N_B), GPIO_FN(EX_WAIT2), GPIO_FN(MSIOF2_RXD), | ||
| 1887 | GPIO_FN(VI1_R2), GPIO_FN(VI1_R2_B), GPIO_FN(VI2_G2), | ||
| 1888 | GPIO_FN(VI2_DATA5_VI2_B5_B), GPIO_FN(A14), GPIO_FN(SCIFB2_TXD_B), | ||
| 1889 | GPIO_FN(ATACS11_N), GPIO_FN(MSIOF2_SS1), GPIO_FN(A15), | ||
| 1890 | GPIO_FN(SCIFB2_SCK_B), GPIO_FN(ATARD1_N), GPIO_FN(MSIOF2_SS2), | ||
| 1891 | GPIO_FN(A16), GPIO_FN(ATAWR1_N), GPIO_FN(A17), GPIO_FN(AD_DO_B), | ||
| 1892 | GPIO_FN(ATADIR1_N), GPIO_FN(A18), GPIO_FN(AD_CLK_B), GPIO_FN(ATAG1_N), | ||
| 1893 | GPIO_FN(A19), GPIO_FN(AD_NCS_N_B), GPIO_FN(ATACS01_N), | ||
| 1894 | GPIO_FN(EX_WAIT0_B), GPIO_FN(A20), GPIO_FN(SPCLK), GPIO_FN(VI1_R3), | ||
| 1895 | GPIO_FN(VI1_R3_B), GPIO_FN(VI2_G4), | ||
| 1896 | |||
| 1897 | /*IPSR4*/ | ||
| 1898 | GPIO_FN(A21), GPIO_FN(MOSI_IO0), GPIO_FN(VI1_R4), GPIO_FN(VI1_R4_B), | ||
| 1899 | GPIO_FN(VI2_G5), GPIO_FN(A22), GPIO_FN(MISO_IO1), GPIO_FN(VI1_R5), | ||
| 1900 | GPIO_FN(VI1_R5_B), GPIO_FN(VI2_G6), GPIO_FN(A23), GPIO_FN(IO2), | ||
| 1901 | GPIO_FN(VI1_G7), GPIO_FN(VI1_G7_B), GPIO_FN(VI2_G7), GPIO_FN(A24), | ||
| 1902 | GPIO_FN(IO3), GPIO_FN(VI1_R7), GPIO_FN(VI1_R7_B), GPIO_FN(VI2_CLKENB), | ||
| 1903 | GPIO_FN(VI2_CLKENB_B), GPIO_FN(A25), GPIO_FN(SSL), GPIO_FN(VI1_G6), | ||
| 1904 | GPIO_FN(VI1_G6_B), GPIO_FN(VI2_FIELD), GPIO_FN(VI2_FIELD_B), | ||
| 1905 | GPIO_FN(CS0_N), GPIO_FN(VI1_R6), GPIO_FN(VI1_R6_B), GPIO_FN(VI2_G3), | ||
| 1906 | GPIO_FN(MSIOF0_SS2_B), GPIO_FN(CS1_N_A26), GPIO_FN(SPEEDIN), | ||
| 1907 | GPIO_FN(VI0_R7), GPIO_FN(VI0_R7_B), GPIO_FN(VI2_CLK), | ||
| 1908 | GPIO_FN(VI2_CLK_B), GPIO_FN(EX_CS0_N), GPIO_FN(HRX1_B), | ||
| 1909 | GPIO_FN(VI1_G5), GPIO_FN(VI1_G5_B), GPIO_FN(VI2_R0), GPIO_FN(HTX0_B), | ||
| 1910 | GPIO_FN(MSIOF0_SS1_B), GPIO_FN(EX_CS1_N), GPIO_FN(GPS_CLK), | ||
| 1911 | GPIO_FN(HCTS1_N_B), GPIO_FN(VI1_FIELD), GPIO_FN(VI1_FIELD_B), | ||
| 1912 | GPIO_FN(VI2_R1), GPIO_FN(EX_CS2_N), GPIO_FN(GPS_SIGN), | ||
| 1913 | GPIO_FN(HRTS1_N_B), GPIO_FN(VI3_CLKENB), GPIO_FN(VI1_G0), | ||
| 1914 | GPIO_FN(VI1_G0_B), GPIO_FN(VI2_R2), | ||
| 1915 | |||
| 1916 | /*IPSR5*/ | ||
| 1917 | GPIO_FN(EX_CS3_N), GPIO_FN(GPS_MAG), GPIO_FN(VI3_FIELD), | ||
| 1918 | GPIO_FN(VI1_G1), GPIO_FN(VI1_G1_B), GPIO_FN(VI2_R3), GPIO_FN(EX_CS4_N), | ||
| 1919 | GPIO_FN(MSIOF1_SCK_B), GPIO_FN(VI3_HSYNC_N), GPIO_FN(VI2_HSYNC_N), | ||
| 1920 | GPIO_FN(SCL1), GPIO_FN(VI2_HSYNC_N_B), GPIO_FN(INTC_EN0_N), | ||
| 1921 | GPIO_FN(SCL1_CIS), GPIO_FN(EX_CS5_N), GPIO_FN(CAN0_RX), | ||
| 1922 | GPIO_FN(MSIOF1_RXD_B), GPIO_FN(VI3_VSYNC_N), GPIO_FN(VI1_G2), | ||
| 1923 | GPIO_FN(VI1_G2_B), GPIO_FN(VI2_R4), GPIO_FN(SDA1), GPIO_FN(INTC_EN1_N), | ||
| 1924 | GPIO_FN(SDA1_CIS), GPIO_FN(BS_N), GPIO_FN(IETX), GPIO_FN(HTX1_B), | ||
| 1925 | GPIO_FN(CAN1_TX), GPIO_FN(DRACK0), GPIO_FN(IETX_C), GPIO_FN(RD_N), | ||
| 1926 | GPIO_FN(CAN0_TX), GPIO_FN(SCIFA0_SCK_B), GPIO_FN(RD_WR_N), | ||
| 1927 | GPIO_FN(VI1_G3), GPIO_FN(VI1_G3_B), GPIO_FN(VI2_R5), | ||
| 1928 | GPIO_FN(SCIFA0_RXD_B), GPIO_FN(INTC_IRQ4_N), GPIO_FN(WE0_N), | ||
| 1929 | GPIO_FN(IECLK), GPIO_FN(CAN_CLK), GPIO_FN(VI2_VSYNC_N), | ||
| 1930 | GPIO_FN(SCIFA0_TXD_B), GPIO_FN(VI2_VSYNC_N_B), GPIO_FN(WE1_N), | ||
| 1931 | GPIO_FN(IERX), GPIO_FN(CAN1_RX), GPIO_FN(VI1_G4), GPIO_FN(VI1_G4_B), | ||
| 1932 | GPIO_FN(VI2_R6), GPIO_FN(SCIFA0_CTS_N_B), GPIO_FN(IERX_C), | ||
| 1933 | GPIO_FN(EX_WAIT0), GPIO_FN(IRQ3), GPIO_FN(INTC_IRQ3_N), | ||
| 1934 | GPIO_FN(VI3_CLK), GPIO_FN(SCIFA0_RTS_N_B), GPIO_FN(HRX0_B), | ||
| 1935 | GPIO_FN(MSIOF0_SCK_B), GPIO_FN(DREQ0_N), GPIO_FN(VI1_HSYNC_N), | ||
| 1936 | GPIO_FN(VI1_HSYNC_N_B), GPIO_FN(VI2_R7), GPIO_FN(SSI_SCK78_C), | ||
| 1937 | GPIO_FN(SSI_WS78_B), | ||
| 1938 | |||
| 1939 | /*IPSR6*/ | ||
| 1940 | GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), | ||
| 1941 | GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), | ||
| 1942 | GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB), | ||
| 1943 | GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B), | ||
| 1944 | GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B), | ||
| 1945 | GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B), | ||
| 1946 | GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2), | ||
| 1947 | GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B), | ||
| 1948 | GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV), | ||
| 1949 | GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D), | ||
| 1950 | GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E), | ||
| 1951 | GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B), | ||
| 1952 | GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E), | ||
| 1953 | GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0), | ||
| 1954 | GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C), | ||
| 1955 | GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1), | ||
| 1956 | GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B), | ||
| 1957 | GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G), | ||
| 1958 | GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E), | ||
| 1959 | GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E), | ||
| 1960 | GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E), | ||
| 1961 | GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F), | ||
| 1962 | |||
| 1963 | /*IPSR7*/ | ||
| 1964 | GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E), | ||
| 1965 | GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1), | ||
| 1966 | GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G), | ||
| 1967 | GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN), | ||
| 1968 | GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC), | ||
| 1969 | GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0), | ||
| 1970 | GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C), | ||
| 1971 | GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC), | ||
| 1972 | GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C), | ||
| 1973 | GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B), | ||
| 1974 | GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1), | ||
| 1975 | GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C), | ||
| 1976 | GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0), | ||
| 1977 | GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C), | ||
| 1978 | GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C), | ||
| 1979 | GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), | ||
| 1980 | GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), | ||
| 1981 | GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), | ||
| 1982 | |||
| 1983 | /*IPSR8*/ | ||
| 1984 | GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3), | ||
| 1985 | GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N), | ||
| 1986 | GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N), | ||
| 1987 | GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N), | ||
| 1988 | GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1), | ||
| 1989 | GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER), | ||
| 1990 | GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK), | ||
| 1991 | GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV), | ||
| 1992 | GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D), | ||
| 1993 | GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1), | ||
| 1994 | GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC), | ||
| 1995 | GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO), | ||
| 1996 | GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D), | ||
| 1997 | GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4), | ||
| 1998 | GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC), | ||
| 1999 | GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT), | ||
| 2000 | GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK), | ||
| 2001 | GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD), | ||
| 2002 | GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B), | ||
| 2003 | |||
| 2004 | /*IPSR9*/ | ||
| 2005 | GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B), | ||
| 2006 | GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B), | ||
| 2007 | GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B), | ||
| 2008 | GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B), | ||
| 2009 | GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B), | ||
| 2010 | GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B), | ||
| 2011 | GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B), | ||
| 2012 | GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B), | ||
| 2013 | GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B), | ||
| 2014 | GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B), | ||
| 2015 | GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN), | ||
| 2016 | GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER), | ||
| 2017 | GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK), | ||
| 2018 | GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1), | ||
| 2019 | GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B), | ||
| 2020 | GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL), | ||
| 2021 | GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0), | ||
| 2022 | GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD), | ||
| 2023 | GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP), | ||
| 2024 | GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D), | ||
| 2025 | GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B), | ||
| 2026 | |||
| 2027 | /*IPSR10*/ | ||
| 2028 | GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1), | ||
| 2029 | GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B), | ||
| 2030 | GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B), | ||
| 2031 | GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK), | ||
| 2032 | GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B), | ||
| 2033 | GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD), | ||
| 2034 | GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E), | ||
| 2035 | GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B), | ||
| 2036 | GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0), | ||
| 2037 | GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E), | ||
| 2038 | GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B), | ||
| 2039 | GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1), | ||
| 2040 | GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B), | ||
| 2041 | GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C), | ||
| 2042 | GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2), | ||
| 2043 | GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK), | ||
| 2044 | GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B), | ||
| 2045 | GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3), | ||
| 2046 | GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B), | ||
| 2047 | GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B), | ||
| 2048 | GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4), | ||
| 2049 | GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0), | ||
| 2050 | GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B), | ||
| 2051 | GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B), | ||
| 2052 | |||
| 2053 | /*IPSR11*/ | ||
| 2054 | GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B), | ||
| 2055 | GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B), | ||
| 2056 | GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B), | ||
| 2057 | GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK), | ||
| 2058 | GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0), | ||
| 2059 | GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1), | ||
| 2060 | GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA), | ||
| 2061 | GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD), | ||
| 2062 | GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0), | ||
| 2063 | GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5), | ||
| 2064 | GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B), | ||
| 2065 | GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F), | ||
| 2066 | GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B), | ||
| 2067 | GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D), | ||
| 2068 | GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT), | ||
| 2069 | GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C), | ||
| 2070 | GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129), | ||
| 2071 | GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0), | ||
| 2072 | |||
| 2073 | /*IPSR12*/ | ||
| 2074 | GPIO_FN(SSI_WS0129), GPIO_FN(CAN0_TX_B), GPIO_FN(MOUT1), | ||
| 2075 | GPIO_FN(SSI_SDATA0), GPIO_FN(CAN0_RX_B), GPIO_FN(MOUT2), | ||
| 2076 | GPIO_FN(SSI_SDATA1), GPIO_FN(CAN1_TX_B), GPIO_FN(MOUT5), | ||
| 2077 | GPIO_FN(SSI_SDATA2), GPIO_FN(CAN1_RX_B), GPIO_FN(SSI_SCK1), | ||
| 2078 | GPIO_FN(MOUT6), GPIO_FN(SSI_SCK34), GPIO_FN(STP_OPWM_0), | ||
| 2079 | GPIO_FN(SCIFB0_SCK), GPIO_FN(MSIOF1_SCK), GPIO_FN(CAN_DEBUG_HW_TRIGGER), | ||
| 2080 | GPIO_FN(SSI_WS34), GPIO_FN(STP_IVCXO27_0), GPIO_FN(SCIFB0_RXD), | ||
| 2081 | GPIO_FN(MSIOF1_SYNC), GPIO_FN(CAN_STEP0), GPIO_FN(SSI_SDATA3), | ||
| 2082 | GPIO_FN(STP_ISCLK_0), GPIO_FN(SCIFB0_TXD), GPIO_FN(MSIOF1_SS1), | ||
| 2083 | GPIO_FN(CAN_TXCLK), GPIO_FN(SSI_SCK4), GPIO_FN(STP_ISD_0), | ||
| 2084 | GPIO_FN(SCIFB0_CTS_N), GPIO_FN(MSIOF1_SS2), GPIO_FN(SSI_SCK5_C), | ||
| 2085 | GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(SSI_WS4), GPIO_FN(STP_ISEN_0), | ||
| 2086 | GPIO_FN(SCIFB0_RTS_N), GPIO_FN(MSIOF1_TXD), GPIO_FN(SSI_WS5_C), | ||
| 2087 | GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(SSI_SDATA4), GPIO_FN(STP_ISSYNC_0), | ||
| 2088 | GPIO_FN(MSIOF1_RXD), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(SSI_SCK5), | ||
| 2089 | GPIO_FN(SCIFB1_SCK), GPIO_FN(IERX_B), GPIO_FN(DU2_EXHSYNC_DU2_HSYNC), | ||
| 2090 | GPIO_FN(QSTH_QHS), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(SSI_WS5), | ||
| 2091 | GPIO_FN(SCIFB1_RXD), GPIO_FN(IECLK_B), GPIO_FN(DU2_EXVSYNC_DU2_VSYNC), | ||
| 2092 | GPIO_FN(QSTB_QHE), GPIO_FN(CAN_DEBUGOUT4), | ||
| 2093 | |||
| 2094 | /*IPSR13*/ | ||
| 2095 | GPIO_FN(SSI_SDATA5), GPIO_FN(SCIFB1_TXD), GPIO_FN(IETX_B), | ||
| 2096 | GPIO_FN(DU2_DR2), GPIO_FN(LCDOUT2), GPIO_FN(CAN_DEBUGOUT5), | ||
| 2097 | GPIO_FN(SSI_SCK6), GPIO_FN(SCIFB1_CTS_N), GPIO_FN(BPFCLK_D), | ||
| 2098 | GPIO_FN(RDS_CLK_C), GPIO_FN(DU2_DR3), GPIO_FN(LCDOUT3), | ||
| 2099 | GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(BPFCLK_F), GPIO_FN(RDS_CLK_E), | ||
| 2100 | GPIO_FN(SSI_WS6), GPIO_FN(SCIFB1_RTS_N), GPIO_FN(CAN0_TX_D), | ||
| 2101 | GPIO_FN(DU2_DR4), GPIO_FN(LCDOUT4), GPIO_FN(CAN_DEBUGOUT7), | ||
| 2102 | GPIO_FN(SSI_SDATA6), GPIO_FN(FMIN_D), GPIO_FN(RDS_DATA_C), | ||
| 2103 | GPIO_FN(DU2_DR5), GPIO_FN(LCDOUT5), GPIO_FN(CAN_DEBUGOUT8), | ||
| 2104 | GPIO_FN(SSI_SCK78), GPIO_FN(STP_IVCXO27_1), GPIO_FN(SCK1), | ||
| 2105 | GPIO_FN(SCIFA1_SCK), GPIO_FN(DU2_DR6), GPIO_FN(LCDOUT6), | ||
| 2106 | GPIO_FN(CAN_DEBUGOUT9), GPIO_FN(SSI_WS78), GPIO_FN(STP_ISCLK_1), | ||
| 2107 | GPIO_FN(SCIFB2_SCK), GPIO_FN(SCIFA2_CTS_N), GPIO_FN(DU2_DR7), | ||
| 2108 | GPIO_FN(LCDOUT7), GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SSI_SDATA7), | ||
| 2109 | GPIO_FN(STP_ISD_1), GPIO_FN(SCIFB2_RXD), GPIO_FN(SCIFA2_RTS_N), | ||
| 2110 | GPIO_FN(TCLK2), GPIO_FN(QSTVA_QVS), GPIO_FN(CAN_DEBUGOUT11), | ||
| 2111 | GPIO_FN(BPFCLK_E), GPIO_FN(RDS_CLK_D), GPIO_FN(SSI_SDATA7_B), | ||
| 2112 | GPIO_FN(FMIN_G), GPIO_FN(RDS_DATA_F), GPIO_FN(SSI_SDATA8), | ||
| 2113 | GPIO_FN(STP_ISEN_1), GPIO_FN(SCIFB2_TXD), GPIO_FN(CAN0_TX_C), | ||
| 2114 | GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SDATA8_B), GPIO_FN(SSI_SDATA9), | ||
| 2115 | GPIO_FN(STP_ISSYNC_1), GPIO_FN(SCIFB2_CTS_N), GPIO_FN(SSI_WS1), | ||
| 2116 | GPIO_FN(SSI_SDATA5_C), GPIO_FN(CAN_DEBUGOUT13), GPIO_FN(AUDIO_CLKA), | ||
| 2117 | GPIO_FN(SCIFB2_RTS_N), GPIO_FN(CAN_DEBUGOUT14), | ||
| 2118 | |||
| 2119 | /*IPSR14*/ | ||
| 2120 | GPIO_FN(AUDIO_CLKB), GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_RX_D), | ||
| 2121 | GPIO_FN(DVC_MUTE), GPIO_FN(CAN0_RX_C), GPIO_FN(CAN_DEBUGOUT15), | ||
| 2122 | GPIO_FN(REMOCON), GPIO_FN(SCIFA0_SCK), GPIO_FN(HSCK1), GPIO_FN(SCK0), | ||
| 2123 | GPIO_FN(MSIOF3_SS2), GPIO_FN(DU2_DG2), GPIO_FN(LCDOUT10), | ||
| 2124 | GPIO_FN(SDA1_C), GPIO_FN(SDA1_CIS_C), GPIO_FN(SCIFA0_RXD), | ||
| 2125 | GPIO_FN(HRX1), GPIO_FN(RX0), GPIO_FN(DU2_DR0), GPIO_FN(LCDOUT0), | ||
| 2126 | GPIO_FN(SCIFA0_TXD), GPIO_FN(HTX1), GPIO_FN(TX0), GPIO_FN(DU2_DR1), | ||
| 2127 | GPIO_FN(LCDOUT1), GPIO_FN(SCIFA0_CTS_N), GPIO_FN(HCTS1_N), | ||
| 2128 | GPIO_FN(CTS0_N), GPIO_FN(MSIOF3_SYNC), GPIO_FN(DU2_DG3), | ||
| 2129 | GPIO_FN(LCDOUT11), GPIO_FN(PWM0_B), GPIO_FN(SCL1_C), | ||
| 2130 | GPIO_FN(SCL1_CIS_C), GPIO_FN(SCIFA0_RTS_N), GPIO_FN(HRTS1_N), | ||
| 2131 | GPIO_FN(RTS0_N_TANS), GPIO_FN(MSIOF3_SS1), GPIO_FN(DU2_DG0), | ||
| 2132 | GPIO_FN(LCDOUT8), GPIO_FN(PWM1_B), GPIO_FN(SCIFA1_RXD), GPIO_FN(AD_DI), | ||
| 2133 | GPIO_FN(RX1), GPIO_FN(DU2_EXODDF_DU2_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), | ||
| 2134 | GPIO_FN(SCIFA1_TXD), GPIO_FN(AD_DO), GPIO_FN(TX1), GPIO_FN(DU2_DG1), | ||
| 2135 | GPIO_FN(LCDOUT9), GPIO_FN(SCIFA1_CTS_N), GPIO_FN(AD_CLK), | ||
| 2136 | GPIO_FN(CTS1_N), GPIO_FN(MSIOF3_RXD), GPIO_FN(DU0_DOTCLKOUT), | ||
| 2137 | GPIO_FN(QCLK), GPIO_FN(SCIFA1_RTS_N), GPIO_FN(AD_NCS_N), | ||
| 2138 | GPIO_FN(RTS1_N_TANS), GPIO_FN(MSIOF3_TXD), GPIO_FN(DU1_DOTCLKOUT), | ||
| 2139 | GPIO_FN(QSTVB_QVE), GPIO_FN(HRTS0_N_C), | ||
| 2140 | |||
| 2141 | /*IPSR15*/ | ||
| 2142 | GPIO_FN(SCIFA2_SCK), GPIO_FN(FMCLK), GPIO_FN(MSIOF3_SCK), | ||
| 2143 | GPIO_FN(DU2_DG7), GPIO_FN(LCDOUT15), GPIO_FN(SCIF_CLK_B), | ||
| 2144 | GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN), GPIO_FN(DU2_DB0), | ||
| 2145 | GPIO_FN(LCDOUT16), GPIO_FN(SCL2), GPIO_FN(SCL2_CIS), | ||
| 2146 | GPIO_FN(SCIFA2_TXD), GPIO_FN(BPFCLK), GPIO_FN(DU2_DB1), | ||
| 2147 | GPIO_FN(LCDOUT17), GPIO_FN(SDA2), GPIO_FN(SDA2_CIS), GPIO_FN(HSCK0), | ||
| 2148 | GPIO_FN(TS_SDEN0), GPIO_FN(DU2_DG4), GPIO_FN(LCDOUT12), | ||
| 2149 | GPIO_FN(HCTS0_N_C), GPIO_FN(HRX0), GPIO_FN(DU2_DB2), GPIO_FN(LCDOUT18), | ||
| 2150 | GPIO_FN(HTX0), GPIO_FN(DU2_DB3), GPIO_FN(LCDOUT19), GPIO_FN(HCTS0_N), | ||
| 2151 | GPIO_FN(SSI_SCK9), GPIO_FN(DU2_DB4), GPIO_FN(LCDOUT20), | ||
| 2152 | GPIO_FN(HRTS0_N), GPIO_FN(SSI_WS9), GPIO_FN(DU2_DB5), | ||
| 2153 | GPIO_FN(LCDOUT21), GPIO_FN(MSIOF0_SCK), GPIO_FN(TS_SDAT0), | ||
| 2154 | GPIO_FN(ADICLK), GPIO_FN(DU2_DB6), GPIO_FN(LCDOUT22), | ||
| 2155 | GPIO_FN(MSIOF0_SYNC), GPIO_FN(TS_SCK0), GPIO_FN(SSI_SCK2), | ||
| 2156 | GPIO_FN(ADIDATA), GPIO_FN(DU2_DB7), GPIO_FN(LCDOUT23), | ||
| 2157 | GPIO_FN(SCIFA2_RXD_B), GPIO_FN(MSIOF0_SS1), GPIO_FN(ADICHS0), | ||
| 2158 | GPIO_FN(DU2_DG5), GPIO_FN(LCDOUT13), GPIO_FN(MSIOF0_TXD), | ||
| 2159 | GPIO_FN(ADICHS1), GPIO_FN(DU2_DG6), GPIO_FN(LCDOUT14), | ||
| 2160 | |||
| 2161 | /*IPSR16*/ | ||
| 2162 | GPIO_FN(MSIOF0_SS2), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(ADICHS2), | ||
| 2163 | GPIO_FN(DU2_DISP), GPIO_FN(QPOLA), GPIO_FN(HTX0_C), | ||
| 2164 | GPIO_FN(SCIFA2_TXD_B), GPIO_FN(MSIOF0_RXD), GPIO_FN(TS_SPSYNC0), | ||
| 2165 | GPIO_FN(SSI_WS2), GPIO_FN(ADICS_SAMP), GPIO_FN(DU2_CDE), | ||
| 2166 | GPIO_FN(QPOLB), GPIO_FN(HRX0_C), GPIO_FN(USB1_PWEN), | ||
| 2167 | GPIO_FN(AUDIO_CLKOUT_D), GPIO_FN(USB1_OVC), GPIO_FN(TCLK1_B), | ||
| 2168 | }; | ||
| 2169 | |||
| 2170 | static struct pinmux_cfg_reg pinmux_config_regs[] = { | ||
| 2171 | { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { | ||
| 2172 | GP_0_31_FN, FN_IP3_17_15, | ||
| 2173 | GP_0_30_FN, FN_IP3_14_12, | ||
| 2174 | GP_0_29_FN, FN_IP3_11_8, | ||
| 2175 | GP_0_28_FN, FN_IP3_7_4, | ||
| 2176 | GP_0_27_FN, FN_IP3_3_0, | ||
| 2177 | GP_0_26_FN, FN_IP2_28_26, | ||
| 2178 | GP_0_25_FN, FN_IP2_25_22, | ||
| 2179 | GP_0_24_FN, FN_IP2_21_18, | ||
| 2180 | GP_0_23_FN, FN_IP2_17_15, | ||
| 2181 | GP_0_22_FN, FN_IP2_14_12, | ||
| 2182 | GP_0_21_FN, FN_IP2_11_9, | ||
| 2183 | GP_0_20_FN, FN_IP2_8_6, | ||
| 2184 | GP_0_19_FN, FN_IP2_5_3, | ||
| 2185 | GP_0_18_FN, FN_IP2_2_0, | ||
| 2186 | GP_0_17_FN, FN_IP1_29_28, | ||
| 2187 | GP_0_16_FN, FN_IP1_27_26, | ||
| 2188 | GP_0_15_FN, FN_IP1_25_22, | ||
| 2189 | GP_0_14_FN, FN_IP1_21_18, | ||
| 2190 | GP_0_13_FN, FN_IP1_17_15, | ||
| 2191 | GP_0_12_FN, FN_IP1_14_12, | ||
| 2192 | GP_0_11_FN, FN_IP1_11_8, | ||
| 2193 | GP_0_10_FN, FN_IP1_7_4, | ||
| 2194 | GP_0_9_FN, FN_IP1_3_0, | ||
| 2195 | GP_0_8_FN, FN_IP0_30_27, | ||
| 2196 | GP_0_7_FN, FN_IP0_26_23, | ||
| 2197 | GP_0_6_FN, FN_IP0_22_20, | ||
| 2198 | GP_0_5_FN, FN_IP0_19_16, | ||
| 2199 | GP_0_4_FN, FN_IP0_15_12, | ||
| 2200 | GP_0_3_FN, FN_IP0_11_9, | ||
| 2201 | GP_0_2_FN, FN_IP0_8_6, | ||
| 2202 | GP_0_1_FN, FN_IP0_5_3, | ||
| 2203 | GP_0_0_FN, FN_IP0_2_0 } | ||
| 2204 | }, | ||
| 2205 | { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { | ||
| 2206 | 0, 0, | ||
| 2207 | 0, 0, | ||
| 2208 | GP_1_29_FN, FN_IP6_13_11, | ||
| 2209 | GP_1_28_FN, FN_IP6_10_9, | ||
| 2210 | GP_1_27_FN, FN_IP6_8_6, | ||
| 2211 | GP_1_26_FN, FN_IP6_5_3, | ||
| 2212 | GP_1_25_FN, FN_IP6_2_0, | ||
| 2213 | GP_1_24_FN, FN_IP5_29_27, | ||
| 2214 | GP_1_23_FN, FN_IP5_26_24, | ||
| 2215 | GP_1_22_FN, FN_IP5_23_21, | ||
| 2216 | GP_1_21_FN, FN_IP5_20_18, | ||
| 2217 | GP_1_20_FN, FN_IP5_17_15, | ||
| 2218 | GP_1_19_FN, FN_IP5_14_13, | ||
| 2219 | GP_1_18_FN, FN_IP5_12_10, | ||
| 2220 | GP_1_17_FN, FN_IP5_9_6, | ||
| 2221 | GP_1_16_FN, FN_IP5_5_3, | ||
| 2222 | GP_1_15_FN, FN_IP5_2_0, | ||
| 2223 | GP_1_14_FN, FN_IP4_29_27, | ||
| 2224 | GP_1_13_FN, FN_IP4_26_24, | ||
| 2225 | GP_1_12_FN, FN_IP4_23_21, | ||
| 2226 | GP_1_11_FN, FN_IP4_20_18, | ||
| 2227 | GP_1_10_FN, FN_IP4_17_15, | ||
| 2228 | GP_1_9_FN, FN_IP4_14_12, | ||
| 2229 | GP_1_8_FN, FN_IP4_11_9, | ||
| 2230 | GP_1_7_FN, FN_IP4_8_6, | ||
| 2231 | GP_1_6_FN, FN_IP4_5_3, | ||
| 2232 | GP_1_5_FN, FN_IP4_2_0, | ||
| 2233 | GP_1_4_FN, FN_IP3_31_29, | ||
| 2234 | GP_1_3_FN, FN_IP3_28_26, | ||
| 2235 | GP_1_2_FN, FN_IP3_25_23, | ||
| 2236 | GP_1_1_FN, FN_IP3_22_20, | ||
| 2237 | GP_1_0_FN, FN_IP3_19_18, } | ||
| 2238 | }, | ||
| 2239 | { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { | ||
| 2240 | 0, 0, | ||
| 2241 | 0, 0, | ||
| 2242 | GP_2_29_FN, FN_IP7_15_13, | ||
| 2243 | GP_2_28_FN, FN_IP7_12_10, | ||
| 2244 | GP_2_27_FN, FN_IP7_9_8, | ||
| 2245 | GP_2_26_FN, FN_IP7_7_6, | ||
| 2246 | GP_2_25_FN, FN_IP7_5_3, | ||
| 2247 | GP_2_24_FN, FN_IP7_2_0, | ||
| 2248 | GP_2_23_FN, FN_IP6_31_29, | ||
| 2249 | GP_2_22_FN, FN_IP6_28_26, | ||
| 2250 | GP_2_21_FN, FN_IP6_25_23, | ||
| 2251 | GP_2_20_FN, FN_IP6_22_20, | ||
| 2252 | GP_2_19_FN, FN_IP6_19_17, | ||
| 2253 | GP_2_18_FN, FN_IP6_16_14, | ||
| 2254 | GP_2_17_FN, FN_VI1_DATA7_VI1_B7, | ||
| 2255 | GP_2_16_FN, FN_IP8_27, | ||
| 2256 | GP_2_15_FN, FN_IP8_26, | ||
| 2257 | GP_2_14_FN, FN_IP8_25_24, | ||
| 2258 | GP_2_13_FN, FN_IP8_23_22, | ||
| 2259 | GP_2_12_FN, FN_IP8_21_20, | ||
| 2260 | GP_2_11_FN, FN_IP8_19_18, | ||
| 2261 | GP_2_10_FN, FN_IP8_17_16, | ||
| 2262 | GP_2_9_FN, FN_IP8_15_14, | ||
| 2263 | GP_2_8_FN, FN_IP8_13_12, | ||
| 2264 | GP_2_7_FN, FN_IP8_11_10, | ||
| 2265 | GP_2_6_FN, FN_IP8_9_8, | ||
| 2266 | GP_2_5_FN, FN_IP8_7_6, | ||
| 2267 | GP_2_4_FN, FN_IP8_5_4, | ||
| 2268 | GP_2_3_FN, FN_IP8_3_2, | ||
| 2269 | GP_2_2_FN, FN_IP8_1_0, | ||
| 2270 | GP_2_1_FN, FN_IP7_30_29, | ||
| 2271 | GP_2_0_FN, FN_IP7_28_27 } | ||
| 2272 | }, | ||
| 2273 | { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { | ||
| 2274 | GP_3_31_FN, FN_IP11_21_18, | ||
| 2275 | GP_3_30_FN, FN_IP11_17_15, | ||
| 2276 | GP_3_29_FN, FN_IP11_14_13, | ||
| 2277 | GP_3_28_FN, FN_IP11_12_11, | ||
| 2278 | GP_3_27_FN, FN_IP11_10_9, | ||
| 2279 | GP_3_26_FN, FN_IP11_8_7, | ||
| 2280 | GP_3_25_FN, FN_IP11_6_5, | ||
| 2281 | GP_3_24_FN, FN_IP11_4, | ||
| 2282 | GP_3_23_FN, FN_IP11_3_0, | ||
| 2283 | GP_3_22_FN, FN_IP10_29_26, | ||
| 2284 | GP_3_21_FN, FN_IP10_25_23, | ||
| 2285 | GP_3_20_FN, FN_IP10_22_19, | ||
| 2286 | GP_3_19_FN, FN_IP10_18_15, | ||
| 2287 | GP_3_18_FN, FN_IP10_14_11, | ||
| 2288 | GP_3_17_FN, FN_IP10_10_7, | ||
| 2289 | GP_3_16_FN, FN_IP10_6_4, | ||
| 2290 | GP_3_15_FN, FN_IP10_3_0, | ||
| 2291 | GP_3_14_FN, FN_IP9_31_28, | ||
| 2292 | GP_3_13_FN, FN_IP9_27_26, | ||
| 2293 | GP_3_12_FN, FN_IP9_25_24, | ||
| 2294 | GP_3_11_FN, FN_IP9_23_22, | ||
| 2295 | GP_3_10_FN, FN_IP9_21_20, | ||
| 2296 | GP_3_9_FN, FN_IP9_19_18, | ||
| 2297 | GP_3_8_FN, FN_IP9_17_16, | ||
| 2298 | GP_3_7_FN, FN_IP9_15_12, | ||
| 2299 | GP_3_6_FN, FN_IP9_11_8, | ||
| 2300 | GP_3_5_FN, FN_IP9_7_6, | ||
| 2301 | GP_3_4_FN, FN_IP9_5_4, | ||
| 2302 | GP_3_3_FN, FN_IP9_3_2, | ||
| 2303 | GP_3_2_FN, FN_IP9_1_0, | ||
| 2304 | GP_3_1_FN, FN_IP8_30_29, | ||
| 2305 | GP_3_0_FN, FN_IP8_28 } | ||
| 2306 | }, | ||
| 2307 | { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { | ||
| 2308 | GP_4_31_FN, FN_IP14_18_16, | ||
| 2309 | GP_4_30_FN, FN_IP14_15_12, | ||
| 2310 | GP_4_29_FN, FN_IP14_11_9, | ||
| 2311 | GP_4_28_FN, FN_IP14_8_6, | ||
| 2312 | GP_4_27_FN, FN_IP14_5_3, | ||
| 2313 | GP_4_26_FN, FN_IP14_2_0, | ||
| 2314 | GP_4_25_FN, FN_IP13_30_29, | ||
| 2315 | GP_4_24_FN, FN_IP13_28_26, | ||
| 2316 | GP_4_23_FN, FN_IP13_25_23, | ||
| 2317 | GP_4_22_FN, FN_IP13_22_19, | ||
| 2318 | GP_4_21_FN, FN_IP13_18_16, | ||
| 2319 | GP_4_20_FN, FN_IP13_15_13, | ||
| 2320 | GP_4_19_FN, FN_IP13_12_10, | ||
| 2321 | GP_4_18_FN, FN_IP13_9_7, | ||
| 2322 | GP_4_17_FN, FN_IP13_6_3, | ||
| 2323 | GP_4_16_FN, FN_IP13_2_0, | ||
| 2324 | GP_4_15_FN, FN_IP12_30_28, | ||
| 2325 | GP_4_14_FN, FN_IP12_27_25, | ||
| 2326 | GP_4_13_FN, FN_IP12_24_23, | ||
| 2327 | GP_4_12_FN, FN_IP12_22_20, | ||
| 2328 | GP_4_11_FN, FN_IP12_19_17, | ||
| 2329 | GP_4_10_FN, FN_IP12_16_14, | ||
| 2330 | GP_4_9_FN, FN_IP12_13_11, | ||
| 2331 | GP_4_8_FN, FN_IP12_10_8, | ||
| 2332 | GP_4_7_FN, FN_IP12_7_6, | ||
| 2333 | GP_4_6_FN, FN_IP12_5_4, | ||
| 2334 | GP_4_5_FN, FN_IP12_3_2, | ||
| 2335 | GP_4_4_FN, FN_IP12_1_0, | ||
| 2336 | GP_4_3_FN, FN_IP11_31_30, | ||
| 2337 | GP_4_2_FN, FN_IP11_29_27, | ||
| 2338 | GP_4_1_FN, FN_IP11_26_24, | ||
| 2339 | GP_4_0_FN, FN_IP11_23_22 } | ||
| 2340 | }, | ||
| 2341 | { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { | ||
| 2342 | GP_5_31_FN, FN_IP7_24_22, | ||
| 2343 | GP_5_30_FN, FN_IP7_21_19, | ||
| 2344 | GP_5_29_FN, FN_IP7_18_16, | ||
| 2345 | GP_5_28_FN, FN_DU_DOTCLKIN2, | ||
| 2346 | GP_5_27_FN, FN_IP7_26_25, | ||
| 2347 | GP_5_26_FN, FN_DU_DOTCLKIN0, | ||
| 2348 | GP_5_25_FN, FN_AVS2, | ||
| 2349 | GP_5_24_FN, FN_AVS1, | ||
| 2350 | GP_5_23_FN, FN_USB2_OVC, | ||
| 2351 | GP_5_22_FN, FN_USB2_PWEN, | ||
| 2352 | GP_5_21_FN, FN_IP16_7, | ||
| 2353 | GP_5_20_FN, FN_IP16_6, | ||
| 2354 | GP_5_19_FN, FN_USB0_OVC_VBUS, | ||
| 2355 | GP_5_18_FN, FN_USB0_PWEN, | ||
| 2356 | GP_5_17_FN, FN_IP16_5_3, | ||
| 2357 | GP_5_16_FN, FN_IP16_2_0, | ||
| 2358 | GP_5_15_FN, FN_IP15_29_28, | ||
| 2359 | GP_5_14_FN, FN_IP15_27_26, | ||
| 2360 | GP_5_13_FN, FN_IP15_25_23, | ||
| 2361 | GP_5_12_FN, FN_IP15_22_20, | ||
| 2362 | GP_5_11_FN, FN_IP15_19_18, | ||
| 2363 | GP_5_10_FN, FN_IP15_17_16, | ||
| 2364 | GP_5_9_FN, FN_IP15_15_14, | ||
| 2365 | GP_5_8_FN, FN_IP15_13_12, | ||
| 2366 | GP_5_7_FN, FN_IP15_11_9, | ||
| 2367 | GP_5_6_FN, FN_IP15_8_6, | ||
| 2368 | GP_5_5_FN, FN_IP15_5_3, | ||
| 2369 | GP_5_4_FN, FN_IP15_2_0, | ||
| 2370 | GP_5_3_FN, FN_IP14_30_28, | ||
| 2371 | GP_5_2_FN, FN_IP14_27_25, | ||
| 2372 | GP_5_1_FN, FN_IP14_24_22, | ||
| 2373 | GP_5_0_FN, FN_IP14_21_19 } | ||
| 2374 | }, | ||
| 2375 | { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, | ||
| 2376 | 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { | ||
| 2377 | /* IP0_31 [1] */ | ||
| 2378 | 0, 0, | ||
| 2379 | /* IP0_30_27 [4] */ | ||
| 2380 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, | ||
| 2381 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, | ||
| 2382 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2383 | /* IP0_26_23 [4] */ | ||
| 2384 | FN_D7, FN_AD_DI_B, FN_SDA2_C, | ||
| 2385 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, | ||
| 2386 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2387 | /* IP0_22_20 [3] */ | ||
| 2388 | FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, | ||
| 2389 | FN_SCL2_CIS_C, 0, 0, | ||
| 2390 | /* IP0_19_16 [4] */ | ||
| 2391 | FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, | ||
| 2392 | FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, | ||
| 2393 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2394 | /* IP0_15_12 [4] */ | ||
| 2395 | FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, | ||
| 2396 | FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, | ||
| 2397 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2398 | /* IP0_11_9 [3] */ | ||
| 2399 | FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, | ||
| 2400 | 0, 0, 0, | ||
| 2401 | /* IP0_8_6 [3] */ | ||
| 2402 | FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, | ||
| 2403 | 0, 0, 0, | ||
| 2404 | /* IP0_5_3 [3] */ | ||
| 2405 | FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, | ||
| 2406 | 0, 0, 0, | ||
| 2407 | /* IP0_2_0 [3] */ | ||
| 2408 | FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, | ||
| 2409 | 0, 0, 0, } | ||
| 2410 | }, | ||
| 2411 | { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, | ||
| 2412 | 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { | ||
| 2413 | /* IP1_31_30 [2] */ | ||
| 2414 | 0, 0, 0, 0, | ||
| 2415 | /* IP1_29_28 [2] */ | ||
| 2416 | FN_A1, FN_PWM4, 0, 0, | ||
| 2417 | /* IP1_27_26 [2] */ | ||
| 2418 | FN_A0, FN_PWM3, 0, 0, | ||
| 2419 | /* IP1_25_22 [4] */ | ||
| 2420 | FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, | ||
| 2421 | FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, | ||
| 2422 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2423 | /* IP1_21_18 [4] */ | ||
| 2424 | FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, | ||
| 2425 | FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, | ||
| 2426 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2427 | /* IP1_17_15 [3] */ | ||
| 2428 | FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, | ||
| 2429 | FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, | ||
| 2430 | 0, 0, 0, | ||
| 2431 | /* IP1_14_12 [3] */ | ||
| 2432 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | ||
| 2433 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | ||
| 2434 | 0, 0, | ||
| 2435 | /* IP1_11_8 [4] */ | ||
| 2436 | FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, | ||
| 2437 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, | ||
| 2438 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2439 | /* IP1_7_4 [4] */ | ||
| 2440 | FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, | ||
| 2441 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, | ||
| 2442 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2443 | /* IP1_3_0 [4] */ | ||
| 2444 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, | ||
| 2445 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, | ||
| 2446 | 0, 0, 0, 0, 0, 0, 0, 0, 0, } | ||
| 2447 | }, | ||
| 2448 | { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, | ||
| 2449 | 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { | ||
| 2450 | /* IP2_31_29 [3] */ | ||
| 2451 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2452 | /* IP2_28_26 [3] */ | ||
| 2453 | FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, | ||
| 2454 | FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, | ||
| 2455 | /* IP2_25_22 [4] */ | ||
| 2456 | FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, | ||
| 2457 | FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, | ||
| 2458 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2459 | /* IP2_21_18 [4] */ | ||
| 2460 | FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, | ||
| 2461 | FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, | ||
| 2462 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2463 | /* IP2_17_15 [3] */ | ||
| 2464 | FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, | ||
| 2465 | 0, 0, 0, 0, | ||
| 2466 | /* IP2_14_12 [3] */ | ||
| 2467 | FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, | ||
| 2468 | /* IP2_11_9 [3] */ | ||
| 2469 | FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, | ||
| 2470 | /* IP2_8_6 [3] */ | ||
| 2471 | FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, | ||
| 2472 | /* IP2_5_3 [3] */ | ||
| 2473 | FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, | ||
| 2474 | /* IP2_2_0 [3] */ | ||
| 2475 | FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } | ||
| 2476 | }, | ||
| 2477 | { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, | ||
| 2478 | 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { | ||
| 2479 | /* IP3_31_29 [3] */ | ||
| 2480 | FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, | ||
| 2481 | 0, 0, 0, | ||
| 2482 | /* IP3_28_26 [3] */ | ||
| 2483 | FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, | ||
| 2484 | 0, 0, 0, 0, | ||
| 2485 | /* IP3_25_23 [3] */ | ||
| 2486 | FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, | ||
| 2487 | /* IP3_22_20 [3] */ | ||
| 2488 | FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, | ||
| 2489 | /* IP3_19_18 [2] */ | ||
| 2490 | FN_A16, FN_ATAWR1_N, 0, 0, | ||
| 2491 | /* IP3_17_15 [3] */ | ||
| 2492 | FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, | ||
| 2493 | 0, 0, 0, 0, | ||
| 2494 | /* IP3_14_12 [3] */ | ||
| 2495 | FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, | ||
| 2496 | 0, 0, 0, 0, | ||
| 2497 | /* IP3_11_8 [4] */ | ||
| 2498 | FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, | ||
| 2499 | FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, | ||
| 2500 | FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2501 | /* IP3_7_4 [4] */ | ||
| 2502 | FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, | ||
| 2503 | FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, | ||
| 2504 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2505 | /* IP3_3_0 [4] */ | ||
| 2506 | FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, | ||
| 2507 | FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, | ||
| 2508 | 0, 0, 0, 0, 0, 0, 0, 0, } | ||
| 2509 | }, | ||
| 2510 | { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, | ||
| 2511 | 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | ||
| 2512 | /* IP4_31_30 [2] */ | ||
| 2513 | 0, 0, 0, 0, | ||
| 2514 | /* IP4_29_27 [3] */ | ||
| 2515 | FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, | ||
| 2516 | FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, | ||
| 2517 | /* IP4_26_24 [3] */ | ||
| 2518 | FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, | ||
| 2519 | FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, | ||
| 2520 | /* IP4_23_21 [3] */ | ||
| 2521 | FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, | ||
| 2522 | FN_HTX0_B, FN_MSIOF0_SS1_B, 0, | ||
| 2523 | /* IP4_20_18 [3] */ | ||
| 2524 | FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, | ||
| 2525 | FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, | ||
| 2526 | /* IP4_17_15 [3] */ | ||
| 2527 | FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, | ||
| 2528 | 0, 0, 0, | ||
| 2529 | /* IP4_14_12 [3] */ | ||
| 2530 | FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, | ||
| 2531 | FN_VI2_FIELD_B, 0, 0, | ||
| 2532 | /* IP4_11_9 [3] */ | ||
| 2533 | FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, | ||
| 2534 | FN_VI2_CLKENB_B, 0, 0, | ||
| 2535 | /* IP4_8_6 [3] */ | ||
| 2536 | FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, | ||
| 2537 | /* IP4_5_3 [3] */ | ||
| 2538 | FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, | ||
| 2539 | /* IP4_2_0 [3] */ | ||
| 2540 | FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, | ||
| 2541 | } | ||
| 2542 | }, | ||
| 2543 | { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, | ||
| 2544 | 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { | ||
| 2545 | /* IP5_31_30 [2] */ | ||
| 2546 | 0, 0, 0, 0, | ||
| 2547 | /* IP5_29_27 [3] */ | ||
| 2548 | FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, | ||
| 2549 | FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, | ||
| 2550 | /* IP5_26_24 [3] */ | ||
| 2551 | FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, | ||
| 2552 | FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, | ||
| 2553 | FN_MSIOF0_SCK_B, 0, | ||
| 2554 | /* IP5_23_21 [3] */ | ||
| 2555 | FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, | ||
| 2556 | FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, | ||
| 2557 | FN_IERX_C, 0, | ||
| 2558 | /* IP5_20_18 [3] */ | ||
| 2559 | FN_WE0_N, FN_IECLK, FN_CAN_CLK, | ||
| 2560 | FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, | ||
| 2561 | /* IP5_17_15 [3] */ | ||
| 2562 | FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, | ||
| 2563 | FN_INTC_IRQ4_N, 0, 0, | ||
| 2564 | /* IP5_14_13 [2] */ | ||
| 2565 | FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, | ||
| 2566 | /* IP5_12_10 [3] */ | ||
| 2567 | FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, | ||
| 2568 | 0, 0, | ||
| 2569 | /* IP5_9_6 [4] */ | ||
| 2570 | FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, | ||
| 2571 | FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, | ||
| 2572 | FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, | ||
| 2573 | /* IP5_5_3 [3] */ | ||
| 2574 | FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, | ||
| 2575 | FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, | ||
| 2576 | FN_INTC_EN0_N, FN_SCL1_CIS, | ||
| 2577 | /* IP5_2_0 [3] */ | ||
| 2578 | FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, | ||
| 2579 | FN_VI2_R3, 0, 0, } | ||
| 2580 | }, | ||
| 2581 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, | ||
| 2582 | 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { | ||
| 2583 | /* IP6_31_29 [3] */ | ||
| 2584 | FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, | ||
| 2585 | FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, | ||
| 2586 | /* IP6_28_26 [3] */ | ||
| 2587 | FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, | ||
| 2588 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, | ||
| 2589 | /* IP6_25_23 [3] */ | ||
| 2590 | FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, | ||
| 2591 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, | ||
| 2592 | /* IP6_22_20 [3] */ | ||
| 2593 | FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, | ||
| 2594 | FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, | ||
| 2595 | /* IP6_19_17 [3] */ | ||
| 2596 | FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, | ||
| 2597 | FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, | ||
| 2598 | /* IP6_16_14 [3] */ | ||
| 2599 | FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, | ||
| 2600 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, | ||
| 2601 | FN_SCL2_CIS_E, 0, | ||
| 2602 | /* IP6_13_11 [3] */ | ||
| 2603 | FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | ||
| 2604 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, | ||
| 2605 | /* IP6_10_9 [2] */ | ||
| 2606 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, | ||
| 2607 | /* IP6_8_6 [3] */ | ||
| 2608 | FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, | ||
| 2609 | FN_SSI_SDATA8_C, 0, 0, 0, | ||
| 2610 | /* IP6_5_3 [3] */ | ||
| 2611 | FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, | ||
| 2612 | FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, | ||
| 2613 | /* IP6_2_0 [3] */ | ||
| 2614 | FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, | ||
| 2615 | FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } | ||
| 2616 | }, | ||
| 2617 | { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, | ||
| 2618 | 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { | ||
| 2619 | /* IP7_31 [1] */ | ||
| 2620 | 0, 0, | ||
| 2621 | /* IP7_30_29 [2] */ | ||
| 2622 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, | ||
| 2623 | FN_MII_RXD2, | ||
| 2624 | /* IP7_28_27 [2] */ | ||
| 2625 | FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, | ||
| 2626 | /* IP7_26_25 [2] */ | ||
| 2627 | FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, | ||
| 2628 | /* IP7_24_22 [3] */ | ||
| 2629 | FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, | ||
| 2630 | 0, 0, 0, | ||
| 2631 | /* IP7_21_19 [3] */ | ||
| 2632 | FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, | ||
| 2633 | FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, | ||
| 2634 | /* IP7_18_16 [3] */ | ||
| 2635 | FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | ||
| 2636 | FN_GLO_SS_C, 0, 0, 0, | ||
| 2637 | /* IP7_15_13 [3] */ | ||
| 2638 | FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, | ||
| 2639 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, | ||
| 2640 | /* IP7_12_10 [3] */ | ||
| 2641 | FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, | ||
| 2642 | FN_GLO_SCLK_C, 0, 0, 0, | ||
| 2643 | /* IP7_9_8 [2] */ | ||
| 2644 | FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, | ||
| 2645 | /* IP7_7_6 [2] */ | ||
| 2646 | FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, | ||
| 2647 | /* IP7_5_3 [3] */ | ||
| 2648 | FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, | ||
| 2649 | 0, 0, 0, | ||
| 2650 | /* IP7_2_0 [3] */ | ||
| 2651 | FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, | ||
| 2652 | FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } | ||
| 2653 | }, | ||
| 2654 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, | ||
| 2655 | 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, | ||
| 2656 | 2, 2, 2, 2, 2, 2, 2) { | ||
| 2657 | /* IP8_31 [1] */ | ||
| 2658 | 0, 0, | ||
| 2659 | /* IP8_30_29 [2] */ | ||
| 2660 | FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, | ||
| 2661 | /* IP8_28 [1] */ | ||
| 2662 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, | ||
| 2663 | /* IP8_27 [1] */ | ||
| 2664 | FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, | ||
| 2665 | /* IP8_26 [1] */ | ||
| 2666 | FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, | ||
| 2667 | /* IP8_25_24 [2] */ | ||
| 2668 | FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, | ||
| 2669 | FN_AVB_MAGIC, FN_MII_MAGIC, | ||
| 2670 | /* IP8_23_22 [2] */ | ||
| 2671 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, | ||
| 2672 | /* IP8_21_20 [2] */ | ||
| 2673 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, | ||
| 2674 | FN_MII_MDIO, | ||
| 2675 | /* IP8_19_18 [2] */ | ||
| 2676 | FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, | ||
| 2677 | /* IP8_17_16 [2] */ | ||
| 2678 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, | ||
| 2679 | /* IP8_15_14 [2] */ | ||
| 2680 | FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, | ||
| 2681 | /* IP8_13_12 [2] */ | ||
| 2682 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, | ||
| 2683 | /* IP8_11_10 [2] */ | ||
| 2684 | FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, | ||
| 2685 | /* IP8_9_8 [2] */ | ||
| 2686 | FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, | ||
| 2687 | /* IP8_7_6 [2] */ | ||
| 2688 | FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, | ||
| 2689 | /* IP8_5_4 [2] */ | ||
| 2690 | FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, | ||
| 2691 | /* IP8_3_2 [2] */ | ||
| 2692 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, | ||
| 2693 | /* IP8_1_0 [2] */ | ||
| 2694 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } | ||
| 2695 | }, | ||
| 2696 | { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, | ||
| 2697 | 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { | ||
| 2698 | /* IP9_31_28 [4] */ | ||
| 2699 | FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, | ||
| 2700 | FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, | ||
| 2701 | FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, | ||
| 2702 | /* IP9_27_26 [2] */ | ||
| 2703 | FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, | ||
| 2704 | /* IP9_25_24 [2] */ | ||
| 2705 | FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, | ||
| 2706 | /* IP9_23_22 [2] */ | ||
| 2707 | FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, | ||
| 2708 | /* IP9_21_20 [2] */ | ||
| 2709 | FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, | ||
| 2710 | /* IP9_19_18 [2] */ | ||
| 2711 | FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, | ||
| 2712 | /* IP9_17_16 [2] */ | ||
| 2713 | FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, | ||
| 2714 | /* IP9_15_12 [4] */ | ||
| 2715 | FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, | ||
| 2716 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, | ||
| 2717 | FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, | ||
| 2718 | /* IP9_11_8 [4] */ | ||
| 2719 | FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, | ||
| 2720 | FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, | ||
| 2721 | FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, | ||
| 2722 | /* IP9_7_6 [2] */ | ||
| 2723 | FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, | ||
| 2724 | /* IP9_5_4 [2] */ | ||
| 2725 | FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, | ||
| 2726 | /* IP9_3_2 [2] */ | ||
| 2727 | FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, | ||
| 2728 | /* IP9_1_0 [2] */ | ||
| 2729 | FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } | ||
| 2730 | }, | ||
| 2731 | { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, | ||
| 2732 | 2, 4, 3, 4, 4, 4, 4, 3, 4) { | ||
| 2733 | /* IP10_31_30 [2] */ | ||
| 2734 | 0, 0, 0, 0, | ||
| 2735 | /* IP10_29_26 [4] */ | ||
| 2736 | FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, | ||
| 2737 | FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, | ||
| 2738 | FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, | ||
| 2739 | /* IP10_25_23 [3] */ | ||
| 2740 | FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, | ||
| 2741 | FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, | ||
| 2742 | /* IP10_22_19 [4] */ | ||
| 2743 | FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, | ||
| 2744 | FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, | ||
| 2745 | FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, | ||
| 2746 | /* IP10_18_15 [4] */ | ||
| 2747 | FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, | ||
| 2748 | FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, | ||
| 2749 | FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, | ||
| 2750 | 0, 0, 0, 0, 0, 0, | ||
| 2751 | /* IP10_14_11 [4] */ | ||
| 2752 | FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, | ||
| 2753 | FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, | ||
| 2754 | FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, | ||
| 2755 | 0, 0, 0, 0, 0, 0, 0, | ||
| 2756 | /* IP10_10_7 [4] */ | ||
| 2757 | FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, | ||
| 2758 | FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, | ||
| 2759 | FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, | ||
| 2760 | 0, 0, 0, 0, 0, 0, 0, | ||
| 2761 | /* IP10_6_4 [3] */ | ||
| 2762 | FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, | ||
| 2763 | FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, | ||
| 2764 | FN_VI3_DATA0_B, 0, | ||
| 2765 | /* IP10_3_0 [4] */ | ||
| 2766 | FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, | ||
| 2767 | FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, | ||
| 2768 | FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } | ||
| 2769 | }, | ||
| 2770 | { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, | ||
| 2771 | 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | ||
| 2772 | /* IP11_31_30 [2] */ | ||
| 2773 | FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, | ||
| 2774 | /* IP11_29_27 [3] */ | ||
| 2775 | FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, | ||
| 2776 | FN_RDS_CLK_B, 0, 0, | ||
| 2777 | /* IP11_26_24 [3] */ | ||
| 2778 | FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, | ||
| 2779 | 0, 0, 0, | ||
| 2780 | /* IP11_23_22 [2] */ | ||
| 2781 | FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, | ||
| 2782 | /* IP11_21_18 [4] */ | ||
| 2783 | FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, | ||
| 2784 | FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, | ||
| 2785 | FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0, | ||
| 2786 | /* IP11_17_15 [3] */ | ||
| 2787 | FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, | ||
| 2788 | FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, | ||
| 2789 | /* IP11_14_13 [2] */ | ||
| 2790 | FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, | ||
| 2791 | /* IP11_12_11 [2] */ | ||
| 2792 | FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, | ||
| 2793 | /* IP11_10_9 [2] */ | ||
| 2794 | FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, | ||
| 2795 | /* IP11_8_7 [2] */ | ||
| 2796 | FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, | ||
| 2797 | /* IP11_6_5 [2] */ | ||
| 2798 | FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, | ||
| 2799 | /* IP11_4 [1] */ | ||
| 2800 | FN_SD3_CLK, FN_MMC1_CLK, | ||
| 2801 | /* IP11_3_0 [4] */ | ||
| 2802 | FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, | ||
| 2803 | FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, | ||
| 2804 | FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } | ||
| 2805 | }, | ||
| 2806 | { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, | ||
| 2807 | 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { | ||
| 2808 | /* IP12_31 [1] */ | ||
| 2809 | 0, 0, | ||
| 2810 | /* IP12_30_28 [3] */ | ||
| 2811 | FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, | ||
| 2812 | FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, | ||
| 2813 | FN_CAN_DEBUGOUT4, 0, 0, | ||
| 2814 | /* IP12_27_25 [3] */ | ||
| 2815 | FN_SSI_SCK5, FN_SCIFB1_SCK, | ||
| 2816 | FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, | ||
| 2817 | FN_CAN_DEBUGOUT3, 0, 0, | ||
| 2818 | /* IP12_24_23 [2] */ | ||
| 2819 | FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, | ||
| 2820 | FN_CAN_DEBUGOUT2, | ||
| 2821 | /* IP12_22_20 [3] */ | ||
| 2822 | FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, | ||
| 2823 | FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, | ||
| 2824 | /* IP12_19_17 [3] */ | ||
| 2825 | FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, | ||
| 2826 | FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, | ||
| 2827 | /* IP12_16_14 [3] */ | ||
| 2828 | FN_SSI_SDATA3, FN_STP_ISCLK_0, | ||
| 2829 | FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, | ||
| 2830 | /* IP12_13_11 [3] */ | ||
| 2831 | FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, | ||
| 2832 | FN_CAN_STEP0, 0, 0, 0, | ||
| 2833 | /* IP12_10_8 [3] */ | ||
| 2834 | FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, | ||
| 2835 | FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, | ||
| 2836 | /* IP12_7_6 [2] */ | ||
| 2837 | FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, | ||
| 2838 | /* IP12_5_4 [2] */ | ||
| 2839 | FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, | ||
| 2840 | /* IP12_3_2 [2] */ | ||
| 2841 | FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, | ||
| 2842 | /* IP12_1_0 [2] */ | ||
| 2843 | FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } | ||
| 2844 | }, | ||
| 2845 | { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, | ||
| 2846 | 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { | ||
| 2847 | /* IP13_31 [1] */ | ||
| 2848 | 0, 0, | ||
| 2849 | /* IP13_30_29 [2] */ | ||
| 2850 | FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, | ||
| 2851 | /* IP13_28_26 [3] */ | ||
| 2852 | FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, | ||
| 2853 | FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, | ||
| 2854 | /* IP13_25_23 [3] */ | ||
| 2855 | FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, | ||
| 2856 | FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, | ||
| 2857 | /* IP13_22_19 [4] */ | ||
| 2858 | FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, | ||
| 2859 | FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, | ||
| 2860 | FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F, | ||
| 2861 | 0, 0, 0, 0, | ||
| 2862 | /* IP13_18_16 [3] */ | ||
| 2863 | FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, | ||
| 2864 | FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, | ||
| 2865 | /* IP13_15_13 [3] */ | ||
| 2866 | FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, | ||
| 2867 | FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, | ||
| 2868 | /* IP13_12_10 [3] */ | ||
| 2869 | FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, | ||
| 2870 | FN_CAN_DEBUGOUT8, 0, 0, | ||
| 2871 | /* IP13_9_7 [3] */ | ||
| 2872 | FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, | ||
| 2873 | FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, | ||
| 2874 | /* IP13_6_3 [4] */ | ||
| 2875 | FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, | ||
| 2876 | FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, | ||
| 2877 | FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0, | ||
| 2878 | /* IP13_2_0 [3] */ | ||
| 2879 | FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, | ||
| 2880 | FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } | ||
| 2881 | }, | ||
| 2882 | { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, | ||
| 2883 | 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { | ||
| 2884 | /* IP14_30 [1] */ | ||
| 2885 | 0, 0, | ||
| 2886 | /* IP14_30_28 [3] */ | ||
| 2887 | FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, | ||
| 2888 | FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, | ||
| 2889 | FN_HRTS0_N_C, 0, | ||
| 2890 | /* IP14_27_25 [3] */ | ||
| 2891 | FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, | ||
| 2892 | FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, | ||
| 2893 | /* IP14_24_22 [3] */ | ||
| 2894 | FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, | ||
| 2895 | FN_LCDOUT9, 0, 0, 0, | ||
| 2896 | /* IP14_21_19 [3] */ | ||
| 2897 | FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, | ||
| 2898 | FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, | ||
| 2899 | /* IP14_18_16 [3] */ | ||
| 2900 | FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, | ||
| 2901 | FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, | ||
| 2902 | /* IP14_15_12 [4] */ | ||
| 2903 | FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, | ||
| 2904 | FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, | ||
| 2905 | 0, 0, 0, 0, 0, 0, 0, | ||
| 2906 | /* IP14_11_9 [3] */ | ||
| 2907 | FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, | ||
| 2908 | 0, 0, 0, | ||
| 2909 | /* IP14_8_6 [3] */ | ||
| 2910 | FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, | ||
| 2911 | 0, 0, 0, | ||
| 2912 | /* IP14_5_3 [3] */ | ||
| 2913 | FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, | ||
| 2914 | FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, | ||
| 2915 | /* IP14_2_0 [3] */ | ||
| 2916 | FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, | ||
| 2917 | FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, | ||
| 2918 | FN_REMOCON, 0, } | ||
| 2919 | }, | ||
| 2920 | { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, | ||
| 2921 | 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { | ||
| 2922 | /* IP15_31_30 [2] */ | ||
| 2923 | 0, 0, 0, 0, | ||
| 2924 | /* IP15_29_28 [2] */ | ||
| 2925 | FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, | ||
| 2926 | /* IP15_27_26 [2] */ | ||
| 2927 | FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, | ||
| 2928 | /* IP15_25_23 [3] */ | ||
| 2929 | FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, | ||
| 2930 | FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0, | ||
| 2931 | /* IP15_22_20 [3] */ | ||
| 2932 | FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, | ||
| 2933 | FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, | ||
| 2934 | /* IP15_19_18 [2] */ | ||
| 2935 | FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, | ||
| 2936 | /* IP15_17_16 [2] */ | ||
| 2937 | FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, | ||
| 2938 | /* IP15_15_14 [2] */ | ||
| 2939 | FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, | ||
| 2940 | /* IP15_13_12 [2] */ | ||
| 2941 | FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, | ||
| 2942 | /* IP15_11_9 [3] */ | ||
| 2943 | FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, | ||
| 2944 | 0, 0, 0, | ||
| 2945 | /* IP15_8_6 [3] */ | ||
| 2946 | FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, | ||
| 2947 | FN_SDA2, FN_SDA2_CIS, 0, | ||
| 2948 | /* IP15_5_3 [3] */ | ||
| 2949 | FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, | ||
| 2950 | FN_SCL2, FN_SCL2_CIS, 0, | ||
| 2951 | /* IP15_2_0 [3] */ | ||
| 2952 | FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, | ||
| 2953 | FN_LCDOUT15, FN_SCIF_CLK_B, 0, } | ||
| 2954 | }, | ||
| 2955 | { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, | ||
| 2956 | 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { | ||
| 2957 | /* IP16_31_28 [4] */ | ||
| 2958 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2959 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2960 | /* IP16_27_24 [4] */ | ||
| 2961 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2962 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2963 | /* IP16_23_20 [4] */ | ||
| 2964 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2965 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2966 | /* IP16_19_16 [4] */ | ||
| 2967 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2968 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2969 | /* IP16_15_12 [4] */ | ||
| 2970 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2971 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2972 | /* IP16_11_8 [4] */ | ||
| 2973 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2974 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 2975 | /* IP16_7 [1] */ | ||
| 2976 | FN_USB1_OVC, FN_TCLK1_B, | ||
| 2977 | /* IP16_6 [1] */ | ||
| 2978 | FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, | ||
| 2979 | /* IP16_5_3 [3] */ | ||
| 2980 | FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, | ||
| 2981 | FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0, | ||
| 2982 | /* IP16_2_0 [3] */ | ||
| 2983 | FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, | ||
| 2984 | FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } | ||
| 2985 | }, | ||
| 2986 | { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, | ||
| 2987 | 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, | ||
| 2988 | 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { | ||
| 2989 | /* SEL_SCIF1 [3] */ | ||
| 2990 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, | ||
| 2991 | FN_SEL_SCIF1_4, 0, 0, 0, | ||
| 2992 | /* SEL_SCIFB [2] */ | ||
| 2993 | FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, | ||
| 2994 | /* SEL_SCIFB2 [2] */ | ||
| 2995 | FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, | ||
| 2996 | /* SEL_SCIFB1 [3] */ | ||
| 2997 | FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, | ||
| 2998 | FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, | ||
| 2999 | FN_SEL_SCIFB1_6, 0, | ||
| 3000 | /* SEL_SCIFA1 [2] */ | ||
| 3001 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, | ||
| 3002 | FN_SEL_SCIFA1_3, | ||
| 3003 | /* SEL_SCIF0 [1] */ | ||
| 3004 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, | ||
| 3005 | /* SEL_SCIFA [1] */ | ||
| 3006 | FN_SEL_SCFA_0, FN_SEL_SCFA_1, | ||
| 3007 | /* SEL_SOF1 [1] */ | ||
| 3008 | FN_SEL_SOF1_0, FN_SEL_SOF1_1, | ||
| 3009 | /* SEL_SSI7 [2] */ | ||
| 3010 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, | ||
| 3011 | /* SEL_SSI6 [1] */ | ||
| 3012 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | ||
| 3013 | /* SEL_SSI5 [2] */ | ||
| 3014 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, | ||
| 3015 | /* SEL_VI3 [1] */ | ||
| 3016 | FN_SEL_VI3_0, FN_SEL_VI3_1, | ||
| 3017 | /* SEL_VI2 [1] */ | ||
| 3018 | FN_SEL_VI2_0, FN_SEL_VI2_1, | ||
| 3019 | /* SEL_VI1 [1] */ | ||
| 3020 | FN_SEL_VI1_0, FN_SEL_VI1_1, | ||
| 3021 | /* SEL_VI0 [1] */ | ||
| 3022 | FN_SEL_VI0_0, FN_SEL_VI0_1, | ||
| 3023 | /* SEL_TSIF1 [2] */ | ||
| 3024 | FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, | ||
| 3025 | /* RESERVED [1] */ | ||
| 3026 | 0, 0, | ||
| 3027 | /* SEL_LBS [1] */ | ||
| 3028 | FN_SEL_LBS_0, FN_SEL_LBS_1, | ||
| 3029 | /* SEL_TSIF0 [2] */ | ||
| 3030 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | ||
| 3031 | /* SEL_SOF3 [1] */ | ||
| 3032 | FN_SEL_SOF3_0, FN_SEL_SOF3_1, | ||
| 3033 | /* SEL_SOF0 [1] */ | ||
| 3034 | FN_SEL_SOF0_0, FN_SEL_SOF0_1, } | ||
| 3035 | }, | ||
| 3036 | { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, | ||
| 3037 | 2, 1, 1, 1, 1, 2, 1, 2, 1, | ||
| 3038 | 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) { | ||
| 3039 | /* RESEVED [2] */ | ||
| 3040 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3041 | /* RESEVED [1] */ | ||
| 3042 | 0, 0, | ||
| 3043 | /* SEL_TMU1 [1] */ | ||
| 3044 | FN_SEL_TMU1_0, FN_SEL_TMU1_1, | ||
| 3045 | /* SEL_HSCIF1 [1] */ | ||
| 3046 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | ||
| 3047 | /* SEL_SCIFCLK [1] */ | ||
| 3048 | FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, | ||
| 3049 | /* SEL_CAN0 [2] */ | ||
| 3050 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | ||
| 3051 | /* SEL_CANCLK [1] */ | ||
| 3052 | FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, | ||
| 3053 | /* SEL_SCIFA2 [2] */ | ||
| 3054 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, | ||
| 3055 | /* SEL_CAN1 [1] */ | ||
| 3056 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, | ||
| 3057 | /* RESEVED [2] */ | ||
| 3058 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3059 | /* RESEVED [1] */ | ||
| 3060 | 0, 0, | ||
| 3061 | /* SEL_ADI [1] */ | ||
| 3062 | FN_SEL_ADI_0, FN_SEL_ADI_1, | ||
| 3063 | /* SEL_SSP [1] */ | ||
| 3064 | FN_SEL_SSP_0, FN_SEL_SSP_1, | ||
| 3065 | /* SEL_FM [3] */ | ||
| 3066 | FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, | ||
| 3067 | FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, | ||
| 3068 | /* SEL_HSCIF0 [3] */ | ||
| 3069 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, | ||
| 3070 | FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, | ||
| 3071 | /* SEL_GPS [2] */ | ||
| 3072 | FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, | ||
| 3073 | /* SEL_RDS [3] */ | ||
| 3074 | FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, | ||
| 3075 | FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0, | ||
| 3076 | /* SEL_SIM [2] */ | ||
| 3077 | FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, | ||
| 3078 | /* SEL_SSI8 [2] */ | ||
| 3079 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } | ||
| 3080 | }, | ||
| 3081 | { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, | ||
| 3082 | 1, 1, 2, 4, 4, 2, 2, | ||
| 3083 | 4, 2, 3, 2, 3, 2) { | ||
| 3084 | /* SEL_IICDVFS [1] */ | ||
| 3085 | FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, | ||
| 3086 | /* SEL_IIC0 [1] */ | ||
| 3087 | FN_SEL_IIC0_0, FN_SEL_IIC0_1, | ||
| 3088 | /* RESEVED [2] */ | ||
| 3089 | 0, 0, 0, 0, | ||
| 3090 | /* RESEVED [4] */ | ||
| 3091 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3092 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3093 | /* RESEVED [4] */ | ||
| 3094 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3095 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3096 | /* RESEVED [2] */ | ||
| 3097 | 0, 0, 0, 0, | ||
| 3098 | /* SEL_IEB [2] */ | ||
| 3099 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, | ||
| 3100 | /* RESEVED [4] */ | ||
| 3101 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3102 | 0, 0, 0, 0, 0, 0, 0, 0, | ||
| 3103 | /* RESEVED [2] */ | ||
| 3104 | 0, 0, 0, 0, | ||
| 3105 | /* SEL_IIC2 [3] */ | ||
| 3106 | FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, | ||
| 3107 | FN_SEL_IIC2_4, 0, 0, 0, | ||
| 3108 | /* SEL_IIC1 [2] */ | ||
| 3109 | FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, | ||
| 3110 | /* SEL_I2C2 [3] */ | ||
| 3111 | FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, | ||
| 3112 | FN_SEL_I2C2_4, 0, 0, 0, | ||
| 3113 | /* SEL_I2C1 [2] */ | ||
| 3114 | FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } | ||
| 3115 | }, | ||
| 3116 | { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, | ||
| 3117 | { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { | ||
| 3118 | 0, 0, | ||
| 3119 | 0, 0, | ||
| 3120 | GP_1_29_IN, GP_1_29_OUT, | ||
| 3121 | GP_1_28_IN, GP_1_28_OUT, | ||
| 3122 | GP_1_27_IN, GP_1_27_OUT, | ||
| 3123 | GP_1_26_IN, GP_1_26_OUT, | ||
| 3124 | GP_1_25_IN, GP_1_25_OUT, | ||
| 3125 | GP_1_24_IN, GP_1_24_OUT, | ||
| 3126 | GP_1_23_IN, GP_1_23_OUT, | ||
| 3127 | GP_1_22_IN, GP_1_22_OUT, | ||
| 3128 | GP_1_21_IN, GP_1_21_OUT, | ||
| 3129 | GP_1_20_IN, GP_1_20_OUT, | ||
| 3130 | GP_1_19_IN, GP_1_19_OUT, | ||
| 3131 | GP_1_18_IN, GP_1_18_OUT, | ||
| 3132 | GP_1_17_IN, GP_1_17_OUT, | ||
| 3133 | GP_1_16_IN, GP_1_16_OUT, | ||
| 3134 | GP_1_15_IN, GP_1_15_OUT, | ||
| 3135 | GP_1_14_IN, GP_1_14_OUT, | ||
| 3136 | GP_1_13_IN, GP_1_13_OUT, | ||
| 3137 | GP_1_12_IN, GP_1_12_OUT, | ||
| 3138 | GP_1_11_IN, GP_1_11_OUT, | ||
| 3139 | GP_1_10_IN, GP_1_10_OUT, | ||
| 3140 | GP_1_9_IN, GP_1_9_OUT, | ||
| 3141 | GP_1_8_IN, GP_1_8_OUT, | ||
| 3142 | GP_1_7_IN, GP_1_7_OUT, | ||
| 3143 | GP_1_6_IN, GP_1_6_OUT, | ||
| 3144 | GP_1_5_IN, GP_1_5_OUT, | ||
| 3145 | GP_1_4_IN, GP_1_4_OUT, | ||
| 3146 | GP_1_3_IN, GP_1_3_OUT, | ||
| 3147 | GP_1_2_IN, GP_1_2_OUT, | ||
| 3148 | GP_1_1_IN, GP_1_1_OUT, | ||
| 3149 | GP_1_0_IN, GP_1_0_OUT, } | ||
| 3150 | }, | ||
| 3151 | { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { | ||
| 3152 | 0, 0, | ||
| 3153 | 0, 0, | ||
| 3154 | GP_2_29_IN, GP_2_29_OUT, | ||
| 3155 | GP_2_28_IN, GP_2_28_OUT, | ||
| 3156 | GP_2_27_IN, GP_2_27_OUT, | ||
| 3157 | GP_2_26_IN, GP_2_26_OUT, | ||
| 3158 | GP_2_25_IN, GP_2_25_OUT, | ||
| 3159 | GP_2_24_IN, GP_2_24_OUT, | ||
| 3160 | GP_2_23_IN, GP_2_23_OUT, | ||
| 3161 | GP_2_22_IN, GP_2_22_OUT, | ||
| 3162 | GP_2_21_IN, GP_2_21_OUT, | ||
| 3163 | GP_2_20_IN, GP_2_20_OUT, | ||
| 3164 | GP_2_19_IN, GP_2_19_OUT, | ||
| 3165 | GP_2_18_IN, GP_2_18_OUT, | ||
| 3166 | GP_2_17_IN, GP_2_17_OUT, | ||
| 3167 | GP_2_16_IN, GP_2_16_OUT, | ||
| 3168 | GP_2_15_IN, GP_2_15_OUT, | ||
| 3169 | GP_2_14_IN, GP_2_14_OUT, | ||
| 3170 | GP_2_13_IN, GP_2_13_OUT, | ||
| 3171 | GP_2_12_IN, GP_2_12_OUT, | ||
| 3172 | GP_2_11_IN, GP_2_11_OUT, | ||
| 3173 | GP_2_10_IN, GP_2_10_OUT, | ||
| 3174 | GP_2_9_IN, GP_2_9_OUT, | ||
| 3175 | GP_2_8_IN, GP_2_8_OUT, | ||
| 3176 | GP_2_7_IN, GP_2_7_OUT, | ||
| 3177 | GP_2_6_IN, GP_2_6_OUT, | ||
| 3178 | GP_2_5_IN, GP_2_5_OUT, | ||
| 3179 | GP_2_4_IN, GP_2_4_OUT, | ||
| 3180 | GP_2_3_IN, GP_2_3_OUT, | ||
| 3181 | GP_2_2_IN, GP_2_2_OUT, | ||
| 3182 | GP_2_1_IN, GP_2_1_OUT, | ||
| 3183 | GP_2_0_IN, GP_2_0_OUT, } | ||
| 3184 | }, | ||
| 3185 | { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, | ||
| 3186 | { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, | ||
| 3187 | { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, | ||
| 3188 | { }, | ||
| 3189 | }; | ||
| 3190 | |||
| 3191 | static const struct pinmux_data_reg pinmux_data_regs[] = { | ||
| 3192 | { PINMUX_DATA_REG("INDT0", 0xE605000C, 32) { GP_INDT(0) } }, | ||
| 3193 | { PINMUX_DATA_REG("INDT1", 0xE605100C, 32) { | ||
| 3194 | 0, 0, GP_1_29_DATA, GP_1_28_DATA, | ||
| 3195 | GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, | ||
| 3196 | GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, | ||
| 3197 | GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, | ||
| 3198 | GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, | ||
| 3199 | GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, | ||
| 3200 | GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, | ||
| 3201 | GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } | ||
| 3202 | }, | ||
| 3203 | { PINMUX_DATA_REG("INDT2", 0xE605200C, 32) { | ||
| 3204 | 0, 0, GP_2_29_DATA, GP_2_28_DATA, | ||
| 3205 | GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, | ||
| 3206 | GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, | ||
| 3207 | GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, | ||
| 3208 | GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, | ||
| 3209 | GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, | ||
| 3210 | GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, | ||
| 3211 | GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } | ||
| 3212 | }, | ||
| 3213 | { PINMUX_DATA_REG("INDT3", 0xE605300C, 32) { GP_INDT(3) } }, | ||
| 3214 | { PINMUX_DATA_REG("INDT4", 0xE605400C, 32) { GP_INDT(4) } }, | ||
| 3215 | { PINMUX_DATA_REG("INDT5", 0xE605500C, 32) { GP_INDT(5) } }, | ||
| 3216 | { }, | ||
| 3217 | }; | ||
| 3218 | |||
| 3219 | const struct sh_pfc_soc_info r8a7790_pinmux_info = { | ||
| 3220 | .name = "r8a77900_pfc", | ||
| 3221 | .unlock_reg = 0xe6060000, /* PMMR */ | ||
| 3222 | |||
| 3223 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, | ||
| 3224 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, | ||
| 3225 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | ||
| 3226 | |||
| 3227 | .pins = pinmux_pins, | ||
| 3228 | .nr_pins = ARRAY_SIZE(pinmux_pins), | ||
| 3229 | |||
| 3230 | .func_gpios = pinmux_func_gpios, | ||
| 3231 | .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), | ||
| 3232 | |||
| 3233 | .cfg_regs = pinmux_config_regs, | ||
| 3234 | .data_regs = pinmux_data_regs, | ||
| 3235 | |||
| 3236 | .gpio_data = pinmux_data, | ||
| 3237 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | ||
| 3238 | }; | ||