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authorOlof Johansson <olof@lixom.net>2013-04-03 02:06:48 -0400
committerOlof Johansson <olof@lixom.net>2013-04-03 02:06:57 -0400
commite382328a811fd6ffdb77ee16ff6a9e92e07561c5 (patch)
tree0f88d2b72d13842924570e1019e320e1e57d36b9 /drivers/pinctrl/sh-pfc/pfc-r8a7740.c
parent2f7053e0ecbe8908a130207bc01b7b3f9f854ef8 (diff)
parent202ac6a21a79500ef5aab4cd8665be2597e9345c (diff)
Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10 Highlights: * Compilation fixes for sh7269 and for when CONFIG_BUG is not set * sh-pfc Support for r8a73a4 SoC * Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10 * tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (185 commits) sh-pfc: r8a73a4: Remove unused GPIO bias data ARM: shmobile: r8a73a4: Remove all GPIO enums sh-pfc: r8a73a4: Remove function GPIOs ARM: shmobile: r8a73a4: Remove IRQC function GPIOs ARM: shmobile: r8a73a4: Remove SCIF function GPIOs sh-pfc: r8a73a4: Remove IRQC function GPIOS sh-pfc: r8a73a4: Remove SCIF function GPIOS sh-pfc: r8a73a4: Add IRQC pin groups and functions sh-pfc: r8a73a4: Add SCIF pin groups and functions sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support sh-pfc: r8a73a4: GPIO IRQ support sh-pfc: r8a73a4: Support sparse GPIO numbers sh-pfc: Add r8a73a4 pinmux support sh-pfc: r8a7779: Split DU input and output pixel clocks sh-pfc: r8a7779: Remove GPIO data ARM: shmobile: r8a7779: Register GPIO devices sh-pfc: Configure pins as GPIOs at request time when handled externally sh-pfc: Skip gpiochip registration when no GPIO resource is found sh-pfc: Make GPIO support optional sh-pfc: Make function GPIOs support optional ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7740.c')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c626
1 files changed, 538 insertions, 88 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 2b528280e3c1..bbd87d29bfd0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -577,7 +577,7 @@ enum {
577 PINMUX_MARK_END, 577 PINMUX_MARK_END,
578}; 578};
579 579
580static pinmux_enum_t pinmux_data[] = { 580static const pinmux_enum_t pinmux_data[] = {
581 /* specify valid pin states for each pin in GPIO mode */ 581 /* specify valid pin states for each pin in GPIO mode */
582 582
583 /* I/O and Pull U/D */ 583 /* I/O and Pull U/D */
@@ -1654,11 +1654,532 @@ static pinmux_enum_t pinmux_data[] = {
1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), 1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1655}; 1655};
1656 1656
1657static struct pinmux_gpio pinmux_gpios[] = { 1657static struct sh_pfc_pin pinmux_pins[] = {
1658
1659 /* PORT */
1660 GPIO_PORT_ALL(), 1658 GPIO_PORT_ALL(),
1659};
1660
1661/* - LCD0 ------------------------------------------------------------------- */
1662static const unsigned int lcd0_data8_pins[] = {
1663 /* D[0:7] */
1664 58, 57, 56, 55, 54, 53, 52, 51,
1665};
1666static const unsigned int lcd0_data8_mux[] = {
1667 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1668 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1669};
1670static const unsigned int lcd0_data9_pins[] = {
1671 /* D[0:8] */
1672 58, 57, 56, 55, 54, 53, 52, 51,
1673 50,
1674};
1675static const unsigned int lcd0_data9_mux[] = {
1676 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1677 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1678 LCD0_D8_MARK,
1679};
1680static const unsigned int lcd0_data12_pins[] = {
1681 /* D[0:11] */
1682 58, 57, 56, 55, 54, 53, 52, 51,
1683 50, 49, 48, 47,
1684};
1685static const unsigned int lcd0_data12_mux[] = {
1686 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1687 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1688 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1689};
1690static const unsigned int lcd0_data16_pins[] = {
1691 /* D[0:15] */
1692 58, 57, 56, 55, 54, 53, 52, 51,
1693 50, 49, 48, 47, 46, 45, 44, 43,
1694};
1695static const unsigned int lcd0_data16_mux[] = {
1696 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1697 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1698 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1699 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1700};
1701static const unsigned int lcd0_data18_pins[] = {
1702 /* D[0:17] */
1703 58, 57, 56, 55, 54, 53, 52, 51,
1704 50, 49, 48, 47, 46, 45, 44, 43,
1705 42, 41,
1706};
1707static const unsigned int lcd0_data18_mux[] = {
1708 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1709 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1710 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1711 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1712 LCD0_D16_MARK, LCD0_D17_MARK,
1713};
1714static const unsigned int lcd0_data24_0_pins[] = {
1715 /* D[0:23] */
1716 58, 57, 56, 55, 54, 53, 52, 51,
1717 50, 49, 48, 47, 46, 45, 44, 43,
1718 42, 41, 40, 4, 3, 2, 0, 1,
1719};
1720static const unsigned int lcd0_data24_0_mux[] = {
1721 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1722 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1723 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1724 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1725 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
1726 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
1727 LCD0_D23_PORT1_MARK,
1728};
1729static const unsigned int lcd0_data24_1_pins[] = {
1730 /* D[0:23] */
1731 58, 57, 56, 55, 54, 53, 52, 51,
1732 50, 49, 48, 47, 46, 45, 44, 43,
1733 42, 41, 163, 162, 161, 158, 160, 159,
1734};
1735static const unsigned int lcd0_data24_1_mux[] = {
1736 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1737 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1738 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1739 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
1740 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
1741 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
1742};
1743static const unsigned int lcd0_display_pins[] = {
1744 /* DON, VCPWC, VEPWC */
1745 61, 59, 60,
1746};
1747static const unsigned int lcd0_display_mux[] = {
1748 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
1749};
1750static const unsigned int lcd0_lclk_0_pins[] = {
1751 /* LCLK */
1752 102,
1753};
1754static const unsigned int lcd0_lclk_0_mux[] = {
1755 LCD0_LCLK_PORT102_MARK,
1756};
1757static const unsigned int lcd0_lclk_1_pins[] = {
1758 /* LCLK */
1759 165,
1760};
1761static const unsigned int lcd0_lclk_1_mux[] = {
1762 LCD0_LCLK_PORT165_MARK,
1763};
1764static const unsigned int lcd0_sync_pins[] = {
1765 /* VSYN, HSYN, DCK, DISP */
1766 63, 64, 62, 65,
1767};
1768static const unsigned int lcd0_sync_mux[] = {
1769 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
1770};
1771static const unsigned int lcd0_sys_pins[] = {
1772 /* CS, WR, RD, RS */
1773 64, 62, 164, 65,
1774};
1775static const unsigned int lcd0_sys_mux[] = {
1776 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
1777};
1778/* - LCD1 ------------------------------------------------------------------- */
1779static const unsigned int lcd1_data8_pins[] = {
1780 /* D[0:7] */
1781 4, 3, 2, 1, 0, 91, 92, 23,
1782};
1783static const unsigned int lcd1_data8_mux[] = {
1784 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1785 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1786};
1787static const unsigned int lcd1_data9_pins[] = {
1788 /* D[0:8] */
1789 4, 3, 2, 1, 0, 91, 92, 23,
1790 93,
1791};
1792static const unsigned int lcd1_data9_mux[] = {
1793 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1794 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1795 LCD1_D8_MARK,
1796};
1797static const unsigned int lcd1_data12_pins[] = {
1798 /* D[0:12] */
1799 4, 3, 2, 1, 0, 91, 92, 23,
1800 93, 94, 21, 201,
1801};
1802static const unsigned int lcd1_data12_mux[] = {
1803 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1804 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1805 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1806};
1807static const unsigned int lcd1_data16_pins[] = {
1808 /* D[0:15] */
1809 4, 3, 2, 1, 0, 91, 92, 23,
1810 93, 94, 21, 201, 200, 199, 196, 195,
1811};
1812static const unsigned int lcd1_data16_mux[] = {
1813 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1814 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1815 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1816 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1817};
1818static const unsigned int lcd1_data18_pins[] = {
1819 /* D[0:17] */
1820 4, 3, 2, 1, 0, 91, 92, 23,
1821 93, 94, 21, 201, 200, 199, 196, 195,
1822 194, 193,
1823};
1824static const unsigned int lcd1_data18_mux[] = {
1825 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1826 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1827 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1828 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1829 LCD1_D16_MARK, LCD1_D17_MARK,
1830};
1831static const unsigned int lcd1_data24_pins[] = {
1832 /* D[0:23] */
1833 4, 3, 2, 1, 0, 91, 92, 23,
1834 93, 94, 21, 201, 200, 199, 196, 195,
1835 194, 193, 198, 197, 75, 74, 15, 14,
1836};
1837static const unsigned int lcd1_data24_mux[] = {
1838 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1839 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1840 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1841 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1842 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
1843 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
1844};
1845static const unsigned int lcd1_display_pins[] = {
1846 /* DON, VCPWC, VEPWC */
1847 100, 5, 6,
1848};
1849static const unsigned int lcd1_display_mux[] = {
1850 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
1851};
1852static const unsigned int lcd1_lclk_pins[] = {
1853 /* LCLK */
1854 40,
1855};
1856static const unsigned int lcd1_lclk_mux[] = {
1857 LCD1_LCLK_MARK,
1858};
1859static const unsigned int lcd1_sync_pins[] = {
1860 /* VSYN, HSYN, DCK, DISP */
1861 98, 97, 99, 12,
1862};
1863static const unsigned int lcd1_sync_mux[] = {
1864 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
1865};
1866static const unsigned int lcd1_sys_pins[] = {
1867 /* CS, WR, RD, RS */
1868 97, 99, 13, 12,
1869};
1870static const unsigned int lcd1_sys_mux[] = {
1871 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
1872};
1873/* - MMCIF ------------------------------------------------------------------ */
1874static const unsigned int mmc0_data1_0_pins[] = {
1875 /* D[0] */
1876 68,
1877};
1878static const unsigned int mmc0_data1_0_mux[] = {
1879 MMC0_D0_PORT68_MARK,
1880};
1881static const unsigned int mmc0_data4_0_pins[] = {
1882 /* D[0:3] */
1883 68, 69, 70, 71,
1884};
1885static const unsigned int mmc0_data4_0_mux[] = {
1886 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
1887};
1888static const unsigned int mmc0_data8_0_pins[] = {
1889 /* D[0:7] */
1890 68, 69, 70, 71, 72, 73, 74, 75,
1891};
1892static const unsigned int mmc0_data8_0_mux[] = {
1893 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
1894 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
1895};
1896static const unsigned int mmc0_ctrl_0_pins[] = {
1897 /* CMD, CLK */
1898 67, 66,
1899};
1900static const unsigned int mmc0_ctrl_0_mux[] = {
1901 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
1902};
1903
1904static const unsigned int mmc0_data1_1_pins[] = {
1905 /* D[0] */
1906 149,
1907};
1908static const unsigned int mmc0_data1_1_mux[] = {
1909 MMC1_D0_PORT149_MARK,
1910};
1911static const unsigned int mmc0_data4_1_pins[] = {
1912 /* D[0:3] */
1913 149, 148, 147, 146,
1914};
1915static const unsigned int mmc0_data4_1_mux[] = {
1916 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
1917};
1918static const unsigned int mmc0_data8_1_pins[] = {
1919 /* D[0:7] */
1920 149, 148, 147, 146, 145, 144, 143, 142,
1921};
1922static const unsigned int mmc0_data8_1_mux[] = {
1923 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
1924 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
1925};
1926static const unsigned int mmc0_ctrl_1_pins[] = {
1927 /* CMD, CLK */
1928 104, 103,
1929};
1930static const unsigned int mmc0_ctrl_1_mux[] = {
1931 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
1932};
1933/* - SDHI0 ------------------------------------------------------------------ */
1934static const unsigned int sdhi0_data1_pins[] = {
1935 /* D0 */
1936 77,
1937};
1938static const unsigned int sdhi0_data1_mux[] = {
1939 SDHI0_D0_MARK,
1940};
1941static const unsigned int sdhi0_data4_pins[] = {
1942 /* D[0:3] */
1943 77, 78, 79, 80,
1944};
1945static const unsigned int sdhi0_data4_mux[] = {
1946 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
1947};
1948static const unsigned int sdhi0_ctrl_pins[] = {
1949 /* CMD, CLK */
1950 76, 82,
1951};
1952static const unsigned int sdhi0_ctrl_mux[] = {
1953 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
1954};
1955static const unsigned int sdhi0_cd_pins[] = {
1956 /* CD */
1957 81,
1958};
1959static const unsigned int sdhi0_cd_mux[] = {
1960 SDHI0_CD_MARK,
1961};
1962static const unsigned int sdhi0_wp_pins[] = {
1963 /* WP */
1964 83,
1965};
1966static const unsigned int sdhi0_wp_mux[] = {
1967 SDHI0_WP_MARK,
1968};
1969/* - SDHI1 ------------------------------------------------------------------ */
1970static const unsigned int sdhi1_data1_pins[] = {
1971 /* D0 */
1972 68,
1973};
1974static const unsigned int sdhi1_data1_mux[] = {
1975 SDHI1_D0_MARK,
1976};
1977static const unsigned int sdhi1_data4_pins[] = {
1978 /* D[0:3] */
1979 68, 69, 70, 71,
1980};
1981static const unsigned int sdhi1_data4_mux[] = {
1982 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
1983};
1984static const unsigned int sdhi1_ctrl_pins[] = {
1985 /* CMD, CLK */
1986 67, 66,
1987};
1988static const unsigned int sdhi1_ctrl_mux[] = {
1989 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
1990};
1991static const unsigned int sdhi1_cd_pins[] = {
1992 /* CD */
1993 72,
1994};
1995static const unsigned int sdhi1_cd_mux[] = {
1996 SDHI1_CD_MARK,
1997};
1998static const unsigned int sdhi1_wp_pins[] = {
1999 /* WP */
2000 73,
2001};
2002static const unsigned int sdhi1_wp_mux[] = {
2003 SDHI1_WP_MARK,
2004};
2005/* - SDHI2 ------------------------------------------------------------------ */
2006static const unsigned int sdhi2_data1_pins[] = {
2007 /* D0 */
2008 205,
2009};
2010static const unsigned int sdhi2_data1_mux[] = {
2011 SDHI2_D0_MARK,
2012};
2013static const unsigned int sdhi2_data4_pins[] = {
2014 /* D[0:3] */
2015 205, 206, 207, 208,
2016};
2017static const unsigned int sdhi2_data4_mux[] = {
2018 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2019};
2020static const unsigned int sdhi2_ctrl_pins[] = {
2021 /* CMD, CLK */
2022 204, 203,
2023};
2024static const unsigned int sdhi2_ctrl_mux[] = {
2025 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2026};
2027static const unsigned int sdhi2_cd_0_pins[] = {
2028 /* CD */
2029 202,
2030};
2031static const unsigned int sdhi2_cd_0_mux[] = {
2032 SDHI2_CD_PORT202_MARK,
2033};
2034static const unsigned int sdhi2_wp_0_pins[] = {
2035 /* WP */
2036 177,
2037};
2038static const unsigned int sdhi2_wp_0_mux[] = {
2039 SDHI2_WP_PORT177_MARK,
2040};
2041static const unsigned int sdhi2_cd_1_pins[] = {
2042 /* CD */
2043 24,
2044};
2045static const unsigned int sdhi2_cd_1_mux[] = {
2046 SDHI2_CD_PORT24_MARK,
2047};
2048static const unsigned int sdhi2_wp_1_pins[] = {
2049 /* WP */
2050 25,
2051};
2052static const unsigned int sdhi2_wp_1_mux[] = {
2053 SDHI2_WP_PORT25_MARK,
2054};
2055
2056static const struct sh_pfc_pin_group pinmux_groups[] = {
2057 SH_PFC_PIN_GROUP(lcd0_data8),
2058 SH_PFC_PIN_GROUP(lcd0_data9),
2059 SH_PFC_PIN_GROUP(lcd0_data12),
2060 SH_PFC_PIN_GROUP(lcd0_data16),
2061 SH_PFC_PIN_GROUP(lcd0_data18),
2062 SH_PFC_PIN_GROUP(lcd0_data24_0),
2063 SH_PFC_PIN_GROUP(lcd0_data24_1),
2064 SH_PFC_PIN_GROUP(lcd0_display),
2065 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2066 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2067 SH_PFC_PIN_GROUP(lcd0_sync),
2068 SH_PFC_PIN_GROUP(lcd0_sys),
2069 SH_PFC_PIN_GROUP(lcd1_data8),
2070 SH_PFC_PIN_GROUP(lcd1_data9),
2071 SH_PFC_PIN_GROUP(lcd1_data12),
2072 SH_PFC_PIN_GROUP(lcd1_data16),
2073 SH_PFC_PIN_GROUP(lcd1_data18),
2074 SH_PFC_PIN_GROUP(lcd1_data24),
2075 SH_PFC_PIN_GROUP(lcd1_display),
2076 SH_PFC_PIN_GROUP(lcd1_lclk),
2077 SH_PFC_PIN_GROUP(lcd1_sync),
2078 SH_PFC_PIN_GROUP(lcd1_sys),
2079 SH_PFC_PIN_GROUP(mmc0_data1_0),
2080 SH_PFC_PIN_GROUP(mmc0_data4_0),
2081 SH_PFC_PIN_GROUP(mmc0_data8_0),
2082 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2083 SH_PFC_PIN_GROUP(mmc0_data1_1),
2084 SH_PFC_PIN_GROUP(mmc0_data4_1),
2085 SH_PFC_PIN_GROUP(mmc0_data8_1),
2086 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2087 SH_PFC_PIN_GROUP(sdhi0_data1),
2088 SH_PFC_PIN_GROUP(sdhi0_data4),
2089 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2090 SH_PFC_PIN_GROUP(sdhi0_cd),
2091 SH_PFC_PIN_GROUP(sdhi0_wp),
2092 SH_PFC_PIN_GROUP(sdhi1_data1),
2093 SH_PFC_PIN_GROUP(sdhi1_data4),
2094 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2095 SH_PFC_PIN_GROUP(sdhi1_cd),
2096 SH_PFC_PIN_GROUP(sdhi1_wp),
2097 SH_PFC_PIN_GROUP(sdhi2_data1),
2098 SH_PFC_PIN_GROUP(sdhi2_data4),
2099 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2100 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2101 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2102 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2103 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2104};
2105
2106static const char * const lcd0_groups[] = {
2107 "lcd0_data8",
2108 "lcd0_data9",
2109 "lcd0_data12",
2110 "lcd0_data16",
2111 "lcd0_data18",
2112 "lcd0_data24_0",
2113 "lcd0_data24_1",
2114 "lcd0_display",
2115 "lcd0_lclk_0",
2116 "lcd0_lclk_1",
2117 "lcd0_sync",
2118 "lcd0_sys",
2119};
2120
2121static const char * const lcd1_groups[] = {
2122 "lcd1_data8",
2123 "lcd1_data9",
2124 "lcd1_data12",
2125 "lcd1_data16",
2126 "lcd1_data18",
2127 "lcd1_data24",
2128 "lcd1_display",
2129 "lcd1_lclk",
2130 "lcd1_sync",
2131 "lcd1_sys",
2132};
2133
2134static const char * const mmc0_groups[] = {
2135 "mmc0_data1_0",
2136 "mmc0_data4_0",
2137 "mmc0_data8_0",
2138 "mmc0_ctrl_0",
2139 "mmc0_data1_1",
2140 "mmc0_data4_1",
2141 "mmc0_data8_1",
2142 "mmc0_ctrl_1",
2143};
2144
2145static const char * const sdhi0_groups[] = {
2146 "sdhi0_data1",
2147 "sdhi0_data4",
2148 "sdhi0_ctrl",
2149 "sdhi0_cd",
2150 "sdhi0_wp",
2151};
2152
2153static const char * const sdhi1_groups[] = {
2154 "sdhi1_data1",
2155 "sdhi1_data4",
2156 "sdhi1_ctrl",
2157 "sdhi1_cd",
2158 "sdhi1_wp",
2159};
2160
2161static const char * const sdhi2_groups[] = {
2162 "sdhi2_data1",
2163 "sdhi2_data4",
2164 "sdhi2_ctrl",
2165 "sdhi2_cd_0",
2166 "sdhi2_wp_0",
2167 "sdhi2_cd_1",
2168 "sdhi2_wp_1",
2169};
2170
2171static const struct sh_pfc_function pinmux_functions[] = {
2172 SH_PFC_FUNCTION(lcd0),
2173 SH_PFC_FUNCTION(lcd1),
2174 SH_PFC_FUNCTION(mmc0),
2175 SH_PFC_FUNCTION(sdhi0),
2176 SH_PFC_FUNCTION(sdhi1),
2177 SH_PFC_FUNCTION(sdhi2),
2178};
1661 2179
2180#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2181
2182static const struct pinmux_func pinmux_func_gpios[] = {
1662 /* IRQ */ 2183 /* IRQ */
1663 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), 2184 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1664 GPIO_FN(IRQ1), 2185 GPIO_FN(IRQ1),
@@ -1792,43 +2313,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1792 GPIO_FN(SCIFB_RTS_PORT172), 2313 GPIO_FN(SCIFB_RTS_PORT172),
1793 GPIO_FN(SCIFB_CTS_PORT173), 2314 GPIO_FN(SCIFB_CTS_PORT173),
1794 2315
1795 /* LCD0 */
1796 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1797 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1798 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1799 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1800 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1801 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1802 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1803 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1804 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1805 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1806 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1807
1808 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1809 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1810 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1811 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1812
1813 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1814 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1815 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1816 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1817
1818 /* LCD1 */
1819 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1820 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1821 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1822 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1823 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1824 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1825 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1826 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1827 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1828 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1829 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1830 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1831
1832 /* RSPI */ 2316 /* RSPI */
1833 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), 2317 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1834 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), 2318 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
@@ -1889,26 +2373,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1889 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ 2373 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1890 GPIO_FN(SIM_D_PORT199), 2374 GPIO_FN(SIM_D_PORT199),
1891 2375
1892 /* SDHI0 */
1893 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1894 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1895 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1896
1897 /* SDHI1 */
1898 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1899 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1900 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1901
1902 /* SDHI2 */
1903 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1904 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1905
1906 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1907 GPIO_FN(SDHI2_WP_PORT25),
1908
1909 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1910 GPIO_FN(SDHI2_CD_PORT202),
1911
1912 /* MSIOF2 */ 2376 /* MSIOF2 */
1913 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), 2377 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1914 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), 2378 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
@@ -1953,21 +2417,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1953 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), 2417 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1954 GPIO_FN(MEMC_A0), 2418 GPIO_FN(MEMC_A0),
1955 2419
1956 /* MMC */
1957 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1958 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1959 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1960 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1961 GPIO_FN(MMC0_CLK_PORT66),
1962 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1963
1964 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1965 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1966 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1967 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1968 GPIO_FN(MMC1_CLK_PORT103),
1969 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1970
1971 /* MSIOF0 */ 2420 /* MSIOF0 */
1972 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), 2421 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1973 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), 2422 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
@@ -2126,7 +2575,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
2126 GPIO_FN(TRACEAUD_FROM_MEMC), 2575 GPIO_FN(TRACEAUD_FROM_MEMC),
2127}; 2576};
2128 2577
2129static struct pinmux_cfg_reg pinmux_config_regs[] = { 2578static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2130 PORTCR(0, 0xe6050000), /* PORT0CR */ 2579 PORTCR(0, 0xe6050000), /* PORT0CR */
2131 PORTCR(1, 0xe6050001), /* PORT1CR */ 2580 PORTCR(1, 0xe6050001), /* PORT1CR */
2132 PORTCR(2, 0xe6050002), /* PORT2CR */ 2581 PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2440,7 +2889,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2440 { }, 2889 { },
2441}; 2890};
2442 2891
2443static struct pinmux_data_reg pinmux_data_regs[] = { 2892static const struct pinmux_data_reg pinmux_data_regs[] = {
2444 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { 2893 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2445 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 2894 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2446 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 2895 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2544,7 +2993,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2544 { }, 2993 { },
2545}; 2994};
2546 2995
2547static struct pinmux_irq pinmux_irqs[] = { 2996static const struct pinmux_irq pinmux_irqs[] = {
2548 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ 2997 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
2549 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ 2998 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
2550 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ 2999 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
@@ -2579,11 +3028,8 @@ static struct pinmux_irq pinmux_irqs[] = {
2579 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ 3028 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
2580}; 3029};
2581 3030
2582struct sh_pfc_soc_info r8a7740_pinmux_info = { 3031const struct sh_pfc_soc_info r8a7740_pinmux_info = {
2583 .name = "r8a7740_pfc", 3032 .name = "r8a7740_pfc",
2584 .reserved_id = PINMUX_RESERVED,
2585 .data = { PINMUX_DATA_BEGIN,
2586 PINMUX_DATA_END },
2587 .input = { PINMUX_INPUT_BEGIN, 3033 .input = { PINMUX_INPUT_BEGIN,
2588 PINMUX_INPUT_END }, 3034 PINMUX_INPUT_END },
2589 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, 3035 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
@@ -2592,15 +3038,19 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
2592 PINMUX_INPUT_PULLDOWN_END }, 3038 PINMUX_INPUT_PULLDOWN_END },
2593 .output = { PINMUX_OUTPUT_BEGIN, 3039 .output = { PINMUX_OUTPUT_BEGIN,
2594 PINMUX_OUTPUT_END }, 3040 PINMUX_OUTPUT_END },
2595 .mark = { PINMUX_MARK_BEGIN,
2596 PINMUX_MARK_END },
2597 .function = { PINMUX_FUNCTION_BEGIN, 3041 .function = { PINMUX_FUNCTION_BEGIN,
2598 PINMUX_FUNCTION_END }, 3042 PINMUX_FUNCTION_END },
2599 3043
2600 .first_gpio = GPIO_PORT0, 3044 .pins = pinmux_pins,
2601 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, 3045 .nr_pins = ARRAY_SIZE(pinmux_pins),
3046 .groups = pinmux_groups,
3047 .nr_groups = ARRAY_SIZE(pinmux_groups),
3048 .functions = pinmux_functions,
3049 .nr_functions = ARRAY_SIZE(pinmux_functions),
3050
3051 .func_gpios = pinmux_func_gpios,
3052 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2602 3053
2603 .gpios = pinmux_gpios,
2604 .cfg_regs = pinmux_config_regs, 3054 .cfg_regs = pinmux_config_regs,
2605 .data_regs = pinmux_data_regs, 3055 .data_regs = pinmux_data_regs,
2606 3056
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 11:25:30 -0500