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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-04-19 05:52:59 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-04 08:04:25 -0400
commitb79839024f41bca04098eff0f85e66cf20c15a2a (patch)
tree747260b339a25edbc4aef6f6609ae6d024a945b4 /drivers/pinctrl/sh-pfc/pfc-r8a7740.c
parenta37d60659fbef3560c7b4fa5f9d7cf34863f3ae2 (diff)
sh-pfc: r8a7740: Hardcode the LCDC0 output
The r8a7740 has two LCDC units and two sets of LCDC output signals. By default LCDC0 is routed to the LCD0 signals, and LCDC1 to the LCD1 signals. However, LCDC1 can be routed to the LCD0 signals by setting bit MSEL6 in MSEL3CR (the LCD0 signals are further pinmuxed the usual way). This could be configured by duplicating the LCD0 pin groups for LCDC1. However, this would unnecessarily complicate the LCD pin groups, as no r8a7740 board supported in mainline use such a configuration. Hardcode the MSEL3CR MSEL6 bit to 0 for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7740.c')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 5a77d3934564..9afc7b0ef7d8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -277,8 +277,6 @@ enum {
277 SCIFB_CTS_PORT173_MARK, 277 SCIFB_CTS_PORT173_MARK,
278 278
279 /* LCD0 */ 279 /* LCD0 */
280 LCDC0_SELECT_MARK,
281
282 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, 280 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
283 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, 281 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
284 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, 282 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
@@ -301,8 +299,6 @@ enum {
301 LCD0_LCLK_PORT102_MARK, 299 LCD0_LCLK_PORT102_MARK,
302 300
303 /* LCD1 */ 301 /* LCD1 */
304 LCDC1_SELECT_MARK,
305
306 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, 302 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
307 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, 303 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
308 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, 304 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
@@ -1002,7 +998,7 @@ static const pinmux_enum_t pinmux_data[] = {
1002 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), 998 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
1003 999
1004 /* Port58 */ 1000 /* Port58 */
1005 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), 1001 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
1006 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), 1002 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
1007 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), 1003 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
1008 PINMUX_DATA(DV_D0_MARK, PORT58_FN6), 1004 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
@@ -1649,10 +1645,6 @@ static const pinmux_enum_t pinmux_data[] = {
1649 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), 1645 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1650 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), 1646 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1651 1647
1652 /* LCDC select */
1653 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1654 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1655
1656 /* SDENC */ 1648 /* SDENC */
1657 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), 1649 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1658 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), 1650 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
@@ -3578,10 +3570,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
3578 /* IRREM */ 3570 /* IRREM */
3579 GPIO_FN(IROUT), 3571 GPIO_FN(IROUT),
3580 3572
3581 /* LCDC */
3582 GPIO_FN(LCDC0_SELECT),
3583 GPIO_FN(LCDC1_SELECT),
3584
3585 /* SDENC */ 3573 /* SDENC */
3586 GPIO_FN(SDENC_CPG), 3574 GPIO_FN(SDENC_CPG),
3587 GPIO_FN(SDENC_DV_CLKI), 3575 GPIO_FN(SDENC_DV_CLKI),