aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl/pinctrl-u300.c
diff options
context:
space:
mode:
authorLinus Walleij <linus.walleij@linaro.org>2011-12-18 17:44:26 -0500
committerLinus Walleij <linus.walleij@linaro.org>2012-01-03 03:10:08 -0500
commit3bece55aa5356af0171aaa64fd9c4f7601c47f1c (patch)
tree8dd08d51859062defc424ff234f1032b89e9410e /drivers/pinctrl/pinctrl-u300.c
parent43699dea1ea21a0d5786317a794cb2ba27a6f4fe (diff)
pinctrl: rename U300 and SIRF pin controllers
For stringent order, rename the pinmux-* pin controllers to pinctrl-* and also rename the Kconfig symbols and in-kernel users. Cc: Rongjun Ying <Rongjun.Ying@csr.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-u300.c')
-rw-r--r--drivers/pinctrl/pinctrl-u300.c1157
1 files changed, 1157 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
new file mode 100644
index 000000000000..7e89b367a7e5
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -0,0 +1,1157 @@
1/*
2 * Driver for the U300 pin controller
3 *
4 * Based on the original U300 padmux functions
5 * Copyright (C) 2009-2011 ST-Ericsson AB
6 * Author: Martin Persson <martin.persson@stericsson.com>
7 * Author: Linus Walleij <linus.walleij@linaro.org>
8 *
9 * The DB3350 design and control registers are oriented around pads rather than
10 * pins, so we enumerate the pads we can mux rather than actual pins. The pads
11 * are connected to different pins in different packaging types, so it would
12 * be confusing.
13 */
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/err.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22
23/*
24 * Register definitions for the U300 Padmux control registers in the
25 * system controller
26 */
27
28/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
29#define U300_SYSCON_PMC1LR 0x007C
30#define U300_SYSCON_PMC1LR_MASK 0xFFFF
31#define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
32#define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
33#define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
34/* For BS335 */
35#define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
36#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
37/* For BS365 */
38#define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
39#define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
40/* Common defs */
41#define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
42#define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
43#define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
44#define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
45#define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
46#define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
47#define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
48#define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
49#define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
50#define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
51#define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
52#define U300_SYSCON_PMC1LR_ETM_APP 0x0100
53#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
54#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
55#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
56#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
57#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
58#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
59#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
60#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
61#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
62#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
63#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
64#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
65#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
66#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
67#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
68#define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
69#define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
70#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
71#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
72#define U300_SYSCON_PMC1LR_EMIF_1 0x0003
73/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
74#define U300_SYSCON_PMC1HR 0x007E
75#define U300_SYSCON_PMC1HR_MASK 0xFFFF
76#define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
77#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
78#define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
79#define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
80#define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
81#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
82#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
83#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
84#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
85#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
86#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
87#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
88#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
89#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
90#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
91#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
92#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
93#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
94#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
95#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
96#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
97#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
98#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
99#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
100#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
101#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
102#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
103#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
104#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
105#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
106#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
107#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
108#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
109#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
110#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
111#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
112#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
113/* Padmux 2 control */
114#define U300_SYSCON_PMC2R 0x100
115#define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
116#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
117#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
118#define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
119#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
120#define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
121#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
122#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
123#define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
124#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
125#define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
126#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
127#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
128#define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
129#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
130#define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
131#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
132#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
133#define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
134#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
135#define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
136#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
137#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
138#define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
139#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
140/* TODO: More SYSCON registers missing */
141#define U300_SYSCON_PMC3R 0x10C
142#define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
143#define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
144#define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
145#define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
146/* TODO: Missing other configs */
147#define U300_SYSCON_PMC4R 0x168
148#define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
149#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
150#define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
151#define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
152#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
153#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
154#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
155#define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
156#define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
157#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
158#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
159#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
160#define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
161#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
162#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
163#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
164
165#define DRIVER_NAME "pinmux-u300"
166
167/*
168 * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
169 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
170 * Data taken from the PadRing chart, arranged like this:
171 *
172 * 0 ..... 104
173 * 466 105
174 * . .
175 * . .
176 * 358 224
177 * 357 .... 225
178 */
179#define U300_NUM_PADS 467
180
181/* Pad names for the pinmux subsystem */
182static const struct pinctrl_pin_desc u300_pads[] = {
183 /* Pads along the top edge of the chip */
184 PINCTRL_PIN(0, "P PAD VDD 28"),
185 PINCTRL_PIN(1, "P PAD GND 28"),
186 PINCTRL_PIN(2, "PO SIM RST N"),
187 PINCTRL_PIN(3, "VSSIO 25"),
188 PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
189 PINCTRL_PIN(5, "PWR VSSCOMMON"),
190 PINCTRL_PIN(6, "PI ADC I1 POS"),
191 PINCTRL_PIN(7, "PI ADC I1 NEG"),
192 PINCTRL_PIN(8, "PWR VSSAD0"),
193 PINCTRL_PIN(9, "PWR VCCAD0"),
194 PINCTRL_PIN(10, "PI ADC Q1 NEG"),
195 PINCTRL_PIN(11, "PI ADC Q1 POS"),
196 PINCTRL_PIN(12, "PWR VDDAD"),
197 PINCTRL_PIN(13, "PWR GNDAD"),
198 PINCTRL_PIN(14, "PI ADC I2 POS"),
199 PINCTRL_PIN(15, "PI ADC I2 NEG"),
200 PINCTRL_PIN(16, "PWR VSSAD1"),
201 PINCTRL_PIN(17, "PWR VCCAD1"),
202 PINCTRL_PIN(18, "PI ADC Q2 NEG"),
203 PINCTRL_PIN(19, "PI ADC Q2 POS"),
204 PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
205 PINCTRL_PIN(21, "PWR VCCGPAD"),
206 PINCTRL_PIN(22, "PI TX POW"),
207 PINCTRL_PIN(23, "PWR VSSGPAD"),
208 PINCTRL_PIN(24, "PO DAC I POS"),
209 PINCTRL_PIN(25, "PO DAC I NEG"),
210 PINCTRL_PIN(26, "PO DAC Q POS"),
211 PINCTRL_PIN(27, "PO DAC Q NEG"),
212 PINCTRL_PIN(28, "PWR VSSDA"),
213 PINCTRL_PIN(29, "PWR VCCDA"),
214 PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
215 PINCTRL_PIN(31, "P PAD VDDIO 11"),
216 PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
217 PINCTRL_PIN(33, "PI PLL 26 VCONT"),
218 PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
219 PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
220 PINCTRL_PIN(36, "VDDA PLL ESD"),
221 PINCTRL_PIN(37, "VSSA PLL ESD"),
222 PINCTRL_PIN(38, "VSS PLL"),
223 PINCTRL_PIN(39, "VDDC PLL"),
224 PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
225 PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
226 PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
227 PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
228 PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
229 PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
230 PINCTRL_PIN(46, "P PAD VSSIO 11"),
231 PINCTRL_PIN(47, "P PAD VSSIO 12"),
232 PINCTRL_PIN(48, "PI POW RST N"),
233 PINCTRL_PIN(49, "VDDC IO"),
234 PINCTRL_PIN(50, "P PAD VDDIO 16"),
235 PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
236 PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
237 PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
238 PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
239 PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
240 PINCTRL_PIN(56, "PO GSM PA ENABLE"),
241 PINCTRL_PIN(57, "PO RF DATA STRB"),
242 PINCTRL_PIN(58, "PO RF DATA2"),
243 PINCTRL_PIN(59, "PIO RF DATA1"),
244 PINCTRL_PIN(60, "PIO RF DATA0"),
245 PINCTRL_PIN(61, "P PAD VDD 11"),
246 PINCTRL_PIN(62, "P PAD GND 11"),
247 PINCTRL_PIN(63, "P PAD VSSIO 16"),
248 PINCTRL_PIN(64, "P PAD VDDIO 18"),
249 PINCTRL_PIN(65, "PO RF CTRL STRB2"),
250 PINCTRL_PIN(66, "PO RF CTRL STRB1"),
251 PINCTRL_PIN(67, "PO RF CTRL STRB0"),
252 PINCTRL_PIN(68, "PIO RF CTRL DATA"),
253 PINCTRL_PIN(69, "PO RF CTRL CLK"),
254 PINCTRL_PIN(70, "PO TX ADC STRB"),
255 PINCTRL_PIN(71, "PO ANT SW 2"),
256 PINCTRL_PIN(72, "PO ANT SW 3"),
257 PINCTRL_PIN(73, "PO ANT SW 0"),
258 PINCTRL_PIN(74, "PO ANT SW 1"),
259 PINCTRL_PIN(75, "PO M CLKRQ"),
260 PINCTRL_PIN(76, "PI M CLK"),
261 PINCTRL_PIN(77, "PI RTC CLK"),
262 PINCTRL_PIN(78, "P PAD VDD 8"),
263 PINCTRL_PIN(79, "P PAD GND 8"),
264 PINCTRL_PIN(80, "P PAD VSSIO 13"),
265 PINCTRL_PIN(81, "P PAD VDDIO 13"),
266 PINCTRL_PIN(82, "PO SYS 1 CLK"),
267 PINCTRL_PIN(83, "PO SYS 2 CLK"),
268 PINCTRL_PIN(84, "PO SYS 0 CLK"),
269 PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
270 PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
271 PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
272 PINCTRL_PIN(88, "PO RESOUT2 RST N"),
273 PINCTRL_PIN(89, "PO RESOUT1 RST N"),
274 PINCTRL_PIN(90, "PO RESOUT0 RST N"),
275 PINCTRL_PIN(91, "PI SERVICE N"),
276 PINCTRL_PIN(92, "P PAD VDD 29"),
277 PINCTRL_PIN(93, "P PAD GND 29"),
278 PINCTRL_PIN(94, "P PAD VSSIO 8"),
279 PINCTRL_PIN(95, "P PAD VDDIO 8"),
280 PINCTRL_PIN(96, "PI EXT IRQ1 N"),
281 PINCTRL_PIN(97, "PI EXT IRQ0 N"),
282 PINCTRL_PIN(98, "PIO DC ON"),
283 PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
284 PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
285 PINCTRL_PIN(101, "P PAD VDD 12"),
286 PINCTRL_PIN(102, "P PAD GND 12"),
287 PINCTRL_PIN(103, "P PAD VSSIO 14"),
288 PINCTRL_PIN(104, "P PAD VDDIO 14"),
289 /* Pads along the right edge of the chip */
290 PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
291 PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
292 PINCTRL_PIN(107, "PO KEY OUT0"),
293 PINCTRL_PIN(108, "PO KEY OUT1"),
294 PINCTRL_PIN(109, "PO KEY OUT2"),
295 PINCTRL_PIN(110, "PO KEY OUT3"),
296 PINCTRL_PIN(111, "PO KEY OUT4"),
297 PINCTRL_PIN(112, "PI KEY IN0"),
298 PINCTRL_PIN(113, "PI KEY IN1"),
299 PINCTRL_PIN(114, "PI KEY IN2"),
300 PINCTRL_PIN(115, "P PAD VDDIO 15"),
301 PINCTRL_PIN(116, "P PAD VSSIO 15"),
302 PINCTRL_PIN(117, "P PAD GND 13"),
303 PINCTRL_PIN(118, "P PAD VDD 13"),
304 PINCTRL_PIN(119, "PI KEY IN3"),
305 PINCTRL_PIN(120, "PI KEY IN4"),
306 PINCTRL_PIN(121, "PI KEY IN5"),
307 PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
308 PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
309 PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
310 PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
311 PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
312 PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
313 PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
314 PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
315 PINCTRL_PIN(130, "P PAD VDD 17"),
316 PINCTRL_PIN(131, "P PAD GND 17"),
317 PINCTRL_PIN(132, "P PAD VSSIO 19"),
318 PINCTRL_PIN(133, "P PAD VDDIO 19"),
319 PINCTRL_PIN(134, "UART0 RTS"),
320 PINCTRL_PIN(135, "UART0 CTS"),
321 PINCTRL_PIN(136, "UART0 TX"),
322 PINCTRL_PIN(137, "UART0 RX"),
323 PINCTRL_PIN(138, "PIO ACC SPI DO"),
324 PINCTRL_PIN(139, "PIO ACC SPI DI"),
325 PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
326 PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
327 PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
328 PINCTRL_PIN(143, "PIO ACC SPI CLK"),
329 PINCTRL_PIN(144, "PO PDI EXT RST N"),
330 PINCTRL_PIN(145, "P PAD VDDIO 22"),
331 PINCTRL_PIN(146, "P PAD VSSIO 22"),
332 PINCTRL_PIN(147, "P PAD GND 18"),
333 PINCTRL_PIN(148, "P PAD VDD 18"),
334 PINCTRL_PIN(149, "PIO PDI C0"),
335 PINCTRL_PIN(150, "PIO PDI C1"),
336 PINCTRL_PIN(151, "PIO PDI C2"),
337 PINCTRL_PIN(152, "PIO PDI C3"),
338 PINCTRL_PIN(153, "PIO PDI C4"),
339 PINCTRL_PIN(154, "PIO PDI C5"),
340 PINCTRL_PIN(155, "PIO PDI D0"),
341 PINCTRL_PIN(156, "PIO PDI D1"),
342 PINCTRL_PIN(157, "PIO PDI D2"),
343 PINCTRL_PIN(158, "PIO PDI D3"),
344 PINCTRL_PIN(159, "P PAD VDDIO 21"),
345 PINCTRL_PIN(160, "P PAD VSSIO 21"),
346 PINCTRL_PIN(161, "PIO PDI D4"),
347 PINCTRL_PIN(162, "PIO PDI D5"),
348 PINCTRL_PIN(163, "PIO PDI D6"),
349 PINCTRL_PIN(164, "PIO PDI D7"),
350 PINCTRL_PIN(165, "PIO MS INS"),
351 PINCTRL_PIN(166, "MMC DATA DIR LS"),
352 PINCTRL_PIN(167, "MMC DATA 3"),
353 PINCTRL_PIN(168, "MMC DATA 2"),
354 PINCTRL_PIN(169, "MMC DATA 1"),
355 PINCTRL_PIN(170, "MMC DATA 0"),
356 PINCTRL_PIN(171, "MMC CMD DIR LS"),
357 PINCTRL_PIN(172, "P PAD VDD 27"),
358 PINCTRL_PIN(173, "P PAD GND 27"),
359 PINCTRL_PIN(174, "P PAD VSSIO 20"),
360 PINCTRL_PIN(175, "P PAD VDDIO 20"),
361 PINCTRL_PIN(176, "MMC CMD"),
362 PINCTRL_PIN(177, "MMC CLK"),
363 PINCTRL_PIN(178, "PIO APP GPIO 14"),
364 PINCTRL_PIN(179, "PIO APP GPIO 13"),
365 PINCTRL_PIN(180, "PIO APP GPIO 11"),
366 PINCTRL_PIN(181, "PIO APP GPIO 25"),
367 PINCTRL_PIN(182, "PIO APP GPIO 24"),
368 PINCTRL_PIN(183, "PIO APP GPIO 23"),
369 PINCTRL_PIN(184, "PIO APP GPIO 22"),
370 PINCTRL_PIN(185, "PIO APP GPIO 21"),
371 PINCTRL_PIN(186, "PIO APP GPIO 20"),
372 PINCTRL_PIN(187, "P PAD VDD 19"),
373 PINCTRL_PIN(188, "P PAD GND 19"),
374 PINCTRL_PIN(189, "P PAD VSSIO 23"),
375 PINCTRL_PIN(190, "P PAD VDDIO 23"),
376 PINCTRL_PIN(191, "PIO APP GPIO 19"),
377 PINCTRL_PIN(192, "PIO APP GPIO 18"),
378 PINCTRL_PIN(193, "PIO APP GPIO 17"),
379 PINCTRL_PIN(194, "PIO APP GPIO 16"),
380 PINCTRL_PIN(195, "PI CI D1"),
381 PINCTRL_PIN(196, "PI CI D0"),
382 PINCTRL_PIN(197, "PI CI HSYNC"),
383 PINCTRL_PIN(198, "PI CI VSYNC"),
384 PINCTRL_PIN(199, "PI CI EXT CLK"),
385 PINCTRL_PIN(200, "PO CI EXT RST N"),
386 PINCTRL_PIN(201, "P PAD VSSIO 43"),
387 PINCTRL_PIN(202, "P PAD VDDIO 43"),
388 PINCTRL_PIN(203, "PI CI D6"),
389 PINCTRL_PIN(204, "PI CI D7"),
390 PINCTRL_PIN(205, "PI CI D2"),
391 PINCTRL_PIN(206, "PI CI D3"),
392 PINCTRL_PIN(207, "PI CI D4"),
393 PINCTRL_PIN(208, "PI CI D5"),
394 PINCTRL_PIN(209, "PI CI D8"),
395 PINCTRL_PIN(210, "PI CI D9"),
396 PINCTRL_PIN(211, "P PAD VDD 20"),
397 PINCTRL_PIN(212, "P PAD GND 20"),
398 PINCTRL_PIN(213, "P PAD VSSIO 24"),
399 PINCTRL_PIN(214, "P PAD VDDIO 24"),
400 PINCTRL_PIN(215, "P PAD VDDIO 26"),
401 PINCTRL_PIN(216, "PO EMIF 1 A26"),
402 PINCTRL_PIN(217, "PO EMIF 1 A25"),
403 PINCTRL_PIN(218, "P PAD VSSIO 26"),
404 PINCTRL_PIN(219, "PO EMIF 1 A24"),
405 PINCTRL_PIN(220, "PO EMIF 1 A23"),
406 /* Pads along the bottom edge of the chip */
407 PINCTRL_PIN(221, "PO EMIF 1 A22"),
408 PINCTRL_PIN(222, "PO EMIF 1 A21"),
409 PINCTRL_PIN(223, "P PAD VDD 21"),
410 PINCTRL_PIN(224, "P PAD GND 21"),
411 PINCTRL_PIN(225, "P PAD VSSIO 27"),
412 PINCTRL_PIN(226, "P PAD VDDIO 27"),
413 PINCTRL_PIN(227, "PO EMIF 1 A20"),
414 PINCTRL_PIN(228, "PO EMIF 1 A19"),
415 PINCTRL_PIN(229, "PO EMIF 1 A18"),
416 PINCTRL_PIN(230, "PO EMIF 1 A17"),
417 PINCTRL_PIN(231, "P PAD VDDIO 28"),
418 PINCTRL_PIN(232, "P PAD VSSIO 28"),
419 PINCTRL_PIN(233, "PO EMIF 1 A16"),
420 PINCTRL_PIN(234, "PIO EMIF 1 D15"),
421 PINCTRL_PIN(235, "PO EMIF 1 A15"),
422 PINCTRL_PIN(236, "PIO EMIF 1 D14"),
423 PINCTRL_PIN(237, "P PAD VDD 22"),
424 PINCTRL_PIN(238, "P PAD GND 22"),
425 PINCTRL_PIN(239, "P PAD VSSIO 29"),
426 PINCTRL_PIN(240, "P PAD VDDIO 29"),
427 PINCTRL_PIN(241, "PO EMIF 1 A14"),
428 PINCTRL_PIN(242, "PIO EMIF 1 D13"),
429 PINCTRL_PIN(243, "PO EMIF 1 A13"),
430 PINCTRL_PIN(244, "PIO EMIF 1 D12"),
431 PINCTRL_PIN(245, "P PAD VSSIO 30"),
432 PINCTRL_PIN(246, "P PAD VDDIO 30"),
433 PINCTRL_PIN(247, "PO EMIF 1 A12"),
434 PINCTRL_PIN(248, "PIO EMIF 1 D11"),
435 PINCTRL_PIN(249, "PO EMIF 1 A11"),
436 PINCTRL_PIN(250, "PIO EMIF 1 D10"),
437 PINCTRL_PIN(251, "P PAD VSSIO 31"),
438 PINCTRL_PIN(252, "P PAD VDDIO 31"),
439 PINCTRL_PIN(253, "PO EMIF 1 A10"),
440 PINCTRL_PIN(254, "PIO EMIF 1 D09"),
441 PINCTRL_PIN(255, "PO EMIF 1 A09"),
442 PINCTRL_PIN(256, "P PAD VDDIO 32"),
443 PINCTRL_PIN(257, "P PAD VSSIO 32"),
444 PINCTRL_PIN(258, "P PAD GND 24"),
445 PINCTRL_PIN(259, "P PAD VDD 24"),
446 PINCTRL_PIN(260, "PIO EMIF 1 D08"),
447 PINCTRL_PIN(261, "PO EMIF 1 A08"),
448 PINCTRL_PIN(262, "PIO EMIF 1 D07"),
449 PINCTRL_PIN(263, "PO EMIF 1 A07"),
450 PINCTRL_PIN(264, "P PAD VDDIO 33"),
451 PINCTRL_PIN(265, "P PAD VSSIO 33"),
452 PINCTRL_PIN(266, "PIO EMIF 1 D06"),
453 PINCTRL_PIN(267, "PO EMIF 1 A06"),
454 PINCTRL_PIN(268, "PIO EMIF 1 D05"),
455 PINCTRL_PIN(269, "PO EMIF 1 A05"),
456 PINCTRL_PIN(270, "P PAD VDDIO 34"),
457 PINCTRL_PIN(271, "P PAD VSSIO 34"),
458 PINCTRL_PIN(272, "PIO EMIF 1 D04"),
459 PINCTRL_PIN(273, "PO EMIF 1 A04"),
460 PINCTRL_PIN(274, "PIO EMIF 1 D03"),
461 PINCTRL_PIN(275, "PO EMIF 1 A03"),
462 PINCTRL_PIN(276, "P PAD VDDIO 35"),
463 PINCTRL_PIN(277, "P PAD VSSIO 35"),
464 PINCTRL_PIN(278, "P PAD GND 23"),
465 PINCTRL_PIN(279, "P PAD VDD 23"),
466 PINCTRL_PIN(280, "PIO EMIF 1 D02"),
467 PINCTRL_PIN(281, "PO EMIF 1 A02"),
468 PINCTRL_PIN(282, "PIO EMIF 1 D01"),
469 PINCTRL_PIN(283, "PO EMIF 1 A01"),
470 PINCTRL_PIN(284, "P PAD VDDIO 36"),
471 PINCTRL_PIN(285, "P PAD VSSIO 36"),
472 PINCTRL_PIN(286, "PIO EMIF 1 D00"),
473 PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
474 PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
475 PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
476 PINCTRL_PIN(290, "P PAD VDDIO 37"),
477 PINCTRL_PIN(291, "P PAD VSSIO 37"),
478 PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
479 PINCTRL_PIN(293, "PO EMIF 1 OE N"),
480 PINCTRL_PIN(294, "PO EMIF 1 WE N"),
481 PINCTRL_PIN(295, "P PAD VDDIO 38"),
482 PINCTRL_PIN(296, "P PAD VSSIO 38"),
483 PINCTRL_PIN(297, "PO EMIF 1 CLK"),
484 PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
485 PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
486 PINCTRL_PIN(300, "P PAD VDDIO 42"),
487 PINCTRL_PIN(301, "P PAD VSSIO 42"),
488 PINCTRL_PIN(302, "P PAD GND 31"),
489 PINCTRL_PIN(303, "P PAD VDD 31"),
490 PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
491 PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
492 PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
493 PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
494 PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
495 PINCTRL_PIN(309, "P PAD VDD 25"),
496 PINCTRL_PIN(310, "P PAD GND 25"),
497 PINCTRL_PIN(311, "P PAD VSSIO 39"),
498 PINCTRL_PIN(312, "P PAD VDDIO 39"),
499 PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
500 PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
501 PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
502 PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
503 PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
504 PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
505 PINCTRL_PIN(319, "P PAD VDD 30"),
506 PINCTRL_PIN(320, "P PAD GND 30"),
507 PINCTRL_PIN(321, "P PAD VSSIO 44"),
508 PINCTRL_PIN(322, "P PAD VDDIO 44"),
509 PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
510 PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
511 PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
512 PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
513 PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
514 PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
515 PINCTRL_PIN(329, "P PAD VDD 26"),
516 PINCTRL_PIN(330, "P PAD GND 26"),
517 PINCTRL_PIN(331, "P PAD VSSIO 40"),
518 PINCTRL_PIN(332, "P PAD VDDIO 40"),
519 PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
520 PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
521 PINCTRL_PIN(335, "PO ETM TRACE CLK"),
522 PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
523 PINCTRL_PIN(337, "PIO ACC GPIO 33"),
524 PINCTRL_PIN(338, "PIO ACC GPIO 32"),
525 PINCTRL_PIN(339, "PIO ACC GPIO 30"),
526 PINCTRL_PIN(340, "PIO ACC GPIO 29"),
527 PINCTRL_PIN(341, "P PAD VDDIO 17"),
528 PINCTRL_PIN(342, "P PAD VSSIO 17"),
529 PINCTRL_PIN(343, "P PAD GND 15"),
530 PINCTRL_PIN(344, "P PAD VDD 15"),
531 PINCTRL_PIN(345, "PIO ACC GPIO 28"),
532 PINCTRL_PIN(346, "PIO ACC GPIO 27"),
533 PINCTRL_PIN(347, "PIO ACC GPIO 16"),
534 PINCTRL_PIN(348, "PI TAP TMS"),
535 PINCTRL_PIN(349, "PI TAP TDI"),
536 PINCTRL_PIN(350, "PO TAP TDO"),
537 PINCTRL_PIN(351, "PI TAP RST N"),
538 /* Pads along the left edge of the chip */
539 PINCTRL_PIN(352, "PI EMU MODE 0"),
540 PINCTRL_PIN(353, "PO TAP RET CLK"),
541 PINCTRL_PIN(354, "PI TAP CLK"),
542 PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
543 PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
544 PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
545 PINCTRL_PIN(358, "P PAD VDDIO 1"),
546 PINCTRL_PIN(359, "P PAD VSSIO 1"),
547 PINCTRL_PIN(360, "P PAD GND 1"),
548 PINCTRL_PIN(361, "P PAD VDD 1"),
549 PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
550 PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
551 PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
552 PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
553 PINCTRL_PIN(366, "PIO EMIF 0 D15"),
554 PINCTRL_PIN(367, "PO EMIF 0 A15"),
555 PINCTRL_PIN(368, "PIO EMIF 0 D14"),
556 PINCTRL_PIN(369, "PO EMIF 0 A14"),
557 PINCTRL_PIN(370, "PIO EMIF 0 D13"),
558 PINCTRL_PIN(371, "PO EMIF 0 A13"),
559 PINCTRL_PIN(372, "P PAD VDDIO 2"),
560 PINCTRL_PIN(373, "P PAD VSSIO 2"),
561 PINCTRL_PIN(374, "P PAD GND 2"),
562 PINCTRL_PIN(375, "P PAD VDD 2"),
563 PINCTRL_PIN(376, "PIO EMIF 0 D12"),
564 PINCTRL_PIN(377, "PO EMIF 0 A12"),
565 PINCTRL_PIN(378, "PIO EMIF 0 D11"),
566 PINCTRL_PIN(379, "PO EMIF 0 A11"),
567 PINCTRL_PIN(380, "PIO EMIF 0 D10"),
568 PINCTRL_PIN(381, "PO EMIF 0 A10"),
569 PINCTRL_PIN(382, "PIO EMIF 0 D09"),
570 PINCTRL_PIN(383, "PO EMIF 0 A09"),
571 PINCTRL_PIN(384, "PIO EMIF 0 D08"),
572 PINCTRL_PIN(385, "PO EMIF 0 A08"),
573 PINCTRL_PIN(386, "PIO EMIF 0 D07"),
574 PINCTRL_PIN(387, "PO EMIF 0 A07"),
575 PINCTRL_PIN(388, "P PAD VDDIO 3"),
576 PINCTRL_PIN(389, "P PAD VSSIO 3"),
577 PINCTRL_PIN(390, "P PAD GND 3"),
578 PINCTRL_PIN(391, "P PAD VDD 3"),
579 PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
580 PINCTRL_PIN(393, "PIO EMIF 0 D06"),
581 PINCTRL_PIN(394, "PO EMIF 0 A06"),
582 PINCTRL_PIN(395, "PIO EMIF 0 D05"),
583 PINCTRL_PIN(396, "PO EMIF 0 A05"),
584 PINCTRL_PIN(397, "PIO EMIF 0 D04"),
585 PINCTRL_PIN(398, "PO EMIF 0 A04"),
586 PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
587 PINCTRL_PIN(400, "PWR VDDCO AF"),
588 PINCTRL_PIN(401, "PWR EFUSE HV1"),
589 PINCTRL_PIN(402, "P PAD VSSIO 4"),
590 PINCTRL_PIN(403, "P PAD VDDIO 4"),
591 PINCTRL_PIN(404, "P PAD GND 4"),
592 PINCTRL_PIN(405, "P PAD VDD 4"),
593 PINCTRL_PIN(406, "PIO EMIF 0 D03"),
594 PINCTRL_PIN(407, "PO EMIF 0 A03"),
595 PINCTRL_PIN(408, "PWR EFUSE HV2"),
596 PINCTRL_PIN(409, "PWR EFUSE HV3"),
597 PINCTRL_PIN(410, "PIO EMIF 0 D02"),
598 PINCTRL_PIN(411, "PO EMIF 0 A02"),
599 PINCTRL_PIN(412, "PIO EMIF 0 D01"),
600 PINCTRL_PIN(413, "P PAD VDDIO 5"),
601 PINCTRL_PIN(414, "P PAD VSSIO 5"),
602 PINCTRL_PIN(415, "P PAD GND 5"),
603 PINCTRL_PIN(416, "P PAD VDD 5"),
604 PINCTRL_PIN(417, "PO EMIF 0 A01"),
605 PINCTRL_PIN(418, "PIO EMIF 0 D00"),
606 PINCTRL_PIN(419, "IF 0 SD CLK"),
607 PINCTRL_PIN(420, "APP SPI CLK"),
608 PINCTRL_PIN(421, "APP SPI DO"),
609 PINCTRL_PIN(422, "APP SPI DI"),
610 PINCTRL_PIN(423, "APP SPI CS0"),
611 PINCTRL_PIN(424, "APP SPI CS1"),
612 PINCTRL_PIN(425, "APP SPI CS2"),
613 PINCTRL_PIN(426, "PIO APP GPIO 10"),
614 PINCTRL_PIN(427, "P PAD VDDIO 41"),
615 PINCTRL_PIN(428, "P PAD VSSIO 41"),
616 PINCTRL_PIN(429, "P PAD GND 6"),
617 PINCTRL_PIN(430, "P PAD VDD 6"),
618 PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
619 PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
620 PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
621 PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
622 PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
623 PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
624 PINCTRL_PIN(437, "PIO USB PU"),
625 PINCTRL_PIN(438, "PIO USB SP"),
626 PINCTRL_PIN(439, "PIO USB DAT VP"),
627 PINCTRL_PIN(440, "PIO USB SE0 VM"),
628 PINCTRL_PIN(441, "PIO USB OE"),
629 PINCTRL_PIN(442, "PIO USB SUSP"),
630 PINCTRL_PIN(443, "P PAD VSSIO 6"),
631 PINCTRL_PIN(444, "P PAD VDDIO 6"),
632 PINCTRL_PIN(445, "PIO USB PUEN"),
633 PINCTRL_PIN(446, "PIO ACC UART0 RX"),
634 PINCTRL_PIN(447, "PIO ACC UART0 TX"),
635 PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
636 PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
637 PINCTRL_PIN(450, "PIO ACC UART3 RX"),
638 PINCTRL_PIN(451, "PIO ACC UART3 TX"),
639 PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
640 PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
641 PINCTRL_PIN(454, "PIO ACC IRDA TX"),
642 PINCTRL_PIN(455, "P PAD VDDIO 7"),
643 PINCTRL_PIN(456, "P PAD VSSIO 7"),
644 PINCTRL_PIN(457, "P PAD GND 7"),
645 PINCTRL_PIN(458, "P PAD VDD 7"),
646 PINCTRL_PIN(459, "PIO ACC IRDA RX"),
647 PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
648 PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
649 PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
650 PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
651 PINCTRL_PIN(464, "PO SIM CLK"),
652 PINCTRL_PIN(465, "PIO ACC IRDA SD"),
653 PINCTRL_PIN(466, "PIO SIM DATA"),
654};
655
656/**
657 * @dev: a pointer back to containing device
658 * @virtbase: the offset to the controller in virtual memory
659 */
660struct u300_pmx {
661 struct device *dev;
662 struct pinctrl_dev *pctl;
663 u32 phybase;
664 u32 physize;
665 void __iomem *virtbase;
666};
667
668/**
669 * u300_pmx_registers - the array of registers read/written for each pinmux
670 * shunt setting
671 */
672const u32 u300_pmx_registers[] = {
673 U300_SYSCON_PMC1LR,
674 U300_SYSCON_PMC1HR,
675 U300_SYSCON_PMC2R,
676 U300_SYSCON_PMC3R,
677 U300_SYSCON_PMC4R,
678};
679
680/**
681 * struct u300_pin_group - describes a U300 pin group
682 * @name: the name of this specific pin group
683 * @pins: an array of discrete physical pins used in this group, taken
684 * from the driver-local pin enumeration space
685 * @num_pins: the number of pins in this group array, i.e. the number of
686 * elements in .pins so we can iterate over that array
687 */
688struct u300_pin_group {
689 const char *name;
690 const unsigned int *pins;
691 const unsigned num_pins;
692};
693
694/**
695 * struct pmx_onmask - mask bits to enable/disable padmux
696 * @mask: mask bits to disable
697 * @val: mask bits to enable
698 *
699 * onmask lazy dog:
700 * onmask = {
701 * {"PMC1LR" mask, "PMC1LR" value},
702 * {"PMC1HR" mask, "PMC1HR" value},
703 * {"PMC2R" mask, "PMC2R" value},
704 * {"PMC3R" mask, "PMC3R" value},
705 * {"PMC4R" mask, "PMC4R" value}
706 * }
707 */
708struct u300_pmx_mask {
709 u16 mask;
710 u16 bits;
711};
712
713/* The chip power pins are VDD, GND, VDDIO and VSSIO */
714static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
715 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
716 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
717 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
718 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
719 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
720 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
721 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
722 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
723 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
724static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
725 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
726 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
727 417, 418 };
728static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
729 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
730 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
731 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
732 304, 305, 306, 307, 308, 313, 314, 315 };
733static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
734static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
735static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
736
737static const struct u300_pmx_mask emif0_mask[] = {
738 {0, 0},
739 {0, 0},
740 {0, 0},
741 {0, 0},
742 {0, 0},
743};
744
745static const struct u300_pmx_mask emif1_mask[] = {
746 /*
747 * This connects the SDRAM to CS2 and a NAND flash to
748 * CS0 on the EMIF.
749 */
750 {
751 U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
752 U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
753 U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
754 U300_SYSCON_PMC1LR_EMIF_1_MASK,
755 U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
756 U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
757 U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
758 U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
759 },
760 {0, 0},
761 {0, 0},
762 {0, 0},
763 {0, 0},
764};
765
766static const struct u300_pmx_mask uart0_mask[] = {
767 {0, 0},
768 {
769 U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
770 U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
771 U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
772 U300_SYSCON_PMC1HR_APP_UART0_2_UART0
773 },
774 {0, 0},
775 {0, 0},
776 {0, 0},
777};
778
779static const struct u300_pmx_mask mmc0_mask[] = {
780 { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
781 {0, 0},
782 {0, 0},
783 {0, 0},
784 { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
785 U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
786};
787
788static const struct u300_pmx_mask spi0_mask[] = {
789 {0, 0},
790 {
791 U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
792 U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
793 U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
794 U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
795 U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
796 U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
797 },
798 {0, 0},
799 {0, 0},
800 {0, 0}
801};
802
803static const struct u300_pin_group u300_pin_groups[] = {
804 {
805 .name = "powergrp",
806 .pins = power_pins,
807 .num_pins = ARRAY_SIZE(power_pins),
808 },
809 {
810 .name = "emif0grp",
811 .pins = emif0_pins,
812 .num_pins = ARRAY_SIZE(emif0_pins),
813 },
814 {
815 .name = "emif1grp",
816 .pins = emif1_pins,
817 .num_pins = ARRAY_SIZE(emif1_pins),
818 },
819 {
820 .name = "uart0grp",
821 .pins = uart0_pins,
822 .num_pins = ARRAY_SIZE(uart0_pins),
823 },
824 {
825 .name = "mmc0grp",
826 .pins = mmc0_pins,
827 .num_pins = ARRAY_SIZE(mmc0_pins),
828 },
829 {
830 .name = "spi0grp",
831 .pins = spi0_pins,
832 .num_pins = ARRAY_SIZE(spi0_pins),
833 },
834};
835
836static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
837{
838 if (selector >= ARRAY_SIZE(u300_pin_groups))
839 return -EINVAL;
840 return 0;
841}
842
843static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
844 unsigned selector)
845{
846 if (selector >= ARRAY_SIZE(u300_pin_groups))
847 return NULL;
848 return u300_pin_groups[selector].name;
849}
850
851static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
852 const unsigned **pins,
853 unsigned *num_pins)
854{
855 if (selector >= ARRAY_SIZE(u300_pin_groups))
856 return -EINVAL;
857 *pins = u300_pin_groups[selector].pins;
858 *num_pins = u300_pin_groups[selector].num_pins;
859 return 0;
860}
861
862static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
863 unsigned offset)
864{
865 seq_printf(s, " " DRIVER_NAME);
866}
867
868static struct pinctrl_ops u300_pctrl_ops = {
869 .list_groups = u300_list_groups,
870 .get_group_name = u300_get_group_name,
871 .get_group_pins = u300_get_group_pins,
872 .pin_dbg_show = u300_pin_dbg_show,
873};
874
875/*
876 * Here we define the available functions and their corresponding pin groups
877 */
878
879/**
880 * struct u300_pmx_func - describes U300 pinmux functions
881 * @name: the name of this specific function
882 * @groups: corresponding pin groups
883 * @onmask: bits to set to enable this when doing pin muxing
884 */
885struct u300_pmx_func {
886 const char *name;
887 const char * const *groups;
888 const unsigned num_groups;
889 const struct u300_pmx_mask *mask;
890};
891
892static const char * const powergrps[] = { "powergrp" };
893static const char * const emif0grps[] = { "emif0grp" };
894static const char * const emif1grps[] = { "emif1grp" };
895static const char * const uart0grps[] = { "uart0grp" };
896static const char * const mmc0grps[] = { "mmc0grp" };
897static const char * const spi0grps[] = { "spi0grp" };
898
899static const struct u300_pmx_func u300_pmx_functions[] = {
900 {
901 .name = "power",
902 .groups = powergrps,
903 .num_groups = ARRAY_SIZE(powergrps),
904 /* Mask is N/A */
905 },
906 {
907 .name = "emif0",
908 .groups = emif0grps,
909 .num_groups = ARRAY_SIZE(emif0grps),
910 .mask = emif0_mask,
911 },
912 {
913 .name = "emif1",
914 .groups = emif1grps,
915 .num_groups = ARRAY_SIZE(emif1grps),
916 .mask = emif1_mask,
917 },
918 {
919 .name = "uart0",
920 .groups = uart0grps,
921 .num_groups = ARRAY_SIZE(uart0grps),
922 .mask = uart0_mask,
923 },
924 {
925 .name = "mmc0",
926 .groups = mmc0grps,
927 .num_groups = ARRAY_SIZE(mmc0grps),
928 .mask = mmc0_mask,
929 },
930 {
931 .name = "spi0",
932 .groups = spi0grps,
933 .num_groups = ARRAY_SIZE(spi0grps),
934 .mask = spi0_mask,
935 },
936};
937
938static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
939 bool enable)
940{
941 u16 regval, val, mask;
942 int i;
943 const struct u300_pmx_mask *upmx_mask;
944
945 upmx_mask = u300_pmx_functions[selector].mask;
946 for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
947 if (enable)
948 val = upmx_mask->bits;
949 else
950 val = 0;
951
952 mask = upmx_mask->mask;
953 if (mask != 0) {
954 regval = readw(upmx->virtbase + u300_pmx_registers[i]);
955 regval &= ~mask;
956 regval |= val;
957 writew(regval, upmx->virtbase + u300_pmx_registers[i]);
958 }
959 upmx_mask++;
960 }
961}
962
963static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
964 unsigned group)
965{
966 struct u300_pmx *upmx;
967
968 /* There is nothing to do with the power pins */
969 if (selector == 0)
970 return 0;
971
972 upmx = pinctrl_dev_get_drvdata(pctldev);
973 u300_pmx_endisable(upmx, selector, true);
974
975 return 0;
976}
977
978static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
979 unsigned group)
980{
981 struct u300_pmx *upmx;
982
983 /* There is nothing to do with the power pins */
984 if (selector == 0)
985 return;
986
987 upmx = pinctrl_dev_get_drvdata(pctldev);
988 u300_pmx_endisable(upmx, selector, false);
989}
990
991static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
992{
993 if (selector >= ARRAY_SIZE(u300_pmx_functions))
994 return -EINVAL;
995 return 0;
996}
997
998static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
999 unsigned selector)
1000{
1001 return u300_pmx_functions[selector].name;
1002}
1003
1004static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1005 const char * const **groups,
1006 unsigned * const num_groups)
1007{
1008 *groups = u300_pmx_functions[selector].groups;
1009 *num_groups = u300_pmx_functions[selector].num_groups;
1010 return 0;
1011}
1012
1013static struct pinmux_ops u300_pmx_ops = {
1014 .list_functions = u300_pmx_list_funcs,
1015 .get_function_name = u300_pmx_get_func_name,
1016 .get_function_groups = u300_pmx_get_groups,
1017 .enable = u300_pmx_enable,
1018 .disable = u300_pmx_disable,
1019};
1020
1021/*
1022 * GPIO ranges handled by the application-side COH901XXX GPIO controller
1023 * Very many pins can be converted into GPIO pins, but we only list those
1024 * that are useful in practice to cut down on tables.
1025 */
1026#define U300_GPIO_RANGE(a, b, c) { .name = "COH901XXX", .id = a, .base= a, \
1027 .pin_base = b, .npins = c }
1028
1029static struct pinctrl_gpio_range u300_gpio_ranges[] = {
1030 U300_GPIO_RANGE(10, 426, 1),
1031 U300_GPIO_RANGE(11, 180, 1),
1032 U300_GPIO_RANGE(12, 165, 1), /* MS/MMC card insertion */
1033 U300_GPIO_RANGE(13, 179, 1),
1034 U300_GPIO_RANGE(14, 178, 1),
1035 U300_GPIO_RANGE(16, 194, 1),
1036 U300_GPIO_RANGE(17, 193, 1),
1037 U300_GPIO_RANGE(18, 192, 1),
1038 U300_GPIO_RANGE(19, 191, 1),
1039 U300_GPIO_RANGE(20, 186, 1),
1040 U300_GPIO_RANGE(21, 185, 1),
1041 U300_GPIO_RANGE(22, 184, 1),
1042 U300_GPIO_RANGE(23, 183, 1),
1043 U300_GPIO_RANGE(24, 182, 1),
1044 U300_GPIO_RANGE(25, 181, 1),
1045};
1046
1047static struct pinctrl_desc u300_pmx_desc = {
1048 .name = DRIVER_NAME,
1049 .pins = u300_pads,
1050 .npins = ARRAY_SIZE(u300_pads),
1051 .maxpin = U300_NUM_PADS-1,
1052 .pctlops = &u300_pctrl_ops,
1053 .pmxops = &u300_pmx_ops,
1054 .owner = THIS_MODULE,
1055};
1056
1057static int __init u300_pmx_probe(struct platform_device *pdev)
1058{
1059 struct u300_pmx *upmx;
1060 struct resource *res;
1061 int ret;
1062 int i;
1063
1064 /* Create state holders etc for this driver */
1065 upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1066 if (!upmx)
1067 return -ENOMEM;
1068
1069 upmx->dev = &pdev->dev;
1070
1071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1072 if (!res) {
1073 ret = -ENOENT;
1074 goto out_no_resource;
1075 }
1076 upmx->phybase = res->start;
1077 upmx->physize = resource_size(res);
1078
1079 if (request_mem_region(upmx->phybase, upmx->physize,
1080 DRIVER_NAME) == NULL) {
1081 ret = -ENOMEM;
1082 goto out_no_memregion;
1083 }
1084
1085 upmx->virtbase = ioremap(upmx->phybase, upmx->physize);
1086 if (!upmx->virtbase) {
1087 ret = -ENOMEM;
1088 goto out_no_remap;
1089 }
1090
1091 upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx);
1092 if (!upmx->pctl) {
1093 dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
1094 ret = -EINVAL;
1095 goto out_no_pmx;
1096 }
1097
1098 /* We will handle a range of GPIO pins */
1099 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++)
1100 pinctrl_add_gpio_range(upmx->pctl, &u300_gpio_ranges[i]);
1101
1102 platform_set_drvdata(pdev, upmx);
1103
1104 dev_info(&pdev->dev, "initialized U300 pinmux driver\n");
1105
1106 return 0;
1107
1108out_no_pmx:
1109 iounmap(upmx->virtbase);
1110out_no_remap:
1111 platform_set_drvdata(pdev, NULL);
1112out_no_memregion:
1113 release_mem_region(upmx->phybase, upmx->physize);
1114out_no_resource:
1115 devm_kfree(&pdev->dev, upmx);
1116 return ret;
1117}
1118
1119static int __exit u300_pmx_remove(struct platform_device *pdev)
1120{
1121 struct u300_pmx *upmx = platform_get_drvdata(pdev);
1122 int i;
1123
1124 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++)
1125 pinctrl_remove_gpio_range(upmx->pctl, &u300_gpio_ranges[i]);
1126 pinctrl_unregister(upmx->pctl);
1127 iounmap(upmx->virtbase);
1128 release_mem_region(upmx->phybase, upmx->physize);
1129 platform_set_drvdata(pdev, NULL);
1130 devm_kfree(&pdev->dev, upmx);
1131
1132 return 0;
1133}
1134
1135static struct platform_driver u300_pmx_driver = {
1136 .driver = {
1137 .name = DRIVER_NAME,
1138 .owner = THIS_MODULE,
1139 },
1140 .remove = __exit_p(u300_pmx_remove),
1141};
1142
1143static int __init u300_pmx_init(void)
1144{
1145 return platform_driver_probe(&u300_pmx_driver, u300_pmx_probe);
1146}
1147arch_initcall(u300_pmx_init);
1148
1149static void __exit u300_pmx_exit(void)
1150{
1151 platform_driver_unregister(&u300_pmx_driver);
1152}
1153module_exit(u300_pmx_exit);
1154
1155MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1156MODULE_DESCRIPTION("U300 pin control driver");
1157MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 09:30:36 -0500