pinctrl: sunxi: Add external interrupts support

The port controller IP found in the Allwinner A10 and A13 can use few of
the pins it manage as an interrupt source, called external interrupts in
the datasheet.

The number of these external interrupts are SoCs specific, but the
current upper limit is 32. In order to work, the external interrupts'
pins have to be muxed to a specific function to generate an interrupt.

This patch adds the irqchip and the needed logic to use the PIO
controller as an interrupt controller.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 68 insertions, 0 deletions

diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index e921621059ce..d68047d8f699 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -344,9 +344,31 @@
 #define PULL_PINS_BITS          2
 #define PULL_PINS_MASK          0x03
 
+#define SUNXI_IRQ_NUMBER        32
+
+#define IRQ_CFG_REG             0x200
+#define IRQ_CFG_IRQ_PER_REG             8
+#define IRQ_CFG_IRQ_BITS                4
+#define IRQ_CFG_IRQ_MASK                ((1 << IRQ_CFG_IRQ_BITS) - 1)
+#define IRQ_CTRL_REG            0x210
+#define IRQ_CTRL_IRQ_PER_REG            32
+#define IRQ_CTRL_IRQ_BITS               1
+#define IRQ_CTRL_IRQ_MASK               ((1 << IRQ_CTRL_IRQ_BITS) - 1)
+#define IRQ_STATUS_REG          0x214
+#define IRQ_STATUS_IRQ_PER_REG          32
+#define IRQ_STATUS_IRQ_BITS             1
+#define IRQ_STATUS_IRQ_MASK             ((1 << IRQ_STATUS_IRQ_BITS) - 1)
+
+#define IRQ_EDGE_RISING         0x00
+#define IRQ_EDGE_FALLING        0x01
+#define IRQ_LEVEL_HIGH          0x02
+#define IRQ_LEVEL_LOW           0x03
+#define IRQ_EDGE_BOTH           0x04
+
 struct sunxi_desc_function {
         const char      *name;
         u8              muxval;
+        u8              irqnum;
 };
 
 struct sunxi_desc_pin {
@@ -378,10 +400,13 @@ struct sunxi_pinctrl {
         struct gpio_chip                *chip;
         struct sunxi_pinctrl_desc       *desc;
         struct device                   *dev;
+        struct irq_domain               *domain;
         struct sunxi_pinctrl_function   *functions;
         unsigned                        nfunctions;
         struct sunxi_pinctrl_group      *groups;
         unsigned                        ngroups;
+        int                             irq;
+        int                             irq_array[SUNXI_IRQ_NUMBER];
         struct pinctrl_dev              *pctl_dev;
 };
 
@@ -398,6 +423,13 @@ struct sunxi_pinctrl {
                 .muxval = _val,                                 \
         }
 
+#define SUNXI_FUNCTION_IRQ(_val, _irq)                          \
+        {                                                       \
+                .name = "irq",                                  \
+                .muxval = _val,                                 \
+                .irqnum = _irq,                                 \
+        }
+
 /*
  * The sunXi PIO registers are organized as is:
  * 0x00 - 0x0c  Muxing values.
@@ -475,4 +507,40 @@ static inline u32 sunxi_pull_offset(u16 pin)
         return pin_num * PULL_PINS_BITS;
 }
 
+static inline u32 sunxi_irq_cfg_reg(u16 irq)
+{
+        u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
+        return reg + IRQ_CFG_REG;
+}
+
+static inline u32 sunxi_irq_cfg_offset(u16 irq)
+{
+        u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
+        return irq_num * IRQ_CFG_IRQ_BITS;
+}
+
+static inline u32 sunxi_irq_ctrl_reg(u16 irq)
+{
+        u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
+        return reg + IRQ_CTRL_REG;
+}
+
+static inline u32 sunxi_irq_ctrl_offset(u16 irq)
+{
+        u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
+        return irq_num * IRQ_CTRL_IRQ_BITS;
+}
+
+static inline u32 sunxi_irq_status_reg(u16 irq)
+{
+        u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
+        return reg + IRQ_STATUS_REG;
+}
+
+static inline u32 sunxi_irq_status_offset(u16 irq)
+{
+        u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
+        return irq_num * IRQ_STATUS_IRQ_BITS;
+}
+
 #endif /* __PINCTRL_SUNXI_H */