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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-03-06 10:12:44 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-03-07 03:02:34 -0500
commitb5f50bf923edfb1ab1dc3620db90989d5a9dafa5 (patch)
tree3f383c537f410a884a665dc63087e0441d1806e4 /drivers/pinctrl/pinctrl-sunxi.c
parenta7bbdd7f8065b97108830662b31c18fc67449c87 (diff)
pinctrl: sunxi: Add Allwinner A10 pin functions
The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-sunxi.c')
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c733
1 files changed, 571 insertions, 162 deletions
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 46b8f2d4f0a5..74f6d59790fe 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -30,482 +30,856 @@
30static const struct sunxi_desc_pin sun4i_a10_pins[] = { 30static const struct sunxi_desc_pin sun4i_a10_pins[] = {
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
32 SUNXI_FUNCTION(0x0, "gpio_in"), 32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out")), 33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
36 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
35 SUNXI_FUNCTION(0x0, "gpio_in"), 38 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out")), 39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
42 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
38 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out")), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */
47 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
48 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 49 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
41 SUNXI_FUNCTION(0x0, "gpio_in"), 50 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out")), 51 SUNXI_FUNCTION(0x1, "gpio_out"),
52 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */
53 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
54 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 55 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"), 56 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out")), 57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */
59 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 60 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
47 SUNXI_FUNCTION(0x0, "gpio_in"), 61 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out")), 62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */
64 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
49 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 65 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
50 SUNXI_FUNCTION(0x0, "gpio_in"), 66 SUNXI_FUNCTION(0x0, "gpio_in"),
51 SUNXI_FUNCTION(0x1, "gpio_out")), 67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */
69 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 70 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
53 SUNXI_FUNCTION(0x0, "gpio_in"), 71 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out")), 72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */
74 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 75 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
56 SUNXI_FUNCTION(0x0, "gpio_in"), 76 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out")), 77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */
79 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 80 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
59 SUNXI_FUNCTION(0x0, "gpio_in"), 81 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out")), 82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */
84 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 85 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
62 SUNXI_FUNCTION(0x0, "gpio_in"), 86 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"), 87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */
64 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 89 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 90 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
66 SUNXI_FUNCTION(0x0, "gpio_in"), 91 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"), 92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */
68 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 94 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
69 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
70 SUNXI_FUNCTION(0x0, "gpio_in"), 96 SUNXI_FUNCTION(0x0, "gpio_in"),
71 SUNXI_FUNCTION(0x1, "gpio_out"), 97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */
99 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
72 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 100 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
74 SUNXI_FUNCTION(0x0, "gpio_in"), 102 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"), 103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */
105 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
76 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 106 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
78 SUNXI_FUNCTION(0x0, "gpio_in"), 108 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"), 109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */
111 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
80 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 112 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
82 SUNXI_FUNCTION(0x0, "gpio_in"), 114 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"), 115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */
117 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
84 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 118 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
86 SUNXI_FUNCTION(0x0, "gpio_in"), 120 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"), 121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */
123 SUNXI_FUNCTION(0x3, "can"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 124 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 125 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
90 SUNXI_FUNCTION(0x0, "gpio_in"), 126 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 127 SUNXI_FUNCTION(0x1, "gpio_out"),
128 SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */
129 SUNXI_FUNCTION(0x3, "can"), /* RX */
92 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 130 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
93 /* Hole */ 131 /* Hole */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
95 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out")), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
97 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
98 SUNXI_FUNCTION(0x0, "gpio_in"), 137 SUNXI_FUNCTION(0x0, "gpio_in"),
99 SUNXI_FUNCTION(0x1, "gpio_out")), 138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
101 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out")), 142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 144 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
104 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out")), 146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
107 SUNXI_FUNCTION(0x0, "gpio_in"), 149 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out")), 150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 152 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
110 SUNXI_FUNCTION(0x0, "gpio_in"), 153 SUNXI_FUNCTION(0x0, "gpio_in"),
111 SUNXI_FUNCTION(0x1, "gpio_out")), 154 SUNXI_FUNCTION(0x1, "gpio_out"),
155 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
156 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
113 SUNXI_FUNCTION(0x0, "gpio_in"), 158 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out")), 159 SUNXI_FUNCTION(0x1, "gpio_out"),
160 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
161 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 162 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
116 SUNXI_FUNCTION(0x0, "gpio_in"), 163 SUNXI_FUNCTION(0x0, "gpio_in"),
117 SUNXI_FUNCTION(0x1, "gpio_out")), 164 SUNXI_FUNCTION(0x1, "gpio_out"),
165 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
166 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 167 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
119 SUNXI_FUNCTION(0x0, "gpio_in"), 168 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out")), 169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
171 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
122 SUNXI_FUNCTION(0x0, "gpio_in"), 173 SUNXI_FUNCTION(0x0, "gpio_in"),
123 SUNXI_FUNCTION(0x1, "gpio_out")), 174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 176 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
125 SUNXI_FUNCTION(0x0, "gpio_in"), 177 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out")), 178 SUNXI_FUNCTION(0x1, "gpio_out"),
179 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 180 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
128 SUNXI_FUNCTION(0x0, "gpio_in"), 181 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out")), 182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
131 SUNXI_FUNCTION(0x0, "gpio_in"), 185 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out")), 186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
188 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 189 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
134 SUNXI_FUNCTION(0x0, "gpio_in"), 190 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out")), 191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
137 SUNXI_FUNCTION(0x0, "gpio_in"), 194 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out")), 195 SUNXI_FUNCTION(0x1, "gpio_out"),
196 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
197 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 198 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
140 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out")), 200 SUNXI_FUNCTION(0x1, "gpio_out"),
201 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
202 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
143 SUNXI_FUNCTION(0x0, "gpio_in"), 204 SUNXI_FUNCTION(0x0, "gpio_in"),
144 SUNXI_FUNCTION(0x1, "gpio_out")), 205 SUNXI_FUNCTION(0x1, "gpio_out"),
206 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
207 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
146 SUNXI_FUNCTION(0x0, "gpio_in"), 209 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out")), 210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
212 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
149 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out")), 215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
151 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
152 SUNXI_FUNCTION(0x0, "gpio_in"), 218 SUNXI_FUNCTION(0x0, "gpio_in"),
153 SUNXI_FUNCTION(0x1, "gpio_out")), 219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 221 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
155 SUNXI_FUNCTION(0x0, "gpio_in"), 222 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out")), 223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 225 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
158 SUNXI_FUNCTION(0x0, "gpio_in"), 226 SUNXI_FUNCTION(0x0, "gpio_in"),
159 SUNXI_FUNCTION(0x1, "gpio_out")), 227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 229 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
161 SUNXI_FUNCTION(0x0, "gpio_in"), 230 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"), 231 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "uart0")), /* TX */ 232 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
233 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 234 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
165 SUNXI_FUNCTION(0x0, "gpio_in"), 235 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"), 236 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "uart0")), /* RX */ 237 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
238 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
168 /* Hole */ 239 /* Hole */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
170 SUNXI_FUNCTION(0x0, "gpio_in"), 241 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out")), 242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
173 SUNXI_FUNCTION(0x0, "gpio_in"), 246 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out")), 247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
249 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
176 SUNXI_FUNCTION(0x0, "gpio_in"), 251 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out")), 252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
254 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
178 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
179 SUNXI_FUNCTION(0x0, "gpio_in"), 256 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out")), 257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
182 SUNXI_FUNCTION(0x0, "gpio_in"), 260 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out")), 261 SUNXI_FUNCTION(0x1, "gpio_out"),
262 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 263 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
185 SUNXI_FUNCTION(0x0, "gpio_in"), 264 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out")), 265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
188 SUNXI_FUNCTION(0x0, "gpio_in"), 268 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out")), 269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
271 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
191 SUNXI_FUNCTION(0x0, "gpio_in"), 273 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out")), 274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
276 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 277 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
194 SUNXI_FUNCTION(0x0, "gpio_in"), 278 SUNXI_FUNCTION(0x0, "gpio_in"),
195 SUNXI_FUNCTION(0x1, "gpio_out")), 279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
281 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 282 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
197 SUNXI_FUNCTION(0x0, "gpio_in"), 283 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out")), 284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
286 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
200 SUNXI_FUNCTION(0x0, "gpio_in"), 288 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out")), 289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
291 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
203 SUNXI_FUNCTION(0x0, "gpio_in"), 293 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out")), 294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
296 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
206 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out")), 299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
209 SUNXI_FUNCTION(0x0, "gpio_in"), 302 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out")), 303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
212 SUNXI_FUNCTION(0x0, "gpio_in"), 306 SUNXI_FUNCTION(0x0, "gpio_in"),
213 SUNXI_FUNCTION(0x1, "gpio_out")), 307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
214 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
215 SUNXI_FUNCTION(0x0, "gpio_in"), 310 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out")), 311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
218 SUNXI_FUNCTION(0x0, "gpio_in"), 314 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out")), 315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
221 SUNXI_FUNCTION(0x0, "gpio_in"), 318 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out")), 319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
223 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 321 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
224 SUNXI_FUNCTION(0x0, "gpio_in"), 322 SUNXI_FUNCTION(0x0, "gpio_in"),
225 SUNXI_FUNCTION(0x1, "gpio_out")), 323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 325 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
227 SUNXI_FUNCTION(0x0, "gpio_in"), 326 SUNXI_FUNCTION(0x0, "gpio_in"),
228 SUNXI_FUNCTION(0x1, "gpio_out")), 327 SUNXI_FUNCTION(0x1, "gpio_out"),
328 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
329 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
230 SUNXI_FUNCTION(0x0, "gpio_in"), 331 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out")), 332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
334 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
233 SUNXI_FUNCTION(0x0, "gpio_in"), 336 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out")), 337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
339 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
236 SUNXI_FUNCTION(0x0, "gpio_in"), 341 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out")), 342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
344 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
239 SUNXI_FUNCTION(0x0, "gpio_in"), 346 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out")), 347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 349 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
242 SUNXI_FUNCTION(0x0, "gpio_in"), 350 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out")), 351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
244 /* Hole */ 353 /* Hole */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
246 SUNXI_FUNCTION(0x0, "gpio_in"), 355 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out")), 356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
358 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 359 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
249 SUNXI_FUNCTION(0x0, "gpio_in"), 360 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out")), 361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
363 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 364 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
252 SUNXI_FUNCTION(0x0, "gpio_in"), 365 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out")), 366 SUNXI_FUNCTION(0x1, "gpio_out"),
367 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
368 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
255 SUNXI_FUNCTION(0x0, "gpio_in"), 370 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out")), 371 SUNXI_FUNCTION(0x1, "gpio_out"),
372 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
373 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 374 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
258 SUNXI_FUNCTION(0x0, "gpio_in"), 375 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out")), 376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
378 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 379 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
261 SUNXI_FUNCTION(0x0, "gpio_in"), 380 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out")), 381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
383 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 384 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
264 SUNXI_FUNCTION(0x0, "gpio_in"), 385 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out")), 386 SUNXI_FUNCTION(0x1, "gpio_out"),
387 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
388 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 389 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
267 SUNXI_FUNCTION(0x0, "gpio_in"), 390 SUNXI_FUNCTION(0x0, "gpio_in"),
268 SUNXI_FUNCTION(0x1, "gpio_out")), 391 SUNXI_FUNCTION(0x1, "gpio_out"),
392 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
393 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 394 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
270 SUNXI_FUNCTION(0x0, "gpio_in"), 395 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out")), 396 SUNXI_FUNCTION(0x1, "gpio_out"),
397 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
398 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 399 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
273 SUNXI_FUNCTION(0x0, "gpio_in"), 400 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out")), 401 SUNXI_FUNCTION(0x1, "gpio_out"),
402 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
403 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 404 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
276 SUNXI_FUNCTION(0x0, "gpio_in"), 405 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out")), 406 SUNXI_FUNCTION(0x1, "gpio_out"),
407 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
408 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 409 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
279 SUNXI_FUNCTION(0x0, "gpio_in"), 410 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out")), 411 SUNXI_FUNCTION(0x1, "gpio_out"),
412 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
413 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 414 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
282 SUNXI_FUNCTION(0x0, "gpio_in"), 415 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out")), 416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
418 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 419 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
285 SUNXI_FUNCTION(0x0, "gpio_in"), 420 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out")), 421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
423 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 424 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
288 SUNXI_FUNCTION(0x0, "gpio_in"), 425 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out")), 426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
428 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 429 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
291 SUNXI_FUNCTION(0x0, "gpio_in"), 430 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out")), 431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
433 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 434 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
294 SUNXI_FUNCTION(0x0, "gpio_in"), 435 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out")), 436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
438 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
296 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 439 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
297 SUNXI_FUNCTION(0x0, "gpio_in"), 440 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out")), 441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
443 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 444 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
300 SUNXI_FUNCTION(0x0, "gpio_in"), 445 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out")), 446 SUNXI_FUNCTION(0x1, "gpio_out"),
447 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
448 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
303 SUNXI_FUNCTION(0x0, "gpio_in"), 450 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out")), 451 SUNXI_FUNCTION(0x1, "gpio_out"),
452 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
453 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 454 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
306 SUNXI_FUNCTION(0x0, "gpio_in"), 455 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out")), 456 SUNXI_FUNCTION(0x1, "gpio_out"),
457 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
458 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 459 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
309 SUNXI_FUNCTION(0x0, "gpio_in"), 460 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out")), 461 SUNXI_FUNCTION(0x1, "gpio_out"),
462 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
463 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 464 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
312 SUNXI_FUNCTION(0x0, "gpio_in"), 465 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out")), 466 SUNXI_FUNCTION(0x1, "gpio_out"),
467 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
468 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 469 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
315 SUNXI_FUNCTION(0x0, "gpio_in"), 470 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out")), 471 SUNXI_FUNCTION(0x1, "gpio_out"),
472 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
473 SUNXI_FUNCTION(0x3, "sim")), /* DET */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
318 SUNXI_FUNCTION(0x0, "gpio_in"), 475 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out")), 476 SUNXI_FUNCTION(0x1, "gpio_out"),
477 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
478 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
321 SUNXI_FUNCTION(0x0, "gpio_in"), 480 SUNXI_FUNCTION(0x0, "gpio_in"),
322 SUNXI_FUNCTION(0x1, "gpio_out")), 481 SUNXI_FUNCTION(0x1, "gpio_out"),
482 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
483 SUNXI_FUNCTION(0x3, "sim")), /* RST */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 484 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
324 SUNXI_FUNCTION(0x0, "gpio_in"), 485 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out")), 486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
488 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 489 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
327 SUNXI_FUNCTION(0x0, "gpio_in"), 490 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out")), 491 SUNXI_FUNCTION(0x1, "gpio_out"),
492 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
493 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
329 /* Hole */ 494 /* Hole */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 495 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
331 SUNXI_FUNCTION(0x0, "gpio_in"), 496 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out")), 497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
499 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 500 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
334 SUNXI_FUNCTION(0x0, "gpio_in"), 501 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out")), 502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
504 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 505 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
337 SUNXI_FUNCTION(0x0, "gpio_in"), 506 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out")), 507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
509 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
340 SUNXI_FUNCTION(0x0, "gpio_in"), 511 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out")), 512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
514 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
343 SUNXI_FUNCTION(0x0, "gpio_in"), 516 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out")), 517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
519 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 520 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
346 SUNXI_FUNCTION(0x0, "gpio_in"), 521 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out")), 522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
524 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
525 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
348 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
349 SUNXI_FUNCTION(0x0, "gpio_in"), 527 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out")), 528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
530 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
352 SUNXI_FUNCTION(0x0, "gpio_in"), 532 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out")), 533 SUNXI_FUNCTION(0x1, "gpio_out"),
534 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
535 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
355 SUNXI_FUNCTION(0x0, "gpio_in"), 537 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out")), 538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
540 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
358 SUNXI_FUNCTION(0x0, "gpio_in"), 542 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out")), 543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
545 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
361 SUNXI_FUNCTION(0x0, "gpio_in"), 547 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out")), 548 SUNXI_FUNCTION(0x1, "gpio_out"),
549 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
550 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
364 SUNXI_FUNCTION(0x0, "gpio_in"), 552 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out")), 553 SUNXI_FUNCTION(0x1, "gpio_out"),
554 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
555 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
366 /* Hole */ 556 /* Hole */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 557 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
368 SUNXI_FUNCTION(0x0, "gpio_in"), 558 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out")), 559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
561 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 562 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
371 SUNXI_FUNCTION(0x0, "gpio_in"), 563 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out")), 564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
566 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
374 SUNXI_FUNCTION(0x0, "gpio_in"), 568 SUNXI_FUNCTION(0x0, "gpio_in"),
375 SUNXI_FUNCTION(0x1, "gpio_out"), 569 SUNXI_FUNCTION(0x1, "gpio_out"),
570 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
376 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 571 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 572 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
378 SUNXI_FUNCTION(0x0, "gpio_in"), 573 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out")), 574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
576 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
381 SUNXI_FUNCTION(0x0, "gpio_in"), 578 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"), 579 SUNXI_FUNCTION(0x1, "gpio_out"),
580 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
383 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 581 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
384 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
385 SUNXI_FUNCTION(0x0, "gpio_in"), 583 SUNXI_FUNCTION(0x0, "gpio_in"),
386 SUNXI_FUNCTION(0x1, "gpio_out")), 584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
586 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
387 /* Hole */ 587 /* Hole */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
389 SUNXI_FUNCTION(0x0, "gpio_in"), 589 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out")), 590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
592 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
392 SUNXI_FUNCTION(0x0, "gpio_in"), 595 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out")), 596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
598 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
394 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
395 SUNXI_FUNCTION(0x0, "gpio_in"), 601 SUNXI_FUNCTION(0x0, "gpio_in"),
396 SUNXI_FUNCTION(0x1, "gpio_out")), 602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
604 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
605 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
398 SUNXI_FUNCTION(0x0, "gpio_in"), 607 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out")), 608 SUNXI_FUNCTION(0x1, "gpio_out"),
609 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
610 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
611 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
401 SUNXI_FUNCTION(0x0, "gpio_in"), 613 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out")), 614 SUNXI_FUNCTION(0x1, "gpio_out"),
615 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
616 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
617 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
618 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
404 SUNXI_FUNCTION(0x0, "gpio_in"), 620 SUNXI_FUNCTION(0x0, "gpio_in"),
405 SUNXI_FUNCTION(0x1, "gpio_out")), 621 SUNXI_FUNCTION(0x1, "gpio_out"),
622 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
623 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
624 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
625 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
406 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
407 SUNXI_FUNCTION(0x0, "gpio_in"), 627 SUNXI_FUNCTION(0x0, "gpio_in"),
408 SUNXI_FUNCTION(0x1, "gpio_out")), 628 SUNXI_FUNCTION(0x1, "gpio_out"),
629 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
630 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
631 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
632 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
409 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 633 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
410 SUNXI_FUNCTION(0x0, "gpio_in"), 634 SUNXI_FUNCTION(0x0, "gpio_in"),
411 SUNXI_FUNCTION(0x1, "gpio_out")), 635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
637 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
638 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
639 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
413 SUNXI_FUNCTION(0x0, "gpio_in"), 641 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out")), 642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
644 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
645 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
646 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 647 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
416 SUNXI_FUNCTION(0x0, "gpio_in"), 648 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out")), 649 SUNXI_FUNCTION(0x1, "gpio_out"),
650 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
651 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
652 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
653 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
419 SUNXI_FUNCTION(0x0, "gpio_in"), 655 SUNXI_FUNCTION(0x0, "gpio_in"),
420 SUNXI_FUNCTION(0x1, "gpio_out")), 656 SUNXI_FUNCTION(0x1, "gpio_out"),
657 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
658 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
659 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
660 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 661 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
422 SUNXI_FUNCTION(0x0, "gpio_in"), 662 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out")), 663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
665 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
666 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
667 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
424 /* Hole */ 668 /* Hole */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
426 SUNXI_FUNCTION(0x0, "gpio_in"), 670 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out")), 671 SUNXI_FUNCTION(0x1, "gpio_out"),
672 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
673 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
674 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
675 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 676 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
429 SUNXI_FUNCTION(0x0, "gpio_in"), 677 SUNXI_FUNCTION(0x0, "gpio_in"),
430 SUNXI_FUNCTION(0x1, "gpio_out")), 678 SUNXI_FUNCTION(0x1, "gpio_out"),
679 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
680 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
681 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
682 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
432 SUNXI_FUNCTION(0x0, "gpio_in"), 684 SUNXI_FUNCTION(0x0, "gpio_in"),
433 SUNXI_FUNCTION(0x1, "gpio_out")), 685 SUNXI_FUNCTION(0x1, "gpio_out"),
686 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
687 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
688 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
689 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 690 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
435 SUNXI_FUNCTION(0x0, "gpio_in"), 691 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out")), 692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
694 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
695 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
438 SUNXI_FUNCTION(0x0, "gpio_in"), 698 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out")), 699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
703 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
441 SUNXI_FUNCTION(0x0, "gpio_in"), 705 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out")), 706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
708 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
709 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
710 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
444 SUNXI_FUNCTION(0x0, "gpio_in"), 712 SUNXI_FUNCTION(0x0, "gpio_in"),
445 SUNXI_FUNCTION(0x1, "gpio_out")), 713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
715 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
716 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
717 SUNXI_FUNCTION(0x5, "ms"), /* BS */
718 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
447 SUNXI_FUNCTION(0x0, "gpio_in"), 720 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out")), 721 SUNXI_FUNCTION(0x1, "gpio_out"),
722 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
723 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
724 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
725 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
726 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 727 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
450 SUNXI_FUNCTION(0x0, "gpio_in"), 728 SUNXI_FUNCTION(0x0, "gpio_in"),
451 SUNXI_FUNCTION(0x1, "gpio_out")), 729 SUNXI_FUNCTION(0x1, "gpio_out"),
730 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
731 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
732 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
733 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
734 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 735 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
453 SUNXI_FUNCTION(0x0, "gpio_in"), 736 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out")), 737 SUNXI_FUNCTION(0x1, "gpio_out"),
738 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
739 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
740 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
741 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
742 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 743 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
456 SUNXI_FUNCTION(0x0, "gpio_in"), 744 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out")), 745 SUNXI_FUNCTION(0x1, "gpio_out"),
746 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
747 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
748 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
749 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
750 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 751 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
459 SUNXI_FUNCTION(0x0, "gpio_in"), 752 SUNXI_FUNCTION(0x0, "gpio_in"),
460 SUNXI_FUNCTION(0x1, "gpio_out")), 753 SUNXI_FUNCTION(0x1, "gpio_out"),
754 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
755 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
756 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
757 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
462 SUNXI_FUNCTION(0x0, "gpio_in"), 760 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out")), 761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
464 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 766 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
465 SUNXI_FUNCTION(0x0, "gpio_in"), 767 SUNXI_FUNCTION(0x0, "gpio_in"),
466 SUNXI_FUNCTION(0x1, "gpio_out")), 768 SUNXI_FUNCTION(0x1, "gpio_out"),
769 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
770 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
771 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
772 SUNXI_FUNCTION(0x5, "sim"), /* RST */
773 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 774 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
468 SUNXI_FUNCTION(0x0, "gpio_in"), 775 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out")), 776 SUNXI_FUNCTION(0x1, "gpio_out"),
777 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
778 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
779 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
780 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
781 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 782 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
471 SUNXI_FUNCTION(0x0, "gpio_in"), 783 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out")), 784 SUNXI_FUNCTION(0x1, "gpio_out"),
785 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
786 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
787 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
788 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
789 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
473 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 790 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
474 SUNXI_FUNCTION(0x0, "gpio_in"), 791 SUNXI_FUNCTION(0x0, "gpio_in"),
475 SUNXI_FUNCTION(0x1, "gpio_out")), 792 SUNXI_FUNCTION(0x1, "gpio_out"),
793 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
794 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
795 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
796 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
477 SUNXI_FUNCTION(0x0, "gpio_in"), 798 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out")), 799 SUNXI_FUNCTION(0x1, "gpio_out"),
800 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
801 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
802 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
803 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
804 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 805 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
480 SUNXI_FUNCTION(0x0, "gpio_in"), 806 SUNXI_FUNCTION(0x0, "gpio_in"),
481 SUNXI_FUNCTION(0x1, "gpio_out")), 807 SUNXI_FUNCTION(0x1, "gpio_out"),
808 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
809 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
810 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
811 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
812 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
483 SUNXI_FUNCTION(0x0, "gpio_in"), 814 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out")), 815 SUNXI_FUNCTION(0x1, "gpio_out"),
816 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
817 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
818 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
819 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
820 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 821 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
486 SUNXI_FUNCTION(0x0, "gpio_in"), 822 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out")), 823 SUNXI_FUNCTION(0x1, "gpio_out"),
824 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
825 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
826 SUNXI_FUNCTION(0x4, "can"), /* TX */
827 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 828 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
489 SUNXI_FUNCTION(0x0, "gpio_in"), 829 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out")), 830 SUNXI_FUNCTION(0x1, "gpio_out"),
831 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
832 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
833 SUNXI_FUNCTION(0x4, "can"), /* RX */
834 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
492 SUNXI_FUNCTION(0x0, "gpio_in"), 836 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out")), 837 SUNXI_FUNCTION(0x1, "gpio_out"),
838 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
839 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
840 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
841 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
842 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
494 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
495 SUNXI_FUNCTION(0x0, "gpio_in"), 844 SUNXI_FUNCTION(0x0, "gpio_in"),
496 SUNXI_FUNCTION(0x1, "gpio_out")), 845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
847 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
848 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
849 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
850 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
498 SUNXI_FUNCTION(0x0, "gpio_in"), 852 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out")), 853 SUNXI_FUNCTION(0x1, "gpio_out"),
854 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
855 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
856 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
857 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
858 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
501 SUNXI_FUNCTION(0x0, "gpio_in"), 860 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out")), 861 SUNXI_FUNCTION(0x1, "gpio_out"),
862 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
863 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
864 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
865 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
866 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
504 SUNXI_FUNCTION(0x0, "gpio_in"), 868 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out")), 869 SUNXI_FUNCTION(0x1, "gpio_out"),
870 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
871 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
872 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
873 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
874 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 875 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
507 SUNXI_FUNCTION(0x0, "gpio_in"), 876 SUNXI_FUNCTION(0x0, "gpio_in"),
508 SUNXI_FUNCTION(0x1, "gpio_out")), 877 SUNXI_FUNCTION(0x1, "gpio_out"),
878 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
879 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
880 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
881 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
882 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
509 /* Hole */ 883 /* Hole */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 884 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
511 SUNXI_FUNCTION(0x0, "gpio_in"), 885 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -518,61 +892,96 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
518 SUNXI_FUNCTION(0x1, "gpio_out")), 892 SUNXI_FUNCTION(0x1, "gpio_out")),
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 893 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
520 SUNXI_FUNCTION(0x0, "gpio_in"), 894 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out")), 895 SUNXI_FUNCTION(0x1, "gpio_out"),
896 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
522 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
523 SUNXI_FUNCTION(0x0, "gpio_in"), 898 SUNXI_FUNCTION(0x0, "gpio_in"),
524 SUNXI_FUNCTION(0x1, "gpio_out")), 899 SUNXI_FUNCTION(0x1, "gpio_out"),
900 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
525 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
526 SUNXI_FUNCTION(0x0, "gpio_in"), 902 SUNXI_FUNCTION(0x0, "gpio_in"),
527 SUNXI_FUNCTION(0x1, "gpio_out")), 903 SUNXI_FUNCTION(0x1, "gpio_out"),
904 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
528 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 905 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
529 SUNXI_FUNCTION(0x0, "gpio_in"), 906 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out")), 907 SUNXI_FUNCTION(0x1, "gpio_out"),
908 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 909 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
532 SUNXI_FUNCTION(0x0, "gpio_in"), 910 SUNXI_FUNCTION(0x0, "gpio_in"),
533 SUNXI_FUNCTION(0x1, "gpio_out")), 911 SUNXI_FUNCTION(0x1, "gpio_out"),
912 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 913 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
535 SUNXI_FUNCTION(0x0, "gpio_in"), 914 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out")), 915 SUNXI_FUNCTION(0x1, "gpio_out"),
916 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
537 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 917 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
538 SUNXI_FUNCTION(0x0, "gpio_in"), 918 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out")), 919 SUNXI_FUNCTION(0x1, "gpio_out"),
920 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
541 SUNXI_FUNCTION(0x0, "gpio_in"), 922 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out")), 923 SUNXI_FUNCTION(0x1, "gpio_out"),
924 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
925 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
543 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
544 SUNXI_FUNCTION(0x0, "gpio_in"), 927 SUNXI_FUNCTION(0x0, "gpio_in"),
545 SUNXI_FUNCTION(0x1, "gpio_out")), 928 SUNXI_FUNCTION(0x1, "gpio_out"),
929 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
930 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
547 SUNXI_FUNCTION(0x0, "gpio_in"), 932 SUNXI_FUNCTION(0x0, "gpio_in"),
548 SUNXI_FUNCTION(0x1, "gpio_out")), 933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
935 SUNXI_FUNCTION(0x3, "uart6")), /* TX */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
550 SUNXI_FUNCTION(0x0, "gpio_in"), 937 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out")), 938 SUNXI_FUNCTION(0x1, "gpio_out"),
939 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
940 SUNXI_FUNCTION(0x3, "uart6")), /* RX */
552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 941 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
553 SUNXI_FUNCTION(0x0, "gpio_in"), 942 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out")), 943 SUNXI_FUNCTION(0x1, "gpio_out"),
944 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
945 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
946 SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 947 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
556 SUNXI_FUNCTION(0x0, "gpio_in"), 948 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out")), 949 SUNXI_FUNCTION(0x1, "gpio_out"),
950 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
951 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
952 SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 953 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
559 SUNXI_FUNCTION(0x0, "gpio_in"), 954 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out")), 955 SUNXI_FUNCTION(0x1, "gpio_out"),
956 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
957 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 958 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
562 SUNXI_FUNCTION(0x0, "gpio_in"), 959 SUNXI_FUNCTION(0x0, "gpio_in"),
563 SUNXI_FUNCTION(0x1, "gpio_out")), 960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
962 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 963 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
565 SUNXI_FUNCTION(0x0, "gpio_in"), 964 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out")), 965 SUNXI_FUNCTION(0x1, "gpio_out"),
966 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
967 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 968 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
568 SUNXI_FUNCTION(0x0, "gpio_in"), 969 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out")), 970 SUNXI_FUNCTION(0x1, "gpio_out"),
971 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
972 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 973 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
571 SUNXI_FUNCTION(0x0, "gpio_in"), 974 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out")), 975 SUNXI_FUNCTION(0x1, "gpio_out"),
976 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
977 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
978 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 979 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
574 SUNXI_FUNCTION(0x0, "gpio_in"), 980 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out")), 981 SUNXI_FUNCTION(0x1, "gpio_out"),
982 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
983 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
984 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
576}; 985};
577 986
578static const struct sunxi_desc_pin sun5i_a13_pins[] = { 987static const struct sunxi_desc_pin sun5i_a13_pins[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 22:35:16 -0400