Merge tag 'v3.11-rc7' into devel

Merged in this to avoid conflicts with the big locking fixes
from upstream.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:
	drivers/pinctrl/pinctrl-sunxi.c

1 files changed, 53 insertions, 5 deletions

diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 8dbd465b01d3..532202bbfc33 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -279,11 +279,14 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 {
         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
         struct sunxi_pinctrl_group *g = &pctl->groups[group];
+        unsigned long flags;
         u32 val, mask;
         u16 strength;
         u8 dlevel;
         int i;
 
+        spin_lock_irqsave(&pctl->lock, flags);
+
         for (i = 0; i < num_configs; i++) {
                 switch (pinconf_to_config_param(configs[i])) {
                 case PIN_CONFIG_DRIVE_STRENGTH:
@@ -319,11 +322,12 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
                 default:
                         break;
                 }
-
                 /* cache the config value */
                 g->config = configs[i];
         } /* for each config */
 
+        spin_unlock_irqrestore(&pctl->lock, flags);
+
         return 0;
 }
 
@@ -365,11 +369,17 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
                                  u8 config)
 {
         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        unsigned long flags;
+        u32 val, mask;
+
+        spin_lock_irqsave(&pctl->lock, flags);
 
-        u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
-        u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
+        val = readl(pctl->membase + sunxi_mux_reg(pin));
+        mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
         writel((val & ~mask) | config << sunxi_mux_offset(pin),
                 pctl->membase + sunxi_mux_reg(pin));
+
+        spin_unlock_irqrestore(&pctl->lock, flags);
 }
 
 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
@@ -469,8 +479,21 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
         u32 reg = sunxi_data_reg(offset);
         u8 index = sunxi_data_offset(offset);
+        unsigned long flags;
+        u32 regval;
+
+        spin_lock_irqsave(&pctl->lock, flags);
+
+        regval = readl(pctl->membase + reg);
+
+        if (value)
+                regval |= BIT(index);
+        else
+                regval &= ~(BIT(index));
 
-        writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
+        writel(regval, pctl->membase + reg);
+
+        spin_unlock_irqrestore(&pctl->lock, flags);
 }
 
 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
@@ -531,6 +554,8 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
         u32 reg = sunxi_irq_cfg_reg(d->hwirq);
         u8 index = sunxi_irq_cfg_offset(d->hwirq);
+        unsigned long flags;
+        u32 regval;
         u8 mode;
 
         switch (type) {
@@ -553,7 +578,13 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
                 return -EINVAL;
         }
 
-        writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
+        spin_lock_irqsave(&pctl->lock, flags);
+
+        regval = readl(pctl->membase + reg);
+        regval &= ~IRQ_CFG_IRQ_MASK;
+        writel(regval | (mode << index), pctl->membase + reg);
+
+        spin_unlock_irqrestore(&pctl->lock, flags);
 
         return 0;
 }
@@ -565,14 +596,19 @@ static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
         u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
         u32 status_reg = sunxi_irq_status_reg(d->hwirq);
         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
+        unsigned long flags;
         u32 val;
 
+        spin_lock_irqsave(&pctl->lock, flags);
+
         /* Mask the IRQ */
         val = readl(pctl->membase + ctrl_reg);
         writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
 
         /* Clear the IRQ */
         writel(1 << status_idx, pctl->membase + status_reg);
+
+        spin_unlock_irqrestore(&pctl->lock, flags);
 }
 
 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
@@ -580,11 +616,16 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
+        unsigned long flags;
         u32 val;
 
+        spin_lock_irqsave(&pctl->lock, flags);
+
         /* Mask the IRQ */
         val = readl(pctl->membase + reg);
         writel(val & ~(1 << idx), pctl->membase + reg);
+
+        spin_unlock_irqrestore(&pctl->lock, flags);
 }
 
 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
@@ -593,6 +634,7 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
         struct sunxi_desc_function *func;
         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
+        unsigned long flags;
         u32 val;
 
         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
@@ -602,9 +644,13 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
         /* Change muxing to INT mode */
         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 
+        spin_lock_irqsave(&pctl->lock, flags);
+
         /* Unmask the IRQ */
         val = readl(pctl->membase + reg);
         writel(val | (1 << idx), pctl->membase + reg);
+
+        spin_unlock_irqrestore(&pctl->lock, flags);
 }
 
 static struct irq_chip sunxi_pinctrl_irq_chip = {
@@ -759,6 +805,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
                 return -ENOMEM;
         platform_set_drvdata(pdev, pctl);
 
+        spin_lock_init(&pctl->lock);
+
         pctl->membase = of_iomap(node, 0);
         if (!pctl->membase)
                 return -ENOMEM;