diff options
author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2013-03-27 09:12:33 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2013-04-09 04:47:52 -0400 |
commit | cb51f8e8e3ff0944a5113ec40623240d0664f0ff (patch) | |
tree | 72cd45737fb95bed3710e65a70a7fd91637245d3 /drivers/pinctrl/pinctrl-sunxi.c | |
parent | 8dc3568d5527bfdb61afadea9284814a705b64ff (diff) |
pinctrl: sunxi: Rename wemac functions to emac
The pin functions associated to the ethernet controller were introduced
with the label "wemac", which was the name of the ethernet driver in the
allwinner source tree, while the real name of the IP is actually "emac",
as advertised in several documents including the datasheet.
Since this is part of the device tree bindings, and that these part of
the bindings have not yet be released in a kernel version, it seems like
the good timing to change it and assure consistency.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-sunxi.c')
-rw-r--r-- | drivers/pinctrl/pinctrl-sunxi.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index 617d351a0a44..c52fc2c08732 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c | |||
@@ -32,101 +32,101 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { | |||
32 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, | 32 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, |
33 | SUNXI_FUNCTION(0x0, "gpio_in"), | 33 | SUNXI_FUNCTION(0x0, "gpio_in"), |
34 | SUNXI_FUNCTION(0x1, "gpio_out"), | 34 | SUNXI_FUNCTION(0x1, "gpio_out"), |
35 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */ | 35 | SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ |
36 | SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ | 36 | SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ |
37 | SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ | 37 | SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ |
38 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, | 38 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, |
39 | SUNXI_FUNCTION(0x0, "gpio_in"), | 39 | SUNXI_FUNCTION(0x0, "gpio_in"), |
40 | SUNXI_FUNCTION(0x1, "gpio_out"), | 40 | SUNXI_FUNCTION(0x1, "gpio_out"), |
41 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */ | 41 | SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ |
42 | SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ | 42 | SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ |
43 | SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ | 43 | SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ |
44 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, | 44 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, |
45 | SUNXI_FUNCTION(0x0, "gpio_in"), | 45 | SUNXI_FUNCTION(0x0, "gpio_in"), |
46 | SUNXI_FUNCTION(0x1, "gpio_out"), | 46 | SUNXI_FUNCTION(0x1, "gpio_out"), |
47 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */ | 47 | SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ |
48 | SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ | 48 | SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ |
49 | SUNXI_FUNCTION(0x4, "uart2")), /* TX */ | 49 | SUNXI_FUNCTION(0x4, "uart2")), /* TX */ |
50 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, | 50 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, |
51 | SUNXI_FUNCTION(0x0, "gpio_in"), | 51 | SUNXI_FUNCTION(0x0, "gpio_in"), |
52 | SUNXI_FUNCTION(0x1, "gpio_out"), | 52 | SUNXI_FUNCTION(0x1, "gpio_out"), |
53 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */ | 53 | SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ |
54 | SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ | 54 | SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ |
55 | SUNXI_FUNCTION(0x4, "uart2")), /* RX */ | 55 | SUNXI_FUNCTION(0x4, "uart2")), /* RX */ |
56 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, | 56 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, |
57 | SUNXI_FUNCTION(0x0, "gpio_in"), | 57 | SUNXI_FUNCTION(0x0, "gpio_in"), |
58 | SUNXI_FUNCTION(0x1, "gpio_out"), | 58 | SUNXI_FUNCTION(0x1, "gpio_out"), |
59 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */ | 59 | SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ |
60 | SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ | 60 | SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ |
61 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, | 61 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, |
62 | SUNXI_FUNCTION(0x0, "gpio_in"), | 62 | SUNXI_FUNCTION(0x0, "gpio_in"), |
63 | SUNXI_FUNCTION(0x1, "gpio_out"), | 63 | SUNXI_FUNCTION(0x1, "gpio_out"), |
64 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */ | 64 | SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ |
65 | SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ | 65 | SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ |
66 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, | 66 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, |
67 | SUNXI_FUNCTION(0x0, "gpio_in"), | 67 | SUNXI_FUNCTION(0x0, "gpio_in"), |
68 | SUNXI_FUNCTION(0x1, "gpio_out"), | 68 | SUNXI_FUNCTION(0x1, "gpio_out"), |
69 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */ | 69 | SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ |
70 | SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ | 70 | SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ |
71 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, | 71 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, |
72 | SUNXI_FUNCTION(0x0, "gpio_in"), | 72 | SUNXI_FUNCTION(0x0, "gpio_in"), |
73 | SUNXI_FUNCTION(0x1, "gpio_out"), | 73 | SUNXI_FUNCTION(0x1, "gpio_out"), |
74 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */ | 74 | SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ |
75 | SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ | 75 | SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ |
76 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, | 76 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, |
77 | SUNXI_FUNCTION(0x0, "gpio_in"), | 77 | SUNXI_FUNCTION(0x0, "gpio_in"), |
78 | SUNXI_FUNCTION(0x1, "gpio_out"), | 78 | SUNXI_FUNCTION(0x1, "gpio_out"), |
79 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */ | 79 | SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ |
80 | SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ | 80 | SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ |
81 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, | 81 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, |
82 | SUNXI_FUNCTION(0x0, "gpio_in"), | 82 | SUNXI_FUNCTION(0x0, "gpio_in"), |
83 | SUNXI_FUNCTION(0x1, "gpio_out"), | 83 | SUNXI_FUNCTION(0x1, "gpio_out"), |
84 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */ | 84 | SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ |
85 | SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ | 85 | SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ |
86 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, | 86 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, |
87 | SUNXI_FUNCTION(0x0, "gpio_in"), | 87 | SUNXI_FUNCTION(0x0, "gpio_in"), |
88 | SUNXI_FUNCTION(0x1, "gpio_out"), | 88 | SUNXI_FUNCTION(0x1, "gpio_out"), |
89 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */ | 89 | SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ |
90 | SUNXI_FUNCTION(0x4, "uart1")), /* TX */ | 90 | SUNXI_FUNCTION(0x4, "uart1")), /* TX */ |
91 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, | 91 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, |
92 | SUNXI_FUNCTION(0x0, "gpio_in"), | 92 | SUNXI_FUNCTION(0x0, "gpio_in"), |
93 | SUNXI_FUNCTION(0x1, "gpio_out"), | 93 | SUNXI_FUNCTION(0x1, "gpio_out"), |
94 | SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */ | 94 | SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ |
95 | SUNXI_FUNCTION(0x4, "uart1")), /* RX */ | 95 | SUNXI_FUNCTION(0x4, "uart1")), /* RX */ |
96 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, | 96 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, |
97 | SUNXI_FUNCTION(0x0, "gpio_in"), | 97 | SUNXI_FUNCTION(0x0, "gpio_in"), |
98 | SUNXI_FUNCTION(0x1, "gpio_out"), | 98 | SUNXI_FUNCTION(0x1, "gpio_out"), |
99 | SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */ | 99 | SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ |
100 | SUNXI_FUNCTION(0x3, "uart6"), /* TX */ | 100 | SUNXI_FUNCTION(0x3, "uart6"), /* TX */ |
101 | SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ | 101 | SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ |
102 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, | 102 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, |
103 | SUNXI_FUNCTION(0x0, "gpio_in"), | 103 | SUNXI_FUNCTION(0x0, "gpio_in"), |
104 | SUNXI_FUNCTION(0x1, "gpio_out"), | 104 | SUNXI_FUNCTION(0x1, "gpio_out"), |
105 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */ | 105 | SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ |
106 | SUNXI_FUNCTION(0x3, "uart6"), /* RX */ | 106 | SUNXI_FUNCTION(0x3, "uart6"), /* RX */ |
107 | SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ | 107 | SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ |
108 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, | 108 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, |
109 | SUNXI_FUNCTION(0x0, "gpio_in"), | 109 | SUNXI_FUNCTION(0x0, "gpio_in"), |
110 | SUNXI_FUNCTION(0x1, "gpio_out"), | 110 | SUNXI_FUNCTION(0x1, "gpio_out"), |
111 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */ | 111 | SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ |
112 | SUNXI_FUNCTION(0x3, "uart7"), /* TX */ | 112 | SUNXI_FUNCTION(0x3, "uart7"), /* TX */ |
113 | SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ | 113 | SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ |
114 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, | 114 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, |
115 | SUNXI_FUNCTION(0x0, "gpio_in"), | 115 | SUNXI_FUNCTION(0x0, "gpio_in"), |
116 | SUNXI_FUNCTION(0x1, "gpio_out"), | 116 | SUNXI_FUNCTION(0x1, "gpio_out"), |
117 | SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */ | 117 | SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ |
118 | SUNXI_FUNCTION(0x3, "uart7"), /* RX */ | 118 | SUNXI_FUNCTION(0x3, "uart7"), /* RX */ |
119 | SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ | 119 | SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ |
120 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, | 120 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, |
121 | SUNXI_FUNCTION(0x0, "gpio_in"), | 121 | SUNXI_FUNCTION(0x0, "gpio_in"), |
122 | SUNXI_FUNCTION(0x1, "gpio_out"), | 122 | SUNXI_FUNCTION(0x1, "gpio_out"), |
123 | SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */ | 123 | SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ |
124 | SUNXI_FUNCTION(0x3, "can"), /* TX */ | 124 | SUNXI_FUNCTION(0x3, "can"), /* TX */ |
125 | SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ | 125 | SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ |
126 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, | 126 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, |
127 | SUNXI_FUNCTION(0x0, "gpio_in"), | 127 | SUNXI_FUNCTION(0x0, "gpio_in"), |
128 | SUNXI_FUNCTION(0x1, "gpio_out"), | 128 | SUNXI_FUNCTION(0x1, "gpio_out"), |
129 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */ | 129 | SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ |
130 | SUNXI_FUNCTION(0x3, "can"), /* RX */ | 130 | SUNXI_FUNCTION(0x3, "can"), /* RX */ |
131 | SUNXI_FUNCTION(0x4, "uart1")), /* RING */ | 131 | SUNXI_FUNCTION(0x4, "uart1")), /* RING */ |
132 | /* Hole */ | 132 | /* Hole */ |