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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-06-09 12:36:03 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-06-17 12:18:32 -0400
commit44abb933f7ecfd879794e335da3fb6a0ca87f375 (patch)
treeb191b9200cdefae0e7cbffb64162b694b35b4c9e /drivers/pinctrl/pinctrl-sunxi-pins.h
parent5ca3353bcee929c3b7bbf39f79038842f443f01a (diff)
pinctrl: sunxi: Move the pins definitions to a separate header
It will allow us to have a cleaner separation between the data needed by the driver to work, and the core logic of the driver in itself, and will allow having too much noise in the core driver in the future. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-sunxi-pins.h')
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h1378
1 files changed, 1378 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
new file mode 100644
index 000000000000..92c6b14761b1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -0,0 +1,1378 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_PINS_H
14#define __PINCTRL_SUNXI_PINS_H
15
16#include "pinctrl-sunxi.h"
17
18static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
834 SUNXI_FUNCTION(0x4, "can"), /* TX */
835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
842 SUNXI_FUNCTION(0x4, "can"), /* RX */
843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005};
1006
1007static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1008 /* Hole */
1009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1010 SUNXI_FUNCTION(0x0, "gpio_in"),
1011 SUNXI_FUNCTION(0x1, "gpio_out"),
1012 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1013 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1014 SUNXI_FUNCTION(0x0, "gpio_in"),
1015 SUNXI_FUNCTION(0x1, "gpio_out"),
1016 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1017 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1018 SUNXI_FUNCTION(0x0, "gpio_in"),
1019 SUNXI_FUNCTION(0x1, "gpio_out"),
1020 SUNXI_FUNCTION(0x2, "pwm"),
1021 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1022 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1023 SUNXI_FUNCTION(0x0, "gpio_in"),
1024 SUNXI_FUNCTION(0x1, "gpio_out"),
1025 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1026 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1028 SUNXI_FUNCTION(0x0, "gpio_in"),
1029 SUNXI_FUNCTION(0x1, "gpio_out"),
1030 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1031 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1032 /* Hole */
1033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1034 SUNXI_FUNCTION(0x0, "gpio_in"),
1035 SUNXI_FUNCTION(0x1, "gpio_out"),
1036 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1037 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1038 /* Hole */
1039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1040 SUNXI_FUNCTION(0x0, "gpio_in"),
1041 SUNXI_FUNCTION(0x1, "gpio_out"),
1042 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1043 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1044 SUNXI_FUNCTION(0x0, "gpio_in"),
1045 SUNXI_FUNCTION(0x1, "gpio_out"),
1046 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1047 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1048 SUNXI_FUNCTION(0x0, "gpio_in"),
1049 SUNXI_FUNCTION(0x1, "gpio_out"),
1050 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1052 SUNXI_FUNCTION(0x0, "gpio_in"),
1053 SUNXI_FUNCTION(0x1, "gpio_out"),
1054 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1055 /* Hole */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1060 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1061 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1062 SUNXI_FUNCTION(0x0, "gpio_in"),
1063 SUNXI_FUNCTION(0x1, "gpio_out"),
1064 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1065 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1066 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1067 SUNXI_FUNCTION(0x0, "gpio_in"),
1068 SUNXI_FUNCTION(0x1, "gpio_out"),
1069 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1070 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1071 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1072 SUNXI_FUNCTION(0x0, "gpio_in"),
1073 SUNXI_FUNCTION(0x1, "gpio_out"),
1074 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1075 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1077 SUNXI_FUNCTION(0x0, "gpio_in"),
1078 SUNXI_FUNCTION(0x1, "gpio_out"),
1079 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1080 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1081 SUNXI_FUNCTION(0x0, "gpio_in"),
1082 SUNXI_FUNCTION(0x1, "gpio_out"),
1083 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1088 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1089 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1090 SUNXI_FUNCTION(0x0, "gpio_in"),
1091 SUNXI_FUNCTION(0x1, "gpio_out"),
1092 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1093 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1094 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1095 SUNXI_FUNCTION(0x0, "gpio_in"),
1096 SUNXI_FUNCTION(0x1, "gpio_out"),
1097 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1098 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1099 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1100 SUNXI_FUNCTION(0x0, "gpio_in"),
1101 SUNXI_FUNCTION(0x1, "gpio_out"),
1102 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1103 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1105 SUNXI_FUNCTION(0x0, "gpio_in"),
1106 SUNXI_FUNCTION(0x1, "gpio_out"),
1107 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1108 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1110 SUNXI_FUNCTION(0x0, "gpio_in"),
1111 SUNXI_FUNCTION(0x1, "gpio_out"),
1112 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1113 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1115 SUNXI_FUNCTION(0x0, "gpio_in"),
1116 SUNXI_FUNCTION(0x1, "gpio_out"),
1117 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1118 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1120 SUNXI_FUNCTION(0x0, "gpio_in"),
1121 SUNXI_FUNCTION(0x1, "gpio_out"),
1122 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1123 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1125 SUNXI_FUNCTION(0x0, "gpio_in"),
1126 SUNXI_FUNCTION(0x1, "gpio_out"),
1127 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1128 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1129 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1130 SUNXI_FUNCTION(0x0, "gpio_in"),
1131 SUNXI_FUNCTION(0x1, "gpio_out"),
1132 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1133 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1134 /* Hole */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1139 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1140 /* Hole */
1141 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1142 SUNXI_FUNCTION(0x0, "gpio_in"),
1143 SUNXI_FUNCTION(0x1, "gpio_out"),
1144 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1149 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1150 SUNXI_FUNCTION(0x0, "gpio_in"),
1151 SUNXI_FUNCTION(0x1, "gpio_out"),
1152 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1153 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1154 SUNXI_FUNCTION(0x0, "gpio_in"),
1155 SUNXI_FUNCTION(0x1, "gpio_out"),
1156 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1158 SUNXI_FUNCTION(0x0, "gpio_in"),
1159 SUNXI_FUNCTION(0x1, "gpio_out"),
1160 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1161 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1162 SUNXI_FUNCTION(0x0, "gpio_in"),
1163 SUNXI_FUNCTION(0x1, "gpio_out"),
1164 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1165 /* Hole */
1166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1167 SUNXI_FUNCTION(0x0, "gpio_in"),
1168 SUNXI_FUNCTION(0x1, "gpio_out"),
1169 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1174 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1175 SUNXI_FUNCTION(0x0, "gpio_in"),
1176 SUNXI_FUNCTION(0x1, "gpio_out"),
1177 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1178 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1179 SUNXI_FUNCTION(0x0, "gpio_in"),
1180 SUNXI_FUNCTION(0x1, "gpio_out"),
1181 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1182 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1183 SUNXI_FUNCTION(0x0, "gpio_in"),
1184 SUNXI_FUNCTION(0x1, "gpio_out"),
1185 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1187 SUNXI_FUNCTION(0x0, "gpio_in"),
1188 SUNXI_FUNCTION(0x1, "gpio_out"),
1189 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1190 /* Hole */
1191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1192 SUNXI_FUNCTION(0x0, "gpio_in"),
1193 SUNXI_FUNCTION(0x1, "gpio_out"),
1194 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1196 SUNXI_FUNCTION(0x0, "gpio_in"),
1197 SUNXI_FUNCTION(0x1, "gpio_out"),
1198 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1219 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1220 SUNXI_FUNCTION(0x0, "gpio_in"),
1221 SUNXI_FUNCTION(0x1, "gpio_out"),
1222 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1223 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1224 SUNXI_FUNCTION(0x0, "gpio_in"),
1225 SUNXI_FUNCTION(0x1, "gpio_out"),
1226 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1228 SUNXI_FUNCTION(0x0, "gpio_in"),
1229 SUNXI_FUNCTION(0x1, "gpio_out"),
1230 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1231 /* Hole */
1232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1233 SUNXI_FUNCTION(0x0, "gpio_in"),
1234 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1235 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1236 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1237 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1238 SUNXI_FUNCTION(0x0, "gpio_in"),
1239 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1240 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1241 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1242 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1243 SUNXI_FUNCTION(0x0, "gpio_in"),
1244 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1245 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1250 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1252 SUNXI_FUNCTION(0x0, "gpio_in"),
1253 SUNXI_FUNCTION(0x1, "gpio_out"),
1254 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1255 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1257 SUNXI_FUNCTION(0x0, "gpio_in"),
1258 SUNXI_FUNCTION(0x1, "gpio_out"),
1259 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1260 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1261 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1262 SUNXI_FUNCTION(0x0, "gpio_in"),
1263 SUNXI_FUNCTION(0x1, "gpio_out"),
1264 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1265 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1267 SUNXI_FUNCTION(0x0, "gpio_in"),
1268 SUNXI_FUNCTION(0x1, "gpio_out"),
1269 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1270 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1271 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1272 SUNXI_FUNCTION(0x0, "gpio_in"),
1273 SUNXI_FUNCTION(0x1, "gpio_out"),
1274 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1275 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1276 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1277 SUNXI_FUNCTION(0x0, "gpio_in"),
1278 SUNXI_FUNCTION(0x1, "gpio_out"),
1279 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1280 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1281 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1282 SUNXI_FUNCTION(0x0, "gpio_in"),
1283 SUNXI_FUNCTION(0x1, "gpio_out"),
1284 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1285 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1287 SUNXI_FUNCTION(0x0, "gpio_in"),
1288 SUNXI_FUNCTION(0x1, "gpio_out"),
1289 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1290 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1291 /* Hole */
1292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1293 SUNXI_FUNCTION(0x0, "gpio_in"),
1294 SUNXI_FUNCTION(0x1, "gpio_out"),
1295 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
1296 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1297 SUNXI_FUNCTION(0x0, "gpio_in"),
1298 SUNXI_FUNCTION(0x1, "gpio_out"),
1299 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
1300 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1301 SUNXI_FUNCTION(0x0, "gpio_in"),
1302 SUNXI_FUNCTION(0x1, "gpio_out"),
1303 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
1308 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1309 SUNXI_FUNCTION(0x0, "gpio_in"),
1310 SUNXI_FUNCTION(0x1, "gpio_out"),
1311 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
1312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1313 SUNXI_FUNCTION(0x0, "gpio_in"),
1314 SUNXI_FUNCTION(0x1, "gpio_out"),
1315 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
1316 /* Hole */
1317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1318 SUNXI_FUNCTION(0x0, "gpio_in"),
1319 SUNXI_FUNCTION(0x1, "gpio_out"),
1320 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1321 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1322 SUNXI_FUNCTION(0x0, "gpio_in"),
1323 SUNXI_FUNCTION(0x1, "gpio_out"),
1324 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1325 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1326 SUNXI_FUNCTION(0x0, "gpio_in"),
1327 SUNXI_FUNCTION(0x1, "gpio_out"),
1328 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1330 SUNXI_FUNCTION(0x0, "gpio_in"),
1331 SUNXI_FUNCTION(0x1, "gpio_out"),
1332 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1333 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1334 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1339 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1340 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1341 /* Hole */
1342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1343 SUNXI_FUNCTION(0x0, "gpio_in"),
1344 SUNXI_FUNCTION(0x1, "gpio_out"),
1345 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1346 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1347 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1348 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1349 SUNXI_FUNCTION(0x0, "gpio_in"),
1350 SUNXI_FUNCTION(0x1, "gpio_out"),
1351 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1352 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1353 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1355 SUNXI_FUNCTION(0x0, "gpio_in"),
1356 SUNXI_FUNCTION(0x1, "gpio_out"),
1357 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1358 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1359 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1364 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1365 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1366};
1367
1368static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1369 .pins = sun4i_a10_pins,
1370 .npins = ARRAY_SIZE(sun4i_a10_pins),
1371};
1372
1373static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
1374 .pins = sun5i_a13_pins,
1375 .npins = ARRAY_SIZE(sun5i_a13_pins),
1376};
1377
1378#endif /* __PINCTRL_SUNXI_PINS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 13:56:57 -0500