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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-08-04 05:47:34 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-08-23 02:56:29 -0400
commitde0c9029d5b7d9e3a5ac7f341be862b0aec57fe5 (patch)
tree3ec9cfa9cbaa6dd9209d29ff6fb786486f4bb626 /drivers/pinctrl/pinctrl-sunxi-pins.h
parent30e71663235596fa4d32eccacce1eaebc24fbf19 (diff)
pinctrl: sunxi: Add Allwinner A31 pins set
The Allwinner A31 SoC uses the same IP than the one found in the A10/A13, with only different pins. Add the pins and the associated functions found in the A31. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-sunxi-pins.h')
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h820
1 files changed, 820 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index c425470fac12..d36a1bfae2d2 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -2005,6 +2005,821 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ 2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
2006}; 2006};
2007 2007
2008static const struct sunxi_desc_pin sun6i_a31_pins[] = {
2009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2010 SUNXI_FUNCTION(0x0, "gpio_in"),
2011 SUNXI_FUNCTION(0x1, "gpio_out"),
2012 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
2013 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
2014 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
2015 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2016 SUNXI_FUNCTION(0x0, "gpio_in"),
2017 SUNXI_FUNCTION(0x1, "gpio_out"),
2018 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
2019 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
2020 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
2021 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2022 SUNXI_FUNCTION(0x0, "gpio_in"),
2023 SUNXI_FUNCTION(0x1, "gpio_out"),
2024 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
2025 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
2026 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
2027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2028 SUNXI_FUNCTION(0x0, "gpio_in"),
2029 SUNXI_FUNCTION(0x1, "gpio_out"),
2030 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
2031 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
2032 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
2033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2034 SUNXI_FUNCTION(0x0, "gpio_in"),
2035 SUNXI_FUNCTION(0x1, "gpio_out"),
2036 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
2037 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
2038 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
2039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2040 SUNXI_FUNCTION(0x0, "gpio_in"),
2041 SUNXI_FUNCTION(0x1, "gpio_out"),
2042 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
2043 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
2044 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
2045 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2046 SUNXI_FUNCTION(0x0, "gpio_in"),
2047 SUNXI_FUNCTION(0x1, "gpio_out"),
2048 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
2049 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
2050 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
2051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2052 SUNXI_FUNCTION(0x0, "gpio_in"),
2053 SUNXI_FUNCTION(0x1, "gpio_out"),
2054 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
2055 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
2056 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
2057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2058 SUNXI_FUNCTION(0x0, "gpio_in"),
2059 SUNXI_FUNCTION(0x1, "gpio_out"),
2060 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
2061 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
2062 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2063 SUNXI_FUNCTION(0x0, "gpio_in"),
2064 SUNXI_FUNCTION(0x1, "gpio_out"),
2065 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
2066 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
2067 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
2068 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
2069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2070 SUNXI_FUNCTION(0x0, "gpio_in"),
2071 SUNXI_FUNCTION(0x1, "gpio_out"),
2072 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
2073 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
2074 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
2075 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
2076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2077 SUNXI_FUNCTION(0x0, "gpio_in"),
2078 SUNXI_FUNCTION(0x1, "gpio_out"),
2079 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
2080 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
2081 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
2082 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
2083 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2084 SUNXI_FUNCTION(0x0, "gpio_in"),
2085 SUNXI_FUNCTION(0x1, "gpio_out"),
2086 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
2087 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
2088 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
2089 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
2090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2091 SUNXI_FUNCTION(0x0, "gpio_in"),
2092 SUNXI_FUNCTION(0x1, "gpio_out"),
2093 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
2094 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
2095 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
2096 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
2097 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2098 SUNXI_FUNCTION(0x0, "gpio_in"),
2099 SUNXI_FUNCTION(0x1, "gpio_out"),
2100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
2101 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
2102 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
2103 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
2104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2105 SUNXI_FUNCTION(0x0, "gpio_in"),
2106 SUNXI_FUNCTION(0x1, "gpio_out"),
2107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
2108 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
2109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2110 SUNXI_FUNCTION(0x0, "gpio_in"),
2111 SUNXI_FUNCTION(0x1, "gpio_out"),
2112 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
2113 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
2114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2115 SUNXI_FUNCTION(0x0, "gpio_in"),
2116 SUNXI_FUNCTION(0x1, "gpio_out"),
2117 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
2118 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
2119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA18,
2120 SUNXI_FUNCTION(0x0, "gpio_in"),
2121 SUNXI_FUNCTION(0x1, "gpio_out"),
2122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
2123 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
2124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA19,
2125 SUNXI_FUNCTION(0x0, "gpio_in"),
2126 SUNXI_FUNCTION(0x1, "gpio_out"),
2127 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
2128 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
2129 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
2130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA20,
2131 SUNXI_FUNCTION(0x0, "gpio_in"),
2132 SUNXI_FUNCTION(0x1, "gpio_out"),
2133 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
2134 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
2135 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
2136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA21,
2137 SUNXI_FUNCTION(0x0, "gpio_in"),
2138 SUNXI_FUNCTION(0x1, "gpio_out"),
2139 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
2140 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
2141 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
2142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA22,
2143 SUNXI_FUNCTION(0x0, "gpio_in"),
2144 SUNXI_FUNCTION(0x1, "gpio_out"),
2145 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
2146 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
2147 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
2148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA23,
2149 SUNXI_FUNCTION(0x0, "gpio_in"),
2150 SUNXI_FUNCTION(0x1, "gpio_out"),
2151 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
2152 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
2153 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
2154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA24,
2155 SUNXI_FUNCTION(0x0, "gpio_in"),
2156 SUNXI_FUNCTION(0x1, "gpio_out"),
2157 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
2158 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
2159 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
2160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA25,
2161 SUNXI_FUNCTION(0x0, "gpio_in"),
2162 SUNXI_FUNCTION(0x1, "gpio_out"),
2163 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
2164 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
2165 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
2166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA26,
2167 SUNXI_FUNCTION(0x0, "gpio_in"),
2168 SUNXI_FUNCTION(0x1, "gpio_out"),
2169 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
2170 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
2171 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA27,
2172 SUNXI_FUNCTION(0x0, "gpio_in"),
2173 SUNXI_FUNCTION(0x1, "gpio_out"),
2174 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
2175 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
2176 /* Hole */
2177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2178 SUNXI_FUNCTION(0x0, "gpio_in"),
2179 SUNXI_FUNCTION(0x1, "gpio_out"),
2180 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2181 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
2182 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
2183 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2184 SUNXI_FUNCTION(0x0, "gpio_in"),
2185 SUNXI_FUNCTION(0x1, "gpio_out"),
2186 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
2187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2188 SUNXI_FUNCTION(0x0, "gpio_in"),
2189 SUNXI_FUNCTION(0x1, "gpio_out"),
2190 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
2191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2192 SUNXI_FUNCTION(0x0, "gpio_in"),
2193 SUNXI_FUNCTION(0x1, "gpio_out"),
2194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
2195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2196 SUNXI_FUNCTION(0x0, "gpio_in"),
2197 SUNXI_FUNCTION(0x1, "gpio_out"),
2198 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
2199 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
2200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2201 SUNXI_FUNCTION(0x0, "gpio_in"),
2202 SUNXI_FUNCTION(0x1, "gpio_out"),
2203 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
2204 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
2205 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
2206 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2207 SUNXI_FUNCTION(0x0, "gpio_in"),
2208 SUNXI_FUNCTION(0x1, "gpio_out"),
2209 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
2210 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
2211 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
2212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2213 SUNXI_FUNCTION(0x0, "gpio_in"),
2214 SUNXI_FUNCTION(0x1, "gpio_out"),
2215 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
2216 /* Hole */
2217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
2218 SUNXI_FUNCTION(0x0, "gpio_in"),
2219 SUNXI_FUNCTION(0x1, "gpio_out"),
2220 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
2221 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
2222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
2223 SUNXI_FUNCTION(0x0, "gpio_in"),
2224 SUNXI_FUNCTION(0x1, "gpio_out"),
2225 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
2226 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
2227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
2228 SUNXI_FUNCTION(0x0, "gpio_in"),
2229 SUNXI_FUNCTION(0x1, "gpio_out"),
2230 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
2231 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
2232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
2233 SUNXI_FUNCTION(0x0, "gpio_in"),
2234 SUNXI_FUNCTION(0x1, "gpio_out"),
2235 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
2236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
2237 SUNXI_FUNCTION(0x0, "gpio_in"),
2238 SUNXI_FUNCTION(0x1, "gpio_out"),
2239 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
2240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
2241 SUNXI_FUNCTION(0x0, "gpio_in"),
2242 SUNXI_FUNCTION(0x1, "gpio_out"),
2243 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
2244 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
2245 SUNXI_FUNCTION(0x0, "gpio_in"),
2246 SUNXI_FUNCTION(0x1, "gpio_out"),
2247 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
2248 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
2249 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
2250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
2251 SUNXI_FUNCTION(0x0, "gpio_in"),
2252 SUNXI_FUNCTION(0x1, "gpio_out"),
2253 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
2254 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
2255 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
2256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
2257 SUNXI_FUNCTION(0x0, "gpio_in"),
2258 SUNXI_FUNCTION(0x1, "gpio_out"),
2259 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
2260 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
2261 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
2262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
2263 SUNXI_FUNCTION(0x0, "gpio_in"),
2264 SUNXI_FUNCTION(0x1, "gpio_out"),
2265 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
2266 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
2267 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
2268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
2269 SUNXI_FUNCTION(0x0, "gpio_in"),
2270 SUNXI_FUNCTION(0x1, "gpio_out"),
2271 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
2272 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
2273 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
2274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
2275 SUNXI_FUNCTION(0x0, "gpio_in"),
2276 SUNXI_FUNCTION(0x1, "gpio_out"),
2277 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
2278 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
2279 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
2280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
2281 SUNXI_FUNCTION(0x0, "gpio_in"),
2282 SUNXI_FUNCTION(0x1, "gpio_out"),
2283 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
2284 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
2285 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
2286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
2287 SUNXI_FUNCTION(0x0, "gpio_in"),
2288 SUNXI_FUNCTION(0x1, "gpio_out"),
2289 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
2290 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
2291 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
2292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
2293 SUNXI_FUNCTION(0x0, "gpio_in"),
2294 SUNXI_FUNCTION(0x1, "gpio_out"),
2295 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
2296 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
2297 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
2298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
2299 SUNXI_FUNCTION(0x0, "gpio_in"),
2300 SUNXI_FUNCTION(0x1, "gpio_out"),
2301 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
2302 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
2303 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
2304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
2305 SUNXI_FUNCTION(0x0, "gpio_in"),
2306 SUNXI_FUNCTION(0x1, "gpio_out"),
2307 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
2308 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
2309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
2310 SUNXI_FUNCTION(0x0, "gpio_in"),
2311 SUNXI_FUNCTION(0x1, "gpio_out"),
2312 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
2313 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
2314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
2315 SUNXI_FUNCTION(0x0, "gpio_in"),
2316 SUNXI_FUNCTION(0x1, "gpio_out"),
2317 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
2318 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
2319 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
2320 SUNXI_FUNCTION(0x0, "gpio_in"),
2321 SUNXI_FUNCTION(0x1, "gpio_out"),
2322 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
2323 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
2324 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
2325 SUNXI_FUNCTION(0x0, "gpio_in"),
2326 SUNXI_FUNCTION(0x1, "gpio_out"),
2327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
2328 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
2329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
2330 SUNXI_FUNCTION(0x0, "gpio_in"),
2331 SUNXI_FUNCTION(0x1, "gpio_out"),
2332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
2333 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
2334 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
2335 SUNXI_FUNCTION(0x0, "gpio_in"),
2336 SUNXI_FUNCTION(0x1, "gpio_out"),
2337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
2338 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
2339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
2340 SUNXI_FUNCTION(0x0, "gpio_in"),
2341 SUNXI_FUNCTION(0x1, "gpio_out"),
2342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
2343 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
2344 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
2345 SUNXI_FUNCTION(0x0, "gpio_in"),
2346 SUNXI_FUNCTION(0x1, "gpio_out"),
2347 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
2348 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
2349 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
2350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC25,
2351 SUNXI_FUNCTION(0x0, "gpio_in"),
2352 SUNXI_FUNCTION(0x1, "gpio_out"),
2353 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
2354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC26,
2355 SUNXI_FUNCTION(0x0, "gpio_in"),
2356 SUNXI_FUNCTION(0x1, "gpio_out"),
2357 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
2358 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC27,
2359 SUNXI_FUNCTION(0x0, "gpio_in"),
2360 SUNXI_FUNCTION(0x1, "gpio_out"),
2361 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
2362 /* Hole */
2363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
2364 SUNXI_FUNCTION(0x0, "gpio_in"),
2365 SUNXI_FUNCTION(0x1, "gpio_out"),
2366 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
2367 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
2368 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
2369 SUNXI_FUNCTION(0x0, "gpio_in"),
2370 SUNXI_FUNCTION(0x1, "gpio_out"),
2371 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
2372 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
2373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
2374 SUNXI_FUNCTION(0x0, "gpio_in"),
2375 SUNXI_FUNCTION(0x1, "gpio_out"),
2376 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
2377 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
2378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
2379 SUNXI_FUNCTION(0x0, "gpio_in"),
2380 SUNXI_FUNCTION(0x1, "gpio_out"),
2381 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
2382 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
2383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
2384 SUNXI_FUNCTION(0x0, "gpio_in"),
2385 SUNXI_FUNCTION(0x1, "gpio_out"),
2386 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
2387 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
2388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
2389 SUNXI_FUNCTION(0x0, "gpio_in"),
2390 SUNXI_FUNCTION(0x1, "gpio_out"),
2391 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
2392 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
2393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
2394 SUNXI_FUNCTION(0x0, "gpio_in"),
2395 SUNXI_FUNCTION(0x1, "gpio_out"),
2396 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
2397 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
2398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
2399 SUNXI_FUNCTION(0x0, "gpio_in"),
2400 SUNXI_FUNCTION(0x1, "gpio_out"),
2401 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
2402 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
2403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
2404 SUNXI_FUNCTION(0x0, "gpio_in"),
2405 SUNXI_FUNCTION(0x1, "gpio_out"),
2406 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
2407 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
2408 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
2409 SUNXI_FUNCTION(0x0, "gpio_in"),
2410 SUNXI_FUNCTION(0x1, "gpio_out"),
2411 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
2412 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
2413 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
2414 SUNXI_FUNCTION(0x0, "gpio_in"),
2415 SUNXI_FUNCTION(0x1, "gpio_out"),
2416 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
2417 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
2418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
2419 SUNXI_FUNCTION(0x0, "gpio_in"),
2420 SUNXI_FUNCTION(0x1, "gpio_out"),
2421 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
2422 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
2423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
2424 SUNXI_FUNCTION(0x0, "gpio_in"),
2425 SUNXI_FUNCTION(0x1, "gpio_out"),
2426 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
2427 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
2428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
2429 SUNXI_FUNCTION(0x0, "gpio_in"),
2430 SUNXI_FUNCTION(0x1, "gpio_out"),
2431 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
2432 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
2433 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
2434 SUNXI_FUNCTION(0x0, "gpio_in"),
2435 SUNXI_FUNCTION(0x1, "gpio_out"),
2436 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
2437 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
2438 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
2439 SUNXI_FUNCTION(0x0, "gpio_in"),
2440 SUNXI_FUNCTION(0x1, "gpio_out"),
2441 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
2442 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
2443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
2444 SUNXI_FUNCTION(0x0, "gpio_in"),
2445 SUNXI_FUNCTION(0x1, "gpio_out"),
2446 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
2447 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
2448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
2449 SUNXI_FUNCTION(0x0, "gpio_in"),
2450 SUNXI_FUNCTION(0x1, "gpio_out"),
2451 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
2452 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
2453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
2454 SUNXI_FUNCTION(0x0, "gpio_in"),
2455 SUNXI_FUNCTION(0x1, "gpio_out"),
2456 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
2457 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
2458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
2459 SUNXI_FUNCTION(0x0, "gpio_in"),
2460 SUNXI_FUNCTION(0x1, "gpio_out"),
2461 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
2462 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
2463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
2464 SUNXI_FUNCTION(0x0, "gpio_in"),
2465 SUNXI_FUNCTION(0x1, "gpio_out"),
2466 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
2467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
2468 SUNXI_FUNCTION(0x0, "gpio_in"),
2469 SUNXI_FUNCTION(0x1, "gpio_out"),
2470 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
2471 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
2472 SUNXI_FUNCTION(0x0, "gpio_in"),
2473 SUNXI_FUNCTION(0x1, "gpio_out"),
2474 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
2475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
2476 SUNXI_FUNCTION(0x0, "gpio_in"),
2477 SUNXI_FUNCTION(0x1, "gpio_out"),
2478 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
2479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
2480 SUNXI_FUNCTION(0x0, "gpio_in"),
2481 SUNXI_FUNCTION(0x1, "gpio_out"),
2482 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
2483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
2484 SUNXI_FUNCTION(0x0, "gpio_in"),
2485 SUNXI_FUNCTION(0x1, "gpio_out"),
2486 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
2487 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
2488 SUNXI_FUNCTION(0x0, "gpio_in"),
2489 SUNXI_FUNCTION(0x1, "gpio_out"),
2490 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
2491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
2492 SUNXI_FUNCTION(0x0, "gpio_in"),
2493 SUNXI_FUNCTION(0x1, "gpio_out"),
2494 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
2495 /* Hole */
2496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
2497 SUNXI_FUNCTION(0x0, "gpio_in"),
2498 SUNXI_FUNCTION(0x1, "gpio_out"),
2499 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
2500 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
2501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
2502 SUNXI_FUNCTION(0x0, "gpio_in"),
2503 SUNXI_FUNCTION(0x1, "gpio_out"),
2504 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
2505 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
2506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
2507 SUNXI_FUNCTION(0x0, "gpio_in"),
2508 SUNXI_FUNCTION(0x1, "gpio_out"),
2509 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
2510 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
2511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
2512 SUNXI_FUNCTION(0x0, "gpio_in"),
2513 SUNXI_FUNCTION(0x1, "gpio_out"),
2514 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
2515 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
2516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
2517 SUNXI_FUNCTION(0x0, "gpio_in"),
2518 SUNXI_FUNCTION(0x1, "gpio_out"),
2519 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
2520 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
2521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
2522 SUNXI_FUNCTION(0x0, "gpio_in"),
2523 SUNXI_FUNCTION(0x1, "gpio_out"),
2524 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
2525 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
2526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
2527 SUNXI_FUNCTION(0x0, "gpio_in"),
2528 SUNXI_FUNCTION(0x1, "gpio_out"),
2529 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
2530 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
2531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
2532 SUNXI_FUNCTION(0x0, "gpio_in"),
2533 SUNXI_FUNCTION(0x1, "gpio_out"),
2534 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
2535 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
2536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
2537 SUNXI_FUNCTION(0x0, "gpio_in"),
2538 SUNXI_FUNCTION(0x1, "gpio_out"),
2539 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
2540 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
2541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
2542 SUNXI_FUNCTION(0x0, "gpio_in"),
2543 SUNXI_FUNCTION(0x1, "gpio_out"),
2544 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
2545 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
2546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
2547 SUNXI_FUNCTION(0x0, "gpio_in"),
2548 SUNXI_FUNCTION(0x1, "gpio_out"),
2549 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
2550 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
2551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
2552 SUNXI_FUNCTION(0x0, "gpio_in"),
2553 SUNXI_FUNCTION(0x1, "gpio_out"),
2554 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
2555 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
2556 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE12,
2557 SUNXI_FUNCTION(0x0, "gpio_in"),
2558 SUNXI_FUNCTION(0x1, "gpio_out"),
2559 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
2560 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
2561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE13,
2562 SUNXI_FUNCTION(0x0, "gpio_in"),
2563 SUNXI_FUNCTION(0x1, "gpio_out"),
2564 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
2565 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
2566 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE14,
2567 SUNXI_FUNCTION(0x0, "gpio_in"),
2568 SUNXI_FUNCTION(0x1, "gpio_out"),
2569 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
2570 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
2571 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE15,
2572 SUNXI_FUNCTION(0x0, "gpio_in"),
2573 SUNXI_FUNCTION(0x1, "gpio_out"),
2574 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
2575 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
2576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE16,
2577 SUNXI_FUNCTION(0x0, "gpio_in"),
2578 SUNXI_FUNCTION(0x1, "gpio_out"),
2579 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
2580 /* Hole */
2581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
2582 SUNXI_FUNCTION(0x0, "gpio_in"),
2583 SUNXI_FUNCTION(0x1, "gpio_out"),
2584 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
2585 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
2586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
2587 SUNXI_FUNCTION(0x0, "gpio_in"),
2588 SUNXI_FUNCTION(0x1, "gpio_out"),
2589 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
2590 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
2591 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
2592 SUNXI_FUNCTION(0x0, "gpio_in"),
2593 SUNXI_FUNCTION(0x1, "gpio_out"),
2594 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
2595 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
2596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
2597 SUNXI_FUNCTION(0x0, "gpio_in"),
2598 SUNXI_FUNCTION(0x1, "gpio_out"),
2599 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
2600 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
2601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
2602 SUNXI_FUNCTION(0x0, "gpio_in"),
2603 SUNXI_FUNCTION(0x1, "gpio_out"),
2604 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
2605 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
2606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
2607 SUNXI_FUNCTION(0x0, "gpio_in"),
2608 SUNXI_FUNCTION(0x1, "gpio_out"),
2609 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
2610 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
2611 /* Hole */
2612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
2613 SUNXI_FUNCTION(0x0, "gpio_in"),
2614 SUNXI_FUNCTION(0x1, "gpio_out"),
2615 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
2616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
2617 SUNXI_FUNCTION(0x0, "gpio_in"),
2618 SUNXI_FUNCTION(0x1, "gpio_out"),
2619 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
2620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
2621 SUNXI_FUNCTION(0x0, "gpio_in"),
2622 SUNXI_FUNCTION(0x1, "gpio_out"),
2623 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
2624 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
2625 SUNXI_FUNCTION(0x0, "gpio_in"),
2626 SUNXI_FUNCTION(0x1, "gpio_out"),
2627 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
2628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
2629 SUNXI_FUNCTION(0x0, "gpio_in"),
2630 SUNXI_FUNCTION(0x1, "gpio_out"),
2631 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
2632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
2633 SUNXI_FUNCTION(0x0, "gpio_in"),
2634 SUNXI_FUNCTION(0x1, "gpio_out"),
2635 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
2636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
2637 SUNXI_FUNCTION(0x0, "gpio_in"),
2638 SUNXI_FUNCTION(0x1, "gpio_out"),
2639 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
2640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
2641 SUNXI_FUNCTION(0x0, "gpio_in"),
2642 SUNXI_FUNCTION(0x1, "gpio_out"),
2643 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
2644 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
2645 SUNXI_FUNCTION(0x0, "gpio_in"),
2646 SUNXI_FUNCTION(0x1, "gpio_out"),
2647 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
2648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
2649 SUNXI_FUNCTION(0x0, "gpio_in"),
2650 SUNXI_FUNCTION(0x1, "gpio_out"),
2651 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
2652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
2653 SUNXI_FUNCTION(0x0, "gpio_in"),
2654 SUNXI_FUNCTION(0x1, "gpio_out"),
2655 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
2656 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
2657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
2658 SUNXI_FUNCTION(0x0, "gpio_in"),
2659 SUNXI_FUNCTION(0x1, "gpio_out"),
2660 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
2661 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
2662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2663 SUNXI_FUNCTION(0x0, "gpio_in"),
2664 SUNXI_FUNCTION(0x1, "gpio_out"),
2665 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
2666 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
2667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
2668 SUNXI_FUNCTION(0x0, "gpio_in"),
2669 SUNXI_FUNCTION(0x1, "gpio_out"),
2670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
2671 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
2672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG14,
2673 SUNXI_FUNCTION(0x0, "gpio_in"),
2674 SUNXI_FUNCTION(0x1, "gpio_out"),
2675 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
2676 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
2677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG15,
2678 SUNXI_FUNCTION(0x0, "gpio_in"),
2679 SUNXI_FUNCTION(0x1, "gpio_out"),
2680 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
2681 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
2682 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG16,
2683 SUNXI_FUNCTION(0x0, "gpio_in"),
2684 SUNXI_FUNCTION(0x1, "gpio_out"),
2685 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2686 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
2687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG17,
2688 SUNXI_FUNCTION(0x0, "gpio_in"),
2689 SUNXI_FUNCTION(0x1, "gpio_out"),
2690 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
2691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG18,
2692 SUNXI_FUNCTION(0x0, "gpio_in"),
2693 SUNXI_FUNCTION(0x1, "gpio_out"),
2694 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
2695 /* Hole */
2696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
2697 SUNXI_FUNCTION(0x0, "gpio_in"),
2698 SUNXI_FUNCTION(0x1, "gpio_out"),
2699 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
2700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
2701 SUNXI_FUNCTION(0x0, "gpio_in"),
2702 SUNXI_FUNCTION(0x1, "gpio_out"),
2703 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
2704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
2705 SUNXI_FUNCTION(0x0, "gpio_in"),
2706 SUNXI_FUNCTION(0x1, "gpio_out"),
2707 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
2708 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
2709 SUNXI_FUNCTION(0x0, "gpio_in"),
2710 SUNXI_FUNCTION(0x1, "gpio_out"),
2711 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
2712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
2713 SUNXI_FUNCTION(0x0, "gpio_in"),
2714 SUNXI_FUNCTION(0x1, "gpio_out"),
2715 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
2716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
2717 SUNXI_FUNCTION(0x0, "gpio_in"),
2718 SUNXI_FUNCTION(0x1, "gpio_out"),
2719 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
2720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
2721 SUNXI_FUNCTION(0x0, "gpio_in"),
2722 SUNXI_FUNCTION(0x1, "gpio_out"),
2723 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
2724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
2725 SUNXI_FUNCTION(0x0, "gpio_in"),
2726 SUNXI_FUNCTION(0x1, "gpio_out"),
2727 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
2728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
2729 SUNXI_FUNCTION(0x0, "gpio_in"),
2730 SUNXI_FUNCTION(0x1, "gpio_out"),
2731 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
2732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
2733 SUNXI_FUNCTION(0x0, "gpio_in"),
2734 SUNXI_FUNCTION(0x1, "gpio_out"),
2735 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
2736 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
2737 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
2738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
2739 SUNXI_FUNCTION(0x0, "gpio_in"),
2740 SUNXI_FUNCTION(0x1, "gpio_out"),
2741 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
2742 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
2743 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
2744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
2745 SUNXI_FUNCTION(0x0, "gpio_in"),
2746 SUNXI_FUNCTION(0x1, "gpio_out"),
2747 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
2748 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
2749 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
2750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
2751 SUNXI_FUNCTION(0x0, "gpio_in"),
2752 SUNXI_FUNCTION(0x1, "gpio_out"),
2753 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
2754 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
2755 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
2756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
2757 SUNXI_FUNCTION(0x0, "gpio_in"),
2758 SUNXI_FUNCTION(0x1, "gpio_out"),
2759 SUNXI_FUNCTION(0x2, "pwm0")),
2760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
2761 SUNXI_FUNCTION(0x0, "gpio_in"),
2762 SUNXI_FUNCTION(0x1, "gpio_out"),
2763 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
2765 SUNXI_FUNCTION(0x0, "gpio_in"),
2766 SUNXI_FUNCTION(0x1, "gpio_out"),
2767 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2768 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
2769 SUNXI_FUNCTION(0x0, "gpio_in"),
2770 SUNXI_FUNCTION(0x1, "gpio_out"),
2771 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
2772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
2773 SUNXI_FUNCTION(0x0, "gpio_in"),
2774 SUNXI_FUNCTION(0x1, "gpio_out"),
2775 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
2776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
2777 SUNXI_FUNCTION(0x0, "gpio_in"),
2778 SUNXI_FUNCTION(0x1, "gpio_out"),
2779 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
2780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
2781 SUNXI_FUNCTION(0x0, "gpio_in"),
2782 SUNXI_FUNCTION(0x1, "gpio_out"),
2783 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
2784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
2785 SUNXI_FUNCTION(0x0, "gpio_in"),
2786 SUNXI_FUNCTION(0x1, "gpio_out"),
2787 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
2788 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
2789 SUNXI_FUNCTION(0x0, "gpio_in"),
2790 SUNXI_FUNCTION(0x1, "gpio_out"),
2791 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
2792 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
2793 SUNXI_FUNCTION(0x0, "gpio_in"),
2794 SUNXI_FUNCTION(0x1, "gpio_out")),
2795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
2796 SUNXI_FUNCTION(0x0, "gpio_in"),
2797 SUNXI_FUNCTION(0x1, "gpio_out")),
2798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
2799 SUNXI_FUNCTION(0x0, "gpio_in"),
2800 SUNXI_FUNCTION(0x1, "gpio_out")),
2801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
2802 SUNXI_FUNCTION(0x0, "gpio_in"),
2803 SUNXI_FUNCTION(0x1, "gpio_out")),
2804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
2805 SUNXI_FUNCTION(0x0, "gpio_in"),
2806 SUNXI_FUNCTION(0x1, "gpio_out")),
2807 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
2808 SUNXI_FUNCTION(0x0, "gpio_in"),
2809 SUNXI_FUNCTION(0x1, "gpio_out")),
2810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH28,
2811 SUNXI_FUNCTION(0x0, "gpio_in"),
2812 SUNXI_FUNCTION(0x1, "gpio_out")),
2813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH29,
2814 SUNXI_FUNCTION(0x0, "gpio_in"),
2815 SUNXI_FUNCTION(0x1, "gpio_out"),
2816 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
2817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH30,
2818 SUNXI_FUNCTION(0x0, "gpio_in"),
2819 SUNXI_FUNCTION(0x1, "gpio_out"),
2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
2821};
2822
2008static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 2823static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
2009 .pins = sun4i_a10_pins, 2824 .pins = sun4i_a10_pins,
2010 .npins = ARRAY_SIZE(sun4i_a10_pins), 2825 .npins = ARRAY_SIZE(sun4i_a10_pins),
@@ -2020,4 +2835,9 @@ static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
2020 .npins = ARRAY_SIZE(sun5i_a13_pins), 2835 .npins = ARRAY_SIZE(sun5i_a13_pins),
2021}; 2836};
2022 2837
2838static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
2839 .pins = sun6i_a31_pins,
2840 .npins = ARRAY_SIZE(sun6i_a31_pins),
2841};
2842
2023#endif /* __PINCTRL_SUNXI_PINS_H */ 2843#endif /* __PINCTRL_SUNXI_PINS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 09:26:05 -0500