pinctrl: sunxi: define A31 R_PIO pin functions

The A31 SoC provides both PL and PM pio bank through the R_PIO block.

These pins all support gpio function and can bbe assigned to system
peripherals (like TWI, P2WI, JTAG, ...)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 74 insertions, 0 deletions

diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 3d6066988a72..51100caf05f9 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -2820,6 +2820,74 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
                   SUNXI_FUNCTION(0x2, "nand1")),        /* CE3 */
 };
 
+static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_twi"),         /* SCK */
+                  SUNXI_FUNCTION(0x3, "s_p2wi")),       /* SCK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_twi"),         /* SDA */
+                  SUNXI_FUNCTION(0x3, "s_p2wi")),       /* SDA */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_uart")),       /* TX */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_uart")),       /* RX */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_ir")),         /* RX */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* MS */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* CK */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* DO */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* DI */
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "1wire")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7,
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "rtc")),          /* CLKO */
+};
+
 static const struct sunxi_desc_pin sun7i_a20_pins[] = {
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
                   SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -3855,6 +3923,12 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
         .npins = ARRAY_SIZE(sun6i_a31_pins),
 };
 
+static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
+        .pins = sun6i_a31_r_pins,
+        .npins = ARRAY_SIZE(sun6i_a31_r_pins),
+        .pin_base = PL_BASE,
+};
+
 static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
         .pins = sun7i_a20_pins,
         .npins = ARRAY_SIZE(sun7i_a20_pins),