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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-08-04 05:58:45 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-08-23 02:56:30 -0400
commit23ac6df45117a9af7178ae581740aecb1791b94a (patch)
treeedd72c6882c47f46a7f1e6085e561fce49dc911f /drivers/pinctrl/pinctrl-sunxi-pins.h
parentde0c9029d5b7d9e3a5ac7f341be862b0aec57fe5 (diff)
pinctrl: sunxi: Add Allwinner A20 pins set
The Allwinner A20 is pin-compatible with the older A10, so the two pin set are quite similar. However, since the A20 has new features, we can't just use the A10 pin set as is, and we need to define our own for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-sunxi-pins.h')
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h1018
1 files changed, 1018 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index d36a1bfae2d2..2c7446a1a199 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -2820,6 +2820,1019 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */ 2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
2821}; 2821};
2822 2822
2823static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2825 SUNXI_FUNCTION(0x0, "gpio_in"),
2826 SUNXI_FUNCTION(0x1, "gpio_out"),
2827 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
2828 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
2829 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
2830 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
2831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2832 SUNXI_FUNCTION(0x0, "gpio_in"),
2833 SUNXI_FUNCTION(0x1, "gpio_out"),
2834 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
2835 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
2836 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
2837 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
2838 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2839 SUNXI_FUNCTION(0x0, "gpio_in"),
2840 SUNXI_FUNCTION(0x1, "gpio_out"),
2841 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
2842 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
2843 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
2844 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
2845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2846 SUNXI_FUNCTION(0x0, "gpio_in"),
2847 SUNXI_FUNCTION(0x1, "gpio_out"),
2848 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
2849 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
2850 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
2851 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
2852 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2853 SUNXI_FUNCTION(0x0, "gpio_in"),
2854 SUNXI_FUNCTION(0x1, "gpio_out"),
2855 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
2856 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
2857 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
2858 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2859 SUNXI_FUNCTION(0x0, "gpio_in"),
2860 SUNXI_FUNCTION(0x1, "gpio_out"),
2861 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
2862 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
2863 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
2864 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2865 SUNXI_FUNCTION(0x0, "gpio_in"),
2866 SUNXI_FUNCTION(0x1, "gpio_out"),
2867 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
2868 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
2869 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
2870 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2871 SUNXI_FUNCTION(0x0, "gpio_in"),
2872 SUNXI_FUNCTION(0x1, "gpio_out"),
2873 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
2874 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
2875 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
2876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2877 SUNXI_FUNCTION(0x0, "gpio_in"),
2878 SUNXI_FUNCTION(0x1, "gpio_out"),
2879 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
2880 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
2881 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
2882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2883 SUNXI_FUNCTION(0x0, "gpio_in"),
2884 SUNXI_FUNCTION(0x1, "gpio_out"),
2885 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
2886 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
2887 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
2888 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
2889 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2890 SUNXI_FUNCTION(0x0, "gpio_in"),
2891 SUNXI_FUNCTION(0x1, "gpio_out"),
2892 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
2893 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
2894 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
2895 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2896 SUNXI_FUNCTION(0x0, "gpio_in"),
2897 SUNXI_FUNCTION(0x1, "gpio_out"),
2898 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
2899 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
2900 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
2901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2902 SUNXI_FUNCTION(0x0, "gpio_in"),
2903 SUNXI_FUNCTION(0x1, "gpio_out"),
2904 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
2905 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
2906 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
2907 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
2908 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2909 SUNXI_FUNCTION(0x0, "gpio_in"),
2910 SUNXI_FUNCTION(0x1, "gpio_out"),
2911 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
2912 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
2913 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
2914 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
2915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2916 SUNXI_FUNCTION(0x0, "gpio_in"),
2917 SUNXI_FUNCTION(0x1, "gpio_out"),
2918 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
2919 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
2920 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
2921 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
2922 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
2923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2924 SUNXI_FUNCTION(0x0, "gpio_in"),
2925 SUNXI_FUNCTION(0x1, "gpio_out"),
2926 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
2927 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
2928 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
2929 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
2930 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2932 SUNXI_FUNCTION(0x0, "gpio_in"),
2933 SUNXI_FUNCTION(0x1, "gpio_out"),
2934 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
2935 SUNXI_FUNCTION(0x3, "can"), /* TX */
2936 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
2937 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
2938 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
2939 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2940 SUNXI_FUNCTION(0x0, "gpio_in"),
2941 SUNXI_FUNCTION(0x1, "gpio_out"),
2942 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
2943 SUNXI_FUNCTION(0x3, "can"), /* RX */
2944 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
2945 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
2946 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2947 /* Hole */
2948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2949 SUNXI_FUNCTION(0x0, "gpio_in"),
2950 SUNXI_FUNCTION(0x1, "gpio_out"),
2951 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2953 SUNXI_FUNCTION(0x0, "gpio_in"),
2954 SUNXI_FUNCTION(0x1, "gpio_out"),
2955 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2956 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2957 SUNXI_FUNCTION(0x0, "gpio_in"),
2958 SUNXI_FUNCTION(0x1, "gpio_out"),
2959 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
2960 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2961 SUNXI_FUNCTION(0x0, "gpio_in"),
2962 SUNXI_FUNCTION(0x1, "gpio_out"),
2963 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
2964 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
2965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2966 SUNXI_FUNCTION(0x0, "gpio_in"),
2967 SUNXI_FUNCTION(0x1, "gpio_out"),
2968 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
2969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2970 SUNXI_FUNCTION(0x0, "gpio_in"),
2971 SUNXI_FUNCTION(0x1, "gpio_out"),
2972 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2973 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
2974 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2975 SUNXI_FUNCTION(0x0, "gpio_in"),
2976 SUNXI_FUNCTION(0x1, "gpio_out"),
2977 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
2978 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
2979 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2980 SUNXI_FUNCTION(0x0, "gpio_in"),
2981 SUNXI_FUNCTION(0x1, "gpio_out"),
2982 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
2983 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
2984 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
2985 SUNXI_FUNCTION(0x0, "gpio_in"),
2986 SUNXI_FUNCTION(0x1, "gpio_out"),
2987 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
2988 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
2989 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
2990 SUNXI_FUNCTION(0x0, "gpio_in"),
2991 SUNXI_FUNCTION(0x1, "gpio_out"),
2992 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
2993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
2994 SUNXI_FUNCTION(0x0, "gpio_in"),
2995 SUNXI_FUNCTION(0x1, "gpio_out"),
2996 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
2997 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
2998 SUNXI_FUNCTION(0x0, "gpio_in"),
2999 SUNXI_FUNCTION(0x1, "gpio_out"),
3000 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
3001 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
3002 SUNXI_FUNCTION(0x0, "gpio_in"),
3003 SUNXI_FUNCTION(0x1, "gpio_out"),
3004 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
3005 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
3006 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
3007 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
3008 SUNXI_FUNCTION(0x0, "gpio_in"),
3009 SUNXI_FUNCTION(0x1, "gpio_out"),
3010 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
3011 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
3012 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
3013 SUNXI_FUNCTION(0x0, "gpio_in"),
3014 SUNXI_FUNCTION(0x1, "gpio_out"),
3015 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
3016 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
3017 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
3018 SUNXI_FUNCTION(0x0, "gpio_in"),
3019 SUNXI_FUNCTION(0x1, "gpio_out"),
3020 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
3021 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
3022 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
3023 SUNXI_FUNCTION(0x0, "gpio_in"),
3024 SUNXI_FUNCTION(0x1, "gpio_out"),
3025 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
3026 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
3027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
3028 SUNXI_FUNCTION(0x0, "gpio_in"),
3029 SUNXI_FUNCTION(0x1, "gpio_out"),
3030 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
3031 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
3032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
3033 SUNXI_FUNCTION(0x0, "gpio_in"),
3034 SUNXI_FUNCTION(0x1, "gpio_out"),
3035 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
3036 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
3037 SUNXI_FUNCTION(0x0, "gpio_in"),
3038 SUNXI_FUNCTION(0x1, "gpio_out"),
3039 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
3040 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
3041 SUNXI_FUNCTION(0x0, "gpio_in"),
3042 SUNXI_FUNCTION(0x1, "gpio_out"),
3043 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
3044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
3045 SUNXI_FUNCTION(0x0, "gpio_in"),
3046 SUNXI_FUNCTION(0x1, "gpio_out"),
3047 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
3048 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
3049 SUNXI_FUNCTION(0x0, "gpio_in"),
3050 SUNXI_FUNCTION(0x1, "gpio_out"),
3051 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
3052 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
3053 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
3054 SUNXI_FUNCTION(0x0, "gpio_in"),
3055 SUNXI_FUNCTION(0x1, "gpio_out"),
3056 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
3057 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
3058 /* Hole */
3059 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
3060 SUNXI_FUNCTION(0x0, "gpio_in"),
3061 SUNXI_FUNCTION(0x1, "gpio_out"),
3062 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
3063 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
3064 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
3065 SUNXI_FUNCTION(0x0, "gpio_in"),
3066 SUNXI_FUNCTION(0x1, "gpio_out"),
3067 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
3068 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
3069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
3070 SUNXI_FUNCTION(0x0, "gpio_in"),
3071 SUNXI_FUNCTION(0x1, "gpio_out"),
3072 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
3073 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
3074 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
3075 SUNXI_FUNCTION(0x0, "gpio_in"),
3076 SUNXI_FUNCTION(0x1, "gpio_out"),
3077 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
3078 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
3079 SUNXI_FUNCTION(0x0, "gpio_in"),
3080 SUNXI_FUNCTION(0x1, "gpio_out"),
3081 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
3082 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
3083 SUNXI_FUNCTION(0x0, "gpio_in"),
3084 SUNXI_FUNCTION(0x1, "gpio_out"),
3085 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
3086 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
3087 SUNXI_FUNCTION(0x0, "gpio_in"),
3088 SUNXI_FUNCTION(0x1, "gpio_out"),
3089 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
3090 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
3091 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
3092 SUNXI_FUNCTION(0x0, "gpio_in"),
3093 SUNXI_FUNCTION(0x1, "gpio_out"),
3094 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
3095 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
3096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
3097 SUNXI_FUNCTION(0x0, "gpio_in"),
3098 SUNXI_FUNCTION(0x1, "gpio_out"),
3099 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
3100 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
3101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
3102 SUNXI_FUNCTION(0x0, "gpio_in"),
3103 SUNXI_FUNCTION(0x1, "gpio_out"),
3104 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
3105 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
3106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
3107 SUNXI_FUNCTION(0x0, "gpio_in"),
3108 SUNXI_FUNCTION(0x1, "gpio_out"),
3109 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
3110 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
3111 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
3112 SUNXI_FUNCTION(0x0, "gpio_in"),
3113 SUNXI_FUNCTION(0x1, "gpio_out"),
3114 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
3115 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
3116 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
3117 SUNXI_FUNCTION(0x0, "gpio_in"),
3118 SUNXI_FUNCTION(0x1, "gpio_out"),
3119 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
3120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
3121 SUNXI_FUNCTION(0x0, "gpio_in"),
3122 SUNXI_FUNCTION(0x1, "gpio_out"),
3123 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
3124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
3125 SUNXI_FUNCTION(0x0, "gpio_in"),
3126 SUNXI_FUNCTION(0x1, "gpio_out"),
3127 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
3128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
3129 SUNXI_FUNCTION(0x0, "gpio_in"),
3130 SUNXI_FUNCTION(0x1, "gpio_out"),
3131 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
3132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
3133 SUNXI_FUNCTION(0x0, "gpio_in"),
3134 SUNXI_FUNCTION(0x1, "gpio_out"),
3135 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
3136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
3137 SUNXI_FUNCTION(0x0, "gpio_in"),
3138 SUNXI_FUNCTION(0x1, "gpio_out"),
3139 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
3140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
3141 SUNXI_FUNCTION(0x0, "gpio_in"),
3142 SUNXI_FUNCTION(0x1, "gpio_out"),
3143 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
3144 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
3145 SUNXI_FUNCTION(0x0, "gpio_in"),
3146 SUNXI_FUNCTION(0x1, "gpio_out"),
3147 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
3148 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
3149 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
3150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
3151 SUNXI_FUNCTION(0x0, "gpio_in"),
3152 SUNXI_FUNCTION(0x1, "gpio_out"),
3153 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
3154 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
3155 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
3156 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
3157 SUNXI_FUNCTION(0x0, "gpio_in"),
3158 SUNXI_FUNCTION(0x1, "gpio_out"),
3159 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
3160 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
3161 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
3162 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
3163 SUNXI_FUNCTION(0x0, "gpio_in"),
3164 SUNXI_FUNCTION(0x1, "gpio_out"),
3165 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
3166 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
3167 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
3168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
3169 SUNXI_FUNCTION(0x0, "gpio_in"),
3170 SUNXI_FUNCTION(0x1, "gpio_out"),
3171 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
3172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
3173 SUNXI_FUNCTION(0x0, "gpio_in"),
3174 SUNXI_FUNCTION(0x1, "gpio_out"),
3175 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
3176 /* Hole */
3177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
3178 SUNXI_FUNCTION(0x0, "gpio_in"),
3179 SUNXI_FUNCTION(0x1, "gpio_out"),
3180 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
3181 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
3182 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
3183 SUNXI_FUNCTION(0x0, "gpio_in"),
3184 SUNXI_FUNCTION(0x1, "gpio_out"),
3185 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
3186 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
3187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
3188 SUNXI_FUNCTION(0x0, "gpio_in"),
3189 SUNXI_FUNCTION(0x1, "gpio_out"),
3190 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
3191 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
3192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
3193 SUNXI_FUNCTION(0x0, "gpio_in"),
3194 SUNXI_FUNCTION(0x1, "gpio_out"),
3195 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
3196 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
3197 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
3198 SUNXI_FUNCTION(0x0, "gpio_in"),
3199 SUNXI_FUNCTION(0x1, "gpio_out"),
3200 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
3201 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
3202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
3203 SUNXI_FUNCTION(0x0, "gpio_in"),
3204 SUNXI_FUNCTION(0x1, "gpio_out"),
3205 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
3206 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
3207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
3208 SUNXI_FUNCTION(0x0, "gpio_in"),
3209 SUNXI_FUNCTION(0x1, "gpio_out"),
3210 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
3211 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
3212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
3213 SUNXI_FUNCTION(0x0, "gpio_in"),
3214 SUNXI_FUNCTION(0x1, "gpio_out"),
3215 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
3216 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
3217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
3218 SUNXI_FUNCTION(0x0, "gpio_in"),
3219 SUNXI_FUNCTION(0x1, "gpio_out"),
3220 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
3221 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
3222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
3223 SUNXI_FUNCTION(0x0, "gpio_in"),
3224 SUNXI_FUNCTION(0x1, "gpio_out"),
3225 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
3226 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
3227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
3228 SUNXI_FUNCTION(0x0, "gpio_in"),
3229 SUNXI_FUNCTION(0x1, "gpio_out"),
3230 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
3231 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
3232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
3233 SUNXI_FUNCTION(0x0, "gpio_in"),
3234 SUNXI_FUNCTION(0x1, "gpio_out"),
3235 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
3236 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
3237 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
3238 SUNXI_FUNCTION(0x0, "gpio_in"),
3239 SUNXI_FUNCTION(0x1, "gpio_out"),
3240 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
3241 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
3242 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
3243 SUNXI_FUNCTION(0x0, "gpio_in"),
3244 SUNXI_FUNCTION(0x1, "gpio_out"),
3245 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
3246 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
3247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
3248 SUNXI_FUNCTION(0x0, "gpio_in"),
3249 SUNXI_FUNCTION(0x1, "gpio_out"),
3250 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
3251 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
3252 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
3253 SUNXI_FUNCTION(0x0, "gpio_in"),
3254 SUNXI_FUNCTION(0x1, "gpio_out"),
3255 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
3256 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
3257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
3258 SUNXI_FUNCTION(0x0, "gpio_in"),
3259 SUNXI_FUNCTION(0x1, "gpio_out"),
3260 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
3261 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
3262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
3263 SUNXI_FUNCTION(0x0, "gpio_in"),
3264 SUNXI_FUNCTION(0x1, "gpio_out"),
3265 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
3266 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
3267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
3268 SUNXI_FUNCTION(0x0, "gpio_in"),
3269 SUNXI_FUNCTION(0x1, "gpio_out"),
3270 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
3271 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
3272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
3273 SUNXI_FUNCTION(0x0, "gpio_in"),
3274 SUNXI_FUNCTION(0x1, "gpio_out"),
3275 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
3276 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
3277 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
3278 SUNXI_FUNCTION(0x0, "gpio_in"),
3279 SUNXI_FUNCTION(0x1, "gpio_out"),
3280 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
3281 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
3282 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
3283 SUNXI_FUNCTION(0x0, "gpio_in"),
3284 SUNXI_FUNCTION(0x1, "gpio_out"),
3285 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
3286 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
3287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
3288 SUNXI_FUNCTION(0x0, "gpio_in"),
3289 SUNXI_FUNCTION(0x1, "gpio_out"),
3290 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
3291 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
3292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
3293 SUNXI_FUNCTION(0x0, "gpio_in"),
3294 SUNXI_FUNCTION(0x1, "gpio_out"),
3295 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
3296 SUNXI_FUNCTION(0x3, "sim")), /* DET */
3297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
3298 SUNXI_FUNCTION(0x0, "gpio_in"),
3299 SUNXI_FUNCTION(0x1, "gpio_out"),
3300 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
3301 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
3302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
3303 SUNXI_FUNCTION(0x0, "gpio_in"),
3304 SUNXI_FUNCTION(0x1, "gpio_out"),
3305 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
3306 SUNXI_FUNCTION(0x3, "sim")), /* RST */
3307 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
3308 SUNXI_FUNCTION(0x0, "gpio_in"),
3309 SUNXI_FUNCTION(0x1, "gpio_out"),
3310 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
3311 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
3312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
3313 SUNXI_FUNCTION(0x0, "gpio_in"),
3314 SUNXI_FUNCTION(0x1, "gpio_out"),
3315 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
3316 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
3317 /* Hole */
3318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
3319 SUNXI_FUNCTION(0x0, "gpio_in"),
3320 SUNXI_FUNCTION(0x1, "gpio_out"),
3321 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
3322 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
3323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
3324 SUNXI_FUNCTION(0x0, "gpio_in"),
3325 SUNXI_FUNCTION(0x1, "gpio_out"),
3326 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
3327 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
3328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
3329 SUNXI_FUNCTION(0x0, "gpio_in"),
3330 SUNXI_FUNCTION(0x1, "gpio_out"),
3331 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
3332 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
3333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
3334 SUNXI_FUNCTION(0x0, "gpio_in"),
3335 SUNXI_FUNCTION(0x1, "gpio_out"),
3336 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
3337 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
3338 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
3339 SUNXI_FUNCTION(0x0, "gpio_in"),
3340 SUNXI_FUNCTION(0x1, "gpio_out"),
3341 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
3342 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
3343 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
3344 SUNXI_FUNCTION(0x0, "gpio_in"),
3345 SUNXI_FUNCTION(0x1, "gpio_out"),
3346 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
3347 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
3348 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
3349 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
3350 SUNXI_FUNCTION(0x0, "gpio_in"),
3351 SUNXI_FUNCTION(0x1, "gpio_out"),
3352 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
3353 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
3354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
3355 SUNXI_FUNCTION(0x0, "gpio_in"),
3356 SUNXI_FUNCTION(0x1, "gpio_out"),
3357 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
3358 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
3359 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
3360 SUNXI_FUNCTION(0x0, "gpio_in"),
3361 SUNXI_FUNCTION(0x1, "gpio_out"),
3362 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
3363 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
3364 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
3365 SUNXI_FUNCTION(0x0, "gpio_in"),
3366 SUNXI_FUNCTION(0x1, "gpio_out"),
3367 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
3368 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
3369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
3370 SUNXI_FUNCTION(0x0, "gpio_in"),
3371 SUNXI_FUNCTION(0x1, "gpio_out"),
3372 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
3373 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
3374 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
3375 SUNXI_FUNCTION(0x0, "gpio_in"),
3376 SUNXI_FUNCTION(0x1, "gpio_out"),
3377 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
3378 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
3379 /* Hole */
3380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
3381 SUNXI_FUNCTION(0x0, "gpio_in"),
3382 SUNXI_FUNCTION(0x1, "gpio_out"),
3383 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
3384 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
3385 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
3386 SUNXI_FUNCTION(0x0, "gpio_in"),
3387 SUNXI_FUNCTION(0x1, "gpio_out"),
3388 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
3389 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
3390 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
3391 SUNXI_FUNCTION(0x0, "gpio_in"),
3392 SUNXI_FUNCTION(0x1, "gpio_out"),
3393 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
3394 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
3395 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
3396 SUNXI_FUNCTION(0x0, "gpio_in"),
3397 SUNXI_FUNCTION(0x1, "gpio_out"),
3398 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
3399 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
3400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
3401 SUNXI_FUNCTION(0x0, "gpio_in"),
3402 SUNXI_FUNCTION(0x1, "gpio_out"),
3403 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
3404 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
3405 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
3406 SUNXI_FUNCTION(0x0, "gpio_in"),
3407 SUNXI_FUNCTION(0x1, "gpio_out"),
3408 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
3409 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
3410 /* Hole */
3411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
3412 SUNXI_FUNCTION(0x0, "gpio_in"),
3413 SUNXI_FUNCTION(0x1, "gpio_out"),
3414 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
3415 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
3416 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
3417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
3418 SUNXI_FUNCTION(0x0, "gpio_in"),
3419 SUNXI_FUNCTION(0x1, "gpio_out"),
3420 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
3421 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
3422 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
3423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
3424 SUNXI_FUNCTION(0x0, "gpio_in"),
3425 SUNXI_FUNCTION(0x1, "gpio_out"),
3426 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
3427 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
3428 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
3429 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
3430 SUNXI_FUNCTION(0x0, "gpio_in"),
3431 SUNXI_FUNCTION(0x1, "gpio_out"),
3432 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
3433 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
3434 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
3435 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
3436 SUNXI_FUNCTION(0x0, "gpio_in"),
3437 SUNXI_FUNCTION(0x1, "gpio_out"),
3438 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
3439 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
3440 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
3441 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
3442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
3443 SUNXI_FUNCTION(0x0, "gpio_in"),
3444 SUNXI_FUNCTION(0x1, "gpio_out"),
3445 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
3446 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
3447 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
3448 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
3449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
3450 SUNXI_FUNCTION(0x0, "gpio_in"),
3451 SUNXI_FUNCTION(0x1, "gpio_out"),
3452 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
3453 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
3454 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3455 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
3456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
3457 SUNXI_FUNCTION(0x0, "gpio_in"),
3458 SUNXI_FUNCTION(0x1, "gpio_out"),
3459 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
3460 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
3461 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3462 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
3463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
3464 SUNXI_FUNCTION(0x0, "gpio_in"),
3465 SUNXI_FUNCTION(0x1, "gpio_out"),
3466 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
3467 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
3468 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3469 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
3470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
3471 SUNXI_FUNCTION(0x0, "gpio_in"),
3472 SUNXI_FUNCTION(0x1, "gpio_out"),
3473 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
3474 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
3475 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3476 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
3477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
3478 SUNXI_FUNCTION(0x0, "gpio_in"),
3479 SUNXI_FUNCTION(0x1, "gpio_out"),
3480 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
3481 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
3482 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3483 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
3484 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
3485 SUNXI_FUNCTION(0x0, "gpio_in"),
3486 SUNXI_FUNCTION(0x1, "gpio_out"),
3487 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
3488 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
3489 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3490 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
3491 /* Hole */
3492 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
3493 SUNXI_FUNCTION(0x0, "gpio_in"),
3494 SUNXI_FUNCTION(0x1, "gpio_out"),
3495 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
3496 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3497 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
3498 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
3499 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
3500 SUNXI_FUNCTION(0x0, "gpio_in"),
3501 SUNXI_FUNCTION(0x1, "gpio_out"),
3502 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
3503 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3504 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
3505 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
3506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
3507 SUNXI_FUNCTION(0x0, "gpio_in"),
3508 SUNXI_FUNCTION(0x1, "gpio_out"),
3509 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
3510 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3511 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
3512 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
3513 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
3514 SUNXI_FUNCTION(0x0, "gpio_in"),
3515 SUNXI_FUNCTION(0x1, "gpio_out"),
3516 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
3517 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3518 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
3519 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
3520 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
3521 SUNXI_FUNCTION(0x0, "gpio_in"),
3522 SUNXI_FUNCTION(0x1, "gpio_out"),
3523 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
3524 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3525 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
3526 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
3527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
3528 SUNXI_FUNCTION(0x0, "gpio_in"),
3529 SUNXI_FUNCTION(0x1, "gpio_out"),
3530 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
3531 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3532 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
3533 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
3534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
3535 SUNXI_FUNCTION(0x0, "gpio_in"),
3536 SUNXI_FUNCTION(0x1, "gpio_out"),
3537 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
3538 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
3539 SUNXI_FUNCTION(0x5, "ms"), /* BS */
3540 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
3541 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
3542 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
3543 SUNXI_FUNCTION(0x0, "gpio_in"),
3544 SUNXI_FUNCTION(0x1, "gpio_out"),
3545 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
3546 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
3547 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
3548 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
3549 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
3550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
3551 SUNXI_FUNCTION(0x0, "gpio_in"),
3552 SUNXI_FUNCTION(0x1, "gpio_out"),
3553 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
3554 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
3555 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
3556 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
3557 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
3558 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
3559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
3560 SUNXI_FUNCTION(0x0, "gpio_in"),
3561 SUNXI_FUNCTION(0x1, "gpio_out"),
3562 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
3563 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
3564 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
3565 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
3566 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
3567 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
3568 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
3569 SUNXI_FUNCTION(0x0, "gpio_in"),
3570 SUNXI_FUNCTION(0x1, "gpio_out"),
3571 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
3572 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
3573 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
3574 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
3575 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
3576 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
3577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
3578 SUNXI_FUNCTION(0x0, "gpio_in"),
3579 SUNXI_FUNCTION(0x1, "gpio_out"),
3580 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
3581 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
3582 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
3583 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
3584 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
3585 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
3586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
3587 SUNXI_FUNCTION(0x0, "gpio_in"),
3588 SUNXI_FUNCTION(0x1, "gpio_out"),
3589 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
3590 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
3591 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
3592 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
3593 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
3594 SUNXI_FUNCTION(0x0, "gpio_in"),
3595 SUNXI_FUNCTION(0x1, "gpio_out"),
3596 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
3597 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
3598 SUNXI_FUNCTION(0x5, "sim"), /* RST */
3599 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
3600 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
3601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
3602 SUNXI_FUNCTION(0x0, "gpio_in"),
3603 SUNXI_FUNCTION(0x1, "gpio_out"),
3604 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
3605 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3606 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
3607 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
3608 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
3609 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
3610 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
3611 SUNXI_FUNCTION(0x0, "gpio_in"),
3612 SUNXI_FUNCTION(0x1, "gpio_out"),
3613 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
3614 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3615 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
3616 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
3617 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
3618 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
3619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
3620 SUNXI_FUNCTION(0x0, "gpio_in"),
3621 SUNXI_FUNCTION(0x1, "gpio_out"),
3622 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
3623 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
3624 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
3625 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
3626 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
3627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
3628 SUNXI_FUNCTION(0x0, "gpio_in"),
3629 SUNXI_FUNCTION(0x1, "gpio_out"),
3630 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
3631 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
3632 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
3633 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
3634 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
3635 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
3636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
3637 SUNXI_FUNCTION(0x0, "gpio_in"),
3638 SUNXI_FUNCTION(0x1, "gpio_out"),
3639 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
3640 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
3641 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
3642 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
3643 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
3644 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
3645 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
3646 SUNXI_FUNCTION(0x0, "gpio_in"),
3647 SUNXI_FUNCTION(0x1, "gpio_out"),
3648 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
3649 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
3650 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
3651 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
3652 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
3653 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
3654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
3655 SUNXI_FUNCTION(0x0, "gpio_in"),
3656 SUNXI_FUNCTION(0x1, "gpio_out"),
3657 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
3658 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
3659 SUNXI_FUNCTION(0x4, "can"), /* TX */
3660 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
3661 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
3662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
3663 SUNXI_FUNCTION(0x0, "gpio_in"),
3664 SUNXI_FUNCTION(0x1, "gpio_out"),
3665 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
3666 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
3667 SUNXI_FUNCTION(0x4, "can"), /* RX */
3668 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
3669 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
3670 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
3671 SUNXI_FUNCTION(0x0, "gpio_in"),
3672 SUNXI_FUNCTION(0x1, "gpio_out"),
3673 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
3674 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
3675 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
3676 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
3677 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
3678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
3679 SUNXI_FUNCTION(0x0, "gpio_in"),
3680 SUNXI_FUNCTION(0x1, "gpio_out"),
3681 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
3682 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
3683 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
3684 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
3685 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
3686 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
3687 SUNXI_FUNCTION(0x0, "gpio_in"),
3688 SUNXI_FUNCTION(0x1, "gpio_out"),
3689 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
3690 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
3691 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
3692 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
3693 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
3694 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
3695 SUNXI_FUNCTION(0x0, "gpio_in"),
3696 SUNXI_FUNCTION(0x1, "gpio_out"),
3697 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
3698 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
3699 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
3700 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
3701 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
3702 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
3703 SUNXI_FUNCTION(0x0, "gpio_in"),
3704 SUNXI_FUNCTION(0x1, "gpio_out"),
3705 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
3706 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
3707 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
3708 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
3709 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
3710 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
3711 SUNXI_FUNCTION(0x0, "gpio_in"),
3712 SUNXI_FUNCTION(0x1, "gpio_out"),
3713 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
3714 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
3715 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
3716 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
3717 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
3718 /* Hole */
3719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
3720 SUNXI_FUNCTION(0x0, "gpio_in"),
3721 SUNXI_FUNCTION(0x1, "gpio_out"),
3722 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
3723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
3724 SUNXI_FUNCTION(0x0, "gpio_in"),
3725 SUNXI_FUNCTION(0x1, "gpio_out"),
3726 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
3727 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
3728 SUNXI_FUNCTION(0x0, "gpio_in"),
3729 SUNXI_FUNCTION(0x1, "gpio_out"),
3730 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
3731 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
3732 SUNXI_FUNCTION(0x0, "gpio_in"),
3733 SUNXI_FUNCTION(0x1, "gpio_out"),
3734 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
3735 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
3736 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
3737 SUNXI_FUNCTION(0x0, "gpio_in"),
3738 SUNXI_FUNCTION(0x1, "gpio_out"),
3739 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
3740 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
3741 SUNXI_FUNCTION(0x0, "gpio_in"),
3742 SUNXI_FUNCTION(0x1, "gpio_out"),
3743 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
3744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
3745 SUNXI_FUNCTION(0x0, "gpio_in"),
3746 SUNXI_FUNCTION(0x1, "gpio_out"),
3747 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
3748 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
3749 SUNXI_FUNCTION(0x0, "gpio_in"),
3750 SUNXI_FUNCTION(0x1, "gpio_out"),
3751 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
3752 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
3753 SUNXI_FUNCTION(0x0, "gpio_in"),
3754 SUNXI_FUNCTION(0x1, "gpio_out"),
3755 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
3756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
3757 SUNXI_FUNCTION(0x0, "gpio_in"),
3758 SUNXI_FUNCTION(0x1, "gpio_out"),
3759 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
3760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
3761 SUNXI_FUNCTION(0x0, "gpio_in"),
3762 SUNXI_FUNCTION(0x1, "gpio_out"),
3763 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
3764 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
3765 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
3766 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
3767 SUNXI_FUNCTION(0x0, "gpio_in"),
3768 SUNXI_FUNCTION(0x1, "gpio_out"),
3769 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
3770 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
3771 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
3772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
3773 SUNXI_FUNCTION(0x0, "gpio_in"),
3774 SUNXI_FUNCTION(0x1, "gpio_out"),
3775 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
3776 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
3777 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
3778 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
3779 SUNXI_FUNCTION(0x0, "gpio_in"),
3780 SUNXI_FUNCTION(0x1, "gpio_out"),
3781 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
3782 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
3783 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
3784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
3785 SUNXI_FUNCTION(0x0, "gpio_in"),
3786 SUNXI_FUNCTION(0x1, "gpio_out"),
3787 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
3788 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
3789 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
3790 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
3791 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
3792 SUNXI_FUNCTION(0x0, "gpio_in"),
3793 SUNXI_FUNCTION(0x1, "gpio_out"),
3794 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
3795 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
3796 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
3797 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
3798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
3799 SUNXI_FUNCTION(0x0, "gpio_in"),
3800 SUNXI_FUNCTION(0x1, "gpio_out"),
3801 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
3802 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
3803 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
3804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
3805 SUNXI_FUNCTION(0x0, "gpio_in"),
3806 SUNXI_FUNCTION(0x1, "gpio_out"),
3807 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
3808 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
3809 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
3810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
3811 SUNXI_FUNCTION(0x0, "gpio_in"),
3812 SUNXI_FUNCTION(0x1, "gpio_out"),
3813 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
3814 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
3815 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
3816 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
3817 SUNXI_FUNCTION(0x0, "gpio_in"),
3818 SUNXI_FUNCTION(0x1, "gpio_out"),
3819 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
3820 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
3821 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
3822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
3823 SUNXI_FUNCTION(0x0, "gpio_in"),
3824 SUNXI_FUNCTION(0x1, "gpio_out"),
3825 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
3826 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
3827 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
3828 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
3829 SUNXI_FUNCTION(0x0, "gpio_in"),
3830 SUNXI_FUNCTION(0x1, "gpio_out"),
3831 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
3832 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
3833 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
3834};
3835
2823static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 3836static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
2824 .pins = sun4i_a10_pins, 3837 .pins = sun4i_a10_pins,
2825 .npins = ARRAY_SIZE(sun4i_a10_pins), 3838 .npins = ARRAY_SIZE(sun4i_a10_pins),
@@ -2840,4 +3853,9 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
2840 .npins = ARRAY_SIZE(sun6i_a31_pins), 3853 .npins = ARRAY_SIZE(sun6i_a31_pins),
2841}; 3854};
2842 3855
3856static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
3857 .pins = sun7i_a20_pins,
3858 .npins = ARRAY_SIZE(sun7i_a20_pins),
3859};
3860
2843#endif /* __PINCTRL_SUNXI_PINS_H */ 3861#endif /* __PINCTRL_SUNXI_PINS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 10:31:29 -0500