pinctrl/nomadik: support other alternate-C functions

Upgrade nomadik pinctrl driver to enable selection of other
alternate-C[1-4] functions on some specific ux500 SoC pins.
Handling of those functions is done thanks to PRCM GPIOCR
registers. This was previously managed in PRCMU driver and
it was not really convenient. Idea is to provide a common
way to control all alternate functions.

Note that this improvement does not support the old-fashioned way
used to control nomadik pins, namely the "nmk_config_pin()" function
and its derivatives.

Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@stericsson.com>
Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 303 insertions, 41 deletions

diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
index 3daf665c84c3..52fc30181f7e 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8540.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -778,50 +778,50 @@ static const struct nmk_pingroup nmk_db8540_groups[] = {
         DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
         DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
 
-        /* Other alt C1 column, these are still configured as alt C */
-        DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C),
+        /* Other alt C1 column */
+        DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C1),
+        DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C1),
 
-        /* Other alt C2 column, these are still configured as alt C */
-        DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C),
+        /* Other alt C2 column */
+        DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C2),
+        DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C2),
 
-        /* Other alt C3 column, these are still configured as alt C */
-        DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C),
+        /* Other alt C3 column */
+        DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C3),
+        DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C3),
 
-        /* Other alt C4 column, these are still configured as alt C */
-        DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C),
-        DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C),
+        /* Other alt C4 column */
+        DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C4),
+        DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C4),
+        DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C4),
+        DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C4),
+        DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C4),
+        DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C4),
 
 };
 
@@ -981,6 +981,265 @@ static const struct nmk_function nmk_db8540_functions[] = {
         FUNCTION(usb)
 };
 
+static const struct prcm_gpiocr_altcx_pin_desc db8540_altcx_pins[] = {
+        PRCM_GPIOCR_ALTCX(8,    true, PRCM_IDX_GPIOCR1, 20,     /* SPI3_CLK */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(9,    true, PRCM_IDX_GPIOCR1, 20,     /* SPI3_RXD */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(10,   true, PRCM_IDX_GPIOCR1, 20,     /* SPI3_FRM */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(11,   true, PRCM_IDX_GPIOCR1, 20,     /* SPI3_TXD */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(23,   true, PRCM_IDX_GPIOCR1, 9,      /* STMAPE_CLK_a */
+                                true, PRCM_IDX_GPIOCR2, 10,     /* SBAG_CLK_a */
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(24,   true, PRCM_IDX_GPIOCR3, 30,     /* U2_RXD_g */
+                                true, PRCM_IDX_GPIOCR2, 10,     /* SBAG_VAL_a */
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(25,   true, PRCM_IDX_GPIOCR1, 9,      /* STMAPE_DAT_a[0] */
+                                true, PRCM_IDX_GPIOCR2, 10,     /* SBAG_D_a[0] */
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(26,   true, PRCM_IDX_GPIOCR1, 9,      /* STMAPE_DAT_a[1] */
+                                true, PRCM_IDX_GPIOCR2, 10,     /* SBAG_D_a[1] */
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(27,   true, PRCM_IDX_GPIOCR1, 9,      /* STMAPE_DAT_a[2] */
+                                true, PRCM_IDX_GPIOCR2, 10,     /* SBAG_D_a[2] */
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(28,   true, PRCM_IDX_GPIOCR1, 9,      /* STMAPE_DAT_a[3] */
+                                true, PRCM_IDX_GPIOCR2, 10,     /* SBAG_D_a[3] */
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(64,   true, PRCM_IDX_GPIOCR1, 15,     /* MODOBS_REFCLK_REQ */
+                                false, 0, 0,
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_CTL */
+                                true, PRCM_IDX_GPIOCR2, 23      /* HW_OBS_APE_PRCMU[17] */
+        ),
+        PRCM_GPIOCR_ALTCX(65,   true, PRCM_IDX_GPIOCR1, 19,     /* MODOBS_PWRCTRL0 */
+                                true, PRCM_IDX_GPIOCR1, 24,     /* Hx_CLK */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_CLK */
+                                true, PRCM_IDX_GPIOCR2, 24      /* HW_OBS_APE_PRCMU[16] */
+        ),
+        PRCM_GPIOCR_ALTCX(66,   true, PRCM_IDX_GPIOCR1, 15,     /* MODOBS_CLKOUT1 */
+                                false, 0, 0,
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[15] */
+                                true, PRCM_IDX_GPIOCR2, 25      /* HW_OBS_APE_PRCMU[15] */
+        ),
+        PRCM_GPIOCR_ALTCX(67,   true, PRCM_IDX_GPIOCR1, 1,      /* MODUART1_TXD_a */
+                                true, PRCM_IDX_GPIOCR1, 6,      /* MODACCUART_TXD_a */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[14] */
+                                true, PRCM_IDX_GPIOCR2, 26      /* HW_OBS_APE_PRCMU[14] */
+        ),
+        PRCM_GPIOCR_ALTCX(70,   true, PRCM_IDX_GPIOCR3, 6,      /* MOD_PRCMU_DEBUG[17] */
+                                true, PRCM_IDX_GPIOCR1, 10,     /* STMMOD_CLK_b */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[13] */
+                                true, PRCM_IDX_GPIOCR2, 27      /* HW_OBS_APE_PRCMU[13] */
+        ),
+        PRCM_GPIOCR_ALTCX(71,   true, PRCM_IDX_GPIOCR3, 6,      /* MOD_PRCMU_DEBUG[16] */
+                                true, PRCM_IDX_GPIOCR1, 10,     /* STMMOD_DAT_b[3] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[12] */
+                                true, PRCM_IDX_GPIOCR2, 27      /* HW_OBS_APE_PRCMU[12] */
+        ),
+        PRCM_GPIOCR_ALTCX(72,   true, PRCM_IDX_GPIOCR3, 6,      /* MOD_PRCMU_DEBUG[15] */
+                                true, PRCM_IDX_GPIOCR1, 10,     /* STMMOD_DAT_b[2] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[11] */
+                                true, PRCM_IDX_GPIOCR2, 27      /* HW_OBS_APE_PRCMU[11] */
+        ),
+        PRCM_GPIOCR_ALTCX(73,   true, PRCM_IDX_GPIOCR3, 6,      /* MOD_PRCMU_DEBUG[14] */
+                                true, PRCM_IDX_GPIOCR1, 10,     /* STMMOD_DAT_b[1] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[10] */
+                                true, PRCM_IDX_GPIOCR2, 27      /* HW_OBS_APE_PRCMU[10] */
+        ),
+        PRCM_GPIOCR_ALTCX(74,   true, PRCM_IDX_GPIOCR3, 6,      /* MOD_PRCMU_DEBUG[13] */
+                                true, PRCM_IDX_GPIOCR1, 10,     /* STMMOD_DAT_b[0] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[9] */
+                                true, PRCM_IDX_GPIOCR2, 27      /* HW_OBS_APE_PRCMU[9] */
+        ),
+        PRCM_GPIOCR_ALTCX(75,   true, PRCM_IDX_GPIOCR1, 12,     /* MODOBS_RESOUT0_N */
+                                true, PRCM_IDX_GPIOCR2, 1,      /* MODUART_STMMUX_RXD_b */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[8] */
+                                true, PRCM_IDX_GPIOCR2, 28      /* HW_OBS_APE_PRCMU[8] */
+        ),
+        PRCM_GPIOCR_ALTCX(76,   true, PRCM_IDX_GPIOCR3, 7,      /* MOD_PRCMU_DEBUG[12] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[7] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[7] */
+                                true, PRCM_IDX_GPIOCR2, 29      /* HW_OBS_APE_PRCMU[7] */
+        ),
+        PRCM_GPIOCR_ALTCX(77,   true, PRCM_IDX_GPIOCR3, 7,      /* MOD_PRCMU_DEBUG[11] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[6] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[6] */
+                                true, PRCM_IDX_GPIOCR2, 29      /* HW_OBS_APE_PRCMU[6] */
+        ),
+        PRCM_GPIOCR_ALTCX(78,   true, PRCM_IDX_GPIOCR3, 7,      /* MOD_PRCMU_DEBUG[10] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[5] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[5] */
+                                true, PRCM_IDX_GPIOCR2, 29      /* HW_OBS_APE_PRCMU[5] */
+        ),
+        PRCM_GPIOCR_ALTCX(79,   true, PRCM_IDX_GPIOCR3, 7,      /* MOD_PRCMU_DEBUG[9] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[4] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[4] */
+                                true, PRCM_IDX_GPIOCR2, 29      /* HW_OBS_APE_PRCMU[4] */
+        ),
+        PRCM_GPIOCR_ALTCX(80,   true, PRCM_IDX_GPIOCR1, 26,     /* MODACC_GPO[0] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[3] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[3] */
+                                true, PRCM_IDX_GPIOCR2, 30      /* HW_OBS_APE_PRCMU[3] */
+        ),
+        PRCM_GPIOCR_ALTCX(81,   true, PRCM_IDX_GPIOCR2, 17,     /* MODACC_GPO[1] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[2] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[2] */
+                                true, PRCM_IDX_GPIOCR2, 30      /* HW_OBS_APE_PRCMU[2] */
+        ),
+        PRCM_GPIOCR_ALTCX(82,   true, PRCM_IDX_GPIOCR3, 8,      /* MOD_PRCMU_DEBUG[8] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[1] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[1] */
+                                true, PRCM_IDX_GPIOCR2, 31      /* HW_OBS_APE_PRCMU[1] */
+        ),
+        PRCM_GPIOCR_ALTCX(83,   true, PRCM_IDX_GPIOCR3, 8,      /* MOD_PRCMU_DEBUG[7] */
+                                true, PRCM_IDX_GPIOCR1, 25,     /* Hx_GPIO[0] */
+                                true, PRCM_IDX_GPIOCR1, 2,      /* TPIU_D[0] */
+                                true, PRCM_IDX_GPIOCR2, 31      /* HW_OBS_APE_PRCMU[0] */
+        ),
+        PRCM_GPIOCR_ALTCX(84,   true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[6] */
+                                true, PRCM_IDX_GPIOCR1, 8,      /* SBAG_CLK_b */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[23] */
+                                true, PRCM_IDX_GPIOCR1, 16      /* MODUART1_RXD_b */
+        ),
+        PRCM_GPIOCR_ALTCX(85,   true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[5] */
+                                true, PRCM_IDX_GPIOCR1, 8,      /* SBAG_D_b[3] */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[22] */
+                                true, PRCM_IDX_GPIOCR1, 16      /* MODUART1_TXD_b */
+        ),
+        PRCM_GPIOCR_ALTCX(86,   true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[0] */
+                                true, PRCM_IDX_GPIOCR2, 18,     /* STMAPE_DAT_b[0] */
+                                true, PRCM_IDX_GPIOCR1, 14,     /* TPIU_D[25] */
+                                true, PRCM_IDX_GPIOCR1, 11      /* STMMOD_DAT_c[0] */
+        ),
+        PRCM_GPIOCR_ALTCX(87,   true, PRCM_IDX_GPIOCR3, 0,      /* MODACC_GPO_a[5] */
+                                true, PRCM_IDX_GPIOCR2, 3,      /* U2_RXD_c */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[24] */
+                                true, PRCM_IDX_GPIOCR1, 21      /* MODUART_STMMUX_RXD_c */
+        ),
+        PRCM_GPIOCR_ALTCX(151,  true, PRCM_IDX_GPIOCR1, 18,     /* REMAP0 */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(152,  true, PRCM_IDX_GPIOCR1, 18,     /* REMAP1 */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(153,  true, PRCM_IDX_GPIOCR3, 2,      /* KP_O_b[6] */
+                                true, PRCM_IDX_GPIOCR1, 8,      /* SBAG_D_b[2] */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[21] */
+                                true, PRCM_IDX_GPIOCR1, 0       /* MODUART1_RTS */
+        ),
+        PRCM_GPIOCR_ALTCX(154,  true, PRCM_IDX_GPIOCR3, 2,      /* KP_I_b[6] */
+                                true, PRCM_IDX_GPIOCR1, 8,      /* SBAG_D_b[1] */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[20] */
+                                true, PRCM_IDX_GPIOCR1, 0       /* MODUART1_CTS */
+        ),
+        PRCM_GPIOCR_ALTCX(155,  true, PRCM_IDX_GPIOCR3, 3,      /* KP_O_b[5] */
+                                true, PRCM_IDX_GPIOCR1, 8,      /* SBAG_D_b[0] */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[19] */
+                                true, PRCM_IDX_GPIOCR1, 5       /* MODACCUART_RXD_c */
+        ),
+        PRCM_GPIOCR_ALTCX(156,  true, PRCM_IDX_GPIOCR3, 3,      /* KP_O_b[4] */
+                                true, PRCM_IDX_GPIOCR1, 8,      /* SBAG_VAL_b */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[18] */
+                                true, PRCM_IDX_GPIOCR1, 5       /* MODACCUART_TXD_b */
+        ),
+        PRCM_GPIOCR_ALTCX(157,  true, PRCM_IDX_GPIOCR3, 4,      /* KP_I_b[5] */
+                                true, PRCM_IDX_GPIOCR1, 23,     /* MODOBS_SERVICE_N */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[17] */
+                                true, PRCM_IDX_GPIOCR1, 14      /* MODACCUART_RTS */
+        ),
+        PRCM_GPIOCR_ALTCX(158,  true, PRCM_IDX_GPIOCR3, 4,      /* KP_I_b[4] */
+                                true, PRCM_IDX_GPIOCR2, 0,      /* U2_TXD_c */
+                                true, PRCM_IDX_GPIOCR1, 3,      /* TPIU_D[16] */
+                                true, PRCM_IDX_GPIOCR1, 14      /* MODACCUART_CTS */
+        ),
+        PRCM_GPIOCR_ALTCX(159,  true, PRCM_IDX_GPIOCR3, 5,      /* KP_O_b[3] */
+                                true, PRCM_IDX_GPIOCR3, 10,     /* MODUART0_RXD */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[31] */
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(160,  true, PRCM_IDX_GPIOCR3, 5,      /* KP_I_b[3] */
+                                true, PRCM_IDX_GPIOCR3, 10,     /* MODUART0_TXD */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[30] */
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(161,  true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[4] */
+                                true, PRCM_IDX_GPIOCR2, 18,     /* STMAPE_CLK_b */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[29] */
+                                true, PRCM_IDX_GPIOCR1, 11      /* STMMOD_CLK_c */
+        ),
+        PRCM_GPIOCR_ALTCX(162,  true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[3] */
+                                true, PRCM_IDX_GPIOCR2, 18,     /* STMAPE_DAT_b[3] */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[28] */
+                                true, PRCM_IDX_GPIOCR1, 11      /* STMMOD_DAT_c[3] */
+        ),
+        PRCM_GPIOCR_ALTCX(163,  true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[2] */
+                                true, PRCM_IDX_GPIOCR2, 18,     /* STMAPE_DAT_b[2] */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[27] */
+                                true, PRCM_IDX_GPIOCR1, 11      /* STMMOD_DAT_c[2] */
+        ),
+        PRCM_GPIOCR_ALTCX(164,  true, PRCM_IDX_GPIOCR3, 9,      /* MOD_PRCMU_DEBUG[1] */
+                                true, PRCM_IDX_GPIOCR2, 18,     /* STMAPE_DAT_b[1] */
+                                true, PRCM_IDX_GPIOCR1, 4,      /* TPIU_D[26] */
+                                true, PRCM_IDX_GPIOCR1, 11      /* STMMOD_DAT_c[1] */
+        ),
+        PRCM_GPIOCR_ALTCX(204,  true, PRCM_IDX_GPIOCR2, 2,      /* U2_RXD_f */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(205,  true, PRCM_IDX_GPIOCR2, 2,      /* U2_TXD_f */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(206,  true, PRCM_IDX_GPIOCR2, 2,      /* U2_CTSn_b */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+        PRCM_GPIOCR_ALTCX(207,  true, PRCM_IDX_GPIOCR2, 2,      /* U2_RTSn_b */
+                                false, 0, 0,
+                                false, 0, 0,
+                                false, 0, 0
+        ),
+};
+
+static const u16 db8540_prcm_gpiocr_regs[] = {
+        [PRCM_IDX_GPIOCR1] = 0x138,
+        [PRCM_IDX_GPIOCR2] = 0x574,
+        [PRCM_IDX_GPIOCR3] = 0x2bc,
+};
+
 static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
         .gpio_ranges = nmk_db8540_ranges,
         .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
@@ -990,6 +1249,9 @@ static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
         .nfunctions = ARRAY_SIZE(nmk_db8540_functions),
         .groups = nmk_db8540_groups,
         .ngroups = ARRAY_SIZE(nmk_db8540_groups),
+        .altcx_pins = db8540_altcx_pins,
+        .npins_altcx = ARRAY_SIZE(db8540_altcx_pins),
+        .prcm_gpiocr_registers = db8540_prcm_gpiocr_regs,
 };
 
 void __devinit