diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2013-02-19 21:32:52 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-04-09 10:52:50 -0400 |
| commit | e16415313c9b00b1adc313e85c2c8a81febe0b98 (patch) | |
| tree | b1e804b1bb647f3984036d9f9befbe53023bc519 /drivers/pinctrl/pinctrl-imx51.c | |
| parent | 36dffd8f49bc1364998db81bee739ea4574d88f7 (diff) | |
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-imx51.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-imx51.c | 1532 |
1 files changed, 507 insertions, 1025 deletions
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c index 9a92aaad150f..db268b920079 100644 --- a/drivers/pinctrl/pinctrl-imx51.c +++ b/drivers/pinctrl/pinctrl-imx51.c | |||
| @@ -23,1015 +23,400 @@ | |||
| 23 | #include "pinctrl-imx.h" | 23 | #include "pinctrl-imx.h" |
| 24 | 24 | ||
| 25 | enum imx51_pads { | 25 | enum imx51_pads { |
| 26 | MX51_PAD_EIM_D16 = 0, | 26 | MX51_PAD_RESERVE0 = 0, |
| 27 | MX51_PAD_EIM_D17 = 1, | 27 | MX51_PAD_RESERVE1 = 1, |
| 28 | MX51_PAD_EIM_D18 = 2, | 28 | MX51_PAD_RESERVE2 = 2, |
| 29 | MX51_PAD_EIM_D19 = 3, | 29 | MX51_PAD_RESERVE3 = 3, |
| 30 | MX51_PAD_EIM_D20 = 4, | 30 | MX51_PAD_RESERVE4 = 4, |
| 31 | MX51_PAD_EIM_D21 = 5, | 31 | MX51_PAD_RESERVE5 = 5, |
| 32 | MX51_PAD_EIM_D22 = 6, | 32 | MX51_PAD_RESERVE6 = 6, |
| 33 | MX51_PAD_EIM_D23 = 7, | 33 | MX51_PAD_EIM_DA0 = 7, |
| 34 | MX51_PAD_EIM_D24 = 8, | 34 | MX51_PAD_EIM_DA1 = 8, |
| 35 | MX51_PAD_EIM_D25 = 9, | 35 | MX51_PAD_EIM_DA2 = 9, |
| 36 | MX51_PAD_EIM_D26 = 10, | 36 | MX51_PAD_EIM_DA3 = 10, |
| 37 | MX51_PAD_EIM_D27 = 11, | 37 | MX51_PAD_EIM_DA4 = 11, |
| 38 | MX51_PAD_EIM_D28 = 12, | 38 | MX51_PAD_EIM_DA5 = 12, |
| 39 | MX51_PAD_EIM_D29 = 13, | 39 | MX51_PAD_EIM_DA6 = 13, |
| 40 | MX51_PAD_EIM_D30 = 14, | 40 | MX51_PAD_EIM_DA7 = 14, |
| 41 | MX51_PAD_EIM_D31 = 15, | 41 | MX51_PAD_EIM_DA8 = 15, |
| 42 | MX51_PAD_EIM_A16 = 16, | 42 | MX51_PAD_EIM_DA9 = 16, |
| 43 | MX51_PAD_EIM_A17 = 17, | 43 | MX51_PAD_EIM_DA10 = 17, |
| 44 | MX51_PAD_EIM_A18 = 18, | 44 | MX51_PAD_EIM_DA11 = 18, |
| 45 | MX51_PAD_EIM_A19 = 19, | 45 | MX51_PAD_EIM_DA12 = 19, |
| 46 | MX51_PAD_EIM_A20 = 20, | 46 | MX51_PAD_EIM_DA13 = 20, |
| 47 | MX51_PAD_EIM_A21 = 21, | 47 | MX51_PAD_EIM_DA14 = 21, |
| 48 | MX51_PAD_EIM_A22 = 22, | 48 | MX51_PAD_EIM_DA15 = 22, |
| 49 | MX51_PAD_EIM_A23 = 23, | 49 | MX51_PAD_EIM_D16 = 23, |
| 50 | MX51_PAD_EIM_A24 = 24, | 50 | MX51_PAD_EIM_D17 = 24, |
| 51 | MX51_PAD_EIM_A25 = 25, | 51 | MX51_PAD_EIM_D18 = 25, |
| 52 | MX51_PAD_EIM_A26 = 26, | 52 | MX51_PAD_EIM_D19 = 26, |
| 53 | MX51_PAD_EIM_A27 = 27, | 53 | MX51_PAD_EIM_D20 = 27, |
| 54 | MX51_PAD_EIM_EB0 = 28, | 54 | MX51_PAD_EIM_D21 = 28, |
| 55 | MX51_PAD_EIM_EB1 = 29, | 55 | MX51_PAD_EIM_D22 = 29, |
| 56 | MX51_PAD_EIM_EB2 = 30, | 56 | MX51_PAD_EIM_D23 = 30, |
| 57 | MX51_PAD_EIM_EB3 = 31, | 57 | MX51_PAD_EIM_D24 = 31, |
| 58 | MX51_PAD_EIM_OE = 32, | 58 | MX51_PAD_EIM_D25 = 32, |
| 59 | MX51_PAD_EIM_CS0 = 33, | 59 | MX51_PAD_EIM_D26 = 33, |
| 60 | MX51_PAD_EIM_CS1 = 34, | 60 | MX51_PAD_EIM_D27 = 34, |
| 61 | MX51_PAD_EIM_CS2 = 35, | 61 | MX51_PAD_EIM_D28 = 35, |
| 62 | MX51_PAD_EIM_CS3 = 36, | 62 | MX51_PAD_EIM_D29 = 36, |
| 63 | MX51_PAD_EIM_CS4 = 37, | 63 | MX51_PAD_EIM_D30 = 37, |
| 64 | MX51_PAD_EIM_CS5 = 38, | 64 | MX51_PAD_EIM_D31 = 38, |
| 65 | MX51_PAD_EIM_DTACK = 39, | 65 | MX51_PAD_EIM_A16 = 39, |
| 66 | MX51_PAD_EIM_LBA = 40, | 66 | MX51_PAD_EIM_A17 = 40, |
| 67 | MX51_PAD_EIM_CRE = 41, | 67 | MX51_PAD_EIM_A18 = 41, |
| 68 | MX51_PAD_DRAM_CS1 = 42, | 68 | MX51_PAD_EIM_A19 = 42, |
| 69 | MX51_PAD_NANDF_WE_B = 43, | 69 | MX51_PAD_EIM_A20 = 43, |
| 70 | MX51_PAD_NANDF_RE_B = 44, | 70 | MX51_PAD_EIM_A21 = 44, |
| 71 | MX51_PAD_NANDF_ALE = 45, | 71 | MX51_PAD_EIM_A22 = 45, |
| 72 | MX51_PAD_NANDF_CLE = 46, | 72 | MX51_PAD_EIM_A23 = 46, |
| 73 | MX51_PAD_NANDF_WP_B = 47, | 73 | MX51_PAD_EIM_A24 = 47, |
| 74 | MX51_PAD_NANDF_RB0 = 48, | 74 | MX51_PAD_EIM_A25 = 48, |
| 75 | MX51_PAD_NANDF_RB1 = 49, | 75 | MX51_PAD_EIM_A26 = 49, |
| 76 | MX51_PAD_NANDF_RB2 = 50, | 76 | MX51_PAD_EIM_A27 = 50, |
| 77 | MX51_PAD_NANDF_RB3 = 51, | 77 | MX51_PAD_EIM_EB0 = 51, |
| 78 | MX51_PAD_GPIO_NAND = 52, | 78 | MX51_PAD_EIM_EB1 = 52, |
| 79 | MX51_PAD_NANDF_CS0 = 53, | 79 | MX51_PAD_EIM_EB2 = 53, |
| 80 | MX51_PAD_NANDF_CS1 = 54, | 80 | MX51_PAD_EIM_EB3 = 54, |
| 81 | MX51_PAD_NANDF_CS2 = 55, | 81 | MX51_PAD_EIM_OE = 55, |
| 82 | MX51_PAD_NANDF_CS3 = 56, | 82 | MX51_PAD_EIM_CS0 = 56, |
| 83 | MX51_PAD_NANDF_CS4 = 57, | 83 | MX51_PAD_EIM_CS1 = 57, |
| 84 | MX51_PAD_NANDF_CS5 = 58, | 84 | MX51_PAD_EIM_CS2 = 58, |
| 85 | MX51_PAD_NANDF_CS6 = 59, | 85 | MX51_PAD_EIM_CS3 = 59, |
| 86 | MX51_PAD_NANDF_CS7 = 60, | 86 | MX51_PAD_EIM_CS4 = 60, |
| 87 | MX51_PAD_NANDF_RDY_INT = 61, | 87 | MX51_PAD_EIM_CS5 = 61, |
| 88 | MX51_PAD_NANDF_D15 = 62, | 88 | MX51_PAD_EIM_DTACK = 62, |
| 89 | MX51_PAD_NANDF_D14 = 63, | 89 | MX51_PAD_EIM_LBA = 63, |
| 90 | MX51_PAD_NANDF_D13 = 64, | 90 | MX51_PAD_EIM_CRE = 64, |
| 91 | MX51_PAD_NANDF_D12 = 65, | 91 | MX51_PAD_DRAM_CS1 = 65, |
| 92 | MX51_PAD_NANDF_D11 = 66, | 92 | MX51_PAD_NANDF_WE_B = 66, |
| 93 | MX51_PAD_NANDF_D10 = 67, | 93 | MX51_PAD_NANDF_RE_B = 67, |
| 94 | MX51_PAD_NANDF_D9 = 68, | 94 | MX51_PAD_NANDF_ALE = 68, |
| 95 | MX51_PAD_NANDF_D8 = 69, | 95 | MX51_PAD_NANDF_CLE = 69, |
| 96 | MX51_PAD_NANDF_D7 = 70, | 96 | MX51_PAD_NANDF_WP_B = 70, |
| 97 | MX51_PAD_NANDF_D6 = 71, | 97 | MX51_PAD_NANDF_RB0 = 71, |
| 98 | MX51_PAD_NANDF_D5 = 72, | 98 | MX51_PAD_NANDF_RB1 = 72, |
| 99 | MX51_PAD_NANDF_D4 = 73, | 99 | MX51_PAD_NANDF_RB2 = 73, |
| 100 | MX51_PAD_NANDF_D3 = 74, | 100 | MX51_PAD_NANDF_RB3 = 74, |
| 101 | MX51_PAD_NANDF_D2 = 75, | 101 | MX51_PAD_GPIO_NAND = 75, |
| 102 | MX51_PAD_NANDF_D1 = 76, | 102 | MX51_PAD_NANDF_CS0 = 76, |
| 103 | MX51_PAD_NANDF_D0 = 77, | 103 | MX51_PAD_NANDF_CS1 = 77, |
| 104 | MX51_PAD_CSI1_D8 = 78, | 104 | MX51_PAD_NANDF_CS2 = 78, |
| 105 | MX51_PAD_CSI1_D9 = 79, | 105 | MX51_PAD_NANDF_CS3 = 79, |
| 106 | MX51_PAD_CSI1_D10 = 80, | 106 | MX51_PAD_NANDF_CS4 = 80, |
| 107 | MX51_PAD_CSI1_D11 = 81, | 107 | MX51_PAD_NANDF_CS5 = 81, |
| 108 | MX51_PAD_CSI1_D12 = 82, | 108 | MX51_PAD_NANDF_CS6 = 82, |
| 109 | MX51_PAD_CSI1_D13 = 83, | 109 | MX51_PAD_NANDF_CS7 = 83, |
| 110 | MX51_PAD_CSI1_D14 = 84, | 110 | MX51_PAD_NANDF_RDY_INT = 84, |
| 111 | MX51_PAD_CSI1_D15 = 85, | 111 | MX51_PAD_NANDF_D15 = 85, |
| 112 | MX51_PAD_CSI1_D16 = 86, | 112 | MX51_PAD_NANDF_D14 = 86, |
| 113 | MX51_PAD_CSI1_D17 = 87, | 113 | MX51_PAD_NANDF_D13 = 87, |
| 114 | MX51_PAD_CSI1_D18 = 88, | 114 | MX51_PAD_NANDF_D12 = 88, |
| 115 | MX51_PAD_CSI1_D19 = 89, | 115 | MX51_PAD_NANDF_D11 = 89, |
| 116 | MX51_PAD_CSI1_VSYNC = 90, | 116 | MX51_PAD_NANDF_D10 = 90, |
| 117 | MX51_PAD_CSI1_HSYNC = 91, | 117 | MX51_PAD_NANDF_D9 = 91, |
| 118 | MX51_PAD_CSI1_PIXCLK = 92, | 118 | MX51_PAD_NANDF_D8 = 92, |
| 119 | MX51_PAD_CSI1_MCLK = 93, | 119 | MX51_PAD_NANDF_D7 = 93, |
| 120 | MX51_PAD_CSI2_D12 = 94, | 120 | MX51_PAD_NANDF_D6 = 94, |
| 121 | MX51_PAD_CSI2_D13 = 95, | 121 | MX51_PAD_NANDF_D5 = 95, |
| 122 | MX51_PAD_CSI2_D14 = 96, | 122 | MX51_PAD_NANDF_D4 = 96, |
| 123 | MX51_PAD_CSI2_D15 = 97, | 123 | MX51_PAD_NANDF_D3 = 97, |
| 124 | MX51_PAD_CSI2_D16 = 98, | 124 | MX51_PAD_NANDF_D2 = 98, |
| 125 | MX51_PAD_CSI2_D17 = 99, | 125 | MX51_PAD_NANDF_D1 = 99, |
| 126 | MX51_PAD_CSI2_D18 = 100, | 126 | MX51_PAD_NANDF_D0 = 100, |
| 127 | MX51_PAD_CSI2_D19 = 101, | 127 | MX51_PAD_CSI1_D8 = 101, |
| 128 | MX51_PAD_CSI2_VSYNC = 102, | 128 | MX51_PAD_CSI1_D9 = 102, |
| 129 | MX51_PAD_CSI2_HSYNC = 103, | 129 | MX51_PAD_CSI1_D10 = 103, |
| 130 | MX51_PAD_CSI2_PIXCLK = 104, | 130 | MX51_PAD_CSI1_D11 = 104, |
| 131 | MX51_PAD_I2C1_CLK = 105, | 131 | MX51_PAD_CSI1_D12 = 105, |
| 132 | MX51_PAD_I2C1_DAT = 106, | 132 | MX51_PAD_CSI1_D13 = 106, |
| 133 | MX51_PAD_AUD3_BB_TXD = 107, | 133 | MX51_PAD_CSI1_D14 = 107, |
| 134 | MX51_PAD_AUD3_BB_RXD = 108, | 134 | MX51_PAD_CSI1_D15 = 108, |
| 135 | MX51_PAD_AUD3_BB_CK = 109, | 135 | MX51_PAD_CSI1_D16 = 109, |
| 136 | MX51_PAD_AUD3_BB_FS = 110, | 136 | MX51_PAD_CSI1_D17 = 110, |
| 137 | MX51_PAD_CSPI1_MOSI = 111, | 137 | MX51_PAD_CSI1_D18 = 111, |
| 138 | MX51_PAD_CSPI1_MISO = 112, | 138 | MX51_PAD_CSI1_D19 = 112, |
| 139 | MX51_PAD_CSPI1_SS0 = 113, | 139 | MX51_PAD_CSI1_VSYNC = 113, |
| 140 | MX51_PAD_CSPI1_SS1 = 114, | 140 | MX51_PAD_CSI1_HSYNC = 114, |
| 141 | MX51_PAD_CSPI1_RDY = 115, | 141 | MX51_PAD_CSI2_D12 = 115, |
| 142 | MX51_PAD_CSPI1_SCLK = 116, | 142 | MX51_PAD_CSI2_D13 = 116, |
| 143 | MX51_PAD_UART1_RXD = 117, | 143 | MX51_PAD_CSI2_D14 = 117, |
| 144 | MX51_PAD_UART1_TXD = 118, | 144 | MX51_PAD_CSI2_D15 = 118, |
| 145 | MX51_PAD_UART1_RTS = 119, | 145 | MX51_PAD_CSI2_D16 = 119, |
| 146 | MX51_PAD_UART1_CTS = 120, | 146 | MX51_PAD_CSI2_D17 = 120, |
| 147 | MX51_PAD_UART2_RXD = 121, | 147 | MX51_PAD_CSI2_D18 = 121, |
| 148 | MX51_PAD_UART2_TXD = 122, | 148 | MX51_PAD_CSI2_D19 = 122, |
| 149 | MX51_PAD_UART3_RXD = 123, | 149 | MX51_PAD_CSI2_VSYNC = 123, |
| 150 | MX51_PAD_UART3_TXD = 124, | 150 | MX51_PAD_CSI2_HSYNC = 124, |
| 151 | MX51_PAD_OWIRE_LINE = 125, | 151 | MX51_PAD_CSI2_PIXCLK = 125, |
| 152 | MX51_PAD_KEY_ROW0 = 126, | 152 | MX51_PAD_I2C1_CLK = 126, |
| 153 | MX51_PAD_KEY_ROW1 = 127, | 153 | MX51_PAD_I2C1_DAT = 127, |
| 154 | MX51_PAD_KEY_ROW2 = 128, | 154 | MX51_PAD_AUD3_BB_TXD = 128, |
| 155 | MX51_PAD_KEY_ROW3 = 129, | 155 | MX51_PAD_AUD3_BB_RXD = 129, |
| 156 | MX51_PAD_KEY_COL0 = 130, | 156 | MX51_PAD_AUD3_BB_CK = 130, |
| 157 | MX51_PAD_KEY_COL1 = 131, | 157 | MX51_PAD_AUD3_BB_FS = 131, |
| 158 | MX51_PAD_KEY_COL2 = 132, | 158 | MX51_PAD_CSPI1_MOSI = 132, |
| 159 | MX51_PAD_KEY_COL3 = 133, | 159 | MX51_PAD_CSPI1_MISO = 133, |
| 160 | MX51_PAD_KEY_COL4 = 134, | 160 | MX51_PAD_CSPI1_SS0 = 134, |
| 161 | MX51_PAD_KEY_COL5 = 135, | 161 | MX51_PAD_CSPI1_SS1 = 135, |
| 162 | MX51_PAD_USBH1_CLK = 136, | 162 | MX51_PAD_CSPI1_RDY = 136, |
| 163 | MX51_PAD_USBH1_DIR = 137, | 163 | MX51_PAD_CSPI1_SCLK = 137, |
| 164 | MX51_PAD_USBH1_STP = 138, | 164 | MX51_PAD_UART1_RXD = 138, |
| 165 | MX51_PAD_USBH1_NXT = 139, | 165 | MX51_PAD_UART1_TXD = 139, |
| 166 | MX51_PAD_USBH1_DATA0 = 140, | 166 | MX51_PAD_UART1_RTS = 140, |
| 167 | MX51_PAD_USBH1_DATA1 = 141, | 167 | MX51_PAD_UART1_CTS = 141, |
| 168 | MX51_PAD_USBH1_DATA2 = 142, | 168 | MX51_PAD_UART2_RXD = 142, |
| 169 | MX51_PAD_USBH1_DATA3 = 143, | 169 | MX51_PAD_UART2_TXD = 143, |
| 170 | MX51_PAD_USBH1_DATA4 = 144, | 170 | MX51_PAD_UART3_RXD = 144, |
| 171 | MX51_PAD_USBH1_DATA5 = 145, | 171 | MX51_PAD_UART3_TXD = 145, |
| 172 | MX51_PAD_USBH1_DATA6 = 146, | 172 | MX51_PAD_OWIRE_LINE = 146, |
| 173 | MX51_PAD_USBH1_DATA7 = 147, | 173 | MX51_PAD_KEY_ROW0 = 147, |
| 174 | MX51_PAD_DI1_PIN11 = 148, | 174 | MX51_PAD_KEY_ROW1 = 148, |
| 175 | MX51_PAD_DI1_PIN12 = 149, | 175 | MX51_PAD_KEY_ROW2 = 149, |
| 176 | MX51_PAD_DI1_PIN13 = 150, | 176 | MX51_PAD_KEY_ROW3 = 150, |
| 177 | MX51_PAD_DI1_D0_CS = 151, | 177 | MX51_PAD_KEY_COL0 = 151, |
| 178 | MX51_PAD_DI1_D1_CS = 152, | 178 | MX51_PAD_KEY_COL1 = 152, |
| 179 | MX51_PAD_DISPB2_SER_DIN = 153, | 179 | MX51_PAD_KEY_COL2 = 153, |
| 180 | MX51_PAD_DISPB2_SER_DIO = 154, | 180 | MX51_PAD_KEY_COL3 = 154, |
| 181 | MX51_PAD_DISPB2_SER_CLK = 155, | 181 | MX51_PAD_KEY_COL4 = 155, |
| 182 | MX51_PAD_DISPB2_SER_RS = 156, | 182 | MX51_PAD_KEY_COL5 = 156, |
| 183 | MX51_PAD_DISP1_DAT0 = 157, | 183 | MX51_PAD_RESERVE7 = 157, |
| 184 | MX51_PAD_DISP1_DAT1 = 158, | 184 | MX51_PAD_USBH1_CLK = 158, |
| 185 | MX51_PAD_DISP1_DAT2 = 159, | 185 | MX51_PAD_USBH1_DIR = 159, |
| 186 | MX51_PAD_DISP1_DAT3 = 160, | 186 | MX51_PAD_USBH1_STP = 160, |
| 187 | MX51_PAD_DISP1_DAT4 = 161, | 187 | MX51_PAD_USBH1_NXT = 161, |
| 188 | MX51_PAD_DISP1_DAT5 = 162, | 188 | MX51_PAD_USBH1_DATA0 = 162, |
| 189 | MX51_PAD_DISP1_DAT6 = 163, | 189 | MX51_PAD_USBH1_DATA1 = 163, |
| 190 | MX51_PAD_DISP1_DAT7 = 164, | 190 | MX51_PAD_USBH1_DATA2 = 164, |
| 191 | MX51_PAD_DISP1_DAT8 = 165, | 191 | MX51_PAD_USBH1_DATA3 = 165, |
| 192 | MX51_PAD_DISP1_DAT9 = 166, | 192 | MX51_PAD_USBH1_DATA4 = 166, |
| 193 | MX51_PAD_DISP1_DAT10 = 167, | 193 | MX51_PAD_USBH1_DATA5 = 167, |
| 194 | MX51_PAD_DISP1_DAT11 = 168, | 194 | MX51_PAD_USBH1_DATA6 = 168, |
| 195 | MX51_PAD_DISP1_DAT12 = 169, | 195 | MX51_PAD_USBH1_DATA7 = 169, |
| 196 | MX51_PAD_DISP1_DAT13 = 170, | 196 | MX51_PAD_DI1_PIN11 = 170, |
| 197 | MX51_PAD_DISP1_DAT14 = 171, | 197 | MX51_PAD_DI1_PIN12 = 171, |
| 198 | MX51_PAD_DISP1_DAT15 = 172, | 198 | MX51_PAD_DI1_PIN13 = 172, |
| 199 | MX51_PAD_DISP1_DAT16 = 173, | 199 | MX51_PAD_DI1_D0_CS = 173, |
| 200 | MX51_PAD_DISP1_DAT17 = 174, | 200 | MX51_PAD_DI1_D1_CS = 174, |
| 201 | MX51_PAD_DISP1_DAT18 = 175, | 201 | MX51_PAD_DISPB2_SER_DIN = 175, |
| 202 | MX51_PAD_DISP1_DAT19 = 176, | 202 | MX51_PAD_DISPB2_SER_DIO = 176, |
| 203 | MX51_PAD_DISP1_DAT20 = 177, | 203 | MX51_PAD_DISPB2_SER_CLK = 177, |
| 204 | MX51_PAD_DISP1_DAT21 = 178, | 204 | MX51_PAD_DISPB2_SER_RS = 178, |
| 205 | MX51_PAD_DISP1_DAT22 = 179, | 205 | MX51_PAD_DISP1_DAT0 = 179, |
| 206 | MX51_PAD_DISP1_DAT23 = 180, | 206 | MX51_PAD_DISP1_DAT1 = 180, |
| 207 | MX51_PAD_DI1_PIN3 = 181, | 207 | MX51_PAD_DISP1_DAT2 = 181, |
| 208 | MX51_PAD_DI1_PIN2 = 182, | 208 | MX51_PAD_DISP1_DAT3 = 182, |
| 209 | MX51_PAD_DI_GP2 = 183, | 209 | MX51_PAD_DISP1_DAT4 = 183, |
| 210 | MX51_PAD_DI_GP3 = 184, | 210 | MX51_PAD_DISP1_DAT5 = 184, |
| 211 | MX51_PAD_DI2_PIN4 = 185, | 211 | MX51_PAD_DISP1_DAT6 = 185, |
| 212 | MX51_PAD_DI2_PIN2 = 186, | 212 | MX51_PAD_DISP1_DAT7 = 186, |
| 213 | MX51_PAD_DI2_PIN3 = 187, | 213 | MX51_PAD_DISP1_DAT8 = 187, |
| 214 | MX51_PAD_DI2_DISP_CLK = 188, | 214 | MX51_PAD_DISP1_DAT9 = 188, |
| 215 | MX51_PAD_DI_GP4 = 189, | 215 | MX51_PAD_DISP1_DAT10 = 189, |
| 216 | MX51_PAD_DISP2_DAT0 = 190, | 216 | MX51_PAD_DISP1_DAT11 = 190, |
| 217 | MX51_PAD_DISP2_DAT1 = 191, | 217 | MX51_PAD_DISP1_DAT12 = 191, |
| 218 | MX51_PAD_DISP2_DAT2 = 192, | 218 | MX51_PAD_DISP1_DAT13 = 192, |
| 219 | MX51_PAD_DISP2_DAT3 = 193, | 219 | MX51_PAD_DISP1_DAT14 = 193, |
| 220 | MX51_PAD_DISP2_DAT4 = 194, | 220 | MX51_PAD_DISP1_DAT15 = 194, |
| 221 | MX51_PAD_DISP2_DAT5 = 195, | 221 | MX51_PAD_DISP1_DAT16 = 195, |
| 222 | MX51_PAD_DISP2_DAT6 = 196, | 222 | MX51_PAD_DISP1_DAT17 = 196, |
| 223 | MX51_PAD_DISP2_DAT7 = 197, | 223 | MX51_PAD_DISP1_DAT18 = 197, |
| 224 | MX51_PAD_DISP2_DAT8 = 198, | 224 | MX51_PAD_DISP1_DAT19 = 198, |
| 225 | MX51_PAD_DISP2_DAT9 = 199, | 225 | MX51_PAD_DISP1_DAT20 = 199, |
| 226 | MX51_PAD_DISP2_DAT10 = 200, | 226 | MX51_PAD_DISP1_DAT21 = 200, |
| 227 | MX51_PAD_DISP2_DAT11 = 201, | 227 | MX51_PAD_DISP1_DAT22 = 201, |
| 228 | MX51_PAD_DISP2_DAT12 = 202, | 228 | MX51_PAD_DISP1_DAT23 = 202, |
| 229 | MX51_PAD_DISP2_DAT13 = 203, | 229 | MX51_PAD_DI1_PIN3 = 203, |
| 230 | MX51_PAD_DISP2_DAT14 = 204, | 230 | MX51_PAD_DI1_PIN2 = 204, |
| 231 | MX51_PAD_DISP2_DAT15 = 205, | 231 | MX51_PAD_RESERVE8 = 205, |
| 232 | MX51_PAD_SD1_CMD = 206, | 232 | MX51_PAD_DI_GP2 = 206, |
| 233 | MX51_PAD_SD1_CLK = 207, | 233 | MX51_PAD_DI_GP3 = 207, |
| 234 | MX51_PAD_SD1_DATA0 = 208, | 234 | MX51_PAD_DI2_PIN4 = 208, |
| 235 | MX51_PAD_EIM_DA0 = 209, | 235 | MX51_PAD_DI2_PIN2 = 209, |
| 236 | MX51_PAD_EIM_DA1 = 210, | 236 | MX51_PAD_DI2_PIN3 = 210, |
| 237 | MX51_PAD_EIM_DA2 = 211, | 237 | MX51_PAD_DI2_DISP_CLK = 211, |
| 238 | MX51_PAD_EIM_DA3 = 212, | 238 | MX51_PAD_DI_GP4 = 212, |
| 239 | MX51_PAD_SD1_DATA1 = 213, | 239 | MX51_PAD_DISP2_DAT0 = 213, |
| 240 | MX51_PAD_EIM_DA4 = 214, | 240 | MX51_PAD_DISP2_DAT1 = 214, |
| 241 | MX51_PAD_EIM_DA5 = 215, | 241 | MX51_PAD_DISP2_DAT2 = 215, |
| 242 | MX51_PAD_EIM_DA6 = 216, | 242 | MX51_PAD_DISP2_DAT3 = 216, |
| 243 | MX51_PAD_EIM_DA7 = 217, | 243 | MX51_PAD_DISP2_DAT4 = 217, |
| 244 | MX51_PAD_SD1_DATA2 = 218, | 244 | MX51_PAD_DISP2_DAT5 = 218, |
| 245 | MX51_PAD_EIM_DA10 = 219, | 245 | MX51_PAD_DISP2_DAT6 = 219, |
| 246 | MX51_PAD_EIM_DA11 = 220, | 246 | MX51_PAD_DISP2_DAT7 = 220, |
| 247 | MX51_PAD_EIM_DA8 = 221, | 247 | MX51_PAD_DISP2_DAT8 = 221, |
| 248 | MX51_PAD_EIM_DA9 = 222, | 248 | MX51_PAD_DISP2_DAT9 = 222, |
| 249 | MX51_PAD_SD1_DATA3 = 223, | 249 | MX51_PAD_DISP2_DAT10 = 223, |
| 250 | MX51_PAD_GPIO1_0 = 224, | 250 | MX51_PAD_DISP2_DAT11 = 224, |
| 251 | MX51_PAD_GPIO1_1 = 225, | 251 | MX51_PAD_DISP2_DAT12 = 225, |
| 252 | MX51_PAD_EIM_DA12 = 226, | 252 | MX51_PAD_DISP2_DAT13 = 226, |
| 253 | MX51_PAD_EIM_DA13 = 227, | 253 | MX51_PAD_DISP2_DAT14 = 227, |
| 254 | MX51_PAD_EIM_DA14 = 228, | 254 | MX51_PAD_DISP2_DAT15 = 228, |
| 255 | MX51_PAD_EIM_DA15 = 229, | 255 | MX51_PAD_SD1_CMD = 229, |
| 256 | MX51_PAD_SD2_CMD = 230, | 256 | MX51_PAD_SD1_CLK = 230, |
| 257 | MX51_PAD_SD2_CLK = 231, | 257 | MX51_PAD_SD1_DATA0 = 231, |
| 258 | MX51_PAD_SD2_DATA0 = 232, | 258 | MX51_PAD_SD1_DATA1 = 232, |
| 259 | MX51_PAD_SD2_DATA1 = 233, | 259 | MX51_PAD_SD1_DATA2 = 233, |
| 260 | MX51_PAD_SD2_DATA2 = 234, | 260 | MX51_PAD_SD1_DATA3 = 234, |
| 261 | MX51_PAD_SD2_DATA3 = 235, | 261 | MX51_PAD_GPIO1_0 = 235, |
| 262 | MX51_PAD_GPIO1_2 = 236, | 262 | MX51_PAD_GPIO1_1 = 236, |
| 263 | MX51_PAD_GPIO1_3 = 237, | 263 | MX51_PAD_SD2_CMD = 237, |
| 264 | MX51_PAD_PMIC_INT_REQ = 238, | 264 | MX51_PAD_SD2_CLK = 238, |
| 265 | MX51_PAD_GPIO1_4 = 239, | 265 | MX51_PAD_SD2_DATA0 = 239, |
| 266 | MX51_PAD_GPIO1_5 = 240, | 266 | MX51_PAD_SD2_DATA1 = 240, |
| 267 | MX51_PAD_GPIO1_6 = 241, | 267 | MX51_PAD_SD2_DATA2 = 241, |
| 268 | MX51_PAD_GPIO1_7 = 242, | 268 | MX51_PAD_SD2_DATA3 = 242, |
| 269 | MX51_PAD_GPIO1_8 = 243, | 269 | MX51_PAD_GPIO1_2 = 243, |
| 270 | MX51_PAD_GPIO1_9 = 244, | 270 | MX51_PAD_GPIO1_3 = 244, |
| 271 | }; | 271 | MX51_PAD_PMIC_INT_REQ = 245, |
| 272 | 272 | MX51_PAD_GPIO1_4 = 246, | |
| 273 | /* imx51 register maps */ | 273 | MX51_PAD_GPIO1_5 = 247, |
| 274 | static struct imx_pin_reg imx51_pin_regs[] = { | 274 | MX51_PAD_GPIO1_6 = 248, |
| 275 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /* MX51_PAD_EIM_D16__AUD4_RXFS */ | 275 | MX51_PAD_GPIO1_7 = 249, |
| 276 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 7, 0x8d8, 0), /* MX51_PAD_EIM_D16__AUD5_TXD */ | 276 | MX51_PAD_GPIO1_8 = 250, |
| 277 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 0, 0x000, 0), /* MX51_PAD_EIM_D16__EIM_D16 */ | 277 | MX51_PAD_GPIO1_9 = 251, |
| 278 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 1, 0x000, 0), /* MX51_PAD_EIM_D16__GPIO2_0 */ | 278 | MX51_PAD_RESERVE9 = 252, |
| 279 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 4, 0x9b4, 0), /* MX51_PAD_EIM_D16__I2C1_SDA */ | 279 | MX51_PAD_RESERVE10 = 253, |
| 280 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 3, 0x000, 0), /* MX51_PAD_EIM_D16__UART2_CTS */ | 280 | MX51_PAD_RESERVE11 = 254, |
| 281 | IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 2, 0x000, 0), /* MX51_PAD_EIM_D16__USBH2_DATA0 */ | 281 | MX51_PAD_RESERVE12 = 255, |
| 282 | IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 7, 0x8d4, 0), /* MX51_PAD_EIM_D17__AUD5_RXD */ | 282 | MX51_PAD_RESERVE13 = 256, |
| 283 | IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 0, 0x000, 0), /* MX51_PAD_EIM_D17__EIM_D17 */ | 283 | MX51_PAD_RESERVE14 = 257, |
| 284 | IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 1, 0x000, 0), /* MX51_PAD_EIM_D17__GPIO2_1 */ | 284 | MX51_PAD_RESERVE15 = 258, |
| 285 | IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 3, 0x9ec, 0), /* MX51_PAD_EIM_D17__UART2_RXD */ | 285 | MX51_PAD_RESERVE16 = 259, |
| 286 | IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 4, 0x000, 0), /* MX51_PAD_EIM_D17__UART3_CTS */ | 286 | MX51_PAD_RESERVE17 = 260, |
| 287 | IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 2, 0x000, 0), /* MX51_PAD_EIM_D17__USBH2_DATA1 */ | 287 | MX51_PAD_RESERVE18 = 261, |
| 288 | IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 7, 0x8e4, 0), /* MX51_PAD_EIM_D18__AUD5_TXC */ | 288 | MX51_PAD_RESERVE19 = 262, |
| 289 | IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 0, 0x000, 0), /* MX51_PAD_EIM_D18__EIM_D18 */ | 289 | MX51_PAD_RESERVE20 = 263, |
| 290 | IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 1, 0x000, 0), /* MX51_PAD_EIM_D18__GPIO2_2 */ | 290 | MX51_PAD_RESERVE21 = 264, |
| 291 | IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 3, 0x000, 0), /* MX51_PAD_EIM_D18__UART2_TXD */ | 291 | MX51_PAD_RESERVE22 = 265, |
| 292 | IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 4, 0x9f0, 1), /* MX51_PAD_EIM_D18__UART3_RTS */ | 292 | MX51_PAD_RESERVE23 = 266, |
| 293 | IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 2, 0x000, 0), /* MX51_PAD_EIM_D18__USBH2_DATA2 */ | 293 | MX51_PAD_RESERVE24 = 267, |
| 294 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 5, 0x000, 0), /* MX51_PAD_EIM_D19__AUD4_RXC */ | 294 | MX51_PAD_RESERVE25 = 268, |
| 295 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 7, 0x8e8, 0), /* MX51_PAD_EIM_D19__AUD5_TXFS */ | 295 | MX51_PAD_RESERVE26 = 269, |
| 296 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 0, 0x000, 0), /* MX51_PAD_EIM_D19__EIM_D19 */ | 296 | MX51_PAD_RESERVE27 = 270, |
| 297 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 1, 0x000, 0), /* MX51_PAD_EIM_D19__GPIO2_3 */ | 297 | MX51_PAD_RESERVE28 = 271, |
| 298 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 4, 0x9b0, 0), /* MX51_PAD_EIM_D19__I2C1_SCL */ | 298 | MX51_PAD_RESERVE29 = 272, |
| 299 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 3, 0x9e8, 1), /* MX51_PAD_EIM_D19__UART2_RTS */ | 299 | MX51_PAD_RESERVE30 = 273, |
| 300 | IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 2, 0x000, 0), /* MX51_PAD_EIM_D19__USBH2_DATA3 */ | 300 | MX51_PAD_RESERVE31 = 274, |
| 301 | IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 5, 0x8c8, 0), /* MX51_PAD_EIM_D20__AUD4_TXD */ | 301 | MX51_PAD_RESERVE32 = 275, |
| 302 | IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 0, 0x000, 0), /* MX51_PAD_EIM_D20__EIM_D20 */ | 302 | MX51_PAD_RESERVE33 = 276, |
| 303 | IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 1, 0x000, 0), /* MX51_PAD_EIM_D20__GPIO2_4 */ | 303 | MX51_PAD_RESERVE34 = 277, |
| 304 | IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 4, 0x000, 0), /* MX51_PAD_EIM_D20__SRTC_ALARM_DEB */ | 304 | MX51_PAD_RESERVE35 = 278, |
| 305 | IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 2, 0x000, 0), /* MX51_PAD_EIM_D20__USBH2_DATA4 */ | 305 | MX51_PAD_RESERVE36 = 279, |
| 306 | IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 5, 0x8c4, 0), /* MX51_PAD_EIM_D21__AUD4_RXD */ | 306 | MX51_PAD_RESERVE37 = 280, |
| 307 | IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 0, 0x000, 0), /* MX51_PAD_EIM_D21__EIM_D21 */ | 307 | MX51_PAD_RESERVE38 = 281, |
| 308 | IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 1, 0x000, 0), /* MX51_PAD_EIM_D21__GPIO2_5 */ | 308 | MX51_PAD_RESERVE39 = 282, |
| 309 | IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 3, 0x000, 0), /* MX51_PAD_EIM_D21__SRTC_ALARM_DEB */ | 309 | MX51_PAD_RESERVE40 = 283, |
| 310 | IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 2, 0x000, 0), /* MX51_PAD_EIM_D21__USBH2_DATA5 */ | 310 | MX51_PAD_RESERVE41 = 284, |
| 311 | IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 5, 0x8cc, 0), /* MX51_PAD_EIM_D22__AUD4_TXC */ | 311 | MX51_PAD_RESERVE42 = 285, |
| 312 | IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 0, 0x000, 0), /* MX51_PAD_EIM_D22__EIM_D22 */ | 312 | MX51_PAD_RESERVE43 = 286, |
| 313 | IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 1, 0x000, 0), /* MX51_PAD_EIM_D22__GPIO2_6 */ | 313 | MX51_PAD_RESERVE44 = 287, |
| 314 | IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 2, 0x000, 0), /* MX51_PAD_EIM_D22__USBH2_DATA6 */ | 314 | MX51_PAD_RESERVE45 = 288, |
| 315 | IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 5, 0x8d0, 0), /* MX51_PAD_EIM_D23__AUD4_TXFS */ | 315 | MX51_PAD_RESERVE46 = 289, |
| 316 | IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 0, 0x000, 0), /* MX51_PAD_EIM_D23__EIM_D23 */ | 316 | MX51_PAD_RESERVE47 = 290, |
| 317 | IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 1, 0x000, 0), /* MX51_PAD_EIM_D23__GPIO2_7 */ | 317 | MX51_PAD_RESERVE48 = 291, |
| 318 | IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 4, 0x000, 0), /* MX51_PAD_EIM_D23__SPDIF_OUT1 */ | 318 | MX51_PAD_RESERVE49 = 292, |
| 319 | IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 2, 0x000, 0), /* MX51_PAD_EIM_D23__USBH2_DATA7 */ | 319 | MX51_PAD_RESERVE50 = 293, |
| 320 | IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 5, 0x8f8, 0), /* MX51_PAD_EIM_D24__AUD6_RXFS */ | 320 | MX51_PAD_RESERVE51 = 294, |
| 321 | IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 0, 0x000, 0), /* MX51_PAD_EIM_D24__EIM_D24 */ | 321 | MX51_PAD_RESERVE52 = 295, |
| 322 | IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 1, 0x000, 0), /* MX51_PAD_EIM_D24__GPIO2_8 */ | 322 | MX51_PAD_RESERVE53 = 296, |
| 323 | IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 4, 0x9bc, 0), /* MX51_PAD_EIM_D24__I2C2_SDA */ | 323 | MX51_PAD_RESERVE54 = 297, |
| 324 | IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 3, 0x000, 0), /* MX51_PAD_EIM_D24__UART3_CTS */ | 324 | MX51_PAD_RESERVE55 = 298, |
| 325 | IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 2, 0x000, 0), /* MX51_PAD_EIM_D24__USBOTG_DATA0 */ | 325 | MX51_PAD_RESERVE56 = 299, |
| 326 | IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 0, 0x000, 0), /* MX51_PAD_EIM_D25__EIM_D25 */ | 326 | MX51_PAD_RESERVE57 = 300, |
| 327 | IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 1, 0x9c8, 0), /* MX51_PAD_EIM_D25__KEY_COL6 */ | 327 | MX51_PAD_RESERVE58 = 301, |
| 328 | IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 4, 0x000, 0), /* MX51_PAD_EIM_D25__UART2_CTS */ | 328 | MX51_PAD_RESERVE59 = 302, |
| 329 | IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 3, 0x9f4, 0), /* MX51_PAD_EIM_D25__UART3_RXD */ | 329 | MX51_PAD_RESERVE60 = 303, |
| 330 | IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 2, 0x000, 0), /* MX51_PAD_EIM_D25__USBOTG_DATA1 */ | 330 | MX51_PAD_RESERVE61 = 304, |
| 331 | IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 0, 0x000, 0), /* MX51_PAD_EIM_D26__EIM_D26 */ | 331 | MX51_PAD_RESERVE62 = 305, |
| 332 | IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 1, 0x9cc, 0), /* MX51_PAD_EIM_D26__KEY_COL7 */ | 332 | MX51_PAD_RESERVE63 = 306, |
| 333 | IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 4, 0x9e8, 3), /* MX51_PAD_EIM_D26__UART2_RTS */ | 333 | MX51_PAD_RESERVE64 = 307, |
| 334 | IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 3, 0x000, 0), /* MX51_PAD_EIM_D26__UART3_TXD */ | 334 | MX51_PAD_RESERVE65 = 308, |
| 335 | IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 2, 0x000, 0), /* MX51_PAD_EIM_D26__USBOTG_DATA2 */ | 335 | MX51_PAD_RESERVE66 = 309, |
| 336 | IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 5, 0x8f4, 0), /* MX51_PAD_EIM_D27__AUD6_RXC */ | 336 | MX51_PAD_RESERVE67 = 310, |
| 337 | IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 0, 0x000, 0), /* MX51_PAD_EIM_D27__EIM_D27 */ | 337 | MX51_PAD_RESERVE68 = 311, |
| 338 | IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 1, 0x000, 0), /* MX51_PAD_EIM_D27__GPIO2_9 */ | 338 | MX51_PAD_RESERVE69 = 312, |
| 339 | IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 4, 0x9b8, 0), /* MX51_PAD_EIM_D27__I2C2_SCL */ | 339 | MX51_PAD_RESERVE70 = 313, |
| 340 | IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 3, 0x9f0, 3), /* MX51_PAD_EIM_D27__UART3_RTS */ | 340 | MX51_PAD_RESERVE71 = 314, |
| 341 | IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 2, 0x000, 0), /* MX51_PAD_EIM_D27__USBOTG_DATA3 */ | 341 | MX51_PAD_RESERVE72 = 315, |
| 342 | IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 5, 0x8f0, 0), /* MX51_PAD_EIM_D28__AUD6_TXD */ | 342 | MX51_PAD_RESERVE73 = 316, |
| 343 | IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 0, 0x000, 0), /* MX51_PAD_EIM_D28__EIM_D28 */ | 343 | MX51_PAD_RESERVE74 = 317, |
| 344 | IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 1, 0x9d0, 0), /* MX51_PAD_EIM_D28__KEY_ROW4 */ | 344 | MX51_PAD_RESERVE75 = 318, |
| 345 | IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 2, 0x000, 0), /* MX51_PAD_EIM_D28__USBOTG_DATA4 */ | 345 | MX51_PAD_RESERVE76 = 319, |
| 346 | IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 5, 0x8ec, 0), /* MX51_PAD_EIM_D29__AUD6_RXD */ | 346 | MX51_PAD_RESERVE77 = 320, |
| 347 | IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 0, 0x000, 0), /* MX51_PAD_EIM_D29__EIM_D29 */ | 347 | MX51_PAD_RESERVE78 = 321, |
| 348 | IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 1, 0x9d4, 0), /* MX51_PAD_EIM_D29__KEY_ROW5 */ | 348 | MX51_PAD_RESERVE79 = 322, |
| 349 | IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 2, 0x000, 0), /* MX51_PAD_EIM_D29__USBOTG_DATA5 */ | 349 | MX51_PAD_RESERVE80 = 323, |
| 350 | IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 5, 0x8fc, 0), /* MX51_PAD_EIM_D30__AUD6_TXC */ | 350 | MX51_PAD_RESERVE81 = 324, |
| 351 | IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 0, 0x000, 0), /* MX51_PAD_EIM_D30__EIM_D30 */ | 351 | MX51_PAD_RESERVE82 = 325, |
| 352 | IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 1, 0x9d8, 0), /* MX51_PAD_EIM_D30__KEY_ROW6 */ | 352 | MX51_PAD_RESERVE83 = 326, |
| 353 | IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 2, 0x000, 0), /* MX51_PAD_EIM_D30__USBOTG_DATA6 */ | 353 | MX51_PAD_RESERVE84 = 327, |
| 354 | IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 5, 0x900, 0), /* MX51_PAD_EIM_D31__AUD6_TXFS */ | 354 | MX51_PAD_RESERVE85 = 328, |
| 355 | IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 0, 0x000, 0), /* MX51_PAD_EIM_D31__EIM_D31 */ | 355 | MX51_PAD_RESERVE86 = 329, |
| 356 | IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 1, 0x9dc, 0), /* MX51_PAD_EIM_D31__KEY_ROW7 */ | 356 | MX51_PAD_RESERVE87 = 330, |
| 357 | IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 2, 0x000, 0), /* MX51_PAD_EIM_D31__USBOTG_DATA7 */ | 357 | MX51_PAD_RESERVE88 = 331, |
| 358 | IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 0, 0x000, 0), /* MX51_PAD_EIM_A16__EIM_A16 */ | 358 | MX51_PAD_RESERVE89 = 332, |
| 359 | IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 1, 0x000, 0), /* MX51_PAD_EIM_A16__GPIO2_10 */ | 359 | MX51_PAD_RESERVE90 = 333, |
| 360 | IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 7, 0x000, 0), /* MX51_PAD_EIM_A16__OSC_FREQ_SEL0 */ | 360 | MX51_PAD_RESERVE91 = 334, |
| 361 | IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 0, 0x000, 0), /* MX51_PAD_EIM_A17__EIM_A17 */ | 361 | MX51_PAD_RESERVE92 = 335, |
| 362 | IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 1, 0x000, 0), /* MX51_PAD_EIM_A17__GPIO2_11 */ | 362 | MX51_PAD_RESERVE93 = 336, |
| 363 | IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 7, 0x000, 0), /* MX51_PAD_EIM_A17__OSC_FREQ_SEL1 */ | 363 | MX51_PAD_RESERVE94 = 337, |
| 364 | IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 7, 0x000, 0), /* MX51_PAD_EIM_A18__BOOT_LPB0 */ | 364 | MX51_PAD_RESERVE95 = 338, |
| 365 | IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 0, 0x000, 0), /* MX51_PAD_EIM_A18__EIM_A18 */ | 365 | MX51_PAD_RESERVE96 = 339, |
| 366 | IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 1, 0x000, 0), /* MX51_PAD_EIM_A18__GPIO2_12 */ | 366 | MX51_PAD_RESERVE97 = 340, |
| 367 | IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 7, 0x000, 0), /* MX51_PAD_EIM_A19__BOOT_LPB1 */ | 367 | MX51_PAD_RESERVE98 = 341, |
| 368 | IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 0, 0x000, 0), /* MX51_PAD_EIM_A19__EIM_A19 */ | 368 | MX51_PAD_RESERVE99 = 342, |
| 369 | IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 1, 0x000, 0), /* MX51_PAD_EIM_A19__GPIO2_13 */ | 369 | MX51_PAD_RESERVE100 = 343, |
| 370 | IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 7, 0x000, 0), /* MX51_PAD_EIM_A20__BOOT_UART_SRC0 */ | 370 | MX51_PAD_RESERVE101 = 344, |
| 371 | IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 0, 0x000, 0), /* MX51_PAD_EIM_A20__EIM_A20 */ | 371 | MX51_PAD_RESERVE102 = 345, |
| 372 | IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 1, 0x000, 0), /* MX51_PAD_EIM_A20__GPIO2_14 */ | 372 | MX51_PAD_RESERVE103 = 346, |
| 373 | IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 7, 0x000, 0), /* MX51_PAD_EIM_A21__BOOT_UART_SRC1 */ | 373 | MX51_PAD_RESERVE104 = 347, |
| 374 | IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 0, 0x000, 0), /* MX51_PAD_EIM_A21__EIM_A21 */ | 374 | MX51_PAD_RESERVE105 = 348, |
| 375 | IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 1, 0x000, 0), /* MX51_PAD_EIM_A21__GPIO2_15 */ | 375 | MX51_PAD_RESERVE106 = 349, |
| 376 | IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 0, 0x000, 0), /* MX51_PAD_EIM_A22__EIM_A22 */ | 376 | MX51_PAD_RESERVE107 = 350, |
| 377 | IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 1, 0x000, 0), /* MX51_PAD_EIM_A22__GPIO2_16 */ | 377 | MX51_PAD_RESERVE108 = 351, |
| 378 | IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 7, 0x000, 0), /* MX51_PAD_EIM_A23__BOOT_HPN_EN */ | 378 | MX51_PAD_RESERVE109 = 352, |
| 379 | IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 0, 0x000, 0), /* MX51_PAD_EIM_A23__EIM_A23 */ | 379 | MX51_PAD_RESERVE110 = 353, |
| 380 | IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 1, 0x000, 0), /* MX51_PAD_EIM_A23__GPIO2_17 */ | 380 | MX51_PAD_RESERVE111 = 354, |
| 381 | IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 0, 0x000, 0), /* MX51_PAD_EIM_A24__EIM_A24 */ | 381 | MX51_PAD_RESERVE112 = 355, |
| 382 | IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 1, 0x000, 0), /* MX51_PAD_EIM_A24__GPIO2_18 */ | 382 | MX51_PAD_RESERVE113 = 356, |
| 383 | IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 2, 0x000, 0), /* MX51_PAD_EIM_A24__USBH2_CLK */ | 383 | MX51_PAD_RESERVE114 = 357, |
| 384 | IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 6, 0x000, 0), /* MX51_PAD_EIM_A25__DISP1_PIN4 */ | 384 | MX51_PAD_RESERVE115 = 358, |
| 385 | IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 0, 0x000, 0), /* MX51_PAD_EIM_A25__EIM_A25 */ | 385 | MX51_PAD_RESERVE116 = 359, |
| 386 | IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 1, 0x000, 0), /* MX51_PAD_EIM_A25__GPIO2_19 */ | 386 | MX51_PAD_RESERVE117 = 360, |
| 387 | IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 2, 0x000, 0), /* MX51_PAD_EIM_A25__USBH2_DIR */ | 387 | MX51_PAD_RESERVE118 = 361, |
| 388 | IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 5, 0x9a0, 0), /* MX51_PAD_EIM_A26__CSI1_DATA_EN */ | 388 | MX51_PAD_RESERVE119 = 362, |
| 389 | IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 6, 0x908, 0), /* MX51_PAD_EIM_A26__DISP2_EXT_CLK */ | 389 | MX51_PAD_RESERVE120 = 363, |
| 390 | IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 0, 0x000, 0), /* MX51_PAD_EIM_A26__EIM_A26 */ | 390 | MX51_PAD_RESERVE121 = 364, |
| 391 | IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 1, 0x000, 0), /* MX51_PAD_EIM_A26__GPIO2_20 */ | 391 | MX51_PAD_CSI1_PIXCLK = 365, |
| 392 | IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 2, 0x000, 0), /* MX51_PAD_EIM_A26__USBH2_STP */ | 392 | MX51_PAD_CSI1_MCLK = 366, |
| 393 | IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 5, 0x99c, 0), /* MX51_PAD_EIM_A27__CSI2_DATA_EN */ | ||
| 394 | IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 6, 0x9a4, 0), /* MX51_PAD_EIM_A27__DISP1_PIN1 */ | ||
| 395 | IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 0, 0x000, 0), /* MX51_PAD_EIM_A27__EIM_A27 */ | ||
| 396 | IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 1, 0x000, 0), /* MX51_PAD_EIM_A27__GPIO2_21 */ | ||
| 397 | IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 2, 0x000, 0), /* MX51_PAD_EIM_A27__USBH2_NXT */ | ||
| 398 | IMX_PIN_REG(MX51_PAD_EIM_EB0, 0x460, 0x0cc, 0, 0x000, 0), /* MX51_PAD_EIM_EB0__EIM_EB0 */ | ||
| 399 | IMX_PIN_REG(MX51_PAD_EIM_EB1, 0x464, 0x0d0, 0, 0x000, 0), /* MX51_PAD_EIM_EB1__EIM_EB1 */ | ||
| 400 | IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 6, 0x8e0, 0), /* MX51_PAD_EIM_EB2__AUD5_RXFS */ | ||
| 401 | IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 5, 0x000, 0), /* MX51_PAD_EIM_EB2__CSI1_D2 */ | ||
| 402 | IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 0, 0x000, 0), /* MX51_PAD_EIM_EB2__EIM_EB2 */ | ||
| 403 | IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 3, 0x954, 0), /* MX51_PAD_EIM_EB2__FEC_MDIO */ | ||
| 404 | IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 1, 0x000, 0), /* MX51_PAD_EIM_EB2__GPIO2_22 */ | ||
| 405 | IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 7, 0x000, 0), /* MX51_PAD_EIM_EB2__GPT_CMPOUT1 */ | ||
| 406 | IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 6, 0x8dc, 0), /* MX51_PAD_EIM_EB3__AUD5_RXC */ | ||
| 407 | IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 5, 0x000, 0), /* MX51_PAD_EIM_EB3__CSI1_D3 */ | ||
| 408 | IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 0, 0x000, 0), /* MX51_PAD_EIM_EB3__EIM_EB3 */ | ||
| 409 | IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 3, 0x95c, 0), /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ | ||
| 410 | IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 1, 0x000, 0), /* MX51_PAD_EIM_EB3__GPIO2_23 */ | ||
| 411 | IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 7, 0x000, 0), /* MX51_PAD_EIM_EB3__GPT_CMPOUT2 */ | ||
| 412 | IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 0, 0x000, 0), /* MX51_PAD_EIM_OE__EIM_OE */ | ||
| 413 | IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 1, 0x000, 0), /* MX51_PAD_EIM_OE__GPIO2_24 */ | ||
| 414 | IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 0, 0x000, 0), /* MX51_PAD_EIM_CS0__EIM_CS0 */ | ||
| 415 | IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 1, 0x000, 0), /* MX51_PAD_EIM_CS0__GPIO2_25 */ | ||
| 416 | IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 0, 0x000, 0), /* MX51_PAD_EIM_CS1__EIM_CS1 */ | ||
| 417 | IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 1, 0x000, 0), /* MX51_PAD_EIM_CS1__GPIO2_26 */ | ||
| 418 | IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 6, 0x8d8, 1), /* MX51_PAD_EIM_CS2__AUD5_TXD */ | ||
| 419 | IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 5, 0x000, 0), /* MX51_PAD_EIM_CS2__CSI1_D4 */ | ||
| 420 | IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 0, 0x000, 0), /* MX51_PAD_EIM_CS2__EIM_CS2 */ | ||
| 421 | IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 3, 0x960, 0), /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ | ||
| 422 | IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 1, 0x000, 0), /* MX51_PAD_EIM_CS2__GPIO2_27 */ | ||
| 423 | IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 2, 0x000, 0), /* MX51_PAD_EIM_CS2__USBOTG_STP */ | ||
| 424 | IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 6, 0x8d4, 1), /* MX51_PAD_EIM_CS3__AUD5_RXD */ | ||
| 425 | IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 5, 0x000, 0), /* MX51_PAD_EIM_CS3__CSI1_D5 */ | ||
| 426 | IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 0, 0x000, 0), /* MX51_PAD_EIM_CS3__EIM_CS3 */ | ||
| 427 | IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 3, 0x964, 0), /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ | ||
| 428 | IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 1, 0x000, 0), /* MX51_PAD_EIM_CS3__GPIO2_28 */ | ||
| 429 | IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 2, 0x000, 0), /* MX51_PAD_EIM_CS3__USBOTG_NXT */ | ||
| 430 | IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 6, 0x8e4, 1), /* MX51_PAD_EIM_CS4__AUD5_TXC */ | ||
| 431 | IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 5, 0x000, 0), /* MX51_PAD_EIM_CS4__CSI1_D6 */ | ||
| 432 | IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 0, 0x000, 0), /* MX51_PAD_EIM_CS4__EIM_CS4 */ | ||
| 433 | IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 3, 0x970, 0), /* MX51_PAD_EIM_CS4__FEC_RX_ER */ | ||
| 434 | IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 1, 0x000, 0), /* MX51_PAD_EIM_CS4__GPIO2_29 */ | ||
| 435 | IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 2, 0x000, 0), /* MX51_PAD_EIM_CS4__USBOTG_CLK */ | ||
| 436 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 6, 0x8e8, 1), /* MX51_PAD_EIM_CS5__AUD5_TXFS */ | ||
| 437 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 5, 0x000, 0), /* MX51_PAD_EIM_CS5__CSI1_D7 */ | ||
| 438 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 4, 0x904, 0), /* MX51_PAD_EIM_CS5__DISP1_EXT_CLK */ | ||
| 439 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 0, 0x000, 0), /* MX51_PAD_EIM_CS5__EIM_CS5 */ | ||
| 440 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 3, 0x950, 0), /* MX51_PAD_EIM_CS5__FEC_CRS */ | ||
| 441 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 1, 0x000, 0), /* MX51_PAD_EIM_CS5__GPIO2_30 */ | ||
| 442 | IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 2, 0x000, 0), /* MX51_PAD_EIM_CS5__USBOTG_DIR */ | ||
| 443 | IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 0, 0x000, 0), /* MX51_PAD_EIM_DTACK__EIM_DTACK */ | ||
| 444 | IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 1, 0x000, 0), /* MX51_PAD_EIM_DTACK__GPIO2_31 */ | ||
| 445 | IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 0, 0x000, 0), /* MX51_PAD_EIM_LBA__EIM_LBA */ | ||
| 446 | IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 1, 0x978, 0), /* MX51_PAD_EIM_LBA__GPIO3_1 */ | ||
| 447 | IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 0, 0x000, 0), /* MX51_PAD_EIM_CRE__EIM_CRE */ | ||
| 448 | IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 1, 0x97c, 0), /* MX51_PAD_EIM_CRE__GPIO3_2 */ | ||
| 449 | IMX_PIN_REG(MX51_PAD_DRAM_CS1, 0x4d0, 0x104, 0, 0x000, 0), /* MX51_PAD_DRAM_CS1__DRAM_CS1 */ | ||
| 450 | IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 3, 0x980, 0), /* MX51_PAD_NANDF_WE_B__GPIO3_3 */ | ||
| 451 | IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 0, 0x000, 0), /* MX51_PAD_NANDF_WE_B__NANDF_WE_B */ | ||
| 452 | IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 1, 0x000, 0), /* MX51_PAD_NANDF_WE_B__PATA_DIOW */ | ||
| 453 | IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 2, 0x93c, 0), /* MX51_PAD_NANDF_WE_B__SD3_DATA0 */ | ||
| 454 | IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 3, 0x984, 0), /* MX51_PAD_NANDF_RE_B__GPIO3_4 */ | ||
| 455 | IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 0, 0x000, 0), /* MX51_PAD_NANDF_RE_B__NANDF_RE_B */ | ||
| 456 | IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 1, 0x000, 0), /* MX51_PAD_NANDF_RE_B__PATA_DIOR */ | ||
| 457 | IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 2, 0x940, 0), /* MX51_PAD_NANDF_RE_B__SD3_DATA1 */ | ||
| 458 | IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 3, 0x988, 0), /* MX51_PAD_NANDF_ALE__GPIO3_5 */ | ||
| 459 | IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 0, 0x000, 0), /* MX51_PAD_NANDF_ALE__NANDF_ALE */ | ||
| 460 | IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 1, 0x000, 0), /* MX51_PAD_NANDF_ALE__PATA_BUFFER_EN */ | ||
| 461 | IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 3, 0x98c, 0), /* MX51_PAD_NANDF_CLE__GPIO3_6 */ | ||
| 462 | IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 0, 0x000, 0), /* MX51_PAD_NANDF_CLE__NANDF_CLE */ | ||
| 463 | IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 1, 0x000, 0), /* MX51_PAD_NANDF_CLE__PATA_RESET_B */ | ||
| 464 | IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 3, 0x990, 0), /* MX51_PAD_NANDF_WP_B__GPIO3_7 */ | ||
| 465 | IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 0, 0x000, 0), /* MX51_PAD_NANDF_WP_B__NANDF_WP_B */ | ||
| 466 | IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 1, 0x000, 0), /* MX51_PAD_NANDF_WP_B__PATA_DMACK */ | ||
| 467 | IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 2, 0x944, 0), /* MX51_PAD_NANDF_WP_B__SD3_DATA2 */ | ||
| 468 | IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 5, 0x930, 0), /* MX51_PAD_NANDF_RB0__ECSPI2_SS1 */ | ||
| 469 | IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 3, 0x994, 0), /* MX51_PAD_NANDF_RB0__GPIO3_8 */ | ||
| 470 | IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 0, 0x000, 0), /* MX51_PAD_NANDF_RB0__NANDF_RB0 */ | ||
| 471 | IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 1, 0x000, 0), /* MX51_PAD_NANDF_RB0__PATA_DMARQ */ | ||
| 472 | IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 2, 0x948, 0), /* MX51_PAD_NANDF_RB0__SD3_DATA3 */ | ||
| 473 | IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 6, 0x91c, 0), /* MX51_PAD_NANDF_RB1__CSPI_MOSI */ | ||
| 474 | IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 2, 0x000, 0), /* MX51_PAD_NANDF_RB1__ECSPI2_RDY */ | ||
| 475 | IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 3, 0x000, 0), /* MX51_PAD_NANDF_RB1__GPIO3_9 */ | ||
| 476 | IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 0, 0x000, 0), /* MX51_PAD_NANDF_RB1__NANDF_RB1 */ | ||
| 477 | IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 1, 0x000, 0), /* MX51_PAD_NANDF_RB1__PATA_IORDY */ | ||
| 478 | IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 5, 0x000, 0), /* MX51_PAD_NANDF_RB1__SD4_CMD */ | ||
| 479 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 5, 0x9a8, 0), /* MX51_PAD_NANDF_RB2__DISP2_WAIT */ | ||
| 480 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 2, 0x000, 0), /* MX51_PAD_NANDF_RB2__ECSPI2_SCLK */ | ||
| 481 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 1, 0x94c, 0), /* MX51_PAD_NANDF_RB2__FEC_COL */ | ||
| 482 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 3, 0x000, 0), /* MX51_PAD_NANDF_RB2__GPIO3_10 */ | ||
| 483 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 0, 0x000, 0), /* MX51_PAD_NANDF_RB2__NANDF_RB2 */ | ||
| 484 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 7, 0x000, 0), /* MX51_PAD_NANDF_RB2__USBH3_H3_DP */ | ||
| 485 | IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 6, 0xa20, 0), /* MX51_PAD_NANDF_RB2__USBH3_NXT */ | ||
| 486 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 5, 0x000, 0), /* MX51_PAD_NANDF_RB3__DISP1_WAIT */ | ||
| 487 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 2, 0x000, 0), /* MX51_PAD_NANDF_RB3__ECSPI2_MISO */ | ||
| 488 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 1, 0x968, 0), /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ | ||
| 489 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 3, 0x000, 0), /* MX51_PAD_NANDF_RB3__GPIO3_11 */ | ||
| 490 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 0, 0x000, 0), /* MX51_PAD_NANDF_RB3__NANDF_RB3 */ | ||
| 491 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 6, 0x9f8, 0), /* MX51_PAD_NANDF_RB3__USBH3_CLK */ | ||
| 492 | IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 7, 0x000, 0), /* MX51_PAD_NANDF_RB3__USBH3_H3_DM */ | ||
| 493 | IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 0, 0x998, 0), /* MX51_PAD_GPIO_NAND__GPIO_NAND */ | ||
| 494 | IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 1, 0x000, 0), /* MX51_PAD_GPIO_NAND__PATA_INTRQ */ | ||
| 495 | IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 3, 0x000, 0), /* MX51_PAD_NANDF_CS0__GPIO3_16 */ | ||
| 496 | IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 0, 0x000, 0), /* MX51_PAD_NANDF_CS0__NANDF_CS0 */ | ||
| 497 | IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 3, 0x000, 0), /* MX51_PAD_NANDF_CS1__GPIO3_17 */ | ||
| 498 | IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 0, 0x000, 0), /* MX51_PAD_NANDF_CS1__NANDF_CS1 */ | ||
| 499 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 6, 0x914, 0), /* MX51_PAD_NANDF_CS2__CSPI_SCLK */ | ||
| 500 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 2, 0x000, 0), /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ | ||
| 501 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 3, 0x000, 0), /* MX51_PAD_NANDF_CS2__GPIO3_18 */ | ||
| 502 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 0, 0x000, 0), /* MX51_PAD_NANDF_CS2__NANDF_CS2 */ | ||
| 503 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 1, 0x000, 0), /* MX51_PAD_NANDF_CS2__PATA_CS_0 */ | ||
| 504 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 5, 0x000, 0), /* MX51_PAD_NANDF_CS2__SD4_CLK */ | ||
| 505 | IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 7, 0x000, 0), /* MX51_PAD_NANDF_CS2__USBH3_H1_DP */ | ||
| 506 | IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 2, 0x000, 0), /* MX51_PAD_NANDF_CS3__FEC_MDC */ | ||
| 507 | IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS3__GPIO3_19 */ | ||
| 508 | IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS3__NANDF_CS3 */ | ||
| 509 | IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS3__PATA_CS_1 */ | ||
| 510 | IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS3__SD4_DAT0 */ | ||
| 511 | IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 7, 0x000, 0), /* MX51_PAD_NANDF_CS3__USBH3_H1_DM */ | ||
| 512 | IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 2, 0x000, 0), /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ | ||
| 513 | IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 3, 0x000, 0), /* MX51_PAD_NANDF_CS4__GPIO3_20 */ | ||
| 514 | IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 0, 0x000, 0), /* MX51_PAD_NANDF_CS4__NANDF_CS4 */ | ||
| 515 | IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 1, 0x000, 0), /* MX51_PAD_NANDF_CS4__PATA_DA_0 */ | ||
| 516 | IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 5, 0x000, 0), /* MX51_PAD_NANDF_CS4__SD4_DAT1 */ | ||
| 517 | IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 7, 0xa24, 0), /* MX51_PAD_NANDF_CS4__USBH3_STP */ | ||
| 518 | IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 2, 0x000, 0), /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ | ||
| 519 | IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 3, 0x000, 0), /* MX51_PAD_NANDF_CS5__GPIO3_21 */ | ||
| 520 | IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 0, 0x000, 0), /* MX51_PAD_NANDF_CS5__NANDF_CS5 */ | ||
| 521 | IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 1, 0x000, 0), /* MX51_PAD_NANDF_CS5__PATA_DA_1 */ | ||
| 522 | IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 5, 0x000, 0), /* MX51_PAD_NANDF_CS5__SD4_DAT2 */ | ||
| 523 | IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 7, 0xa1c, 0), /* MX51_PAD_NANDF_CS5__USBH3_DIR */ | ||
| 524 | IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 7, 0x928, 0), /* MX51_PAD_NANDF_CS6__CSPI_SS3 */ | ||
| 525 | IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 2, 0x000, 0), /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ | ||
| 526 | IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 3, 0x000, 0), /* MX51_PAD_NANDF_CS6__GPIO3_22 */ | ||
| 527 | IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 0, 0x000, 0), /* MX51_PAD_NANDF_CS6__NANDF_CS6 */ | ||
| 528 | IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 1, 0x000, 0), /* MX51_PAD_NANDF_CS6__PATA_DA_2 */ | ||
| 529 | IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 5, 0x000, 0), /* MX51_PAD_NANDF_CS6__SD4_DAT3 */ | ||
| 530 | IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ | ||
| 531 | IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS7__GPIO3_23 */ | ||
| 532 | IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS7__NANDF_CS7 */ | ||
| 533 | IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS7__SD3_CLK */ | ||
| 534 | IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 2, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 */ | ||
| 535 | IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 1, 0x974, 0), /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ | ||
| 536 | IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 3, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__GPIO3_24 */ | ||
| 537 | IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 0, 0x938, 0), /* MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT */ | ||
| 538 | IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 5, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__SD3_CMD */ | ||
| 539 | IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 2, 0x000, 0), /* MX51_PAD_NANDF_D15__ECSPI2_MOSI */ | ||
| 540 | IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 3, 0x000, 0), /* MX51_PAD_NANDF_D15__GPIO3_25 */ | ||
| 541 | IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 0, 0x000, 0), /* MX51_PAD_NANDF_D15__NANDF_D15 */ | ||
| 542 | IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 1, 0x000, 0), /* MX51_PAD_NANDF_D15__PATA_DATA15 */ | ||
| 543 | IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 5, 0x000, 0), /* MX51_PAD_NANDF_D15__SD3_DAT7 */ | ||
| 544 | IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 2, 0x934, 0), /* MX51_PAD_NANDF_D14__ECSPI2_SS3 */ | ||
| 545 | IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 3, 0x000, 0), /* MX51_PAD_NANDF_D14__GPIO3_26 */ | ||
| 546 | IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 0, 0x000, 0), /* MX51_PAD_NANDF_D14__NANDF_D14 */ | ||
| 547 | IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 1, 0x000, 0), /* MX51_PAD_NANDF_D14__PATA_DATA14 */ | ||
| 548 | IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 5, 0x000, 0), /* MX51_PAD_NANDF_D14__SD3_DAT6 */ | ||
| 549 | IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 2, 0x000, 0), /* MX51_PAD_NANDF_D13__ECSPI2_SS2 */ | ||
| 550 | IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 3, 0x000, 0), /* MX51_PAD_NANDF_D13__GPIO3_27 */ | ||
| 551 | IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 0, 0x000, 0), /* MX51_PAD_NANDF_D13__NANDF_D13 */ | ||
| 552 | IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 1, 0x000, 0), /* MX51_PAD_NANDF_D13__PATA_DATA13 */ | ||
| 553 | IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 5, 0x000, 0), /* MX51_PAD_NANDF_D13__SD3_DAT5 */ | ||
| 554 | IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 2, 0x930, 1), /* MX51_PAD_NANDF_D12__ECSPI2_SS1 */ | ||
| 555 | IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 3, 0x000, 0), /* MX51_PAD_NANDF_D12__GPIO3_28 */ | ||
| 556 | IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 0, 0x000, 0), /* MX51_PAD_NANDF_D12__NANDF_D12 */ | ||
| 557 | IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 1, 0x000, 0), /* MX51_PAD_NANDF_D12__PATA_DATA12 */ | ||
| 558 | IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 5, 0x000, 0), /* MX51_PAD_NANDF_D12__SD3_DAT4 */ | ||
| 559 | IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 2, 0x96c, 0), /* MX51_PAD_NANDF_D11__FEC_RX_DV */ | ||
| 560 | IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 3, 0x000, 0), /* MX51_PAD_NANDF_D11__GPIO3_29 */ | ||
| 561 | IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 0, 0x000, 0), /* MX51_PAD_NANDF_D11__NANDF_D11 */ | ||
| 562 | IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 1, 0x000, 0), /* MX51_PAD_NANDF_D11__PATA_DATA11 */ | ||
| 563 | IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 5, 0x948, 1), /* MX51_PAD_NANDF_D11__SD3_DATA3 */ | ||
| 564 | IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 3, 0x000, 0), /* MX51_PAD_NANDF_D10__GPIO3_30 */ | ||
| 565 | IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 0, 0x000, 0), /* MX51_PAD_NANDF_D10__NANDF_D10 */ | ||
| 566 | IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 1, 0x000, 0), /* MX51_PAD_NANDF_D10__PATA_DATA10 */ | ||
| 567 | IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 5, 0x944, 1), /* MX51_PAD_NANDF_D10__SD3_DATA2 */ | ||
| 568 | IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 2, 0x958, 0), /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ | ||
| 569 | IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 3, 0x000, 0), /* MX51_PAD_NANDF_D9__GPIO3_31 */ | ||
| 570 | IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 0, 0x000, 0), /* MX51_PAD_NANDF_D9__NANDF_D9 */ | ||
| 571 | IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 1, 0x000, 0), /* MX51_PAD_NANDF_D9__PATA_DATA9 */ | ||
| 572 | IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 5, 0x940, 1), /* MX51_PAD_NANDF_D9__SD3_DATA1 */ | ||
| 573 | IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 2, 0x000, 0), /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ | ||
| 574 | IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 3, 0x000, 0), /* MX51_PAD_NANDF_D8__GPIO4_0 */ | ||
| 575 | IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 0, 0x000, 0), /* MX51_PAD_NANDF_D8__NANDF_D8 */ | ||
| 576 | IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 1, 0x000, 0), /* MX51_PAD_NANDF_D8__PATA_DATA8 */ | ||
| 577 | IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 5, 0x93c, 1), /* MX51_PAD_NANDF_D8__SD3_DATA0 */ | ||
| 578 | IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 3, 0x000, 0), /* MX51_PAD_NANDF_D7__GPIO4_1 */ | ||
| 579 | IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 0, 0x000, 0), /* MX51_PAD_NANDF_D7__NANDF_D7 */ | ||
| 580 | IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 1, 0x000, 0), /* MX51_PAD_NANDF_D7__PATA_DATA7 */ | ||
| 581 | IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 5, 0x9fc, 0), /* MX51_PAD_NANDF_D7__USBH3_DATA0 */ | ||
| 582 | IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 3, 0x000, 0), /* MX51_PAD_NANDF_D6__GPIO4_2 */ | ||
| 583 | IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 0, 0x000, 0), /* MX51_PAD_NANDF_D6__NANDF_D6 */ | ||
| 584 | IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 1, 0x000, 0), /* MX51_PAD_NANDF_D6__PATA_DATA6 */ | ||
| 585 | IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 2, 0x000, 0), /* MX51_PAD_NANDF_D6__SD4_LCTL */ | ||
| 586 | IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 5, 0xa00, 0), /* MX51_PAD_NANDF_D6__USBH3_DATA1 */ | ||
| 587 | IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 3, 0x000, 0), /* MX51_PAD_NANDF_D5__GPIO4_3 */ | ||
| 588 | IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 0, 0x000, 0), /* MX51_PAD_NANDF_D5__NANDF_D5 */ | ||
| 589 | IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 1, 0x000, 0), /* MX51_PAD_NANDF_D5__PATA_DATA5 */ | ||
| 590 | IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 2, 0x000, 0), /* MX51_PAD_NANDF_D5__SD4_WP */ | ||
| 591 | IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 5, 0xa04, 0), /* MX51_PAD_NANDF_D5__USBH3_DATA2 */ | ||
| 592 | IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 3, 0x000, 0), /* MX51_PAD_NANDF_D4__GPIO4_4 */ | ||
| 593 | IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 0, 0x000, 0), /* MX51_PAD_NANDF_D4__NANDF_D4 */ | ||
| 594 | IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 1, 0x000, 0), /* MX51_PAD_NANDF_D4__PATA_DATA4 */ | ||
| 595 | IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 2, 0x000, 0), /* MX51_PAD_NANDF_D4__SD4_CD */ | ||
| 596 | IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 5, 0xa08, 0), /* MX51_PAD_NANDF_D4__USBH3_DATA3 */ | ||
| 597 | IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 3, 0x000, 0), /* MX51_PAD_NANDF_D3__GPIO4_5 */ | ||
| 598 | IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 0, 0x000, 0), /* MX51_PAD_NANDF_D3__NANDF_D3 */ | ||
| 599 | IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 1, 0x000, 0), /* MX51_PAD_NANDF_D3__PATA_DATA3 */ | ||
| 600 | IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 2, 0x000, 0), /* MX51_PAD_NANDF_D3__SD4_DAT4 */ | ||
| 601 | IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 5, 0xa0c, 0), /* MX51_PAD_NANDF_D3__USBH3_DATA4 */ | ||
| 602 | IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 3, 0x000, 0), /* MX51_PAD_NANDF_D2__GPIO4_6 */ | ||
| 603 | IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 0, 0x000, 0), /* MX51_PAD_NANDF_D2__NANDF_D2 */ | ||
| 604 | IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 1, 0x000, 0), /* MX51_PAD_NANDF_D2__PATA_DATA2 */ | ||
| 605 | IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 2, 0x000, 0), /* MX51_PAD_NANDF_D2__SD4_DAT5 */ | ||
| 606 | IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 5, 0xa10, 0), /* MX51_PAD_NANDF_D2__USBH3_DATA5 */ | ||
| 607 | IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 3, 0x000, 0), /* MX51_PAD_NANDF_D1__GPIO4_7 */ | ||
| 608 | IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 0, 0x000, 0), /* MX51_PAD_NANDF_D1__NANDF_D1 */ | ||
| 609 | IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 1, 0x000, 0), /* MX51_PAD_NANDF_D1__PATA_DATA1 */ | ||
| 610 | IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 2, 0x000, 0), /* MX51_PAD_NANDF_D1__SD4_DAT6 */ | ||
| 611 | IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 5, 0xa14, 0), /* MX51_PAD_NANDF_D1__USBH3_DATA6 */ | ||
| 612 | IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 3, 0x000, 0), /* MX51_PAD_NANDF_D0__GPIO4_8 */ | ||
| 613 | IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 0, 0x000, 0), /* MX51_PAD_NANDF_D0__NANDF_D0 */ | ||
| 614 | IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 1, 0x000, 0), /* MX51_PAD_NANDF_D0__PATA_DATA0 */ | ||
| 615 | IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 2, 0x000, 0), /* MX51_PAD_NANDF_D0__SD4_DAT7 */ | ||
| 616 | IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 5, 0xa18, 0), /* MX51_PAD_NANDF_D0__USBH3_DATA7 */ | ||
| 617 | IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 0, 0x000, 0), /* MX51_PAD_CSI1_D8__CSI1_D8 */ | ||
| 618 | IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 3, 0x998, 1), /* MX51_PAD_CSI1_D8__GPIO3_12 */ | ||
| 619 | IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 0, 0x000, 0), /* MX51_PAD_CSI1_D9__CSI1_D9 */ | ||
| 620 | IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 3, 0x000, 0), /* MX51_PAD_CSI1_D9__GPIO3_13 */ | ||
| 621 | IMX_PIN_REG(MX51_PAD_CSI1_D10, 0x584, 0x19c, 0, 0x000, 0), /* MX51_PAD_CSI1_D10__CSI1_D10 */ | ||
| 622 | IMX_PIN_REG(MX51_PAD_CSI1_D11, 0x588, 0x1a0, 0, 0x000, 0), /* MX51_PAD_CSI1_D11__CSI1_D11 */ | ||
| 623 | IMX_PIN_REG(MX51_PAD_CSI1_D12, 0x58c, 0x1a4, 0, 0x000, 0), /* MX51_PAD_CSI1_D12__CSI1_D12 */ | ||
| 624 | IMX_PIN_REG(MX51_PAD_CSI1_D13, 0x590, 0x1a8, 0, 0x000, 0), /* MX51_PAD_CSI1_D13__CSI1_D13 */ | ||
| 625 | IMX_PIN_REG(MX51_PAD_CSI1_D14, 0x594, 0x1ac, 0, 0x000, 0), /* MX51_PAD_CSI1_D14__CSI1_D14 */ | ||
| 626 | IMX_PIN_REG(MX51_PAD_CSI1_D15, 0x598, 0x1b0, 0, 0x000, 0), /* MX51_PAD_CSI1_D15__CSI1_D15 */ | ||
| 627 | IMX_PIN_REG(MX51_PAD_CSI1_D16, 0x59c, 0x1b4, 0, 0x000, 0), /* MX51_PAD_CSI1_D16__CSI1_D16 */ | ||
| 628 | IMX_PIN_REG(MX51_PAD_CSI1_D17, 0x5a0, 0x1b8, 0, 0x000, 0), /* MX51_PAD_CSI1_D17__CSI1_D17 */ | ||
| 629 | IMX_PIN_REG(MX51_PAD_CSI1_D18, 0x5a4, 0x1bc, 0, 0x000, 0), /* MX51_PAD_CSI1_D18__CSI1_D18 */ | ||
| 630 | IMX_PIN_REG(MX51_PAD_CSI1_D19, 0x5a8, 0x1c0, 0, 0x000, 0), /* MX51_PAD_CSI1_D19__CSI1_D19 */ | ||
| 631 | IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 0, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__CSI1_VSYNC */ | ||
| 632 | IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 3, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__GPIO3_14 */ | ||
| 633 | IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 0, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__CSI1_HSYNC */ | ||
| 634 | IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 3, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__GPIO3_15 */ | ||
| 635 | IMX_PIN_REG(MX51_PAD_CSI1_PIXCLK, 0x5b4, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK */ | ||
| 636 | IMX_PIN_REG(MX51_PAD_CSI1_MCLK, 0x5b8, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_MCLK__CSI1_MCLK */ | ||
| 637 | IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 0, 0x000, 0), /* MX51_PAD_CSI2_D12__CSI2_D12 */ | ||
| 638 | IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 3, 0x000, 0), /* MX51_PAD_CSI2_D12__GPIO4_9 */ | ||
| 639 | IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 0, 0x000, 0), /* MX51_PAD_CSI2_D13__CSI2_D13 */ | ||
| 640 | IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 3, 0x000, 0), /* MX51_PAD_CSI2_D13__GPIO4_10 */ | ||
| 641 | IMX_PIN_REG(MX51_PAD_CSI2_D14, 0x5c4, 0x1d4, 0, 0x000, 0), /* MX51_PAD_CSI2_D14__CSI2_D14 */ | ||
| 642 | IMX_PIN_REG(MX51_PAD_CSI2_D15, 0x5c8, 0x1d8, 0, 0x000, 0), /* MX51_PAD_CSI2_D15__CSI2_D15 */ | ||
| 643 | IMX_PIN_REG(MX51_PAD_CSI2_D16, 0x5cc, 0x1dc, 0, 0x000, 0), /* MX51_PAD_CSI2_D16__CSI2_D16 */ | ||
| 644 | IMX_PIN_REG(MX51_PAD_CSI2_D17, 0x5d0, 0x1e0, 0, 0x000, 0), /* MX51_PAD_CSI2_D17__CSI2_D17 */ | ||
| 645 | IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 0, 0x000, 0), /* MX51_PAD_CSI2_D18__CSI2_D18 */ | ||
| 646 | IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 3, 0x000, 0), /* MX51_PAD_CSI2_D18__GPIO4_11 */ | ||
| 647 | IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 0, 0x000, 0), /* MX51_PAD_CSI2_D19__CSI2_D19 */ | ||
| 648 | IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 3, 0x000, 0), /* MX51_PAD_CSI2_D19__GPIO4_12 */ | ||
| 649 | IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 0, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__CSI2_VSYNC */ | ||
| 650 | IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 3, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__GPIO4_13 */ | ||
| 651 | IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 0, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__CSI2_HSYNC */ | ||
| 652 | IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 3, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__GPIO4_14 */ | ||
| 653 | IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 0, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK */ | ||
| 654 | IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 3, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__GPIO4_15 */ | ||
| 655 | IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 3, 0x000, 0), /* MX51_PAD_I2C1_CLK__GPIO4_16 */ | ||
| 656 | IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 0, 0x000, 0), /* MX51_PAD_I2C1_CLK__I2C1_CLK */ | ||
| 657 | IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 3, 0x000, 0), /* MX51_PAD_I2C1_DAT__GPIO4_17 */ | ||
| 658 | IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 0, 0x000, 0), /* MX51_PAD_I2C1_DAT__I2C1_DAT */ | ||
| 659 | IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ | ||
| 660 | IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__GPIO4_18 */ | ||
| 661 | IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ | ||
| 662 | IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__GPIO4_19 */ | ||
| 663 | IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 1, 0x9f4, 2), /* MX51_PAD_AUD3_BB_RXD__UART3_RXD */ | ||
| 664 | IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ | ||
| 665 | IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__GPIO4_20 */ | ||
| 666 | IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ | ||
| 667 | IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__GPIO4_21 */ | ||
| 668 | IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 1, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__UART3_TXD */ | ||
| 669 | IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 0, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ | ||
| 670 | IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 3, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__GPIO4_22 */ | ||
| 671 | IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 1, 0x9b4, 1), /* MX51_PAD_CSPI1_MOSI__I2C1_SDA */ | ||
| 672 | IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 1, 0x8c4, 1), /* MX51_PAD_CSPI1_MISO__AUD4_RXD */ | ||
| 673 | IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 0, 0x000, 0), /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ | ||
| 674 | IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 3, 0x000, 0), /* MX51_PAD_CSPI1_MISO__GPIO4_23 */ | ||
| 675 | IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 1, 0x8cc, 1), /* MX51_PAD_CSPI1_SS0__AUD4_TXC */ | ||
| 676 | IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS0__ECSPI1_SS0 */ | ||
| 677 | IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ | ||
| 678 | IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 1, 0x8c8, 1), /* MX51_PAD_CSPI1_SS1__AUD4_TXD */ | ||
| 679 | IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS1__ECSPI1_SS1 */ | ||
| 680 | IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ | ||
| 681 | IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 1, 0x8d0, 1), /* MX51_PAD_CSPI1_RDY__AUD4_TXFS */ | ||
| 682 | IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 0, 0x000, 0), /* MX51_PAD_CSPI1_RDY__ECSPI1_RDY */ | ||
| 683 | IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 3, 0x000, 0), /* MX51_PAD_CSPI1_RDY__GPIO4_26 */ | ||
| 684 | IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 0, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ | ||
| 685 | IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 3, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__GPIO4_27 */ | ||
| 686 | IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 1, 0x9b0, 1), /* MX51_PAD_CSPI1_SCLK__I2C1_SCL */ | ||
| 687 | IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 3, 0x000, 0), /* MX51_PAD_UART1_RXD__GPIO4_28 */ | ||
| 688 | IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 0, 0x9e4, 0), /* MX51_PAD_UART1_RXD__UART1_RXD */ | ||
| 689 | IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 3, 0x000, 0), /* MX51_PAD_UART1_TXD__GPIO4_29 */ | ||
| 690 | IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 1, 0x000, 0), /* MX51_PAD_UART1_TXD__PWM2_PWMO */ | ||
| 691 | IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 0, 0x000, 0), /* MX51_PAD_UART1_TXD__UART1_TXD */ | ||
| 692 | IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 3, 0x000, 0), /* MX51_PAD_UART1_RTS__GPIO4_30 */ | ||
| 693 | IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 0, 0x9e0, 0), /* MX51_PAD_UART1_RTS__UART1_RTS */ | ||
| 694 | IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 3, 0x000, 0), /* MX51_PAD_UART1_CTS__GPIO4_31 */ | ||
| 695 | IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 0, 0x000, 0), /* MX51_PAD_UART1_CTS__UART1_CTS */ | ||
| 696 | IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 1, 0x000, 0), /* MX51_PAD_UART2_RXD__FIRI_TXD */ | ||
| 697 | IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 3, 0x000, 0), /* MX51_PAD_UART2_RXD__GPIO1_20 */ | ||
| 698 | IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 0, 0x9ec, 2), /* MX51_PAD_UART2_RXD__UART2_RXD */ | ||
| 699 | IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 1, 0x000, 0), /* MX51_PAD_UART2_TXD__FIRI_RXD */ | ||
| 700 | IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 3, 0x000, 0), /* MX51_PAD_UART2_TXD__GPIO1_21 */ | ||
| 701 | IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 0, 0x000, 0), /* MX51_PAD_UART2_TXD__UART2_TXD */ | ||
| 702 | IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 2, 0x000, 0), /* MX51_PAD_UART3_RXD__CSI1_D0 */ | ||
| 703 | IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 3, 0x000, 0), /* MX51_PAD_UART3_RXD__GPIO1_22 */ | ||
| 704 | IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 0, 0x000, 0), /* MX51_PAD_UART3_RXD__UART1_DTR */ | ||
| 705 | IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 1, 0x9f4, 4), /* MX51_PAD_UART3_RXD__UART3_RXD */ | ||
| 706 | IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 2, 0x000, 0), /* MX51_PAD_UART3_TXD__CSI1_D1 */ | ||
| 707 | IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 3, 0x000, 0), /* MX51_PAD_UART3_TXD__GPIO1_23 */ | ||
| 708 | IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 0, 0x000, 0), /* MX51_PAD_UART3_TXD__UART1_DSR */ | ||
| 709 | IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 1, 0x000, 0), /* MX51_PAD_UART3_TXD__UART3_TXD */ | ||
| 710 | IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 3, 0x000, 0), /* MX51_PAD_OWIRE_LINE__GPIO1_24 */ | ||
| 711 | IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 0, 0x000, 0), /* MX51_PAD_OWIRE_LINE__OWIRE_LINE */ | ||
| 712 | IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 6, 0x000, 0), /* MX51_PAD_OWIRE_LINE__SPDIF_OUT */ | ||
| 713 | IMX_PIN_REG(MX51_PAD_KEY_ROW0, 0x63c, 0x24c, 0, 0x000, 0), /* MX51_PAD_KEY_ROW0__KEY_ROW0 */ | ||
| 714 | IMX_PIN_REG(MX51_PAD_KEY_ROW1, 0x640, 0x250, 0, 0x000, 0), /* MX51_PAD_KEY_ROW1__KEY_ROW1 */ | ||
| 715 | IMX_PIN_REG(MX51_PAD_KEY_ROW2, 0x644, 0x254, 0, 0x000, 0), /* MX51_PAD_KEY_ROW2__KEY_ROW2 */ | ||
| 716 | IMX_PIN_REG(MX51_PAD_KEY_ROW3, 0x648, 0x258, 0, 0x000, 0), /* MX51_PAD_KEY_ROW3__KEY_ROW3 */ | ||
| 717 | IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 0, 0x000, 0), /* MX51_PAD_KEY_COL0__KEY_COL0 */ | ||
| 718 | IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 7, 0x90c, 0), /* MX51_PAD_KEY_COL0__PLL1_BYP */ | ||
| 719 | IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 0, 0x000, 0), /* MX51_PAD_KEY_COL1__KEY_COL1 */ | ||
| 720 | IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 7, 0x910, 0), /* MX51_PAD_KEY_COL1__PLL2_BYP */ | ||
| 721 | IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 0, 0x000, 0), /* MX51_PAD_KEY_COL2__KEY_COL2 */ | ||
| 722 | IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 7, 0x000, 0), /* MX51_PAD_KEY_COL2__PLL3_BYP */ | ||
| 723 | IMX_PIN_REG(MX51_PAD_KEY_COL3, 0x658, 0x268, 0, 0x000, 0), /* MX51_PAD_KEY_COL3__KEY_COL3 */ | ||
| 724 | IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 3, 0x9b8, 1), /* MX51_PAD_KEY_COL4__I2C2_SCL */ | ||
| 725 | IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 0, 0x000, 0), /* MX51_PAD_KEY_COL4__KEY_COL4 */ | ||
| 726 | IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 6, 0x000, 0), /* MX51_PAD_KEY_COL4__SPDIF_OUT1 */ | ||
| 727 | IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 1, 0x000, 0), /* MX51_PAD_KEY_COL4__UART1_RI */ | ||
| 728 | IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 2, 0x9f0, 4), /* MX51_PAD_KEY_COL4__UART3_RTS */ | ||
| 729 | IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 3, 0x9bc, 1), /* MX51_PAD_KEY_COL5__I2C2_SDA */ | ||
| 730 | IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 0, 0x000, 0), /* MX51_PAD_KEY_COL5__KEY_COL5 */ | ||
| 731 | IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 1, 0x000, 0), /* MX51_PAD_KEY_COL5__UART1_DCD */ | ||
| 732 | IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 2, 0x000, 0), /* MX51_PAD_KEY_COL5__UART3_CTS */ | ||
| 733 | IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 1, 0x914, 1), /* MX51_PAD_USBH1_CLK__CSPI_SCLK */ | ||
| 734 | IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 2, 0x000, 0), /* MX51_PAD_USBH1_CLK__GPIO1_25 */ | ||
| 735 | IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 5, 0x9b8, 2), /* MX51_PAD_USBH1_CLK__I2C2_SCL */ | ||
| 736 | IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 0, 0x000, 0), /* MX51_PAD_USBH1_CLK__USBH1_CLK */ | ||
| 737 | IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 1, 0x91c, 1), /* MX51_PAD_USBH1_DIR__CSPI_MOSI */ | ||
| 738 | IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 2, 0x000, 0), /* MX51_PAD_USBH1_DIR__GPIO1_26 */ | ||
| 739 | IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 5, 0x9bc, 2), /* MX51_PAD_USBH1_DIR__I2C2_SDA */ | ||
| 740 | IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 0, 0x000, 0), /* MX51_PAD_USBH1_DIR__USBH1_DIR */ | ||
| 741 | IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 1, 0x000, 0), /* MX51_PAD_USBH1_STP__CSPI_RDY */ | ||
| 742 | IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 2, 0x000, 0), /* MX51_PAD_USBH1_STP__GPIO1_27 */ | ||
| 743 | IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 5, 0x9f4, 6), /* MX51_PAD_USBH1_STP__UART3_RXD */ | ||
| 744 | IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 0, 0x000, 0), /* MX51_PAD_USBH1_STP__USBH1_STP */ | ||
| 745 | IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 1, 0x918, 0), /* MX51_PAD_USBH1_NXT__CSPI_MISO */ | ||
| 746 | IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 2, 0x000, 0), /* MX51_PAD_USBH1_NXT__GPIO1_28 */ | ||
| 747 | IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 5, 0x000, 0), /* MX51_PAD_USBH1_NXT__UART3_TXD */ | ||
| 748 | IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 0, 0x000, 0), /* MX51_PAD_USBH1_NXT__USBH1_NXT */ | ||
| 749 | IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA0__GPIO1_11 */ | ||
| 750 | IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA0__UART2_CTS */ | ||
| 751 | IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA0__USBH1_DATA0 */ | ||
| 752 | IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA1__GPIO1_12 */ | ||
| 753 | IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 1, 0x9ec, 4), /* MX51_PAD_USBH1_DATA1__UART2_RXD */ | ||
| 754 | IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA1__USBH1_DATA1 */ | ||
| 755 | IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA2__GPIO1_13 */ | ||
| 756 | IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA2__UART2_TXD */ | ||
| 757 | IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA2__USBH1_DATA2 */ | ||
| 758 | IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA3__GPIO1_14 */ | ||
| 759 | IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 1, 0x9e8, 5), /* MX51_PAD_USBH1_DATA3__UART2_RTS */ | ||
| 760 | IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA3__USBH1_DATA3 */ | ||
| 761 | IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA4__CSPI_SS0 */ | ||
| 762 | IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA4__GPIO1_15 */ | ||
| 763 | IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA4__USBH1_DATA4 */ | ||
| 764 | IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 1, 0x920, 0), /* MX51_PAD_USBH1_DATA5__CSPI_SS1 */ | ||
| 765 | IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA5__GPIO1_16 */ | ||
| 766 | IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA5__USBH1_DATA5 */ | ||
| 767 | IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 1, 0x928, 1), /* MX51_PAD_USBH1_DATA6__CSPI_SS3 */ | ||
| 768 | IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA6__GPIO1_17 */ | ||
| 769 | IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA6__USBH1_DATA6 */ | ||
| 770 | IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA7__ECSPI1_SS3 */ | ||
| 771 | IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 5, 0x934, 1), /* MX51_PAD_USBH1_DATA7__ECSPI2_SS3 */ | ||
| 772 | IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA7__GPIO1_18 */ | ||
| 773 | IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA7__USBH1_DATA7 */ | ||
| 774 | IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 0, 0x000, 0), /* MX51_PAD_DI1_PIN11__DI1_PIN11 */ | ||
| 775 | IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 7, 0x000, 0), /* MX51_PAD_DI1_PIN11__ECSPI1_SS2 */ | ||
| 776 | IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 4, 0x000, 0), /* MX51_PAD_DI1_PIN11__GPIO3_0 */ | ||
| 777 | IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 0, 0x000, 0), /* MX51_PAD_DI1_PIN12__DI1_PIN12 */ | ||
| 778 | IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 4, 0x978, 1), /* MX51_PAD_DI1_PIN12__GPIO3_1 */ | ||
| 779 | IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 0, 0x000, 0), /* MX51_PAD_DI1_PIN13__DI1_PIN13 */ | ||
| 780 | IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 4, 0x97c, 1), /* MX51_PAD_DI1_PIN13__GPIO3_2 */ | ||
| 781 | IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 0, 0x000, 0), /* MX51_PAD_DI1_D0_CS__DI1_D0_CS */ | ||
| 782 | IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 4, 0x980, 1), /* MX51_PAD_DI1_D0_CS__GPIO3_3 */ | ||
| 783 | IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 0, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DI1_D1_CS */ | ||
| 784 | IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 2, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN14 */ | ||
| 785 | IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 3, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN5 */ | ||
| 786 | IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 4, 0x984, 1), /* MX51_PAD_DI1_D1_CS__GPIO3_4 */ | ||
| 787 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 2, 0x9a4, 1), /* MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 */ | ||
| 788 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 0, 0x9c4, 0), /* MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN */ | ||
| 789 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 4, 0x988, 1), /* MX51_PAD_DISPB2_SER_DIN__GPIO3_5 */ | ||
| 790 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 */ | ||
| 791 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 0, 0x9c4, 1), /* MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO */ | ||
| 792 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 4, 0x98c, 1), /* MX51_PAD_DISPB2_SER_DIO__GPIO3_6 */ | ||
| 793 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 */ | ||
| 794 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 */ | ||
| 795 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK */ | ||
| 796 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 4, 0x990, 1), /* MX51_PAD_DISPB2_SER_CLK__GPIO3_7 */ | ||
| 797 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK */ | ||
| 798 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 */ | ||
| 799 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 */ | ||
| 800 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */ | ||
| 801 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */ | ||
| 802 | IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 4, 0x994, 1), /* MX51_PAD_DISPB2_SER_RS__GPIO3_8 */ | ||
| 803 | IMX_PIN_REG(MX51_PAD_DISP1_DAT0, 0x6cc, 0x2cc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */ | ||
| 804 | IMX_PIN_REG(MX51_PAD_DISP1_DAT1, 0x6d0, 0x2d0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */ | ||
| 805 | IMX_PIN_REG(MX51_PAD_DISP1_DAT2, 0x6d4, 0x2d4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */ | ||
| 806 | IMX_PIN_REG(MX51_PAD_DISP1_DAT3, 0x6d8, 0x2d8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */ | ||
| 807 | IMX_PIN_REG(MX51_PAD_DISP1_DAT4, 0x6dc, 0x2dc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */ | ||
| 808 | IMX_PIN_REG(MX51_PAD_DISP1_DAT5, 0x6e0, 0x2e0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */ | ||
| 809 | IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT6__BOOT_USB_SRC */ | ||
| 810 | IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */ | ||
| 811 | IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG */ | ||
| 812 | IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */ | ||
| 813 | IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT8__BOOT_SRC0 */ | ||
| 814 | IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */ | ||
| 815 | IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT9__BOOT_SRC1 */ | ||
| 816 | IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */ | ||
| 817 | IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE */ | ||
| 818 | IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */ | ||
| 819 | IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 */ | ||
| 820 | IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */ | ||
| 821 | IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL */ | ||
| 822 | IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */ | ||
| 823 | IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 */ | ||
| 824 | IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */ | ||
| 825 | IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 */ | ||
| 826 | IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */ | ||
| 827 | IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH */ | ||
| 828 | IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */ | ||
| 829 | IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 */ | ||
| 830 | IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */ | ||
| 831 | IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 */ | ||
| 832 | IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */ | ||
| 833 | IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 */ | ||
| 834 | IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */ | ||
| 835 | IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN11 */ | ||
| 836 | IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN5 */ | ||
| 837 | IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 */ | ||
| 838 | IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */ | ||
| 839 | IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN12 */ | ||
| 840 | IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN6 */ | ||
| 841 | IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 */ | ||
| 842 | IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */ | ||
| 843 | IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN13 */ | ||
| 844 | IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN7 */ | ||
| 845 | IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 */ | ||
| 846 | IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */ | ||
| 847 | IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN14 */ | ||
| 848 | IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN8 */ | ||
| 849 | IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 */ | ||
| 850 | IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */ | ||
| 851 | IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_D0_CS */ | ||
| 852 | IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_DAT16 */ | ||
| 853 | IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 */ | ||
| 854 | IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */ | ||
| 855 | IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_D1_CS */ | ||
| 856 | IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_DAT17 */ | ||
| 857 | IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_SER_CS */ | ||
| 858 | IMX_PIN_REG(MX51_PAD_DI1_PIN3, 0x72c, 0x32c, 0, 0x000, 0), /* MX51_PAD_DI1_PIN3__DI1_PIN3 */ | ||
| 859 | IMX_PIN_REG(MX51_PAD_DI1_PIN2, 0x734, 0x330, 0, 0x000, 0), /* MX51_PAD_DI1_PIN2__DI1_PIN2 */ | ||
| 860 | IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 0, 0x000, 0), /* MX51_PAD_DI_GP2__DISP1_SER_CLK */ | ||
| 861 | IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 2, 0x9a8, 1), /* MX51_PAD_DI_GP2__DISP2_WAIT */ | ||
| 862 | IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 3, 0x9a0, 1), /* MX51_PAD_DI_GP3__CSI1_DATA_EN */ | ||
| 863 | IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 0, 0x9c0, 0), /* MX51_PAD_DI_GP3__DISP1_SER_DIO */ | ||
| 864 | IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 2, 0x000, 0), /* MX51_PAD_DI_GP3__FEC_TX_ER */ | ||
| 865 | IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 3, 0x99c, 1), /* MX51_PAD_DI2_PIN4__CSI2_DATA_EN */ | ||
| 866 | IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 0, 0x000, 0), /* MX51_PAD_DI2_PIN4__DI2_PIN4 */ | ||
| 867 | IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 2, 0x950, 1), /* MX51_PAD_DI2_PIN4__FEC_CRS */ | ||
| 868 | IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 0, 0x000, 0), /* MX51_PAD_DI2_PIN2__DI2_PIN2 */ | ||
| 869 | IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 2, 0x000, 0), /* MX51_PAD_DI2_PIN2__FEC_MDC */ | ||
| 870 | IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 0, 0x000, 0), /* MX51_PAD_DI2_PIN3__DI2_PIN3 */ | ||
| 871 | IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 2, 0x954, 1), /* MX51_PAD_DI2_PIN3__FEC_MDIO */ | ||
| 872 | IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 0, 0x000, 0), /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */ | ||
| 873 | IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 2, 0x95c, 1), /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */ | ||
| 874 | IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 4, 0x000, 0), /* MX51_PAD_DI_GP4__DI2_PIN15 */ | ||
| 875 | IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 0, 0x9c0, 1), /* MX51_PAD_DI_GP4__DISP1_SER_DIN */ | ||
| 876 | IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 3, 0x000, 0), /* MX51_PAD_DI_GP4__DISP2_PIN1 */ | ||
| 877 | IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 2, 0x960, 1), /* MX51_PAD_DI_GP4__FEC_RDATA2 */ | ||
| 878 | IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */ | ||
| 879 | IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 2, 0x964, 1), /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */ | ||
| 880 | IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 4, 0x9c8, 1), /* MX51_PAD_DISP2_DAT0__KEY_COL6 */ | ||
| 881 | IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 5, 0x9f4, 8), /* MX51_PAD_DISP2_DAT0__UART3_RXD */ | ||
| 882 | IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 3, 0x9f8, 1), /* MX51_PAD_DISP2_DAT0__USBH3_CLK */ | ||
| 883 | IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */ | ||
| 884 | IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 2, 0x970, 1), /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */ | ||
| 885 | IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 4, 0x9cc, 1), /* MX51_PAD_DISP2_DAT1__KEY_COL7 */ | ||
| 886 | IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT1__UART3_TXD */ | ||
| 887 | IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 3, 0xa1c, 1), /* MX51_PAD_DISP2_DAT1__USBH3_DIR */ | ||
| 888 | IMX_PIN_REG(MX51_PAD_DISP2_DAT2, 0x764, 0x35c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */ | ||
| 889 | IMX_PIN_REG(MX51_PAD_DISP2_DAT3, 0x768, 0x360, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */ | ||
| 890 | IMX_PIN_REG(MX51_PAD_DISP2_DAT4, 0x76c, 0x364, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */ | ||
| 891 | IMX_PIN_REG(MX51_PAD_DISP2_DAT5, 0x770, 0x368, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */ | ||
| 892 | IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */ | ||
| 893 | IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */ | ||
| 894 | IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT6__GPIO1_19 */ | ||
| 895 | IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 4, 0x9d0, 1), /* MX51_PAD_DISP2_DAT6__KEY_ROW4 */ | ||
| 896 | IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 3, 0xa24, 1), /* MX51_PAD_DISP2_DAT6__USBH3_STP */ | ||
| 897 | IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */ | ||
| 898 | IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */ | ||
| 899 | IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT7__GPIO1_29 */ | ||
| 900 | IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 4, 0x9d4, 1), /* MX51_PAD_DISP2_DAT7__KEY_ROW5 */ | ||
| 901 | IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 3, 0xa20, 1), /* MX51_PAD_DISP2_DAT7__USBH3_NXT */ | ||
| 902 | IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */ | ||
| 903 | IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */ | ||
| 904 | IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT8__GPIO1_30 */ | ||
| 905 | IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 4, 0x9d8, 1), /* MX51_PAD_DISP2_DAT8__KEY_ROW6 */ | ||
| 906 | IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 3, 0x9fc, 1), /* MX51_PAD_DISP2_DAT8__USBH3_DATA0 */ | ||
| 907 | IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 4, 0x8f4, 1), /* MX51_PAD_DISP2_DAT9__AUD6_RXC */ | ||
| 908 | IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */ | ||
| 909 | IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */ | ||
| 910 | IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT9__GPIO1_31 */ | ||
| 911 | IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 3, 0xa00, 1), /* MX51_PAD_DISP2_DAT9__USBH3_DATA1 */ | ||
| 912 | IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */ | ||
| 913 | IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_SER_CS */ | ||
| 914 | IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 2, 0x94c, 1), /* MX51_PAD_DISP2_DAT10__FEC_COL */ | ||
| 915 | IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 4, 0x9dc, 1), /* MX51_PAD_DISP2_DAT10__KEY_ROW7 */ | ||
| 916 | IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 3, 0xa04, 1), /* MX51_PAD_DISP2_DAT10__USBH3_DATA2 */ | ||
| 917 | IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 4, 0x8f0, 1), /* MX51_PAD_DISP2_DAT11__AUD6_TXD */ | ||
| 918 | IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */ | ||
| 919 | IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 2, 0x968, 1), /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */ | ||
| 920 | IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 7, 0x000, 0), /* MX51_PAD_DISP2_DAT11__GPIO1_10 */ | ||
| 921 | IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 3, 0xa08, 1), /* MX51_PAD_DISP2_DAT11__USBH3_DATA3 */ | ||
| 922 | IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 4, 0x8ec, 1), /* MX51_PAD_DISP2_DAT12__AUD6_RXD */ | ||
| 923 | IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */ | ||
| 924 | IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 2, 0x96c, 1), /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */ | ||
| 925 | IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 3, 0xa0c, 1), /* MX51_PAD_DISP2_DAT12__USBH3_DATA4 */ | ||
| 926 | IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 4, 0x8fc, 1), /* MX51_PAD_DISP2_DAT13__AUD6_TXC */ | ||
| 927 | IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */ | ||
| 928 | IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 2, 0x974, 1), /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */ | ||
| 929 | IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 3, 0xa10, 1), /* MX51_PAD_DISP2_DAT13__USBH3_DATA5 */ | ||
| 930 | IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 4, 0x900, 1), /* MX51_PAD_DISP2_DAT14__AUD6_TXFS */ | ||
| 931 | IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */ | ||
| 932 | IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 2, 0x958, 1), /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */ | ||
| 933 | IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 3, 0xa14, 1), /* MX51_PAD_DISP2_DAT14__USBH3_DATA6 */ | ||
| 934 | IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 4, 0x8f8, 1), /* MX51_PAD_DISP2_DAT15__AUD6_RXFS */ | ||
| 935 | IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP1_SER_CS */ | ||
| 936 | IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */ | ||
| 937 | IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */ | ||
| 938 | IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 3, 0xa18, 1), /* MX51_PAD_DISP2_DAT15__USBH3_DATA7 */ | ||
| 939 | IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 1, 0x8e0, 1), /* MX51_PAD_SD1_CMD__AUD5_RXFS */ | ||
| 940 | IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 2, 0x91c, 2), /* MX51_PAD_SD1_CMD__CSPI_MOSI */ | ||
| 941 | IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 0, 0x000, 0), /* MX51_PAD_SD1_CMD__SD1_CMD */ | ||
| 942 | IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 1, 0x8dc, 1), /* MX51_PAD_SD1_CLK__AUD5_RXC */ | ||
| 943 | IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 2, 0x914, 2), /* MX51_PAD_SD1_CLK__CSPI_SCLK */ | ||
| 944 | IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 0, 0x000, 0), /* MX51_PAD_SD1_CLK__SD1_CLK */ | ||
| 945 | IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 1, 0x8d8, 2), /* MX51_PAD_SD1_DATA0__AUD5_TXD */ | ||
| 946 | IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 2, 0x918, 1), /* MX51_PAD_SD1_DATA0__CSPI_MISO */ | ||
| 947 | IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 0, 0x000, 0), /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ | ||
| 948 | IMX_PIN_REG(MX51_PAD_EIM_DA0, NO_PAD, 0x01c, 0, 0x000, 0), /* MX51_PAD_EIM_DA0__EIM_DA0 */ | ||
| 949 | IMX_PIN_REG(MX51_PAD_EIM_DA1, NO_PAD, 0x020, 0, 0x000, 0), /* MX51_PAD_EIM_DA1__EIM_DA1 */ | ||
| 950 | IMX_PIN_REG(MX51_PAD_EIM_DA2, NO_PAD, 0x024, 0, 0x000, 0), /* MX51_PAD_EIM_DA2__EIM_DA2 */ | ||
| 951 | IMX_PIN_REG(MX51_PAD_EIM_DA3, NO_PAD, 0x028, 0, 0x000, 0), /* MX51_PAD_EIM_DA3__EIM_DA3 */ | ||
| 952 | IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 1, 0x8d4, 2), /* MX51_PAD_SD1_DATA1__AUD5_RXD */ | ||
| 953 | IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 0, 0x000, 0), /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ | ||
| 954 | IMX_PIN_REG(MX51_PAD_EIM_DA4, NO_PAD, 0x02c, 0, 0x000, 0), /* MX51_PAD_EIM_DA4__EIM_DA4 */ | ||
| 955 | IMX_PIN_REG(MX51_PAD_EIM_DA5, NO_PAD, 0x030, 0, 0x000, 0), /* MX51_PAD_EIM_DA5__EIM_DA5 */ | ||
| 956 | IMX_PIN_REG(MX51_PAD_EIM_DA6, NO_PAD, 0x034, 0, 0x000, 0), /* MX51_PAD_EIM_DA6__EIM_DA6 */ | ||
| 957 | IMX_PIN_REG(MX51_PAD_EIM_DA7, NO_PAD, 0x038, 0, 0x000, 0), /* MX51_PAD_EIM_DA7__EIM_DA7 */ | ||
| 958 | IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 1, 0x8e4, 2), /* MX51_PAD_SD1_DATA2__AUD5_TXC */ | ||
| 959 | IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 0, 0x000, 0), /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ | ||
| 960 | IMX_PIN_REG(MX51_PAD_EIM_DA10, NO_PAD, 0x044, 0, 0x000, 0), /* MX51_PAD_EIM_DA10__EIM_DA10 */ | ||
| 961 | IMX_PIN_REG(MX51_PAD_EIM_DA11, NO_PAD, 0x048, 0, 0x000, 0), /* MX51_PAD_EIM_DA11__EIM_DA11 */ | ||
| 962 | IMX_PIN_REG(MX51_PAD_EIM_DA8, NO_PAD, 0x03c, 0, 0x000, 0), /* MX51_PAD_EIM_DA8__EIM_DA8 */ | ||
| 963 | IMX_PIN_REG(MX51_PAD_EIM_DA9, NO_PAD, 0x040, 0, 0x000, 0), /* MX51_PAD_EIM_DA9__EIM_DA9 */ | ||
| 964 | IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 1, 0x8e8, 2), /* MX51_PAD_SD1_DATA3__AUD5_TXFS */ | ||
| 965 | IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 2, 0x920, 1), /* MX51_PAD_SD1_DATA3__CSPI_SS1 */ | ||
| 966 | IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 0, 0x000, 0), /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ | ||
| 967 | IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 2, 0x924, 0), /* MX51_PAD_GPIO1_0__CSPI_SS2 */ | ||
| 968 | IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 1, 0x000, 0), /* MX51_PAD_GPIO1_0__GPIO1_0 */ | ||
| 969 | IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 0, 0x000, 0), /* MX51_PAD_GPIO1_0__SD1_CD */ | ||
| 970 | IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 2, 0x918, 2), /* MX51_PAD_GPIO1_1__CSPI_MISO */ | ||
| 971 | IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 1, 0x000, 0), /* MX51_PAD_GPIO1_1__GPIO1_1 */ | ||
| 972 | IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 0, 0x000, 0), /* MX51_PAD_GPIO1_1__SD1_WP */ | ||
| 973 | IMX_PIN_REG(MX51_PAD_EIM_DA12, NO_PAD, 0x04c, 0, 0x000, 0), /* MX51_PAD_EIM_DA12__EIM_DA12 */ | ||
| 974 | IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */ | ||
| 975 | IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */ | ||
| 976 | IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */ | ||
| 977 | IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */ | ||
| 978 | IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */ | ||
| 979 | IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */ | ||
| 980 | IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */ | ||
| 981 | IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 1, 0x9b4, 2), /* MX51_PAD_SD2_CLK__I2C1_SDA */ | ||
| 982 | IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 0, 0x000, 0), /* MX51_PAD_SD2_CLK__SD2_CLK */ | ||
| 983 | IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 2, 0x918, 3), /* MX51_PAD_SD2_DATA0__CSPI_MISO */ | ||
| 984 | IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 1, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD1_DAT4 */ | ||
| 985 | IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 0, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ | ||
| 986 | IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 1, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD1_DAT5 */ | ||
| 987 | IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 0, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ | ||
| 988 | IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 2, 0x000, 0), /* MX51_PAD_SD2_DATA1__USBH3_H2_DP */ | ||
| 989 | IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 1, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD1_DAT6 */ | ||
| 990 | IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 0, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ | ||
| 991 | IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 2, 0x000, 0), /* MX51_PAD_SD2_DATA2__USBH3_H2_DM */ | ||
| 992 | IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 2, 0x924, 1), /* MX51_PAD_SD2_DATA3__CSPI_SS2 */ | ||
| 993 | IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 1, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD1_DAT7 */ | ||
| 994 | IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 0, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ | ||
| 995 | IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 5, 0x000, 0), /* MX51_PAD_GPIO1_2__CCM_OUT_2 */ | ||
| 996 | IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 0, 0x000, 0), /* MX51_PAD_GPIO1_2__GPIO1_2 */ | ||
| 997 | IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 2, 0x9b8, 3), /* MX51_PAD_GPIO1_2__I2C2_SCL */ | ||
| 998 | IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 7, 0x90c, 1), /* MX51_PAD_GPIO1_2__PLL1_BYP */ | ||
| 999 | IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 1, 0x000, 0), /* MX51_PAD_GPIO1_2__PWM1_PWMO */ | ||
| 1000 | IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 0, 0x000, 0), /* MX51_PAD_GPIO1_3__GPIO1_3 */ | ||
| 1001 | IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 2, 0x9bc, 3), /* MX51_PAD_GPIO1_3__I2C2_SDA */ | ||
| 1002 | IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 7, 0x910, 1), /* MX51_PAD_GPIO1_3__PLL2_BYP */ | ||
| 1003 | IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 1, 0x000, 0), /* MX51_PAD_GPIO1_3__PWM2_PWMO */ | ||
| 1004 | IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 0, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ */ | ||
| 1005 | IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 1, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B */ | ||
| 1006 | IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 4, 0x908, 1), /* MX51_PAD_GPIO1_4__DISP2_EXT_CLK */ | ||
| 1007 | IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 3, 0x938, 1), /* MX51_PAD_GPIO1_4__EIM_RDY */ | ||
| 1008 | IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 0, 0x000, 0), /* MX51_PAD_GPIO1_4__GPIO1_4 */ | ||
| 1009 | IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 2, 0x000, 0), /* MX51_PAD_GPIO1_4__WDOG1_WDOG_B */ | ||
| 1010 | IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 6, 0x000, 0), /* MX51_PAD_GPIO1_5__CSI2_MCLK */ | ||
| 1011 | IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 3, 0x000, 0), /* MX51_PAD_GPIO1_5__DISP2_PIN16 */ | ||
| 1012 | IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 0, 0x000, 0), /* MX51_PAD_GPIO1_5__GPIO1_5 */ | ||
| 1013 | IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 2, 0x000, 0), /* MX51_PAD_GPIO1_5__WDOG2_WDOG_B */ | ||
| 1014 | IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 4, 0x000, 0), /* MX51_PAD_GPIO1_6__DISP2_PIN17 */ | ||
| 1015 | IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 0, 0x000, 0), /* MX51_PAD_GPIO1_6__GPIO1_6 */ | ||
| 1016 | IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 3, 0x000, 0), /* MX51_PAD_GPIO1_6__REF_EN_B */ | ||
| 1017 | IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 3, 0x000, 0), /* MX51_PAD_GPIO1_7__CCM_OUT_0 */ | ||
| 1018 | IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 0, 0x000, 0), /* MX51_PAD_GPIO1_7__GPIO1_7 */ | ||
| 1019 | IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 6, 0x000, 0), /* MX51_PAD_GPIO1_7__SD2_WP */ | ||
| 1020 | IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 2, 0x000, 0), /* MX51_PAD_GPIO1_7__SPDIF_OUT1 */ | ||
| 1021 | IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 2, 0x99c, 2), /* MX51_PAD_GPIO1_8__CSI2_DATA_EN */ | ||
| 1022 | IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 0, 0x000, 0), /* MX51_PAD_GPIO1_8__GPIO1_8 */ | ||
| 1023 | IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 6, 0x000, 0), /* MX51_PAD_GPIO1_8__SD2_CD */ | ||
| 1024 | IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 1, 0x000, 0), /* MX51_PAD_GPIO1_8__USBH3_PWR */ | ||
| 1025 | IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 3, 0x000, 0), /* MX51_PAD_GPIO1_9__CCM_OUT_1 */ | ||
| 1026 | IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 2, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_D1_CS */ | ||
| 1027 | IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 7, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_SER_CS */ | ||
| 1028 | IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 0, 0x000, 0), /* MX51_PAD_GPIO1_9__GPIO1_9 */ | ||
| 1029 | IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 6, 0x000, 0), /* MX51_PAD_GPIO1_9__SD2_LCTL */ | ||
| 1030 | IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 1, 0x000, 0), /* MX51_PAD_GPIO1_9__USBH3_OC */ | ||
| 1031 | }; | 393 | }; |
| 1032 | 394 | ||
| 1033 | /* Pad names for the pinmux subsystem */ | 395 | /* Pad names for the pinmux subsystem */ |
| 1034 | static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { | 396 | static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { |
| 397 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE0), | ||
| 398 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE1), | ||
| 399 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE2), | ||
| 400 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE3), | ||
| 401 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE4), | ||
| 402 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE5), | ||
| 403 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE6), | ||
| 404 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0), | ||
| 405 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1), | ||
| 406 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2), | ||
| 407 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3), | ||
| 408 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4), | ||
| 409 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5), | ||
| 410 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6), | ||
| 411 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7), | ||
| 412 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8), | ||
| 413 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9), | ||
| 414 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10), | ||
| 415 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11), | ||
| 416 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12), | ||
| 417 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13), | ||
| 418 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14), | ||
| 419 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15), | ||
| 1035 | IMX_PINCTRL_PIN(MX51_PAD_EIM_D16), | 420 | IMX_PINCTRL_PIN(MX51_PAD_EIM_D16), |
| 1036 | IMX_PINCTRL_PIN(MX51_PAD_EIM_D17), | 421 | IMX_PINCTRL_PIN(MX51_PAD_EIM_D17), |
| 1037 | IMX_PINCTRL_PIN(MX51_PAD_EIM_D18), | 422 | IMX_PINCTRL_PIN(MX51_PAD_EIM_D18), |
| @@ -1124,8 +509,6 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { | |||
| 1124 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19), | 509 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19), |
| 1125 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC), | 510 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC), |
| 1126 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC), | 511 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC), |
| 1127 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK), | ||
| 1128 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), | ||
| 1129 | IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12), | 512 | IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12), |
| 1130 | IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13), | 513 | IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13), |
| 1131 | IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14), | 514 | IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14), |
| @@ -1168,6 +551,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { | |||
| 1168 | IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3), | 551 | IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3), |
| 1169 | IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4), | 552 | IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4), |
| 1170 | IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5), | 553 | IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5), |
| 554 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE7), | ||
| 1171 | IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK), | 555 | IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK), |
| 1172 | IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR), | 556 | IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR), |
| 1173 | IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP), | 557 | IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP), |
| @@ -1215,6 +599,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { | |||
| 1215 | IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23), | 599 | IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23), |
| 1216 | IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3), | 600 | IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3), |
| 1217 | IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2), | 601 | IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2), |
| 602 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE8), | ||
| 1218 | IMX_PINCTRL_PIN(MX51_PAD_DI_GP2), | 603 | IMX_PINCTRL_PIN(MX51_PAD_DI_GP2), |
| 1219 | IMX_PINCTRL_PIN(MX51_PAD_DI_GP3), | 604 | IMX_PINCTRL_PIN(MX51_PAD_DI_GP3), |
| 1220 | IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4), | 605 | IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4), |
| @@ -1241,27 +626,11 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { | |||
| 1241 | IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD), | 626 | IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD), |
| 1242 | IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK), | 627 | IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK), |
| 1243 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0), | 628 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0), |
| 1244 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0), | ||
| 1245 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1), | ||
| 1246 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2), | ||
| 1247 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3), | ||
| 1248 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1), | 629 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1), |
| 1249 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4), | ||
| 1250 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5), | ||
| 1251 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6), | ||
| 1252 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7), | ||
| 1253 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2), | 630 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2), |
| 1254 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10), | ||
| 1255 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11), | ||
| 1256 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8), | ||
| 1257 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9), | ||
| 1258 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3), | 631 | IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3), |
| 1259 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0), | 632 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0), |
| 1260 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1), | 633 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1), |
| 1261 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12), | ||
| 1262 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13), | ||
| 1263 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14), | ||
| 1264 | IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15), | ||
| 1265 | IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD), | 634 | IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD), |
| 1266 | IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK), | 635 | IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK), |
| 1267 | IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0), | 636 | IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0), |
| @@ -1277,13 +646,126 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = { | |||
| 1277 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7), | 646 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7), |
| 1278 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8), | 647 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8), |
| 1279 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9), | 648 | IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9), |
| 649 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE9), | ||
| 650 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE10), | ||
| 651 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE11), | ||
| 652 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE12), | ||
| 653 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE13), | ||
| 654 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE14), | ||
| 655 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE15), | ||
| 656 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE16), | ||
| 657 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE17), | ||
| 658 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE18), | ||
| 659 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE19), | ||
| 660 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE20), | ||
| 661 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE21), | ||
| 662 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE22), | ||
| 663 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE23), | ||
| 664 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE24), | ||
| 665 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE25), | ||
| 666 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE26), | ||
| 667 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE27), | ||
| 668 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE28), | ||
| 669 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE29), | ||
| 670 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE30), | ||
| 671 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE31), | ||
| 672 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE32), | ||
| 673 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE33), | ||
| 674 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE34), | ||
| 675 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE35), | ||
| 676 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE36), | ||
| 677 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE37), | ||
| 678 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE38), | ||
| 679 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE39), | ||
| 680 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE40), | ||
| 681 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE41), | ||
| 682 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE42), | ||
| 683 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE43), | ||
| 684 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE44), | ||
| 685 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE45), | ||
| 686 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE46), | ||
| 687 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE47), | ||
| 688 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE48), | ||
| 689 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE49), | ||
| 690 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE50), | ||
| 691 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE51), | ||
| 692 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE52), | ||
| 693 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE53), | ||
| 694 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE54), | ||
| 695 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE55), | ||
| 696 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE56), | ||
| 697 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE57), | ||
| 698 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE58), | ||
| 699 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE59), | ||
| 700 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE60), | ||
| 701 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE61), | ||
| 702 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE62), | ||
| 703 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE63), | ||
| 704 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE64), | ||
| 705 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE65), | ||
| 706 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE66), | ||
| 707 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE67), | ||
| 708 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE68), | ||
| 709 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE69), | ||
| 710 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE70), | ||
| 711 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE71), | ||
| 712 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE72), | ||
| 713 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE73), | ||
| 714 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE74), | ||
| 715 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE75), | ||
| 716 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE76), | ||
| 717 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE77), | ||
| 718 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE78), | ||
| 719 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE79), | ||
| 720 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE80), | ||
| 721 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE81), | ||
| 722 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE82), | ||
| 723 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE83), | ||
| 724 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE84), | ||
| 725 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE85), | ||
| 726 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE86), | ||
| 727 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE87), | ||
| 728 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE88), | ||
| 729 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE89), | ||
| 730 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE90), | ||
| 731 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE91), | ||
| 732 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE92), | ||
| 733 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE93), | ||
| 734 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE94), | ||
| 735 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE95), | ||
| 736 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE96), | ||
| 737 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE97), | ||
| 738 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE98), | ||
| 739 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE99), | ||
| 740 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE100), | ||
| 741 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE101), | ||
| 742 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE102), | ||
| 743 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE103), | ||
| 744 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE104), | ||
| 745 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE105), | ||
| 746 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE106), | ||
| 747 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE107), | ||
| 748 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE108), | ||
| 749 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE109), | ||
| 750 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE110), | ||
| 751 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE111), | ||
| 752 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE112), | ||
| 753 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE113), | ||
| 754 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE114), | ||
| 755 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE115), | ||
| 756 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE116), | ||
| 757 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE117), | ||
| 758 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE118), | ||
| 759 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE119), | ||
| 760 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE120), | ||
| 761 | IMX_PINCTRL_PIN(MX51_PAD_RESERVE121), | ||
| 762 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK), | ||
| 763 | IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), | ||
| 1280 | }; | 764 | }; |
| 1281 | 765 | ||
| 1282 | static struct imx_pinctrl_soc_info imx51_pinctrl_info = { | 766 | static struct imx_pinctrl_soc_info imx51_pinctrl_info = { |
| 1283 | .pins = imx51_pinctrl_pads, | 767 | .pins = imx51_pinctrl_pads, |
| 1284 | .npins = ARRAY_SIZE(imx51_pinctrl_pads), | 768 | .npins = ARRAY_SIZE(imx51_pinctrl_pads), |
| 1285 | .pin_regs = imx51_pin_regs, | ||
| 1286 | .npin_regs = ARRAY_SIZE(imx51_pin_regs), | ||
| 1287 | }; | 769 | }; |
| 1288 | 770 | ||
| 1289 | static struct of_device_id imx51_pinctrl_of_match[] = { | 771 | static struct of_device_id imx51_pinctrl_of_match[] = { |