diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2013-02-19 21:32:52 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-04-09 10:52:50 -0400 |
| commit | e16415313c9b00b1adc313e85c2c8a81febe0b98 (patch) | |
| tree | b1e804b1bb647f3984036d9f9befbe53023bc519 /drivers/pinctrl/pinctrl-imx35.c | |
| parent | 36dffd8f49bc1364998db81bee739ea4574d88f7 (diff) | |
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-imx35.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-imx35.c | 2088 |
1 files changed, 767 insertions, 1321 deletions
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c index 6e214110e3d5..c4549829fc47 100644 --- a/drivers/pinctrl/pinctrl-imx35.c +++ b/drivers/pinctrl/pinctrl-imx35.c | |||
| @@ -24,1249 +24,496 @@ | |||
| 24 | #include "pinctrl-imx.h" | 24 | #include "pinctrl-imx.h" |
| 25 | 25 | ||
| 26 | enum imx35_pads { | 26 | enum imx35_pads { |
| 27 | MX35_PAD_CAPTURE = 0, | 27 | MX35_PAD_RESERVE0 = 0, |
| 28 | MX35_PAD_COMPARE = 1, | 28 | MX35_PAD_CAPTURE = 1, |
| 29 | MX35_PAD_WDOG_RST = 2, | 29 | MX35_PAD_COMPARE = 2, |
| 30 | MX35_PAD_GPIO1_0 = 3, | 30 | MX35_PAD_WDOG_RST = 3, |
| 31 | MX35_PAD_GPIO1_1 = 4, | 31 | MX35_PAD_GPIO1_0 = 4, |
| 32 | MX35_PAD_GPIO2_0 = 5, | 32 | MX35_PAD_GPIO1_1 = 5, |
| 33 | MX35_PAD_GPIO3_0 = 6, | 33 | MX35_PAD_GPIO2_0 = 6, |
| 34 | MX35_PAD_RESET_IN_B = 7, | 34 | MX35_PAD_GPIO3_0 = 7, |
| 35 | MX35_PAD_POR_B = 8, | 35 | MX35_PAD_CLKO = 8, |
| 36 | MX35_PAD_CLKO = 9, | 36 | MX35_PAD_VSTBY = 9, |
| 37 | MX35_PAD_BOOT_MODE0 = 10, | 37 | MX35_PAD_A0 = 10, |
| 38 | MX35_PAD_BOOT_MODE1 = 11, | 38 | MX35_PAD_A1 = 11, |
| 39 | MX35_PAD_CLK_MODE0 = 12, | 39 | MX35_PAD_A2 = 12, |
| 40 | MX35_PAD_CLK_MODE1 = 13, | 40 | MX35_PAD_A3 = 13, |
| 41 | MX35_PAD_POWER_FAIL = 14, | 41 | MX35_PAD_A4 = 14, |
| 42 | MX35_PAD_VSTBY = 15, | 42 | MX35_PAD_A5 = 15, |
| 43 | MX35_PAD_A0 = 16, | 43 | MX35_PAD_A6 = 16, |
| 44 | MX35_PAD_A1 = 17, | 44 | MX35_PAD_A7 = 17, |
| 45 | MX35_PAD_A2 = 18, | 45 | MX35_PAD_A8 = 18, |
| 46 | MX35_PAD_A3 = 19, | 46 | MX35_PAD_A9 = 19, |
| 47 | MX35_PAD_A4 = 20, | 47 | MX35_PAD_A10 = 20, |
| 48 | MX35_PAD_A5 = 21, | 48 | MX35_PAD_MA10 = 21, |
| 49 | MX35_PAD_A6 = 22, | 49 | MX35_PAD_A11 = 22, |
| 50 | MX35_PAD_A7 = 23, | 50 | MX35_PAD_A12 = 23, |
| 51 | MX35_PAD_A8 = 24, | 51 | MX35_PAD_A13 = 24, |
| 52 | MX35_PAD_A9 = 25, | 52 | MX35_PAD_A14 = 25, |
| 53 | MX35_PAD_A10 = 26, | 53 | MX35_PAD_A15 = 26, |
| 54 | MX35_PAD_MA10 = 27, | 54 | MX35_PAD_A16 = 27, |
| 55 | MX35_PAD_A11 = 28, | 55 | MX35_PAD_A17 = 28, |
| 56 | MX35_PAD_A12 = 29, | 56 | MX35_PAD_A18 = 29, |
| 57 | MX35_PAD_A13 = 30, | 57 | MX35_PAD_A19 = 30, |
| 58 | MX35_PAD_A14 = 31, | 58 | MX35_PAD_A20 = 31, |
| 59 | MX35_PAD_A15 = 32, | 59 | MX35_PAD_A21 = 32, |
| 60 | MX35_PAD_A16 = 33, | 60 | MX35_PAD_A22 = 33, |
| 61 | MX35_PAD_A17 = 34, | 61 | MX35_PAD_A23 = 34, |
| 62 | MX35_PAD_A18 = 35, | 62 | MX35_PAD_A24 = 35, |
| 63 | MX35_PAD_A19 = 36, | 63 | MX35_PAD_A25 = 36, |
| 64 | MX35_PAD_A20 = 37, | 64 | MX35_PAD_EB0 = 37, |
| 65 | MX35_PAD_A21 = 38, | 65 | MX35_PAD_EB1 = 38, |
| 66 | MX35_PAD_A22 = 39, | 66 | MX35_PAD_OE = 39, |
| 67 | MX35_PAD_A23 = 40, | 67 | MX35_PAD_CS0 = 40, |
| 68 | MX35_PAD_A24 = 41, | 68 | MX35_PAD_CS1 = 41, |
| 69 | MX35_PAD_A25 = 42, | 69 | MX35_PAD_CS2 = 42, |
| 70 | MX35_PAD_SDBA1 = 43, | 70 | MX35_PAD_CS3 = 43, |
| 71 | MX35_PAD_SDBA0 = 44, | 71 | MX35_PAD_CS4 = 44, |
| 72 | MX35_PAD_SD0 = 45, | 72 | MX35_PAD_CS5 = 45, |
| 73 | MX35_PAD_SD1 = 46, | 73 | MX35_PAD_NF_CE0 = 46, |
| 74 | MX35_PAD_SD2 = 47, | 74 | MX35_PAD_LBA = 47, |
| 75 | MX35_PAD_SD3 = 48, | 75 | MX35_PAD_BCLK = 48, |
| 76 | MX35_PAD_SD4 = 49, | 76 | MX35_PAD_RW = 49, |
| 77 | MX35_PAD_SD5 = 50, | 77 | MX35_PAD_NFWE_B = 50, |
| 78 | MX35_PAD_SD6 = 51, | 78 | MX35_PAD_NFRE_B = 51, |
| 79 | MX35_PAD_SD7 = 52, | 79 | MX35_PAD_NFALE = 52, |
| 80 | MX35_PAD_SD8 = 53, | 80 | MX35_PAD_NFCLE = 53, |
| 81 | MX35_PAD_SD9 = 54, | 81 | MX35_PAD_NFWP_B = 54, |
| 82 | MX35_PAD_SD10 = 55, | 82 | MX35_PAD_NFRB = 55, |
| 83 | MX35_PAD_SD11 = 56, | 83 | MX35_PAD_CSI_D8 = 56, |
| 84 | MX35_PAD_SD12 = 57, | 84 | MX35_PAD_CSI_D9 = 57, |
| 85 | MX35_PAD_SD13 = 58, | 85 | MX35_PAD_CSI_D10 = 58, |
| 86 | MX35_PAD_SD14 = 59, | 86 | MX35_PAD_CSI_D11 = 59, |
| 87 | MX35_PAD_SD15 = 60, | 87 | MX35_PAD_CSI_D12 = 60, |
| 88 | MX35_PAD_SD16 = 61, | 88 | MX35_PAD_CSI_D13 = 61, |
| 89 | MX35_PAD_SD17 = 62, | 89 | MX35_PAD_CSI_D14 = 62, |
| 90 | MX35_PAD_SD18 = 63, | 90 | MX35_PAD_CSI_D15 = 63, |
| 91 | MX35_PAD_SD19 = 64, | 91 | MX35_PAD_CSI_MCLK = 64, |
| 92 | MX35_PAD_SD20 = 65, | 92 | MX35_PAD_CSI_VSYNC = 65, |
| 93 | MX35_PAD_SD21 = 66, | 93 | MX35_PAD_CSI_HSYNC = 66, |
| 94 | MX35_PAD_SD22 = 67, | 94 | MX35_PAD_CSI_PIXCLK = 67, |
| 95 | MX35_PAD_SD23 = 68, | 95 | MX35_PAD_I2C1_CLK = 68, |
| 96 | MX35_PAD_SD24 = 69, | 96 | MX35_PAD_I2C1_DAT = 69, |
| 97 | MX35_PAD_SD25 = 70, | 97 | MX35_PAD_I2C2_CLK = 70, |
| 98 | MX35_PAD_SD26 = 71, | 98 | MX35_PAD_I2C2_DAT = 71, |
| 99 | MX35_PAD_SD27 = 72, | 99 | MX35_PAD_STXD4 = 72, |
| 100 | MX35_PAD_SD28 = 73, | 100 | MX35_PAD_SRXD4 = 73, |
| 101 | MX35_PAD_SD29 = 74, | 101 | MX35_PAD_SCK4 = 74, |
| 102 | MX35_PAD_SD30 = 75, | 102 | MX35_PAD_STXFS4 = 75, |
| 103 | MX35_PAD_SD31 = 76, | 103 | MX35_PAD_STXD5 = 76, |
| 104 | MX35_PAD_DQM0 = 77, | 104 | MX35_PAD_SRXD5 = 77, |
| 105 | MX35_PAD_DQM1 = 78, | 105 | MX35_PAD_SCK5 = 78, |
| 106 | MX35_PAD_DQM2 = 79, | 106 | MX35_PAD_STXFS5 = 79, |
| 107 | MX35_PAD_DQM3 = 80, | 107 | MX35_PAD_SCKR = 80, |
| 108 | MX35_PAD_EB0 = 81, | 108 | MX35_PAD_FSR = 81, |
| 109 | MX35_PAD_EB1 = 82, | 109 | MX35_PAD_HCKR = 82, |
| 110 | MX35_PAD_OE = 83, | 110 | MX35_PAD_SCKT = 83, |
| 111 | MX35_PAD_CS0 = 84, | 111 | MX35_PAD_FST = 84, |
| 112 | MX35_PAD_CS1 = 85, | 112 | MX35_PAD_HCKT = 85, |
| 113 | MX35_PAD_CS2 = 86, | 113 | MX35_PAD_TX5_RX0 = 86, |
| 114 | MX35_PAD_CS3 = 87, | 114 | MX35_PAD_TX4_RX1 = 87, |
| 115 | MX35_PAD_CS4 = 88, | 115 | MX35_PAD_TX3_RX2 = 88, |
| 116 | MX35_PAD_CS5 = 89, | 116 | MX35_PAD_TX2_RX3 = 89, |
| 117 | MX35_PAD_NF_CE0 = 90, | 117 | MX35_PAD_TX1 = 90, |
| 118 | MX35_PAD_ECB = 91, | 118 | MX35_PAD_TX0 = 91, |
| 119 | MX35_PAD_LBA = 92, | 119 | MX35_PAD_CSPI1_MOSI = 92, |
| 120 | MX35_PAD_BCLK = 93, | 120 | MX35_PAD_CSPI1_MISO = 93, |
| 121 | MX35_PAD_RW = 94, | 121 | MX35_PAD_CSPI1_SS0 = 94, |
| 122 | MX35_PAD_RAS = 95, | 122 | MX35_PAD_CSPI1_SS1 = 95, |
| 123 | MX35_PAD_CAS = 96, | 123 | MX35_PAD_CSPI1_SCLK = 96, |
| 124 | MX35_PAD_SDWE = 97, | 124 | MX35_PAD_CSPI1_SPI_RDY = 97, |
| 125 | MX35_PAD_SDCKE0 = 98, | 125 | MX35_PAD_RXD1 = 98, |
| 126 | MX35_PAD_SDCKE1 = 99, | 126 | MX35_PAD_TXD1 = 99, |
| 127 | MX35_PAD_SDCLK = 100, | 127 | MX35_PAD_RTS1 = 100, |
| 128 | MX35_PAD_SDQS0 = 101, | 128 | MX35_PAD_CTS1 = 101, |
| 129 | MX35_PAD_SDQS1 = 102, | 129 | MX35_PAD_RXD2 = 102, |
| 130 | MX35_PAD_SDQS2 = 103, | 130 | MX35_PAD_TXD2 = 103, |
| 131 | MX35_PAD_SDQS3 = 104, | 131 | MX35_PAD_RTS2 = 104, |
| 132 | MX35_PAD_NFWE_B = 105, | 132 | MX35_PAD_CTS2 = 105, |
| 133 | MX35_PAD_NFRE_B = 106, | 133 | MX35_PAD_USBOTG_PWR = 106, |
| 134 | MX35_PAD_NFALE = 107, | 134 | MX35_PAD_USBOTG_OC = 107, |
| 135 | MX35_PAD_NFCLE = 108, | 135 | MX35_PAD_LD0 = 108, |
| 136 | MX35_PAD_NFWP_B = 109, | 136 | MX35_PAD_LD1 = 109, |
| 137 | MX35_PAD_NFRB = 110, | 137 | MX35_PAD_LD2 = 110, |
| 138 | MX35_PAD_D15 = 111, | 138 | MX35_PAD_LD3 = 111, |
| 139 | MX35_PAD_D14 = 112, | 139 | MX35_PAD_LD4 = 112, |
| 140 | MX35_PAD_D13 = 113, | 140 | MX35_PAD_LD5 = 113, |
| 141 | MX35_PAD_D12 = 114, | 141 | MX35_PAD_LD6 = 114, |
| 142 | MX35_PAD_D11 = 115, | 142 | MX35_PAD_LD7 = 115, |
| 143 | MX35_PAD_D10 = 116, | 143 | MX35_PAD_LD8 = 116, |
| 144 | MX35_PAD_D9 = 117, | 144 | MX35_PAD_LD9 = 117, |
| 145 | MX35_PAD_D8 = 118, | 145 | MX35_PAD_LD10 = 118, |
| 146 | MX35_PAD_D7 = 119, | 146 | MX35_PAD_LD11 = 119, |
| 147 | MX35_PAD_D6 = 120, | 147 | MX35_PAD_LD12 = 120, |
| 148 | MX35_PAD_D5 = 121, | 148 | MX35_PAD_LD13 = 121, |
| 149 | MX35_PAD_D4 = 122, | 149 | MX35_PAD_LD14 = 122, |
| 150 | MX35_PAD_D3 = 123, | 150 | MX35_PAD_LD15 = 123, |
| 151 | MX35_PAD_D2 = 124, | 151 | MX35_PAD_LD16 = 124, |
| 152 | MX35_PAD_D1 = 125, | 152 | MX35_PAD_LD17 = 125, |
| 153 | MX35_PAD_D0 = 126, | 153 | MX35_PAD_LD18 = 126, |
| 154 | MX35_PAD_CSI_D8 = 127, | 154 | MX35_PAD_LD19 = 127, |
| 155 | MX35_PAD_CSI_D9 = 128, | 155 | MX35_PAD_LD20 = 128, |
| 156 | MX35_PAD_CSI_D10 = 129, | 156 | MX35_PAD_LD21 = 129, |
| 157 | MX35_PAD_CSI_D11 = 130, | 157 | MX35_PAD_LD22 = 130, |
| 158 | MX35_PAD_CSI_D12 = 131, | 158 | MX35_PAD_LD23 = 131, |
| 159 | MX35_PAD_CSI_D13 = 132, | 159 | MX35_PAD_D3_HSYNC = 132, |
| 160 | MX35_PAD_CSI_D14 = 133, | 160 | MX35_PAD_D3_FPSHIFT = 133, |
| 161 | MX35_PAD_CSI_D15 = 134, | 161 | MX35_PAD_D3_DRDY = 134, |
| 162 | MX35_PAD_CSI_MCLK = 135, | 162 | MX35_PAD_CONTRAST = 135, |
| 163 | MX35_PAD_CSI_VSYNC = 136, | 163 | MX35_PAD_D3_VSYNC = 136, |
| 164 | MX35_PAD_CSI_HSYNC = 137, | 164 | MX35_PAD_D3_REV = 137, |
| 165 | MX35_PAD_CSI_PIXCLK = 138, | 165 | MX35_PAD_D3_CLS = 138, |
| 166 | MX35_PAD_I2C1_CLK = 139, | 166 | MX35_PAD_D3_SPL = 139, |
| 167 | MX35_PAD_I2C1_DAT = 140, | 167 | MX35_PAD_SD1_CMD = 140, |
| 168 | MX35_PAD_I2C2_CLK = 141, | 168 | MX35_PAD_SD1_CLK = 141, |
| 169 | MX35_PAD_I2C2_DAT = 142, | 169 | MX35_PAD_SD1_DATA0 = 142, |
| 170 | MX35_PAD_STXD4 = 143, | 170 | MX35_PAD_SD1_DATA1 = 143, |
| 171 | MX35_PAD_SRXD4 = 144, | 171 | MX35_PAD_SD1_DATA2 = 144, |
| 172 | MX35_PAD_SCK4 = 145, | 172 | MX35_PAD_SD1_DATA3 = 145, |
| 173 | MX35_PAD_STXFS4 = 146, | 173 | MX35_PAD_SD2_CMD = 146, |
| 174 | MX35_PAD_STXD5 = 147, | 174 | MX35_PAD_SD2_CLK = 147, |
| 175 | MX35_PAD_SRXD5 = 148, | 175 | MX35_PAD_SD2_DATA0 = 148, |
| 176 | MX35_PAD_SCK5 = 149, | 176 | MX35_PAD_SD2_DATA1 = 149, |
| 177 | MX35_PAD_STXFS5 = 150, | 177 | MX35_PAD_SD2_DATA2 = 150, |
| 178 | MX35_PAD_SCKR = 151, | 178 | MX35_PAD_SD2_DATA3 = 151, |
| 179 | MX35_PAD_FSR = 152, | 179 | MX35_PAD_ATA_CS0 = 152, |
| 180 | MX35_PAD_HCKR = 153, | 180 | MX35_PAD_ATA_CS1 = 153, |
| 181 | MX35_PAD_SCKT = 154, | 181 | MX35_PAD_ATA_DIOR = 154, |
| 182 | MX35_PAD_FST = 155, | 182 | MX35_PAD_ATA_DIOW = 155, |
| 183 | MX35_PAD_HCKT = 156, | 183 | MX35_PAD_ATA_DMACK = 156, |
| 184 | MX35_PAD_TX5_RX0 = 157, | 184 | MX35_PAD_ATA_RESET_B = 157, |
| 185 | MX35_PAD_TX4_RX1 = 158, | 185 | MX35_PAD_ATA_IORDY = 158, |
| 186 | MX35_PAD_TX3_RX2 = 159, | 186 | MX35_PAD_ATA_DATA0 = 159, |
| 187 | MX35_PAD_TX2_RX3 = 160, | 187 | MX35_PAD_ATA_DATA1 = 160, |
| 188 | MX35_PAD_TX1 = 161, | 188 | MX35_PAD_ATA_DATA2 = 161, |
| 189 | MX35_PAD_TX0 = 162, | 189 | MX35_PAD_ATA_DATA3 = 162, |
| 190 | MX35_PAD_CSPI1_MOSI = 163, | 190 | MX35_PAD_ATA_DATA4 = 163, |
| 191 | MX35_PAD_CSPI1_MISO = 164, | 191 | MX35_PAD_ATA_DATA5 = 164, |
| 192 | MX35_PAD_CSPI1_SS0 = 165, | 192 | MX35_PAD_ATA_DATA6 = 165, |
| 193 | MX35_PAD_CSPI1_SS1 = 166, | 193 | MX35_PAD_ATA_DATA7 = 166, |
| 194 | MX35_PAD_CSPI1_SCLK = 167, | 194 | MX35_PAD_ATA_DATA8 = 167, |
| 195 | MX35_PAD_CSPI1_SPI_RDY = 168, | 195 | MX35_PAD_ATA_DATA9 = 168, |
| 196 | MX35_PAD_RXD1 = 169, | 196 | MX35_PAD_ATA_DATA10 = 169, |
| 197 | MX35_PAD_TXD1 = 170, | 197 | MX35_PAD_ATA_DATA11 = 170, |
| 198 | MX35_PAD_RTS1 = 171, | 198 | MX35_PAD_ATA_DATA12 = 171, |
| 199 | MX35_PAD_CTS1 = 172, | 199 | MX35_PAD_ATA_DATA13 = 172, |
| 200 | MX35_PAD_RXD2 = 173, | 200 | MX35_PAD_ATA_DATA14 = 173, |
| 201 | MX35_PAD_TXD2 = 174, | 201 | MX35_PAD_ATA_DATA15 = 174, |
| 202 | MX35_PAD_RTS2 = 175, | 202 | MX35_PAD_ATA_INTRQ = 175, |
| 203 | MX35_PAD_CTS2 = 176, | 203 | MX35_PAD_ATA_BUFF_EN = 176, |
| 204 | MX35_PAD_RTCK = 177, | 204 | MX35_PAD_ATA_DMARQ = 177, |
| 205 | MX35_PAD_TCK = 178, | 205 | MX35_PAD_ATA_DA0 = 178, |
| 206 | MX35_PAD_TMS = 179, | 206 | MX35_PAD_ATA_DA1 = 179, |
| 207 | MX35_PAD_TDI = 180, | 207 | MX35_PAD_ATA_DA2 = 180, |
| 208 | MX35_PAD_TDO = 181, | 208 | MX35_PAD_MLB_CLK = 181, |
| 209 | MX35_PAD_TRSTB = 182, | 209 | MX35_PAD_MLB_DAT = 182, |
| 210 | MX35_PAD_DE_B = 183, | 210 | MX35_PAD_MLB_SIG = 183, |
| 211 | MX35_PAD_SJC_MOD = 184, | 211 | MX35_PAD_FEC_TX_CLK = 184, |
| 212 | MX35_PAD_USBOTG_PWR = 185, | 212 | MX35_PAD_FEC_RX_CLK = 185, |
| 213 | MX35_PAD_USBOTG_OC = 186, | 213 | MX35_PAD_FEC_RX_DV = 186, |
| 214 | MX35_PAD_LD0 = 187, | 214 | MX35_PAD_FEC_COL = 187, |
| 215 | MX35_PAD_LD1 = 188, | 215 | MX35_PAD_FEC_RDATA0 = 188, |
| 216 | MX35_PAD_LD2 = 189, | 216 | MX35_PAD_FEC_TDATA0 = 189, |
| 217 | MX35_PAD_LD3 = 190, | 217 | MX35_PAD_FEC_TX_EN = 190, |
| 218 | MX35_PAD_LD4 = 191, | 218 | MX35_PAD_FEC_MDC = 191, |
| 219 | MX35_PAD_LD5 = 192, | 219 | MX35_PAD_FEC_MDIO = 192, |
| 220 | MX35_PAD_LD6 = 193, | 220 | MX35_PAD_FEC_TX_ERR = 193, |
| 221 | MX35_PAD_LD7 = 194, | 221 | MX35_PAD_FEC_RX_ERR = 194, |
| 222 | MX35_PAD_LD8 = 195, | 222 | MX35_PAD_FEC_CRS = 195, |
| 223 | MX35_PAD_LD9 = 196, | 223 | MX35_PAD_FEC_RDATA1 = 196, |
| 224 | MX35_PAD_LD10 = 197, | 224 | MX35_PAD_FEC_TDATA1 = 197, |
| 225 | MX35_PAD_LD11 = 198, | 225 | MX35_PAD_FEC_RDATA2 = 198, |
| 226 | MX35_PAD_LD12 = 199, | 226 | MX35_PAD_FEC_TDATA2 = 199, |
| 227 | MX35_PAD_LD13 = 200, | 227 | MX35_PAD_FEC_RDATA3 = 200, |
| 228 | MX35_PAD_LD14 = 201, | 228 | MX35_PAD_FEC_TDATA3 = 201, |
| 229 | MX35_PAD_LD15 = 202, | 229 | MX35_PAD_RESERVE1 = 202, |
| 230 | MX35_PAD_LD16 = 203, | 230 | MX35_PAD_RESERVE2 = 203, |
| 231 | MX35_PAD_LD17 = 204, | 231 | MX35_PAD_RESERVE3 = 204, |
| 232 | MX35_PAD_LD18 = 205, | 232 | MX35_PAD_RESERVE4 = 205, |
| 233 | MX35_PAD_LD19 = 206, | 233 | MX35_PAD_RESERVE5 = 206, |
| 234 | MX35_PAD_LD20 = 207, | 234 | MX35_PAD_RESERVE6 = 207, |
| 235 | MX35_PAD_LD21 = 208, | 235 | MX35_PAD_RESERVE7 = 208, |
| 236 | MX35_PAD_LD22 = 209, | 236 | MX35_PAD_RESET_IN_B = 209, |
| 237 | MX35_PAD_LD23 = 210, | 237 | MX35_PAD_POR_B = 210, |
| 238 | MX35_PAD_D3_HSYNC = 211, | 238 | MX35_PAD_RESERVE8 = 211, |
| 239 | MX35_PAD_D3_FPSHIFT = 212, | 239 | MX35_PAD_BOOT_MODE0 = 212, |
| 240 | MX35_PAD_D3_DRDY = 213, | 240 | MX35_PAD_BOOT_MODE1 = 213, |
| 241 | MX35_PAD_CONTRAST = 214, | 241 | MX35_PAD_CLK_MODE0 = 214, |
| 242 | MX35_PAD_D3_VSYNC = 215, | 242 | MX35_PAD_CLK_MODE1 = 215, |
| 243 | MX35_PAD_D3_REV = 216, | 243 | MX35_PAD_POWER_FAIL = 216, |
| 244 | MX35_PAD_D3_CLS = 217, | 244 | MX35_PAD_RESERVE9 = 217, |
| 245 | MX35_PAD_D3_SPL = 218, | 245 | MX35_PAD_RESERVE10 = 218, |
| 246 | MX35_PAD_SD1_CMD = 219, | 246 | MX35_PAD_RESERVE11 = 219, |
| 247 | MX35_PAD_SD1_CLK = 220, | 247 | MX35_PAD_RESERVE12 = 220, |
| 248 | MX35_PAD_SD1_DATA0 = 221, | 248 | MX35_PAD_RESERVE13 = 221, |
| 249 | MX35_PAD_SD1_DATA1 = 222, | 249 | MX35_PAD_RESERVE14 = 222, |
| 250 | MX35_PAD_SD1_DATA2 = 223, | 250 | MX35_PAD_RESERVE15 = 223, |
| 251 | MX35_PAD_SD1_DATA3 = 224, | 251 | MX35_PAD_RESERVE16 = 224, |
| 252 | MX35_PAD_SD2_CMD = 225, | 252 | MX35_PAD_RESERVE17 = 225, |
| 253 | MX35_PAD_SD2_CLK = 226, | 253 | MX35_PAD_RESERVE18 = 226, |
| 254 | MX35_PAD_SD2_DATA0 = 227, | 254 | MX35_PAD_RESERVE19 = 227, |
| 255 | MX35_PAD_SD2_DATA1 = 228, | 255 | MX35_PAD_RESERVE20 = 228, |
| 256 | MX35_PAD_SD2_DATA2 = 229, | 256 | MX35_PAD_RESERVE21 = 229, |
| 257 | MX35_PAD_SD2_DATA3 = 230, | 257 | MX35_PAD_RESERVE22 = 230, |
| 258 | MX35_PAD_ATA_CS0 = 231, | 258 | MX35_PAD_RESERVE23 = 231, |
| 259 | MX35_PAD_ATA_CS1 = 232, | 259 | MX35_PAD_RESERVE24 = 232, |
| 260 | MX35_PAD_ATA_DIOR = 233, | 260 | MX35_PAD_RESERVE25 = 233, |
| 261 | MX35_PAD_ATA_DIOW = 234, | 261 | MX35_PAD_RESERVE26 = 234, |
| 262 | MX35_PAD_ATA_DMACK = 235, | 262 | MX35_PAD_RESERVE27 = 235, |
| 263 | MX35_PAD_ATA_RESET_B = 236, | 263 | MX35_PAD_RESERVE28 = 236, |
| 264 | MX35_PAD_ATA_IORDY = 237, | 264 | MX35_PAD_RESERVE29 = 237, |
| 265 | MX35_PAD_ATA_DATA0 = 238, | 265 | MX35_PAD_RESERVE30 = 238, |
| 266 | MX35_PAD_ATA_DATA1 = 239, | 266 | MX35_PAD_RESERVE31 = 239, |
| 267 | MX35_PAD_ATA_DATA2 = 240, | 267 | MX35_PAD_RESERVE32 = 240, |
| 268 | MX35_PAD_ATA_DATA3 = 241, | 268 | MX35_PAD_RESERVE33 = 241, |
| 269 | MX35_PAD_ATA_DATA4 = 242, | 269 | MX35_PAD_RESERVE34 = 242, |
| 270 | MX35_PAD_ATA_DATA5 = 243, | 270 | MX35_PAD_RESERVE35 = 243, |
| 271 | MX35_PAD_ATA_DATA6 = 244, | 271 | MX35_PAD_RESERVE36 = 244, |
| 272 | MX35_PAD_ATA_DATA7 = 245, | 272 | MX35_PAD_SDBA1 = 245, |
| 273 | MX35_PAD_ATA_DATA8 = 246, | 273 | MX35_PAD_SDBA0 = 246, |
| 274 | MX35_PAD_ATA_DATA9 = 247, | 274 | MX35_PAD_SD0 = 247, |
| 275 | MX35_PAD_ATA_DATA10 = 248, | 275 | MX35_PAD_SD1 = 248, |
| 276 | MX35_PAD_ATA_DATA11 = 249, | 276 | MX35_PAD_SD2 = 249, |
| 277 | MX35_PAD_ATA_DATA12 = 250, | 277 | MX35_PAD_SD3 = 250, |
| 278 | MX35_PAD_ATA_DATA13 = 251, | 278 | MX35_PAD_SD4 = 251, |
| 279 | MX35_PAD_ATA_DATA14 = 252, | 279 | MX35_PAD_SD5 = 252, |
| 280 | MX35_PAD_ATA_DATA15 = 253, | 280 | MX35_PAD_SD6 = 253, |
| 281 | MX35_PAD_ATA_INTRQ = 254, | 281 | MX35_PAD_SD7 = 254, |
| 282 | MX35_PAD_ATA_BUFF_EN = 255, | 282 | MX35_PAD_SD8 = 255, |
| 283 | MX35_PAD_ATA_DMARQ = 256, | 283 | MX35_PAD_SD9 = 256, |
| 284 | MX35_PAD_ATA_DA0 = 257, | 284 | MX35_PAD_SD10 = 257, |
| 285 | MX35_PAD_ATA_DA1 = 258, | 285 | MX35_PAD_SD11 = 258, |
| 286 | MX35_PAD_ATA_DA2 = 259, | 286 | MX35_PAD_SD12 = 259, |
| 287 | MX35_PAD_MLB_CLK = 260, | 287 | MX35_PAD_SD13 = 260, |
| 288 | MX35_PAD_MLB_DAT = 261, | 288 | MX35_PAD_SD14 = 261, |
| 289 | MX35_PAD_MLB_SIG = 262, | 289 | MX35_PAD_SD15 = 262, |
| 290 | MX35_PAD_FEC_TX_CLK = 263, | 290 | MX35_PAD_SD16 = 263, |
| 291 | MX35_PAD_FEC_RX_CLK = 264, | 291 | MX35_PAD_SD17 = 264, |
| 292 | MX35_PAD_FEC_RX_DV = 265, | 292 | MX35_PAD_SD18 = 265, |
| 293 | MX35_PAD_FEC_COL = 266, | 293 | MX35_PAD_SD19 = 266, |
| 294 | MX35_PAD_FEC_RDATA0 = 267, | 294 | MX35_PAD_SD20 = 267, |
| 295 | MX35_PAD_FEC_TDATA0 = 268, | 295 | MX35_PAD_SD21 = 268, |
| 296 | MX35_PAD_FEC_TX_EN = 269, | 296 | MX35_PAD_SD22 = 269, |
| 297 | MX35_PAD_FEC_MDC = 270, | 297 | MX35_PAD_SD23 = 270, |
| 298 | MX35_PAD_FEC_MDIO = 271, | 298 | MX35_PAD_SD24 = 271, |
| 299 | MX35_PAD_FEC_TX_ERR = 272, | 299 | MX35_PAD_SD25 = 272, |
| 300 | MX35_PAD_FEC_RX_ERR = 273, | 300 | MX35_PAD_SD26 = 273, |
| 301 | MX35_PAD_FEC_CRS = 274, | 301 | MX35_PAD_SD27 = 274, |
| 302 | MX35_PAD_FEC_RDATA1 = 275, | 302 | MX35_PAD_SD28 = 275, |
| 303 | MX35_PAD_FEC_TDATA1 = 276, | 303 | MX35_PAD_SD29 = 276, |
| 304 | MX35_PAD_FEC_RDATA2 = 277, | 304 | MX35_PAD_SD30 = 277, |
| 305 | MX35_PAD_FEC_TDATA2 = 278, | 305 | MX35_PAD_SD31 = 278, |
| 306 | MX35_PAD_FEC_RDATA3 = 279, | 306 | MX35_PAD_DQM0 = 279, |
| 307 | MX35_PAD_FEC_TDATA3 = 280, | 307 | MX35_PAD_DQM1 = 280, |
| 308 | MX35_PAD_EXT_ARMCLK = 281, | 308 | MX35_PAD_DQM2 = 281, |
| 309 | MX35_PAD_TEST_MODE = 282, | 309 | MX35_PAD_DQM3 = 282, |
| 310 | }; | 310 | MX35_PAD_RESERVE37 = 283, |
| 311 | 311 | MX35_PAD_RESERVE38 = 284, | |
| 312 | /* imx35 register maps */ | 312 | MX35_PAD_RESERVE39 = 285, |
| 313 | static struct imx_pin_reg imx35_pin_regs[] = { | 313 | MX35_PAD_RESERVE40 = 286, |
| 314 | [0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */ | 314 | MX35_PAD_RESERVE41 = 287, |
| 315 | [1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */ | 315 | MX35_PAD_RESERVE42 = 288, |
| 316 | [2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */ | 316 | MX35_PAD_RESERVE43 = 289, |
| 317 | [3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */ | 317 | MX35_PAD_RESERVE44 = 290, |
| 318 | [4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */ | 318 | MX35_PAD_RESERVE45 = 291, |
| 319 | [5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */ | 319 | MX35_PAD_RESERVE46 = 292, |
| 320 | [6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */ | 320 | MX35_PAD_ECB = 293, |
| 321 | [7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */ | 321 | MX35_PAD_RESERVE47 = 294, |
| 322 | [8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */ | 322 | MX35_PAD_RESERVE48 = 295, |
| 323 | [9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */ | 323 | MX35_PAD_RESERVE49 = 296, |
| 324 | [10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */ | 324 | MX35_PAD_RAS = 297, |
| 325 | [11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */ | 325 | MX35_PAD_CAS = 298, |
| 326 | [12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */ | 326 | MX35_PAD_SDWE = 299, |
| 327 | [13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */ | 327 | MX35_PAD_SDCKE0 = 300, |
| 328 | [14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */ | 328 | MX35_PAD_SDCKE1 = 301, |
| 329 | [15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */ | 329 | MX35_PAD_SDCLK = 302, |
| 330 | [16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */ | 330 | MX35_PAD_SDQS0 = 303, |
| 331 | [17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */ | 331 | MX35_PAD_SDQS1 = 304, |
| 332 | [18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */ | 332 | MX35_PAD_SDQS2 = 305, |
| 333 | [19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */ | 333 | MX35_PAD_SDQS3 = 306, |
| 334 | [20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */ | 334 | MX35_PAD_RESERVE50 = 307, |
| 335 | [21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */ | 335 | MX35_PAD_RESERVE51 = 308, |
| 336 | [22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */ | 336 | MX35_PAD_RESERVE52 = 309, |
| 337 | [23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */ | 337 | MX35_PAD_RESERVE53 = 310, |
| 338 | [24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */ | 338 | MX35_PAD_RESERVE54 = 311, |
| 339 | [25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */ | 339 | MX35_PAD_RESERVE55 = 312, |
| 340 | [26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */ | 340 | MX35_PAD_D15 = 313, |
| 341 | [27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */ | 341 | MX35_PAD_D14 = 314, |
| 342 | [28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */ | 342 | MX35_PAD_D13 = 315, |
| 343 | [29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */ | 343 | MX35_PAD_D12 = 316, |
| 344 | [30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */ | 344 | MX35_PAD_D11 = 317, |
| 345 | [31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */ | 345 | MX35_PAD_D10 = 318, |
| 346 | [32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */ | 346 | MX35_PAD_D9 = 319, |
| 347 | [33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */ | 347 | MX35_PAD_D8 = 320, |
| 348 | [34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */ | 348 | MX35_PAD_D7 = 321, |
| 349 | [35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */ | 349 | MX35_PAD_D6 = 322, |
| 350 | [36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */ | 350 | MX35_PAD_D5 = 323, |
| 351 | [37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */ | 351 | MX35_PAD_D4 = 324, |
| 352 | [38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */ | 352 | MX35_PAD_D3 = 325, |
| 353 | [39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */ | 353 | MX35_PAD_D2 = 326, |
| 354 | [40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */ | 354 | MX35_PAD_D1 = 327, |
| 355 | [41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */ | 355 | MX35_PAD_D0 = 328, |
| 356 | [42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */ | 356 | MX35_PAD_RESERVE56 = 329, |
| 357 | [43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */ | 357 | MX35_PAD_RESERVE57 = 330, |
| 358 | [44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */ | 358 | MX35_PAD_RESERVE58 = 331, |
| 359 | [45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */ | 359 | MX35_PAD_RESERVE59 = 332, |
| 360 | [46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */ | 360 | MX35_PAD_RESERVE60 = 333, |
| 361 | [47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */ | 361 | MX35_PAD_RESERVE61 = 334, |
| 362 | [48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */ | 362 | MX35_PAD_RESERVE62 = 335, |
| 363 | [49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */ | 363 | MX35_PAD_RESERVE63 = 336, |
| 364 | [50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */ | 364 | MX35_PAD_RESERVE64 = 337, |
| 365 | [51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */ | 365 | MX35_PAD_RESERVE65 = 338, |
| 366 | [52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */ | 366 | MX35_PAD_RESERVE66 = 339, |
| 367 | [53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */ | 367 | MX35_PAD_RESERVE67 = 340, |
| 368 | [54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */ | 368 | MX35_PAD_RESERVE68 = 341, |
| 369 | [55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */ | 369 | MX35_PAD_RESERVE69 = 342, |
| 370 | [56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */ | 370 | MX35_PAD_RESERVE70 = 343, |
| 371 | [57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */ | 371 | MX35_PAD_RESERVE71 = 344, |
| 372 | [58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */ | 372 | MX35_PAD_RESERVE72 = 345, |
| 373 | [59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */ | 373 | MX35_PAD_RESERVE73 = 346, |
| 374 | [60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */ | 374 | MX35_PAD_RESERVE74 = 347, |
| 375 | [61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */ | 375 | MX35_PAD_RESERVE75 = 348, |
| 376 | [62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */ | 376 | MX35_PAD_RESERVE76 = 349, |
| 377 | [63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */ | 377 | MX35_PAD_RESERVE77 = 350, |
| 378 | [64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */ | 378 | MX35_PAD_RESERVE78 = 351, |
| 379 | [65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */ | 379 | MX35_PAD_RESERVE79 = 352, |
| 380 | [66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */ | 380 | MX35_PAD_RESERVE80 = 353, |
| 381 | [67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */ | 381 | MX35_PAD_RESERVE81 = 354, |
| 382 | [68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */ | 382 | MX35_PAD_RESERVE82 = 355, |
| 383 | [69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */ | 383 | MX35_PAD_RESERVE83 = 356, |
| 384 | [70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */ | 384 | MX35_PAD_RESERVE84 = 357, |
| 385 | [71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */ | 385 | MX35_PAD_RESERVE85 = 358, |
| 386 | [72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */ | 386 | MX35_PAD_RESERVE86 = 359, |
| 387 | [73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */ | 387 | MX35_PAD_RESERVE87 = 360, |
| 388 | [74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */ | 388 | MX35_PAD_RESERVE88 = 361, |
| 389 | [75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */ | 389 | MX35_PAD_RESERVE89 = 362, |
| 390 | [76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */ | 390 | MX35_PAD_RESERVE90 = 363, |
| 391 | [77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */ | 391 | MX35_PAD_RESERVE91 = 364, |
| 392 | [78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */ | 392 | MX35_PAD_RESERVE92 = 365, |
| 393 | [79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */ | 393 | MX35_PAD_RESERVE93 = 366, |
| 394 | [80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */ | 394 | MX35_PAD_RESERVE94 = 367, |
| 395 | [81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */ | 395 | MX35_PAD_RESERVE95 = 368, |
| 396 | [82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */ | 396 | MX35_PAD_RESERVE96 = 369, |
| 397 | [83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */ | 397 | MX35_PAD_RESERVE97 = 370, |
| 398 | [84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */ | 398 | MX35_PAD_RESERVE98 = 371, |
| 399 | [85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */ | 399 | MX35_PAD_RESERVE99 = 372, |
| 400 | [86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */ | 400 | MX35_PAD_RESERVE100 = 373, |
| 401 | [87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */ | 401 | MX35_PAD_RESERVE101 = 374, |
| 402 | [88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */ | 402 | MX35_PAD_RESERVE102 = 375, |
| 403 | [89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */ | 403 | MX35_PAD_RESERVE103 = 376, |
| 404 | [90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */ | 404 | MX35_PAD_RESERVE104 = 377, |
| 405 | [91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */ | 405 | MX35_PAD_RESERVE105 = 378, |
| 406 | [92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */ | 406 | MX35_PAD_RTCK = 379, |
| 407 | [93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */ | 407 | MX35_PAD_TCK = 380, |
| 408 | [94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */ | 408 | MX35_PAD_TMS = 381, |
| 409 | [95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */ | 409 | MX35_PAD_TDI = 382, |
| 410 | [96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */ | 410 | MX35_PAD_TDO = 383, |
| 411 | [97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */ | 411 | MX35_PAD_TRSTB = 384, |
| 412 | [98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */ | 412 | MX35_PAD_DE_B = 385, |
| 413 | [99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */ | 413 | MX35_PAD_SJC_MOD = 386, |
| 414 | [100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */ | 414 | MX35_PAD_RESERVE106 = 387, |
| 415 | [101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */ | 415 | MX35_PAD_RESERVE107 = 388, |
| 416 | [102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */ | 416 | MX35_PAD_RESERVE108 = 389, |
| 417 | [103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */ | 417 | MX35_PAD_RESERVE109 = 390, |
| 418 | [104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */ | 418 | MX35_PAD_RESERVE110 = 391, |
| 419 | [105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */ | 419 | MX35_PAD_RESERVE111 = 392, |
| 420 | [106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */ | 420 | MX35_PAD_RESERVE112 = 393, |
| 421 | [107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */ | 421 | MX35_PAD_RESERVE113 = 394, |
| 422 | [108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */ | 422 | MX35_PAD_RESERVE114 = 395, |
| 423 | [109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */ | 423 | MX35_PAD_RESERVE115 = 396, |
| 424 | [110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */ | 424 | MX35_PAD_RESERVE116 = 397, |
| 425 | [111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */ | 425 | MX35_PAD_RESERVE117 = 398, |
| 426 | [112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */ | 426 | MX35_PAD_RESERVE118 = 399, |
| 427 | [113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */ | 427 | MX35_PAD_RESERVE119 = 400, |
| 428 | [114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */ | 428 | MX35_PAD_RESERVE120 = 401, |
| 429 | [115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */ | 429 | MX35_PAD_RESERVE121 = 402, |
| 430 | [116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */ | 430 | MX35_PAD_RESERVE122 = 403, |
| 431 | [117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */ | 431 | MX35_PAD_RESERVE123 = 404, |
| 432 | [118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */ | 432 | MX35_PAD_RESERVE124 = 405, |
| 433 | [119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */ | 433 | MX35_PAD_RESERVE125 = 406, |
| 434 | [120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */ | 434 | MX35_PAD_RESERVE126 = 407, |
| 435 | [121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */ | 435 | MX35_PAD_RESERVE127 = 408, |
| 436 | [122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */ | 436 | MX35_PAD_RESERVE128 = 409, |
| 437 | [123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */ | 437 | MX35_PAD_RESERVE129 = 410, |
| 438 | [124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */ | 438 | MX35_PAD_RESERVE130 = 411, |
| 439 | [125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */ | 439 | MX35_PAD_RESERVE131 = 412, |
| 440 | [126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */ | 440 | MX35_PAD_RESERVE132 = 413, |
| 441 | [127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */ | 441 | MX35_PAD_RESERVE133 = 414, |
| 442 | [128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */ | 442 | MX35_PAD_RESERVE134 = 415, |
| 443 | [129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */ | 443 | MX35_PAD_RESERVE135 = 416, |
| 444 | [130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */ | 444 | MX35_PAD_RESERVE136 = 417, |
| 445 | [131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */ | 445 | MX35_PAD_RESERVE137 = 418, |
| 446 | [132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */ | 446 | MX35_PAD_RESERVE138 = 419, |
| 447 | [133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */ | 447 | MX35_PAD_RESERVE139 = 420, |
| 448 | [134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */ | 448 | MX35_PAD_RESERVE140 = 421, |
| 449 | [135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */ | 449 | MX35_PAD_RESERVE141 = 422, |
| 450 | [136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */ | 450 | MX35_PAD_RESERVE142 = 423, |
| 451 | [137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */ | 451 | MX35_PAD_RESERVE143 = 424, |
| 452 | [138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */ | 452 | MX35_PAD_RESERVE144 = 425, |
| 453 | [139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */ | 453 | MX35_PAD_RESERVE145 = 426, |
| 454 | [140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */ | 454 | MX35_PAD_RESERVE146 = 427, |
| 455 | [141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */ | 455 | MX35_PAD_RESERVE147 = 428, |
| 456 | [142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */ | 456 | MX35_PAD_RESERVE148 = 429, |
| 457 | [143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */ | 457 | MX35_PAD_RESERVE149 = 430, |
| 458 | [144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */ | 458 | MX35_PAD_RESERVE150 = 431, |
| 459 | [145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */ | 459 | MX35_PAD_RESERVE151 = 432, |
| 460 | [146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */ | 460 | MX35_PAD_RESERVE152 = 433, |
| 461 | [147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */ | 461 | MX35_PAD_RESERVE153 = 434, |
| 462 | [148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */ | 462 | MX35_PAD_RESERVE154 = 435, |
| 463 | [149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */ | 463 | MX35_PAD_RESERVE155 = 436, |
| 464 | [150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */ | 464 | MX35_PAD_RESERVE156 = 437, |
| 465 | [151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */ | 465 | MX35_PAD_RESERVE157 = 438, |
| 466 | [152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */ | 466 | MX35_PAD_RESERVE158 = 439, |
| 467 | [153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */ | 467 | MX35_PAD_RESERVE159 = 440, |
| 468 | [154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */ | 468 | MX35_PAD_RESERVE160 = 441, |
| 469 | [155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */ | 469 | MX35_PAD_RESERVE161 = 442, |
| 470 | [156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */ | 470 | MX35_PAD_RESERVE162 = 443, |
| 471 | [157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */ | 471 | MX35_PAD_RESERVE163 = 444, |
| 472 | [158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */ | 472 | MX35_PAD_RESERVE164 = 445, |
| 473 | [159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */ | 473 | MX35_PAD_RESERVE165 = 446, |
| 474 | [160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */ | 474 | MX35_PAD_RESERVE166 = 447, |
| 475 | [161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */ | 475 | MX35_PAD_RESERVE167 = 448, |
| 476 | [162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */ | 476 | MX35_PAD_RESERVE168 = 449, |
| 477 | [163] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */ | 477 | MX35_PAD_RESERVE169 = 450, |
| 478 | [164] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */ | 478 | MX35_PAD_RESERVE170 = 451, |
| 479 | [165] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */ | 479 | MX35_PAD_RESERVE171 = 452, |
| 480 | [166] = IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */ | 480 | MX35_PAD_RESERVE172 = 453, |
| 481 | [167] = IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */ | 481 | MX35_PAD_RESERVE173 = 454, |
| 482 | [168] = IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */ | 482 | MX35_PAD_RESERVE174 = 455, |
| 483 | [169] = IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */ | 483 | MX35_PAD_RESERVE175 = 456, |
| 484 | [170] = IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */ | 484 | MX35_PAD_RESERVE176 = 457, |
| 485 | [171] = IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */ | 485 | MX35_PAD_RESERVE177 = 458, |
| 486 | [172] = IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */ | 486 | MX35_PAD_RESERVE178 = 459, |
| 487 | [173] = IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */ | 487 | MX35_PAD_RESERVE179 = 460, |
| 488 | [174] = IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */ | 488 | MX35_PAD_RESERVE180 = 461, |
| 489 | [175] = IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */ | 489 | MX35_PAD_RESERVE181 = 462, |
| 490 | [176] = IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */ | 490 | MX35_PAD_RESERVE182 = 463, |
| 491 | [177] = IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */ | 491 | MX35_PAD_RESERVE183 = 464, |
| 492 | [178] = IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */ | 492 | MX35_PAD_RESERVE184 = 465, |
| 493 | [179] = IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */ | 493 | MX35_PAD_RESERVE185 = 466, |
| 494 | [180] = IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */ | 494 | MX35_PAD_RESERVE186 = 467, |
| 495 | [181] = IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */ | 495 | MX35_PAD_RESERVE187 = 468, |
| 496 | [182] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */ | 496 | MX35_PAD_RESERVE188 = 469, |
| 497 | [183] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */ | 497 | MX35_PAD_RESERVE189 = 470, |
| 498 | [184] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */ | 498 | MX35_PAD_RESERVE190 = 471, |
| 499 | [185] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */ | 499 | MX35_PAD_RESERVE191 = 472, |
| 500 | [186] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */ | 500 | MX35_PAD_RESERVE192 = 473, |
| 501 | [187] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */ | 501 | MX35_PAD_RESERVE193 = 474, |
| 502 | [188] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */ | 502 | MX35_PAD_RESERVE194 = 475, |
| 503 | [189] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */ | 503 | MX35_PAD_RESERVE195 = 476, |
| 504 | [190] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */ | 504 | MX35_PAD_RESERVE196 = 477, |
| 505 | [191] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */ | 505 | MX35_PAD_RESERVE197 = 478, |
| 506 | [192] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */ | 506 | MX35_PAD_RESERVE198 = 479, |
| 507 | [193] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */ | 507 | MX35_PAD_RESERVE199 = 480, |
| 508 | [194] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */ | 508 | MX35_PAD_RESERVE200 = 481, |
| 509 | [195] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */ | 509 | MX35_PAD_RESERVE201 = 482, |
| 510 | [196] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */ | 510 | MX35_PAD_EXT_ARMCLK = 483, |
| 511 | [197] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */ | 511 | MX35_PAD_TEST_MODE = 484, |
| 512 | [198] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */ | ||
| 513 | [199] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */ | ||
| 514 | [200] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */ | ||
| 515 | [201] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */ | ||
| 516 | [202] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */ | ||
| 517 | [203] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */ | ||
| 518 | [204] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */ | ||
| 519 | [205] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */ | ||
| 520 | [206] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */ | ||
| 521 | [207] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */ | ||
| 522 | [208] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */ | ||
| 523 | [209] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */ | ||
| 524 | [210] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */ | ||
| 525 | [211] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */ | ||
| 526 | [212] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */ | ||
| 527 | [213] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */ | ||
| 528 | [214] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */ | ||
| 529 | [215] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */ | ||
| 530 | [216] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */ | ||
| 531 | [217] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */ | ||
| 532 | [218] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */ | ||
| 533 | [219] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */ | ||
| 534 | [220] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */ | ||
| 535 | [221] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */ | ||
| 536 | [222] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */ | ||
| 537 | [223] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */ | ||
| 538 | [224] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */ | ||
| 539 | [225] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */ | ||
| 540 | [226] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */ | ||
| 541 | [227] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */ | ||
| 542 | [228] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */ | ||
| 543 | [229] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */ | ||
| 544 | [230] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */ | ||
| 545 | [231] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */ | ||
| 546 | [232] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */ | ||
| 547 | [233] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */ | ||
| 548 | [234] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */ | ||
| 549 | [235] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */ | ||
| 550 | [236] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */ | ||
| 551 | [237] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */ | ||
| 552 | [238] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */ | ||
| 553 | [239] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */ | ||
| 554 | [240] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */ | ||
| 555 | [241] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */ | ||
| 556 | [242] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */ | ||
| 557 | [243] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */ | ||
| 558 | [244] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */ | ||
| 559 | [245] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */ | ||
| 560 | [246] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */ | ||
| 561 | [247] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */ | ||
| 562 | [248] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */ | ||
| 563 | [249] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */ | ||
| 564 | [250] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */ | ||
| 565 | [251] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */ | ||
| 566 | [252] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */ | ||
| 567 | [253] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */ | ||
| 568 | [254] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */ | ||
| 569 | [255] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */ | ||
| 570 | [256] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */ | ||
| 571 | [257] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */ | ||
| 572 | [258] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */ | ||
| 573 | [259] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */ | ||
| 574 | [260] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */ | ||
| 575 | [261] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */ | ||
| 576 | [262] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */ | ||
| 577 | [263] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */ | ||
| 578 | [264] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */ | ||
| 579 | [265] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */ | ||
| 580 | [266] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */ | ||
| 581 | [267] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */ | ||
| 582 | [268] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */ | ||
| 583 | [269] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */ | ||
| 584 | [270] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */ | ||
| 585 | [271] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */ | ||
| 586 | [272] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */ | ||
| 587 | [273] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */ | ||
| 588 | [274] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */ | ||
| 589 | [275] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */ | ||
| 590 | [276] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */ | ||
| 591 | [277] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */ | ||
| 592 | [278] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */ | ||
| 593 | [279] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */ | ||
| 594 | [280] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */ | ||
| 595 | [281] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */ | ||
| 596 | [282] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */ | ||
| 597 | [283] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */ | ||
| 598 | [284] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */ | ||
| 599 | [285] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */ | ||
| 600 | [286] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */ | ||
| 601 | [287] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */ | ||
| 602 | [288] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */ | ||
| 603 | [289] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */ | ||
| 604 | [290] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */ | ||
| 605 | [291] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */ | ||
| 606 | [292] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */ | ||
| 607 | [293] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */ | ||
| 608 | [294] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */ | ||
| 609 | [295] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */ | ||
| 610 | [296] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */ | ||
| 611 | [297] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */ | ||
| 612 | [298] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */ | ||
| 613 | [299] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */ | ||
| 614 | [300] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */ | ||
| 615 | [301] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */ | ||
| 616 | [302] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */ | ||
| 617 | [303] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */ | ||
| 618 | [304] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */ | ||
| 619 | [305] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */ | ||
| 620 | [306] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */ | ||
| 621 | [307] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */ | ||
| 622 | [308] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */ | ||
| 623 | [309] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */ | ||
| 624 | [310] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */ | ||
| 625 | [311] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */ | ||
| 626 | [312] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */ | ||
| 627 | [313] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */ | ||
| 628 | [314] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */ | ||
| 629 | [315] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */ | ||
| 630 | [316] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */ | ||
| 631 | [317] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */ | ||
| 632 | [318] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */ | ||
| 633 | [319] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */ | ||
| 634 | [320] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */ | ||
| 635 | [321] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */ | ||
| 636 | [322] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */ | ||
| 637 | [323] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */ | ||
| 638 | [324] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */ | ||
| 639 | [325] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */ | ||
| 640 | [326] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */ | ||
| 641 | [327] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */ | ||
| 642 | [328] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */ | ||
| 643 | [329] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */ | ||
| 644 | [330] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */ | ||
| 645 | [331] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */ | ||
| 646 | [332] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */ | ||
| 647 | [333] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */ | ||
| 648 | [334] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */ | ||
| 649 | [335] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */ | ||
| 650 | [336] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */ | ||
| 651 | [337] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */ | ||
| 652 | [338] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */ | ||
| 653 | [339] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */ | ||
| 654 | [340] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */ | ||
| 655 | [341] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */ | ||
| 656 | [342] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */ | ||
| 657 | [343] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */ | ||
| 658 | [344] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */ | ||
| 659 | [345] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */ | ||
| 660 | [346] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */ | ||
| 661 | [347] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */ | ||
| 662 | [348] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */ | ||
| 663 | [349] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */ | ||
| 664 | [350] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */ | ||
| 665 | [351] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */ | ||
| 666 | [352] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */ | ||
| 667 | [353] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */ | ||
| 668 | [354] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */ | ||
| 669 | [355] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */ | ||
| 670 | [356] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */ | ||
| 671 | [357] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */ | ||
| 672 | [358] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */ | ||
| 673 | [359] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */ | ||
| 674 | [360] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */ | ||
| 675 | [361] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */ | ||
| 676 | [362] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */ | ||
| 677 | [363] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */ | ||
| 678 | [364] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */ | ||
| 679 | [365] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */ | ||
| 680 | [366] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */ | ||
| 681 | [367] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */ | ||
| 682 | [368] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */ | ||
| 683 | [369] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */ | ||
| 684 | [370] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */ | ||
| 685 | [371] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */ | ||
| 686 | [372] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */ | ||
| 687 | [373] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */ | ||
| 688 | [374] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */ | ||
| 689 | [375] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */ | ||
| 690 | [376] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */ | ||
| 691 | [377] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */ | ||
| 692 | [378] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */ | ||
| 693 | [379] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */ | ||
| 694 | [380] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */ | ||
| 695 | [381] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */ | ||
| 696 | [382] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */ | ||
| 697 | [383] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */ | ||
| 698 | [384] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */ | ||
| 699 | [385] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */ | ||
| 700 | [386] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */ | ||
| 701 | [387] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */ | ||
| 702 | [388] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */ | ||
| 703 | [389] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */ | ||
| 704 | [390] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */ | ||
| 705 | [391] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */ | ||
| 706 | [392] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */ | ||
| 707 | [393] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */ | ||
| 708 | [394] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */ | ||
| 709 | [395] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */ | ||
| 710 | [396] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */ | ||
| 711 | [397] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */ | ||
| 712 | [398] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */ | ||
| 713 | [399] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */ | ||
| 714 | [400] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */ | ||
| 715 | [401] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */ | ||
| 716 | [402] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */ | ||
| 717 | [403] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */ | ||
| 718 | [404] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */ | ||
| 719 | [405] = IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */ | ||
| 720 | [406] = IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */ | ||
| 721 | [407] = IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */ | ||
| 722 | [408] = IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */ | ||
| 723 | [409] = IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */ | ||
| 724 | [410] = IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */ | ||
| 725 | [411] = IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */ | ||
| 726 | [412] = IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */ | ||
| 727 | [413] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */ | ||
| 728 | [414] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */ | ||
| 729 | [415] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */ | ||
| 730 | [416] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */ | ||
| 731 | [417] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */ | ||
| 732 | [418] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */ | ||
| 733 | [419] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */ | ||
| 734 | [420] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */ | ||
| 735 | [421] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */ | ||
| 736 | [422] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */ | ||
| 737 | [423] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */ | ||
| 738 | [424] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */ | ||
| 739 | [425] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */ | ||
| 740 | [426] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */ | ||
| 741 | [427] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */ | ||
| 742 | [428] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */ | ||
| 743 | [429] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */ | ||
| 744 | [430] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */ | ||
| 745 | [431] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */ | ||
| 746 | [432] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */ | ||
| 747 | [433] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */ | ||
| 748 | [434] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */ | ||
| 749 | [435] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */ | ||
| 750 | [436] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */ | ||
| 751 | [437] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */ | ||
| 752 | [438] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */ | ||
| 753 | [439] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */ | ||
| 754 | [440] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */ | ||
| 755 | [441] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */ | ||
| 756 | [442] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */ | ||
| 757 | [443] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */ | ||
| 758 | [444] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */ | ||
| 759 | [445] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */ | ||
| 760 | [446] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */ | ||
| 761 | [447] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */ | ||
| 762 | [448] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */ | ||
| 763 | [449] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */ | ||
| 764 | [450] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */ | ||
| 765 | [451] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */ | ||
| 766 | [452] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */ | ||
| 767 | [453] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */ | ||
| 768 | [454] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */ | ||
| 769 | [455] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */ | ||
| 770 | [456] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */ | ||
| 771 | [457] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */ | ||
| 772 | [458] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */ | ||
| 773 | [459] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */ | ||
| 774 | [460] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */ | ||
| 775 | [461] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */ | ||
| 776 | [462] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */ | ||
| 777 | [463] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */ | ||
| 778 | [464] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */ | ||
| 779 | [465] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */ | ||
| 780 | [466] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */ | ||
| 781 | [467] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */ | ||
| 782 | [468] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */ | ||
| 783 | [469] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */ | ||
| 784 | [470] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */ | ||
| 785 | [471] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */ | ||
| 786 | [472] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */ | ||
| 787 | [473] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */ | ||
| 788 | [474] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */ | ||
| 789 | [475] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */ | ||
| 790 | [476] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */ | ||
| 791 | [477] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */ | ||
| 792 | [478] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */ | ||
| 793 | [479] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */ | ||
| 794 | [480] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */ | ||
| 795 | [481] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */ | ||
| 796 | [482] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */ | ||
| 797 | [483] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */ | ||
| 798 | [484] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */ | ||
| 799 | [485] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */ | ||
| 800 | [486] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */ | ||
| 801 | [487] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */ | ||
| 802 | [488] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */ | ||
| 803 | [489] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */ | ||
| 804 | [490] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */ | ||
| 805 | [491] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */ | ||
| 806 | [492] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */ | ||
| 807 | [493] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */ | ||
| 808 | [494] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */ | ||
| 809 | [495] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */ | ||
| 810 | [496] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */ | ||
| 811 | [497] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */ | ||
| 812 | [498] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */ | ||
| 813 | [499] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */ | ||
| 814 | [500] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */ | ||
| 815 | [501] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */ | ||
| 816 | [502] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */ | ||
| 817 | [503] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */ | ||
| 818 | [504] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */ | ||
| 819 | [505] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */ | ||
| 820 | [506] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */ | ||
| 821 | [507] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */ | ||
| 822 | [508] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */ | ||
| 823 | [509] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */ | ||
| 824 | [510] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */ | ||
| 825 | [511] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */ | ||
| 826 | [512] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */ | ||
| 827 | [513] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */ | ||
| 828 | [514] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */ | ||
| 829 | [515] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */ | ||
| 830 | [516] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */ | ||
| 831 | [517] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */ | ||
| 832 | [518] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */ | ||
| 833 | [519] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */ | ||
| 834 | [520] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */ | ||
| 835 | [521] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */ | ||
| 836 | [522] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */ | ||
| 837 | [523] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */ | ||
| 838 | [524] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */ | ||
| 839 | [525] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */ | ||
| 840 | [526] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */ | ||
| 841 | [527] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */ | ||
| 842 | [528] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */ | ||
| 843 | [529] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */ | ||
| 844 | [530] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */ | ||
| 845 | [531] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */ | ||
| 846 | [532] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */ | ||
| 847 | [533] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */ | ||
| 848 | [534] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */ | ||
| 849 | [535] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */ | ||
| 850 | [536] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */ | ||
| 851 | [537] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */ | ||
| 852 | [538] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */ | ||
| 853 | [539] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */ | ||
| 854 | [540] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */ | ||
| 855 | [541] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */ | ||
| 856 | [542] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */ | ||
| 857 | [543] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */ | ||
| 858 | [544] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */ | ||
| 859 | [545] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */ | ||
| 860 | [546] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */ | ||
| 861 | [547] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */ | ||
| 862 | [548] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */ | ||
| 863 | [549] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */ | ||
| 864 | [550] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */ | ||
| 865 | [551] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */ | ||
| 866 | [552] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */ | ||
| 867 | [553] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */ | ||
| 868 | [554] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */ | ||
| 869 | [555] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */ | ||
| 870 | [556] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */ | ||
| 871 | [557] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */ | ||
| 872 | [558] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */ | ||
| 873 | [559] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */ | ||
| 874 | [560] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */ | ||
| 875 | [561] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */ | ||
| 876 | [562] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */ | ||
| 877 | [563] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */ | ||
| 878 | [564] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */ | ||
| 879 | [565] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */ | ||
| 880 | [566] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */ | ||
| 881 | [567] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */ | ||
| 882 | [568] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */ | ||
| 883 | [569] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */ | ||
| 884 | [570] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */ | ||
| 885 | [571] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */ | ||
| 886 | [572] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */ | ||
| 887 | [573] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */ | ||
| 888 | [574] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */ | ||
| 889 | [575] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */ | ||
| 890 | [576] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */ | ||
| 891 | [577] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */ | ||
| 892 | [578] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */ | ||
| 893 | [579] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */ | ||
| 894 | [580] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */ | ||
| 895 | [581] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */ | ||
| 896 | [582] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */ | ||
| 897 | [583] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */ | ||
| 898 | [584] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */ | ||
| 899 | [585] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */ | ||
| 900 | [586] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */ | ||
| 901 | [587] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */ | ||
| 902 | [588] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */ | ||
| 903 | [589] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */ | ||
| 904 | [590] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */ | ||
| 905 | [591] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */ | ||
| 906 | [592] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */ | ||
| 907 | [593] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */ | ||
| 908 | [594] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */ | ||
| 909 | [595] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */ | ||
| 910 | [596] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */ | ||
| 911 | [597] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */ | ||
| 912 | [598] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */ | ||
| 913 | [599] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */ | ||
| 914 | [600] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */ | ||
| 915 | [601] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */ | ||
| 916 | [602] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */ | ||
| 917 | [603] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */ | ||
| 918 | [604] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */ | ||
| 919 | [605] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */ | ||
| 920 | [606] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */ | ||
| 921 | [607] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */ | ||
| 922 | [608] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */ | ||
| 923 | [609] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */ | ||
| 924 | [610] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */ | ||
| 925 | [611] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */ | ||
| 926 | [612] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */ | ||
| 927 | [613] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */ | ||
| 928 | [614] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */ | ||
| 929 | [615] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */ | ||
| 930 | [616] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */ | ||
| 931 | [617] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */ | ||
| 932 | [618] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */ | ||
| 933 | [619] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */ | ||
| 934 | [620] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */ | ||
| 935 | [621] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */ | ||
| 936 | [622] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */ | ||
| 937 | [623] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */ | ||
| 938 | [624] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */ | ||
| 939 | [625] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */ | ||
| 940 | [626] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */ | ||
| 941 | [627] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */ | ||
| 942 | [628] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */ | ||
| 943 | [629] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */ | ||
| 944 | [630] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */ | ||
| 945 | [631] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */ | ||
| 946 | [632] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */ | ||
| 947 | [633] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */ | ||
| 948 | [634] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */ | ||
| 949 | [635] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */ | ||
| 950 | [636] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */ | ||
| 951 | [637] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */ | ||
| 952 | [638] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */ | ||
| 953 | [639] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */ | ||
| 954 | [640] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */ | ||
| 955 | [641] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */ | ||
| 956 | [642] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */ | ||
| 957 | [643] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */ | ||
| 958 | [644] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */ | ||
| 959 | [645] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */ | ||
| 960 | [646] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */ | ||
| 961 | [647] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */ | ||
| 962 | [648] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */ | ||
| 963 | [649] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */ | ||
| 964 | [650] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */ | ||
| 965 | [651] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */ | ||
| 966 | [652] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */ | ||
| 967 | [653] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */ | ||
| 968 | [654] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */ | ||
| 969 | [655] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */ | ||
| 970 | [656] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */ | ||
| 971 | [657] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */ | ||
| 972 | [658] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */ | ||
| 973 | [659] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */ | ||
| 974 | [660] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */ | ||
| 975 | [661] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */ | ||
| 976 | [662] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */ | ||
| 977 | [663] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */ | ||
| 978 | [664] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */ | ||
| 979 | [665] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */ | ||
| 980 | [666] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */ | ||
| 981 | [667] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */ | ||
| 982 | [668] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */ | ||
| 983 | [669] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */ | ||
| 984 | [670] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */ | ||
| 985 | [671] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */ | ||
| 986 | [672] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */ | ||
| 987 | [673] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */ | ||
| 988 | [674] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */ | ||
| 989 | [675] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */ | ||
| 990 | [676] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */ | ||
| 991 | [677] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */ | ||
| 992 | [678] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */ | ||
| 993 | [679] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */ | ||
| 994 | [680] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */ | ||
| 995 | [681] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */ | ||
| 996 | [682] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */ | ||
| 997 | [683] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */ | ||
| 998 | [684] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */ | ||
| 999 | [685] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */ | ||
| 1000 | [686] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */ | ||
| 1001 | [687] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */ | ||
| 1002 | [688] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */ | ||
| 1003 | [689] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */ | ||
| 1004 | [690] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */ | ||
| 1005 | [691] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */ | ||
| 1006 | [692] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */ | ||
| 1007 | [693] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */ | ||
| 1008 | [694] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */ | ||
| 1009 | [695] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */ | ||
| 1010 | [696] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */ | ||
| 1011 | [697] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */ | ||
| 1012 | [698] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */ | ||
| 1013 | [699] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */ | ||
| 1014 | [700] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */ | ||
| 1015 | [701] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */ | ||
| 1016 | [702] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */ | ||
| 1017 | [703] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */ | ||
| 1018 | [704] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */ | ||
| 1019 | [705] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */ | ||
| 1020 | [706] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */ | ||
| 1021 | [707] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */ | ||
| 1022 | [708] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */ | ||
| 1023 | [709] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */ | ||
| 1024 | [710] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */ | ||
| 1025 | [711] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */ | ||
| 1026 | [712] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */ | ||
| 1027 | [713] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */ | ||
| 1028 | [714] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */ | ||
| 1029 | [715] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */ | ||
| 1030 | [716] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */ | ||
| 1031 | [717] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */ | ||
| 1032 | [718] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */ | ||
| 1033 | [719] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */ | ||
| 1034 | [720] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */ | ||
| 1035 | [721] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */ | ||
| 1036 | [722] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */ | ||
| 1037 | [723] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */ | ||
| 1038 | [724] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */ | ||
| 1039 | [725] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */ | ||
| 1040 | [726] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */ | ||
| 1041 | [727] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */ | ||
| 1042 | [728] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */ | ||
| 1043 | [729] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */ | ||
| 1044 | [730] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */ | ||
| 1045 | [731] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */ | ||
| 1046 | [732] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */ | ||
| 1047 | [733] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */ | ||
| 1048 | [734] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */ | ||
| 1049 | [735] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */ | ||
| 1050 | [736] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */ | ||
| 1051 | [737] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */ | ||
| 1052 | [738] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */ | ||
| 1053 | [739] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */ | ||
| 1054 | [740] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */ | ||
| 1055 | [741] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */ | ||
| 1056 | [742] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */ | ||
| 1057 | [743] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */ | ||
| 1058 | [744] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */ | ||
| 1059 | [745] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */ | ||
| 1060 | [746] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */ | ||
| 1061 | [747] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */ | ||
| 1062 | [748] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */ | ||
| 1063 | [749] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */ | ||
| 1064 | [750] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */ | ||
| 1065 | [751] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */ | ||
| 1066 | [752] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */ | ||
| 1067 | [753] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */ | ||
| 1068 | [754] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */ | ||
| 1069 | [755] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */ | ||
| 1070 | [756] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */ | ||
| 1071 | [757] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */ | ||
| 1072 | [758] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */ | ||
| 1073 | [759] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */ | ||
| 1074 | [760] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */ | ||
| 1075 | [761] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */ | ||
| 1076 | [762] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */ | ||
| 1077 | [763] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */ | ||
| 1078 | [764] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */ | ||
| 1079 | [765] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */ | ||
| 1080 | [766] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */ | ||
| 1081 | [767] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */ | ||
| 1082 | [768] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */ | ||
| 1083 | [769] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */ | ||
| 1084 | [770] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */ | ||
| 1085 | [771] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */ | ||
| 1086 | [772] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */ | ||
| 1087 | [773] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */ | ||
| 1088 | [774] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */ | ||
| 1089 | [775] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */ | ||
| 1090 | [776] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */ | ||
| 1091 | [777] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */ | ||
| 1092 | [778] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */ | ||
| 1093 | [779] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */ | ||
| 1094 | [780] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */ | ||
| 1095 | [781] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */ | ||
| 1096 | [782] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */ | ||
| 1097 | [783] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */ | ||
| 1098 | [784] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */ | ||
| 1099 | [785] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */ | ||
| 1100 | [786] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */ | ||
| 1101 | [787] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */ | ||
| 1102 | [788] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */ | ||
| 1103 | [789] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */ | ||
| 1104 | [790] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */ | ||
| 1105 | [791] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */ | ||
| 1106 | [792] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */ | ||
| 1107 | [793] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */ | ||
| 1108 | [794] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */ | ||
| 1109 | [795] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */ | ||
| 1110 | [796] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */ | ||
| 1111 | [797] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */ | ||
| 1112 | [798] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */ | ||
| 1113 | [799] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */ | ||
| 1114 | [800] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */ | ||
| 1115 | [801] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */ | ||
| 1116 | [802] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */ | ||
| 1117 | [803] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */ | ||
| 1118 | [804] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */ | ||
| 1119 | [805] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */ | ||
| 1120 | [806] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */ | ||
| 1121 | [807] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */ | ||
| 1122 | [808] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */ | ||
| 1123 | [809] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */ | ||
| 1124 | [810] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */ | ||
| 1125 | [811] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */ | ||
| 1126 | [812] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */ | ||
| 1127 | [813] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */ | ||
| 1128 | [814] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */ | ||
| 1129 | [815] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */ | ||
| 1130 | [816] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */ | ||
| 1131 | [817] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */ | ||
| 1132 | [818] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */ | ||
| 1133 | [819] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */ | ||
| 1134 | [820] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */ | ||
| 1135 | [821] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */ | ||
| 1136 | [822] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */ | ||
| 1137 | [823] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */ | ||
| 1138 | [824] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */ | ||
| 1139 | [825] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */ | ||
| 1140 | [826] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */ | ||
| 1141 | [827] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */ | ||
| 1142 | [828] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */ | ||
| 1143 | [829] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */ | ||
| 1144 | [830] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */ | ||
| 1145 | [831] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */ | ||
| 1146 | [832] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */ | ||
| 1147 | [833] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */ | ||
| 1148 | [834] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */ | ||
| 1149 | [835] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */ | ||
| 1150 | [836] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */ | ||
| 1151 | [837] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */ | ||
| 1152 | [838] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */ | ||
| 1153 | [839] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */ | ||
| 1154 | [840] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */ | ||
| 1155 | [841] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */ | ||
| 1156 | [842] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */ | ||
| 1157 | [843] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */ | ||
| 1158 | [844] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */ | ||
| 1159 | [845] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */ | ||
| 1160 | [846] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */ | ||
| 1161 | [847] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */ | ||
| 1162 | [848] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */ | ||
| 1163 | [849] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */ | ||
| 1164 | [850] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */ | ||
| 1165 | [851] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */ | ||
| 1166 | [852] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */ | ||
| 1167 | [853] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */ | ||
| 1168 | [854] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */ | ||
| 1169 | [855] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */ | ||
| 1170 | [856] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */ | ||
| 1171 | [857] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */ | ||
| 1172 | [858] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */ | ||
| 1173 | [859] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */ | ||
| 1174 | [860] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */ | ||
| 1175 | [861] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */ | ||
| 1176 | [862] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */ | ||
| 1177 | [863] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */ | ||
| 1178 | [864] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */ | ||
| 1179 | [865] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */ | ||
| 1180 | [866] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */ | ||
| 1181 | [867] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */ | ||
| 1182 | [868] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */ | ||
| 1183 | [869] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */ | ||
| 1184 | [870] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */ | ||
| 1185 | [871] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */ | ||
| 1186 | [872] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */ | ||
| 1187 | [873] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */ | ||
| 1188 | [874] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */ | ||
| 1189 | [875] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */ | ||
| 1190 | [876] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */ | ||
| 1191 | [877] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */ | ||
| 1192 | [878] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */ | ||
| 1193 | [879] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */ | ||
| 1194 | [880] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */ | ||
| 1195 | [881] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */ | ||
| 1196 | [882] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */ | ||
| 1197 | [883] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */ | ||
| 1198 | [884] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */ | ||
| 1199 | [885] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */ | ||
| 1200 | [886] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */ | ||
| 1201 | [887] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */ | ||
| 1202 | [888] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */ | ||
| 1203 | [889] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */ | ||
| 1204 | [890] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */ | ||
| 1205 | [891] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */ | ||
| 1206 | [892] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */ | ||
| 1207 | [893] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */ | ||
| 1208 | [894] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */ | ||
| 1209 | [895] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */ | ||
| 1210 | [896] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */ | ||
| 1211 | [897] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */ | ||
| 1212 | [898] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */ | ||
| 1213 | [899] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */ | ||
| 1214 | [900] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */ | ||
| 1215 | [901] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */ | ||
| 1216 | [902] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */ | ||
| 1217 | [903] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */ | ||
| 1218 | [904] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */ | ||
| 1219 | [905] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */ | ||
| 1220 | [906] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */ | ||
| 1221 | [907] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */ | ||
| 1222 | [908] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */ | ||
| 1223 | [909] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */ | ||
| 1224 | [910] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */ | ||
| 1225 | [911] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */ | ||
| 1226 | [912] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */ | ||
| 1227 | [913] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */ | ||
| 1228 | [914] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */ | ||
| 1229 | [915] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */ | ||
| 1230 | [916] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */ | ||
| 1231 | [917] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */ | ||
| 1232 | [918] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */ | ||
| 1233 | [919] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */ | ||
| 1234 | [920] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */ | ||
| 1235 | [921] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */ | ||
| 1236 | [922] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */ | ||
| 1237 | [923] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */ | ||
| 1238 | [924] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */ | ||
| 1239 | [925] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */ | ||
| 1240 | [926] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */ | ||
| 1241 | [927] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */ | ||
| 1242 | [928] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */ | ||
| 1243 | [929] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */ | ||
| 1244 | [930] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */ | ||
| 1245 | [931] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */ | ||
| 1246 | [932] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */ | ||
| 1247 | [933] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */ | ||
| 1248 | [934] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */ | ||
| 1249 | [935] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */ | ||
| 1250 | [936] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */ | ||
| 1251 | [937] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */ | ||
| 1252 | [938] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */ | ||
| 1253 | [939] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */ | ||
| 1254 | [940] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */ | ||
| 1255 | [941] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */ | ||
| 1256 | [942] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */ | ||
| 1257 | [943] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */ | ||
| 1258 | [944] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */ | ||
| 1259 | [945] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */ | ||
| 1260 | [946] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */ | ||
| 1261 | [947] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */ | ||
| 1262 | [948] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */ | ||
| 1263 | [949] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */ | ||
| 1264 | [950] = IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */ | ||
| 1265 | [951] = IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */ | ||
| 1266 | }; | 512 | }; |
| 1267 | 513 | ||
| 1268 | /* Pad names for the pinmux subsystem */ | 514 | /* Pad names for the pinmux subsystem */ |
| 1269 | static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | 515 | static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { |
| 516 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE0), | ||
| 1270 | IMX_PINCTRL_PIN(MX35_PAD_CAPTURE), | 517 | IMX_PINCTRL_PIN(MX35_PAD_CAPTURE), |
| 1271 | IMX_PINCTRL_PIN(MX35_PAD_COMPARE), | 518 | IMX_PINCTRL_PIN(MX35_PAD_COMPARE), |
| 1272 | IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST), | 519 | IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST), |
| @@ -1274,14 +521,7 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | |||
| 1274 | IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1), | 521 | IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1), |
| 1275 | IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0), | 522 | IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0), |
| 1276 | IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0), | 523 | IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0), |
| 1277 | IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B), | ||
| 1278 | IMX_PINCTRL_PIN(MX35_PAD_POR_B), | ||
| 1279 | IMX_PINCTRL_PIN(MX35_PAD_CLKO), | 524 | IMX_PINCTRL_PIN(MX35_PAD_CLKO), |
| 1280 | IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0), | ||
| 1281 | IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1), | ||
| 1282 | IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0), | ||
| 1283 | IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1), | ||
| 1284 | IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL), | ||
| 1285 | IMX_PINCTRL_PIN(MX35_PAD_VSTBY), | 525 | IMX_PINCTRL_PIN(MX35_PAD_VSTBY), |
| 1286 | IMX_PINCTRL_PIN(MX35_PAD_A0), | 526 | IMX_PINCTRL_PIN(MX35_PAD_A0), |
| 1287 | IMX_PINCTRL_PIN(MX35_PAD_A1), | 527 | IMX_PINCTRL_PIN(MX35_PAD_A1), |
| @@ -1310,44 +550,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | |||
| 1310 | IMX_PINCTRL_PIN(MX35_PAD_A23), | 550 | IMX_PINCTRL_PIN(MX35_PAD_A23), |
| 1311 | IMX_PINCTRL_PIN(MX35_PAD_A24), | 551 | IMX_PINCTRL_PIN(MX35_PAD_A24), |
| 1312 | IMX_PINCTRL_PIN(MX35_PAD_A25), | 552 | IMX_PINCTRL_PIN(MX35_PAD_A25), |
| 1313 | IMX_PINCTRL_PIN(MX35_PAD_SDBA1), | ||
| 1314 | IMX_PINCTRL_PIN(MX35_PAD_SDBA0), | ||
| 1315 | IMX_PINCTRL_PIN(MX35_PAD_SD0), | ||
| 1316 | IMX_PINCTRL_PIN(MX35_PAD_SD1), | ||
| 1317 | IMX_PINCTRL_PIN(MX35_PAD_SD2), | ||
| 1318 | IMX_PINCTRL_PIN(MX35_PAD_SD3), | ||
| 1319 | IMX_PINCTRL_PIN(MX35_PAD_SD4), | ||
| 1320 | IMX_PINCTRL_PIN(MX35_PAD_SD5), | ||
| 1321 | IMX_PINCTRL_PIN(MX35_PAD_SD6), | ||
| 1322 | IMX_PINCTRL_PIN(MX35_PAD_SD7), | ||
| 1323 | IMX_PINCTRL_PIN(MX35_PAD_SD8), | ||
| 1324 | IMX_PINCTRL_PIN(MX35_PAD_SD9), | ||
| 1325 | IMX_PINCTRL_PIN(MX35_PAD_SD10), | ||
| 1326 | IMX_PINCTRL_PIN(MX35_PAD_SD11), | ||
| 1327 | IMX_PINCTRL_PIN(MX35_PAD_SD12), | ||
| 1328 | IMX_PINCTRL_PIN(MX35_PAD_SD13), | ||
| 1329 | IMX_PINCTRL_PIN(MX35_PAD_SD14), | ||
| 1330 | IMX_PINCTRL_PIN(MX35_PAD_SD15), | ||
| 1331 | IMX_PINCTRL_PIN(MX35_PAD_SD16), | ||
| 1332 | IMX_PINCTRL_PIN(MX35_PAD_SD17), | ||
| 1333 | IMX_PINCTRL_PIN(MX35_PAD_SD18), | ||
| 1334 | IMX_PINCTRL_PIN(MX35_PAD_SD19), | ||
| 1335 | IMX_PINCTRL_PIN(MX35_PAD_SD20), | ||
| 1336 | IMX_PINCTRL_PIN(MX35_PAD_SD21), | ||
| 1337 | IMX_PINCTRL_PIN(MX35_PAD_SD22), | ||
| 1338 | IMX_PINCTRL_PIN(MX35_PAD_SD23), | ||
| 1339 | IMX_PINCTRL_PIN(MX35_PAD_SD24), | ||
| 1340 | IMX_PINCTRL_PIN(MX35_PAD_SD25), | ||
| 1341 | IMX_PINCTRL_PIN(MX35_PAD_SD26), | ||
| 1342 | IMX_PINCTRL_PIN(MX35_PAD_SD27), | ||
| 1343 | IMX_PINCTRL_PIN(MX35_PAD_SD28), | ||
| 1344 | IMX_PINCTRL_PIN(MX35_PAD_SD29), | ||
| 1345 | IMX_PINCTRL_PIN(MX35_PAD_SD30), | ||
| 1346 | IMX_PINCTRL_PIN(MX35_PAD_SD31), | ||
| 1347 | IMX_PINCTRL_PIN(MX35_PAD_DQM0), | ||
| 1348 | IMX_PINCTRL_PIN(MX35_PAD_DQM1), | ||
| 1349 | IMX_PINCTRL_PIN(MX35_PAD_DQM2), | ||
| 1350 | IMX_PINCTRL_PIN(MX35_PAD_DQM3), | ||
| 1351 | IMX_PINCTRL_PIN(MX35_PAD_EB0), | 553 | IMX_PINCTRL_PIN(MX35_PAD_EB0), |
| 1352 | IMX_PINCTRL_PIN(MX35_PAD_EB1), | 554 | IMX_PINCTRL_PIN(MX35_PAD_EB1), |
| 1353 | IMX_PINCTRL_PIN(MX35_PAD_OE), | 555 | IMX_PINCTRL_PIN(MX35_PAD_OE), |
| @@ -1358,42 +560,15 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | |||
| 1358 | IMX_PINCTRL_PIN(MX35_PAD_CS4), | 560 | IMX_PINCTRL_PIN(MX35_PAD_CS4), |
| 1359 | IMX_PINCTRL_PIN(MX35_PAD_CS5), | 561 | IMX_PINCTRL_PIN(MX35_PAD_CS5), |
| 1360 | IMX_PINCTRL_PIN(MX35_PAD_NF_CE0), | 562 | IMX_PINCTRL_PIN(MX35_PAD_NF_CE0), |
| 1361 | IMX_PINCTRL_PIN(MX35_PAD_ECB), | ||
| 1362 | IMX_PINCTRL_PIN(MX35_PAD_LBA), | 563 | IMX_PINCTRL_PIN(MX35_PAD_LBA), |
| 1363 | IMX_PINCTRL_PIN(MX35_PAD_BCLK), | 564 | IMX_PINCTRL_PIN(MX35_PAD_BCLK), |
| 1364 | IMX_PINCTRL_PIN(MX35_PAD_RW), | 565 | IMX_PINCTRL_PIN(MX35_PAD_RW), |
| 1365 | IMX_PINCTRL_PIN(MX35_PAD_RAS), | ||
| 1366 | IMX_PINCTRL_PIN(MX35_PAD_CAS), | ||
| 1367 | IMX_PINCTRL_PIN(MX35_PAD_SDWE), | ||
| 1368 | IMX_PINCTRL_PIN(MX35_PAD_SDCKE0), | ||
| 1369 | IMX_PINCTRL_PIN(MX35_PAD_SDCKE1), | ||
| 1370 | IMX_PINCTRL_PIN(MX35_PAD_SDCLK), | ||
| 1371 | IMX_PINCTRL_PIN(MX35_PAD_SDQS0), | ||
| 1372 | IMX_PINCTRL_PIN(MX35_PAD_SDQS1), | ||
| 1373 | IMX_PINCTRL_PIN(MX35_PAD_SDQS2), | ||
| 1374 | IMX_PINCTRL_PIN(MX35_PAD_SDQS3), | ||
| 1375 | IMX_PINCTRL_PIN(MX35_PAD_NFWE_B), | 566 | IMX_PINCTRL_PIN(MX35_PAD_NFWE_B), |
| 1376 | IMX_PINCTRL_PIN(MX35_PAD_NFRE_B), | 567 | IMX_PINCTRL_PIN(MX35_PAD_NFRE_B), |
| 1377 | IMX_PINCTRL_PIN(MX35_PAD_NFALE), | 568 | IMX_PINCTRL_PIN(MX35_PAD_NFALE), |
| 1378 | IMX_PINCTRL_PIN(MX35_PAD_NFCLE), | 569 | IMX_PINCTRL_PIN(MX35_PAD_NFCLE), |
| 1379 | IMX_PINCTRL_PIN(MX35_PAD_NFWP_B), | 570 | IMX_PINCTRL_PIN(MX35_PAD_NFWP_B), |
| 1380 | IMX_PINCTRL_PIN(MX35_PAD_NFRB), | 571 | IMX_PINCTRL_PIN(MX35_PAD_NFRB), |
| 1381 | IMX_PINCTRL_PIN(MX35_PAD_D15), | ||
| 1382 | IMX_PINCTRL_PIN(MX35_PAD_D14), | ||
| 1383 | IMX_PINCTRL_PIN(MX35_PAD_D13), | ||
| 1384 | IMX_PINCTRL_PIN(MX35_PAD_D12), | ||
| 1385 | IMX_PINCTRL_PIN(MX35_PAD_D11), | ||
| 1386 | IMX_PINCTRL_PIN(MX35_PAD_D10), | ||
| 1387 | IMX_PINCTRL_PIN(MX35_PAD_D9), | ||
| 1388 | IMX_PINCTRL_PIN(MX35_PAD_D8), | ||
| 1389 | IMX_PINCTRL_PIN(MX35_PAD_D7), | ||
| 1390 | IMX_PINCTRL_PIN(MX35_PAD_D6), | ||
| 1391 | IMX_PINCTRL_PIN(MX35_PAD_D5), | ||
| 1392 | IMX_PINCTRL_PIN(MX35_PAD_D4), | ||
| 1393 | IMX_PINCTRL_PIN(MX35_PAD_D3), | ||
| 1394 | IMX_PINCTRL_PIN(MX35_PAD_D2), | ||
| 1395 | IMX_PINCTRL_PIN(MX35_PAD_D1), | ||
| 1396 | IMX_PINCTRL_PIN(MX35_PAD_D0), | ||
| 1397 | IMX_PINCTRL_PIN(MX35_PAD_CSI_D8), | 572 | IMX_PINCTRL_PIN(MX35_PAD_CSI_D8), |
| 1398 | IMX_PINCTRL_PIN(MX35_PAD_CSI_D9), | 573 | IMX_PINCTRL_PIN(MX35_PAD_CSI_D9), |
| 1399 | IMX_PINCTRL_PIN(MX35_PAD_CSI_D10), | 574 | IMX_PINCTRL_PIN(MX35_PAD_CSI_D10), |
| @@ -1444,14 +619,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | |||
| 1444 | IMX_PINCTRL_PIN(MX35_PAD_TXD2), | 619 | IMX_PINCTRL_PIN(MX35_PAD_TXD2), |
| 1445 | IMX_PINCTRL_PIN(MX35_PAD_RTS2), | 620 | IMX_PINCTRL_PIN(MX35_PAD_RTS2), |
| 1446 | IMX_PINCTRL_PIN(MX35_PAD_CTS2), | 621 | IMX_PINCTRL_PIN(MX35_PAD_CTS2), |
| 1447 | IMX_PINCTRL_PIN(MX35_PAD_RTCK), | ||
| 1448 | IMX_PINCTRL_PIN(MX35_PAD_TCK), | ||
| 1449 | IMX_PINCTRL_PIN(MX35_PAD_TMS), | ||
| 1450 | IMX_PINCTRL_PIN(MX35_PAD_TDI), | ||
| 1451 | IMX_PINCTRL_PIN(MX35_PAD_TDO), | ||
| 1452 | IMX_PINCTRL_PIN(MX35_PAD_TRSTB), | ||
| 1453 | IMX_PINCTRL_PIN(MX35_PAD_DE_B), | ||
| 1454 | IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD), | ||
| 1455 | IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR), | 622 | IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR), |
| 1456 | IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC), | 623 | IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC), |
| 1457 | IMX_PINCTRL_PIN(MX35_PAD_LD0), | 624 | IMX_PINCTRL_PIN(MX35_PAD_LD0), |
| @@ -1548,6 +715,287 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | |||
| 1548 | IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2), | 715 | IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2), |
| 1549 | IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3), | 716 | IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3), |
| 1550 | IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3), | 717 | IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3), |
| 718 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE1), | ||
| 719 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE2), | ||
| 720 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE3), | ||
| 721 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE4), | ||
| 722 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE5), | ||
| 723 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE6), | ||
| 724 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE7), | ||
| 725 | IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B), | ||
| 726 | IMX_PINCTRL_PIN(MX35_PAD_POR_B), | ||
| 727 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE8), | ||
| 728 | IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0), | ||
| 729 | IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1), | ||
| 730 | IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0), | ||
| 731 | IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1), | ||
| 732 | IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL), | ||
| 733 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE9), | ||
| 734 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE10), | ||
| 735 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE11), | ||
| 736 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE12), | ||
| 737 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE13), | ||
| 738 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE14), | ||
| 739 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE15), | ||
| 740 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE16), | ||
| 741 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE17), | ||
| 742 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE18), | ||
| 743 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE19), | ||
| 744 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE20), | ||
| 745 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE21), | ||
| 746 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE22), | ||
| 747 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE23), | ||
| 748 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE24), | ||
| 749 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE25), | ||
| 750 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE26), | ||
| 751 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE27), | ||
| 752 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE28), | ||
| 753 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE29), | ||
| 754 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE30), | ||
| 755 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE31), | ||
| 756 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE32), | ||
| 757 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE33), | ||
| 758 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE34), | ||
| 759 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE35), | ||
| 760 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE36), | ||
| 761 | IMX_PINCTRL_PIN(MX35_PAD_SDBA1), | ||
| 762 | IMX_PINCTRL_PIN(MX35_PAD_SDBA0), | ||
| 763 | IMX_PINCTRL_PIN(MX35_PAD_SD0), | ||
| 764 | IMX_PINCTRL_PIN(MX35_PAD_SD1), | ||
| 765 | IMX_PINCTRL_PIN(MX35_PAD_SD2), | ||
| 766 | IMX_PINCTRL_PIN(MX35_PAD_SD3), | ||
| 767 | IMX_PINCTRL_PIN(MX35_PAD_SD4), | ||
| 768 | IMX_PINCTRL_PIN(MX35_PAD_SD5), | ||
| 769 | IMX_PINCTRL_PIN(MX35_PAD_SD6), | ||
| 770 | IMX_PINCTRL_PIN(MX35_PAD_SD7), | ||
| 771 | IMX_PINCTRL_PIN(MX35_PAD_SD8), | ||
| 772 | IMX_PINCTRL_PIN(MX35_PAD_SD9), | ||
| 773 | IMX_PINCTRL_PIN(MX35_PAD_SD10), | ||
| 774 | IMX_PINCTRL_PIN(MX35_PAD_SD11), | ||
| 775 | IMX_PINCTRL_PIN(MX35_PAD_SD12), | ||
| 776 | IMX_PINCTRL_PIN(MX35_PAD_SD13), | ||
| 777 | IMX_PINCTRL_PIN(MX35_PAD_SD14), | ||
| 778 | IMX_PINCTRL_PIN(MX35_PAD_SD15), | ||
| 779 | IMX_PINCTRL_PIN(MX35_PAD_SD16), | ||
| 780 | IMX_PINCTRL_PIN(MX35_PAD_SD17), | ||
| 781 | IMX_PINCTRL_PIN(MX35_PAD_SD18), | ||
| 782 | IMX_PINCTRL_PIN(MX35_PAD_SD19), | ||
| 783 | IMX_PINCTRL_PIN(MX35_PAD_SD20), | ||
| 784 | IMX_PINCTRL_PIN(MX35_PAD_SD21), | ||
| 785 | IMX_PINCTRL_PIN(MX35_PAD_SD22), | ||
| 786 | IMX_PINCTRL_PIN(MX35_PAD_SD23), | ||
| 787 | IMX_PINCTRL_PIN(MX35_PAD_SD24), | ||
| 788 | IMX_PINCTRL_PIN(MX35_PAD_SD25), | ||
| 789 | IMX_PINCTRL_PIN(MX35_PAD_SD26), | ||
| 790 | IMX_PINCTRL_PIN(MX35_PAD_SD27), | ||
| 791 | IMX_PINCTRL_PIN(MX35_PAD_SD28), | ||
| 792 | IMX_PINCTRL_PIN(MX35_PAD_SD29), | ||
| 793 | IMX_PINCTRL_PIN(MX35_PAD_SD30), | ||
| 794 | IMX_PINCTRL_PIN(MX35_PAD_SD31), | ||
| 795 | IMX_PINCTRL_PIN(MX35_PAD_DQM0), | ||
| 796 | IMX_PINCTRL_PIN(MX35_PAD_DQM1), | ||
| 797 | IMX_PINCTRL_PIN(MX35_PAD_DQM2), | ||
| 798 | IMX_PINCTRL_PIN(MX35_PAD_DQM3), | ||
| 799 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE37), | ||
| 800 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE38), | ||
| 801 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE39), | ||
| 802 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE40), | ||
| 803 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE41), | ||
| 804 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE42), | ||
| 805 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE43), | ||
| 806 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE44), | ||
| 807 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE45), | ||
| 808 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE46), | ||
| 809 | IMX_PINCTRL_PIN(MX35_PAD_ECB), | ||
| 810 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE47), | ||
| 811 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE48), | ||
| 812 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE49), | ||
| 813 | IMX_PINCTRL_PIN(MX35_PAD_RAS), | ||
| 814 | IMX_PINCTRL_PIN(MX35_PAD_CAS), | ||
| 815 | IMX_PINCTRL_PIN(MX35_PAD_SDWE), | ||
| 816 | IMX_PINCTRL_PIN(MX35_PAD_SDCKE0), | ||
| 817 | IMX_PINCTRL_PIN(MX35_PAD_SDCKE1), | ||
| 818 | IMX_PINCTRL_PIN(MX35_PAD_SDCLK), | ||
| 819 | IMX_PINCTRL_PIN(MX35_PAD_SDQS0), | ||
| 820 | IMX_PINCTRL_PIN(MX35_PAD_SDQS1), | ||
| 821 | IMX_PINCTRL_PIN(MX35_PAD_SDQS2), | ||
| 822 | IMX_PINCTRL_PIN(MX35_PAD_SDQS3), | ||
| 823 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE50), | ||
| 824 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE51), | ||
| 825 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE52), | ||
| 826 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE53), | ||
| 827 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE54), | ||
| 828 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE55), | ||
| 829 | IMX_PINCTRL_PIN(MX35_PAD_D15), | ||
| 830 | IMX_PINCTRL_PIN(MX35_PAD_D14), | ||
| 831 | IMX_PINCTRL_PIN(MX35_PAD_D13), | ||
| 832 | IMX_PINCTRL_PIN(MX35_PAD_D12), | ||
| 833 | IMX_PINCTRL_PIN(MX35_PAD_D11), | ||
| 834 | IMX_PINCTRL_PIN(MX35_PAD_D10), | ||
| 835 | IMX_PINCTRL_PIN(MX35_PAD_D9), | ||
| 836 | IMX_PINCTRL_PIN(MX35_PAD_D8), | ||
| 837 | IMX_PINCTRL_PIN(MX35_PAD_D7), | ||
| 838 | IMX_PINCTRL_PIN(MX35_PAD_D6), | ||
| 839 | IMX_PINCTRL_PIN(MX35_PAD_D5), | ||
| 840 | IMX_PINCTRL_PIN(MX35_PAD_D4), | ||
| 841 | IMX_PINCTRL_PIN(MX35_PAD_D3), | ||
| 842 | IMX_PINCTRL_PIN(MX35_PAD_D2), | ||
| 843 | IMX_PINCTRL_PIN(MX35_PAD_D1), | ||
| 844 | IMX_PINCTRL_PIN(MX35_PAD_D0), | ||
| 845 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE56), | ||
| 846 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE57), | ||
| 847 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE58), | ||
| 848 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE59), | ||
| 849 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE60), | ||
| 850 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE61), | ||
| 851 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE62), | ||
| 852 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE63), | ||
| 853 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE64), | ||
| 854 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE65), | ||
| 855 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE66), | ||
| 856 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE67), | ||
| 857 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE68), | ||
| 858 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE69), | ||
| 859 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE70), | ||
| 860 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE71), | ||
| 861 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE72), | ||
| 862 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE73), | ||
| 863 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE74), | ||
| 864 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE75), | ||
| 865 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE76), | ||
| 866 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE77), | ||
| 867 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE78), | ||
| 868 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE79), | ||
| 869 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE80), | ||
| 870 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE81), | ||
| 871 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE82), | ||
| 872 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE83), | ||
| 873 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE84), | ||
| 874 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE85), | ||
| 875 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE86), | ||
| 876 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE87), | ||
| 877 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE88), | ||
| 878 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE89), | ||
| 879 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE90), | ||
| 880 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE91), | ||
| 881 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE92), | ||
| 882 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE93), | ||
| 883 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE94), | ||
| 884 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE95), | ||
| 885 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE96), | ||
| 886 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE97), | ||
| 887 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE98), | ||
| 888 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE99), | ||
| 889 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE100), | ||
| 890 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE101), | ||
| 891 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE102), | ||
| 892 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE103), | ||
| 893 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE104), | ||
| 894 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE105), | ||
| 895 | IMX_PINCTRL_PIN(MX35_PAD_RTCK), | ||
| 896 | IMX_PINCTRL_PIN(MX35_PAD_TCK), | ||
| 897 | IMX_PINCTRL_PIN(MX35_PAD_TMS), | ||
| 898 | IMX_PINCTRL_PIN(MX35_PAD_TDI), | ||
| 899 | IMX_PINCTRL_PIN(MX35_PAD_TDO), | ||
| 900 | IMX_PINCTRL_PIN(MX35_PAD_TRSTB), | ||
| 901 | IMX_PINCTRL_PIN(MX35_PAD_DE_B), | ||
| 902 | IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD), | ||
| 903 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE106), | ||
| 904 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE107), | ||
| 905 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE108), | ||
| 906 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE109), | ||
| 907 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE110), | ||
| 908 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE111), | ||
| 909 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE112), | ||
| 910 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE113), | ||
| 911 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE114), | ||
| 912 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE115), | ||
| 913 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE116), | ||
| 914 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE117), | ||
| 915 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE118), | ||
| 916 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE119), | ||
| 917 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE120), | ||
| 918 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE121), | ||
| 919 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE122), | ||
| 920 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE123), | ||
| 921 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE124), | ||
| 922 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE125), | ||
| 923 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE126), | ||
| 924 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE127), | ||
| 925 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE128), | ||
| 926 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE129), | ||
| 927 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE130), | ||
| 928 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE131), | ||
| 929 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE132), | ||
| 930 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE133), | ||
| 931 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE134), | ||
| 932 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE135), | ||
| 933 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE136), | ||
| 934 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE137), | ||
| 935 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE138), | ||
| 936 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE139), | ||
| 937 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE140), | ||
| 938 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE141), | ||
| 939 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE142), | ||
| 940 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE143), | ||
| 941 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE144), | ||
| 942 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE145), | ||
| 943 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE146), | ||
| 944 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE147), | ||
| 945 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE148), | ||
| 946 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE149), | ||
| 947 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE150), | ||
| 948 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE151), | ||
| 949 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE152), | ||
| 950 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE153), | ||
| 951 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE154), | ||
| 952 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE155), | ||
| 953 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE156), | ||
| 954 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE157), | ||
| 955 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE158), | ||
| 956 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE159), | ||
| 957 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE160), | ||
| 958 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE161), | ||
| 959 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE162), | ||
| 960 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE163), | ||
| 961 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE164), | ||
| 962 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE165), | ||
| 963 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE166), | ||
| 964 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE167), | ||
| 965 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE168), | ||
| 966 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE169), | ||
| 967 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE170), | ||
| 968 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE171), | ||
| 969 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE172), | ||
| 970 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE173), | ||
| 971 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE174), | ||
| 972 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE175), | ||
| 973 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE176), | ||
| 974 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE177), | ||
| 975 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE178), | ||
| 976 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE179), | ||
| 977 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE180), | ||
| 978 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE181), | ||
| 979 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE182), | ||
| 980 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE183), | ||
| 981 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE184), | ||
| 982 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE185), | ||
| 983 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE186), | ||
| 984 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE187), | ||
| 985 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE188), | ||
| 986 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE189), | ||
| 987 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE190), | ||
| 988 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE191), | ||
| 989 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE192), | ||
| 990 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE193), | ||
| 991 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE194), | ||
| 992 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE195), | ||
| 993 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE196), | ||
| 994 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE197), | ||
| 995 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE198), | ||
| 996 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE199), | ||
| 997 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE200), | ||
| 998 | IMX_PINCTRL_PIN(MX35_PAD_RESERVE201), | ||
| 1551 | IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK), | 999 | IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK), |
| 1552 | IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), | 1000 | IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), |
| 1553 | }; | 1001 | }; |
| @@ -1555,8 +1003,6 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = { | |||
| 1555 | static struct imx_pinctrl_soc_info imx35_pinctrl_info = { | 1003 | static struct imx_pinctrl_soc_info imx35_pinctrl_info = { |
| 1556 | .pins = imx35_pinctrl_pads, | 1004 | .pins = imx35_pinctrl_pads, |
| 1557 | .npins = ARRAY_SIZE(imx35_pinctrl_pads), | 1005 | .npins = ARRAY_SIZE(imx35_pinctrl_pads), |
| 1558 | .pin_regs = imx35_pin_regs, | ||
| 1559 | .npin_regs = ARRAY_SIZE(imx35_pin_regs), | ||
| 1560 | }; | 1006 | }; |
| 1561 | 1007 | ||
| 1562 | static struct of_device_id imx35_pinctrl_of_match[] = { | 1008 | static struct of_device_id imx35_pinctrl_of_match[] = { |