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authorTomasz Figa <t.figa@samsung.com>2012-10-11 04:11:09 -0400
committerLinus Walleij <linus.walleij@linaro.org>2012-10-15 03:10:11 -0400
commit40ba6227aeb3712b0cea0c4f9c3e355cf801f4c4 (patch)
tree1c253f6caa545c065c0bfc3c31cbdcf128501016 /drivers/pinctrl/pinctrl-exynos.h
parent62f14c0ef5d1bbd640b42a59f8f084f764a067c4 (diff)
pinctrl: samsung: Assing pin numbers dynamically
This patch modifies the pinctrl-samsung driver to assign numbers to pins dynamically instead of static enumerations. Thanks to this change the amount of code requried to support a SoC can be greatly reduced and the code made more readable. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-exynos.h')
-rw-r--r--drivers/pinctrl/pinctrl-exynos.h11
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 31d0a06174e4..178846739e80 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -165,11 +165,10 @@ enum exynos4210_gpio_xc_start {
165#define EXYNOS_EINT_MAX_PER_BANK 8 165#define EXYNOS_EINT_MAX_PER_BANK 8
166#define EXYNOS_EINT_NR_WKUP_EINT 166#define EXYNOS_EINT_NR_WKUP_EINT
167 167
168#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id) \ 168#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
169 { \ 169 { \
170 .pctl_offset = reg, \ 170 .pctl_offset = reg, \
171 .pin_base = (__gpio##_START), \ 171 .nr_pins = pins, \
172 .nr_pins = (__gpio##_NR), \
173 .func_width = 4, \ 172 .func_width = 4, \
174 .pud_width = 2, \ 173 .pud_width = 2, \
175 .drv_width = 2, \ 174 .drv_width = 2, \
@@ -179,18 +178,16 @@ enum exynos4210_gpio_xc_start {
179 .name = id \ 178 .name = id \
180 } 179 }
181 180
182#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id) \ 181#define EXYNOS_PIN_BANK_EINTG(pins, reg, id) \
183 { \ 182 { \
184 .pctl_offset = reg, \ 183 .pctl_offset = reg, \
185 .pin_base = (__gpio##_START), \ 184 .nr_pins = pins, \
186 .nr_pins = (__gpio##_NR), \
187 .func_width = 4, \ 185 .func_width = 4, \
188 .pud_width = 2, \ 186 .pud_width = 2, \
189 .drv_width = 2, \ 187 .drv_width = 2, \
190 .conpdn_width = 2, \ 188 .conpdn_width = 2, \
191 .pudpdn_width = 2, \ 189 .pudpdn_width = 2, \
192 .eint_type = EINT_TYPE_GPIO, \ 190 .eint_type = EINT_TYPE_GPIO, \
193 .irq_base = (__gpio##_IRQ), \
194 .name = id \ 191 .name = id \
195 } 192 }
196 193