Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
 "This is a rather large set of patches for device drivers that for one
  reason or another the subsystem maintainer preferred to get merged
  through the arm-soc tree.  There are both new drivers as well as
  existing drivers that are getting converted from platform-specific
  code into standalone drivers using the appropriate subsystem specific
  interfaces.

  In particular, we can now have pinctrl, clk, clksource and irqchip
  drivers in one file per driver, without the need to call into platform
  specific interface, or to get called from platform specific code, as
  long as all information about the hardware is provided through a
  device tree.

  Most of the drivers we touch this time are for clocksource.  Since now
  most of them are part of drivers/clocksource, I expect that we won't
  have to touch these again from arm-soc and can let the clocksource
  maintainers take care of these in the future.

  Another larger part of this series is specific to the exynos platform,
  which is seeing some significant effort in upstreaming and
  modernization of its device drivers this time around, which
  unfortunately is also the cause for the churn and a lot of the merge
  conflicts.

  There is one new subsystem that gets merged as part of this series:
  the reset controller interface, which is a very simple interface for
  taking devices on the SoC out of reset or back into reset.  Patches to
  use this interface on i.MX follow later in this merge window, and we
  are going to have other platforms (at least tegra and sirf) get
  converted in 3.11.  This will let us get rid of platform specific
  callbacks in a number of platform independent device drivers."

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
  irqchip: s3c24xx: add missing __init annotations
  ARM: dts: Disable the RTC by default on exynos5
  clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
  ARM: exynos: restore mach/regs-clock.h for exynos5
  clocksource: exynos_mct: fix build error on non-DT
  pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
  irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
  reset: NULL deref on allocation failure
  reset: Add reset controller API
  dt: describe base reset signal binding
  ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
  ARM: EXYNOS: Enable PMUs for exynos4
  irqchip: exynos-combiner: Correct combined IRQs for exynos4
  irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: tegra: fix enum tegra114_clk to match binding
  ...

1 files changed, 108 insertions, 0 deletions

diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index ec1567842a7e..ac742817ebce 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -700,3 +700,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .label          = "exynos4x12-gpio-ctrl3",
         },
 };
+
+/* pin banks of exynos5250 pin-controller 0 */
+static struct samsung_pin_bank exynos5250_pin_banks0[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+        EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
+        EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
+        EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
+        EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
+        EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
+        EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
+        EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
+        EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
+        EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5250 pin-controller 1 */
+static struct samsung_pin_bank exynos5250_pin_banks1[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
+        EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
+        EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
+        EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
+};
+
+/* pin banks of exynos5250 pin-controller 2 */
+static struct samsung_pin_bank exynos5250_pin_banks2[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
+        EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
+};
+
+/* pin banks of exynos5250 pin-controller 3 */
+static struct samsung_pin_bank exynos5250_pin_banks3[] = {
+        EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
+        {
+                /* pin-controller instance 0 data */
+                .pin_banks      = exynos5250_pin_banks0,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
+                .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
+                .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .eint_wkup_init = exynos_eint_wkup_init,
+                .label          = "exynos5250-gpio-ctrl0",
+        }, {
+                /* pin-controller instance 1 data */
+                .pin_banks      = exynos5250_pin_banks1,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos5250-gpio-ctrl1",
+        }, {
+                /* pin-controller instance 2 data */
+                .pin_banks      = exynos5250_pin_banks2,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos5250-gpio-ctrl2",
+        }, {
+                /* pin-controller instance 3 data */
+                .pin_banks      = exynos5250_pin_banks3,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos5250-gpio-ctrl3",
+        },
+};