diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2014-09-03 07:37:38 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2014-09-04 04:05:28 -0400 |
commit | edad3b2a57082f6166b4f13445f70e8d3fc415fb (patch) | |
tree | bd2b9426da58f1775b638b7458a637d5f5e8b129 /drivers/pinctrl/freescale/pinctrl-imx27.c | |
parent | 03e9f0cac5da6af85758276cb4624caf5911f2b9 (diff) |
pinctrl: imx/mxs: move freescale drivers to subdir
This moves all the Freescale-related drivers (i.MX and MXS) to
its own subdirectory to clear the view.
Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Anson Huang <b20788@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Denis Carikli <denis@eukrea.com>
Cc: Markus Pargmann <mpa@pengutronix.de>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/freescale/pinctrl-imx27.c')
-rw-r--r-- | drivers/pinctrl/freescale/pinctrl-imx27.c | 425 |
1 files changed, 425 insertions, 0 deletions
diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c new file mode 100644 index 000000000000..945eccadea74 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c | |||
@@ -0,0 +1,425 @@ | |||
1 | /* | ||
2 | * imx27 pinctrl driver based on imx pinmux core | ||
3 | * | ||
4 | * Copyright (C) 2013 Pengutronix | ||
5 | * | ||
6 | * Author: Markus Pargmann <mpa@pengutronix.de> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | */ | ||
13 | |||
14 | #include <linux/err.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/of.h> | ||
19 | #include <linux/of_device.h> | ||
20 | #include <linux/pinctrl/pinctrl.h> | ||
21 | |||
22 | #include "pinctrl-imx1.h" | ||
23 | |||
24 | #define PAD_ID(port, pin) (port*32 + pin) | ||
25 | #define PA 0 | ||
26 | #define PB 1 | ||
27 | #define PC 2 | ||
28 | #define PD 3 | ||
29 | #define PE 4 | ||
30 | #define PF 5 | ||
31 | |||
32 | enum imx27_pads { | ||
33 | MX27_PAD_USBH2_CLK = PAD_ID(PA, 0), | ||
34 | MX27_PAD_USBH2_DIR = PAD_ID(PA, 1), | ||
35 | MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2), | ||
36 | MX27_PAD_USBH2_NXT = PAD_ID(PA, 3), | ||
37 | MX27_PAD_USBH2_STP = PAD_ID(PA, 4), | ||
38 | MX27_PAD_LSCLK = PAD_ID(PA, 5), | ||
39 | MX27_PAD_LD0 = PAD_ID(PA, 6), | ||
40 | MX27_PAD_LD1 = PAD_ID(PA, 7), | ||
41 | MX27_PAD_LD2 = PAD_ID(PA, 8), | ||
42 | MX27_PAD_LD3 = PAD_ID(PA, 9), | ||
43 | MX27_PAD_LD4 = PAD_ID(PA, 10), | ||
44 | MX27_PAD_LD5 = PAD_ID(PA, 11), | ||
45 | MX27_PAD_LD6 = PAD_ID(PA, 12), | ||
46 | MX27_PAD_LD7 = PAD_ID(PA, 13), | ||
47 | MX27_PAD_LD8 = PAD_ID(PA, 14), | ||
48 | MX27_PAD_LD9 = PAD_ID(PA, 15), | ||
49 | MX27_PAD_LD10 = PAD_ID(PA, 16), | ||
50 | MX27_PAD_LD11 = PAD_ID(PA, 17), | ||
51 | MX27_PAD_LD12 = PAD_ID(PA, 18), | ||
52 | MX27_PAD_LD13 = PAD_ID(PA, 19), | ||
53 | MX27_PAD_LD14 = PAD_ID(PA, 20), | ||
54 | MX27_PAD_LD15 = PAD_ID(PA, 21), | ||
55 | MX27_PAD_LD16 = PAD_ID(PA, 22), | ||
56 | MX27_PAD_LD17 = PAD_ID(PA, 23), | ||
57 | MX27_PAD_REV = PAD_ID(PA, 24), | ||
58 | MX27_PAD_CLS = PAD_ID(PA, 25), | ||
59 | MX27_PAD_PS = PAD_ID(PA, 26), | ||
60 | MX27_PAD_SPL_SPR = PAD_ID(PA, 27), | ||
61 | MX27_PAD_HSYNC = PAD_ID(PA, 28), | ||
62 | MX27_PAD_VSYNC = PAD_ID(PA, 29), | ||
63 | MX27_PAD_CONTRAST = PAD_ID(PA, 30), | ||
64 | MX27_PAD_OE_ACD = PAD_ID(PA, 31), | ||
65 | |||
66 | MX27_PAD_SD2_D0 = PAD_ID(PB, 4), | ||
67 | MX27_PAD_SD2_D1 = PAD_ID(PB, 5), | ||
68 | MX27_PAD_SD2_D2 = PAD_ID(PB, 6), | ||
69 | MX27_PAD_SD2_D3 = PAD_ID(PB, 7), | ||
70 | MX27_PAD_SD2_CMD = PAD_ID(PB, 8), | ||
71 | MX27_PAD_SD2_CLK = PAD_ID(PB, 9), | ||
72 | MX27_PAD_CSI_D0 = PAD_ID(PB, 10), | ||
73 | MX27_PAD_CSI_D1 = PAD_ID(PB, 11), | ||
74 | MX27_PAD_CSI_D2 = PAD_ID(PB, 12), | ||
75 | MX27_PAD_CSI_D3 = PAD_ID(PB, 13), | ||
76 | MX27_PAD_CSI_D4 = PAD_ID(PB, 14), | ||
77 | MX27_PAD_CSI_MCLK = PAD_ID(PB, 15), | ||
78 | MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16), | ||
79 | MX27_PAD_CSI_D5 = PAD_ID(PB, 17), | ||
80 | MX27_PAD_CSI_D6 = PAD_ID(PB, 18), | ||
81 | MX27_PAD_CSI_D7 = PAD_ID(PB, 19), | ||
82 | MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20), | ||
83 | MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21), | ||
84 | MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22), | ||
85 | MX27_PAD_USB_PWR = PAD_ID(PB, 23), | ||
86 | MX27_PAD_USB_OC_B = PAD_ID(PB, 24), | ||
87 | MX27_PAD_USBH1_RCV = PAD_ID(PB, 25), | ||
88 | MX27_PAD_USBH1_FS = PAD_ID(PB, 26), | ||
89 | MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27), | ||
90 | MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28), | ||
91 | MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29), | ||
92 | MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), | ||
93 | MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), | ||
94 | |||
95 | MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), | ||
96 | MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), | ||
97 | MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), | ||
98 | MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8), | ||
99 | MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9), | ||
100 | MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10), | ||
101 | MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11), | ||
102 | MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12), | ||
103 | MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13), | ||
104 | MX27_PAD_TOUT = PAD_ID(PC, 14), | ||
105 | MX27_PAD_TIN = PAD_ID(PC, 15), | ||
106 | MX27_PAD_SSI4_FS = PAD_ID(PC, 16), | ||
107 | MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17), | ||
108 | MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18), | ||
109 | MX27_PAD_SSI4_CLK = PAD_ID(PC, 19), | ||
110 | MX27_PAD_SSI1_FS = PAD_ID(PC, 20), | ||
111 | MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21), | ||
112 | MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22), | ||
113 | MX27_PAD_SSI1_CLK = PAD_ID(PC, 23), | ||
114 | MX27_PAD_SSI2_FS = PAD_ID(PC, 24), | ||
115 | MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25), | ||
116 | MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26), | ||
117 | MX27_PAD_SSI2_CLK = PAD_ID(PC, 27), | ||
118 | MX27_PAD_SSI3_FS = PAD_ID(PC, 28), | ||
119 | MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29), | ||
120 | MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30), | ||
121 | MX27_PAD_SSI3_CLK = PAD_ID(PC, 31), | ||
122 | |||
123 | MX27_PAD_SD3_CMD = PAD_ID(PD, 0), | ||
124 | MX27_PAD_SD3_CLK = PAD_ID(PD, 1), | ||
125 | MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2), | ||
126 | MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3), | ||
127 | MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4), | ||
128 | MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5), | ||
129 | MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6), | ||
130 | MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7), | ||
131 | MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8), | ||
132 | MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9), | ||
133 | MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10), | ||
134 | MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11), | ||
135 | MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12), | ||
136 | MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13), | ||
137 | MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14), | ||
138 | MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15), | ||
139 | MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16), | ||
140 | MX27_PAD_I2C_DATA = PAD_ID(PD, 17), | ||
141 | MX27_PAD_I2C_CLK = PAD_ID(PD, 18), | ||
142 | MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19), | ||
143 | MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20), | ||
144 | MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21), | ||
145 | MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22), | ||
146 | MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23), | ||
147 | MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24), | ||
148 | MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25), | ||
149 | MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26), | ||
150 | MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27), | ||
151 | MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28), | ||
152 | MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29), | ||
153 | MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30), | ||
154 | MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31), | ||
155 | |||
156 | MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0), | ||
157 | MX27_PAD_USBOTG_STP = PAD_ID(PE, 1), | ||
158 | MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2), | ||
159 | MX27_PAD_UART2_CTS = PAD_ID(PE, 3), | ||
160 | MX27_PAD_UART2_RTS = PAD_ID(PE, 4), | ||
161 | MX27_PAD_PWMO = PAD_ID(PE, 5), | ||
162 | MX27_PAD_UART2_TXD = PAD_ID(PE, 6), | ||
163 | MX27_PAD_UART2_RXD = PAD_ID(PE, 7), | ||
164 | MX27_PAD_UART3_TXD = PAD_ID(PE, 8), | ||
165 | MX27_PAD_UART3_RXD = PAD_ID(PE, 9), | ||
166 | MX27_PAD_UART3_CTS = PAD_ID(PE, 10), | ||
167 | MX27_PAD_UART3_RTS = PAD_ID(PE, 11), | ||
168 | MX27_PAD_UART1_TXD = PAD_ID(PE, 12), | ||
169 | MX27_PAD_UART1_RXD = PAD_ID(PE, 13), | ||
170 | MX27_PAD_UART1_CTS = PAD_ID(PE, 14), | ||
171 | MX27_PAD_UART1_RTS = PAD_ID(PE, 15), | ||
172 | MX27_PAD_RTCK = PAD_ID(PE, 16), | ||
173 | MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17), | ||
174 | MX27_PAD_SD1_D0 = PAD_ID(PE, 18), | ||
175 | MX27_PAD_SD1_D1 = PAD_ID(PE, 19), | ||
176 | MX27_PAD_SD1_D2 = PAD_ID(PE, 20), | ||
177 | MX27_PAD_SD1_D3 = PAD_ID(PE, 21), | ||
178 | MX27_PAD_SD1_CMD = PAD_ID(PE, 22), | ||
179 | MX27_PAD_SD1_CLK = PAD_ID(PE, 23), | ||
180 | MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), | ||
181 | MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), | ||
182 | |||
183 | MX27_PAD_NFRB = PAD_ID(PF, 0), | ||
184 | MX27_PAD_NFCLE = PAD_ID(PF, 1), | ||
185 | MX27_PAD_NFWP_B = PAD_ID(PF, 2), | ||
186 | MX27_PAD_NFCE_B = PAD_ID(PF, 3), | ||
187 | MX27_PAD_NFALE = PAD_ID(PF, 4), | ||
188 | MX27_PAD_NFRE_B = PAD_ID(PF, 5), | ||
189 | MX27_PAD_NFWE_B = PAD_ID(PF, 6), | ||
190 | MX27_PAD_PC_POE = PAD_ID(PF, 7), | ||
191 | MX27_PAD_PC_RW_B = PAD_ID(PF, 8), | ||
192 | MX27_PAD_IOIS16 = PAD_ID(PF, 9), | ||
193 | MX27_PAD_PC_RST = PAD_ID(PF, 10), | ||
194 | MX27_PAD_PC_BVD2 = PAD_ID(PF, 11), | ||
195 | MX27_PAD_PC_BVD1 = PAD_ID(PF, 12), | ||
196 | MX27_PAD_PC_VS2 = PAD_ID(PF, 13), | ||
197 | MX27_PAD_PC_VS1 = PAD_ID(PF, 14), | ||
198 | MX27_PAD_CLKO = PAD_ID(PF, 15), | ||
199 | MX27_PAD_PC_PWRON = PAD_ID(PF, 16), | ||
200 | MX27_PAD_PC_READY = PAD_ID(PF, 17), | ||
201 | MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18), | ||
202 | MX27_PAD_PC_CD2_B = PAD_ID(PF, 19), | ||
203 | MX27_PAD_PC_CD1_B = PAD_ID(PF, 20), | ||
204 | MX27_PAD_CS4_B = PAD_ID(PF, 21), | ||
205 | MX27_PAD_CS5_B = PAD_ID(PF, 22), | ||
206 | MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), | ||
207 | }; | ||
208 | |||
209 | /* Pad names for the pinmux subsystem */ | ||
210 | static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { | ||
211 | IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK), | ||
212 | IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR), | ||
213 | IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7), | ||
214 | IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT), | ||
215 | IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP), | ||
216 | IMX_PINCTRL_PIN(MX27_PAD_LSCLK), | ||
217 | IMX_PINCTRL_PIN(MX27_PAD_LD0), | ||
218 | IMX_PINCTRL_PIN(MX27_PAD_LD1), | ||
219 | IMX_PINCTRL_PIN(MX27_PAD_LD2), | ||
220 | IMX_PINCTRL_PIN(MX27_PAD_LD3), | ||
221 | IMX_PINCTRL_PIN(MX27_PAD_LD4), | ||
222 | IMX_PINCTRL_PIN(MX27_PAD_LD5), | ||
223 | IMX_PINCTRL_PIN(MX27_PAD_LD6), | ||
224 | IMX_PINCTRL_PIN(MX27_PAD_LD7), | ||
225 | IMX_PINCTRL_PIN(MX27_PAD_LD8), | ||
226 | IMX_PINCTRL_PIN(MX27_PAD_LD9), | ||
227 | IMX_PINCTRL_PIN(MX27_PAD_LD10), | ||
228 | IMX_PINCTRL_PIN(MX27_PAD_LD11), | ||
229 | IMX_PINCTRL_PIN(MX27_PAD_LD12), | ||
230 | IMX_PINCTRL_PIN(MX27_PAD_LD13), | ||
231 | IMX_PINCTRL_PIN(MX27_PAD_LD14), | ||
232 | IMX_PINCTRL_PIN(MX27_PAD_LD15), | ||
233 | IMX_PINCTRL_PIN(MX27_PAD_LD16), | ||
234 | IMX_PINCTRL_PIN(MX27_PAD_LD17), | ||
235 | IMX_PINCTRL_PIN(MX27_PAD_REV), | ||
236 | IMX_PINCTRL_PIN(MX27_PAD_CLS), | ||
237 | IMX_PINCTRL_PIN(MX27_PAD_PS), | ||
238 | IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR), | ||
239 | IMX_PINCTRL_PIN(MX27_PAD_HSYNC), | ||
240 | IMX_PINCTRL_PIN(MX27_PAD_VSYNC), | ||
241 | IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), | ||
242 | IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), | ||
243 | |||
244 | IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), | ||
245 | IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), | ||
246 | IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), | ||
247 | IMX_PINCTRL_PIN(MX27_PAD_SD2_D3), | ||
248 | IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD), | ||
249 | IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK), | ||
250 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D0), | ||
251 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D1), | ||
252 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D2), | ||
253 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D3), | ||
254 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D4), | ||
255 | IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK), | ||
256 | IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK), | ||
257 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D5), | ||
258 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D6), | ||
259 | IMX_PINCTRL_PIN(MX27_PAD_CSI_D7), | ||
260 | IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC), | ||
261 | IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC), | ||
262 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP), | ||
263 | IMX_PINCTRL_PIN(MX27_PAD_USB_PWR), | ||
264 | IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B), | ||
265 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV), | ||
266 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS), | ||
267 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B), | ||
268 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM), | ||
269 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP), | ||
270 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), | ||
271 | IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), | ||
272 | |||
273 | IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), | ||
274 | IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), | ||
275 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), | ||
276 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6), | ||
277 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0), | ||
278 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2), | ||
279 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1), | ||
280 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4), | ||
281 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3), | ||
282 | IMX_PINCTRL_PIN(MX27_PAD_TOUT), | ||
283 | IMX_PINCTRL_PIN(MX27_PAD_TIN), | ||
284 | IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS), | ||
285 | IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT), | ||
286 | IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT), | ||
287 | IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK), | ||
288 | IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS), | ||
289 | IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT), | ||
290 | IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT), | ||
291 | IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK), | ||
292 | IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS), | ||
293 | IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT), | ||
294 | IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT), | ||
295 | IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK), | ||
296 | IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS), | ||
297 | IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT), | ||
298 | IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT), | ||
299 | IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK), | ||
300 | |||
301 | IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD), | ||
302 | IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK), | ||
303 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0), | ||
304 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1), | ||
305 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2), | ||
306 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3), | ||
307 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4), | ||
308 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5), | ||
309 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6), | ||
310 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7), | ||
311 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8), | ||
312 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9), | ||
313 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10), | ||
314 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11), | ||
315 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12), | ||
316 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13), | ||
317 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14), | ||
318 | IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA), | ||
319 | IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK), | ||
320 | IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2), | ||
321 | IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1), | ||
322 | IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0), | ||
323 | IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK), | ||
324 | IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO), | ||
325 | IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI), | ||
326 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY), | ||
327 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2), | ||
328 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1), | ||
329 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0), | ||
330 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK), | ||
331 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO), | ||
332 | IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI), | ||
333 | |||
334 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT), | ||
335 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP), | ||
336 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR), | ||
337 | IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS), | ||
338 | IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS), | ||
339 | IMX_PINCTRL_PIN(MX27_PAD_PWMO), | ||
340 | IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD), | ||
341 | IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD), | ||
342 | IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD), | ||
343 | IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD), | ||
344 | IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS), | ||
345 | IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS), | ||
346 | IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD), | ||
347 | IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD), | ||
348 | IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS), | ||
349 | IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS), | ||
350 | IMX_PINCTRL_PIN(MX27_PAD_RTCK), | ||
351 | IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B), | ||
352 | IMX_PINCTRL_PIN(MX27_PAD_SD1_D0), | ||
353 | IMX_PINCTRL_PIN(MX27_PAD_SD1_D1), | ||
354 | IMX_PINCTRL_PIN(MX27_PAD_SD1_D2), | ||
355 | IMX_PINCTRL_PIN(MX27_PAD_SD1_D3), | ||
356 | IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD), | ||
357 | IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), | ||
358 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), | ||
359 | IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), | ||
360 | |||
361 | IMX_PINCTRL_PIN(MX27_PAD_NFRB), | ||
362 | IMX_PINCTRL_PIN(MX27_PAD_NFCLE), | ||
363 | IMX_PINCTRL_PIN(MX27_PAD_NFWP_B), | ||
364 | IMX_PINCTRL_PIN(MX27_PAD_NFCE_B), | ||
365 | IMX_PINCTRL_PIN(MX27_PAD_NFALE), | ||
366 | IMX_PINCTRL_PIN(MX27_PAD_NFRE_B), | ||
367 | IMX_PINCTRL_PIN(MX27_PAD_NFWE_B), | ||
368 | IMX_PINCTRL_PIN(MX27_PAD_PC_POE), | ||
369 | IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B), | ||
370 | IMX_PINCTRL_PIN(MX27_PAD_IOIS16), | ||
371 | IMX_PINCTRL_PIN(MX27_PAD_PC_RST), | ||
372 | IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2), | ||
373 | IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1), | ||
374 | IMX_PINCTRL_PIN(MX27_PAD_PC_VS2), | ||
375 | IMX_PINCTRL_PIN(MX27_PAD_PC_VS1), | ||
376 | IMX_PINCTRL_PIN(MX27_PAD_CLKO), | ||
377 | IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON), | ||
378 | IMX_PINCTRL_PIN(MX27_PAD_PC_READY), | ||
379 | IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B), | ||
380 | IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B), | ||
381 | IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B), | ||
382 | IMX_PINCTRL_PIN(MX27_PAD_CS4_B), | ||
383 | IMX_PINCTRL_PIN(MX27_PAD_CS5_B), | ||
384 | IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), | ||
385 | }; | ||
386 | |||
387 | static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { | ||
388 | .pins = imx27_pinctrl_pads, | ||
389 | .npins = ARRAY_SIZE(imx27_pinctrl_pads), | ||
390 | }; | ||
391 | |||
392 | static const struct of_device_id imx27_pinctrl_of_match[] = { | ||
393 | { .compatible = "fsl,imx27-iomuxc", }, | ||
394 | { /* sentinel */ } | ||
395 | }; | ||
396 | |||
397 | static int imx27_pinctrl_probe(struct platform_device *pdev) | ||
398 | { | ||
399 | return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); | ||
400 | } | ||
401 | |||
402 | static struct platform_driver imx27_pinctrl_driver = { | ||
403 | .driver = { | ||
404 | .name = "imx27-pinctrl", | ||
405 | .owner = THIS_MODULE, | ||
406 | .of_match_table = of_match_ptr(imx27_pinctrl_of_match), | ||
407 | }, | ||
408 | .probe = imx27_pinctrl_probe, | ||
409 | .remove = imx1_pinctrl_core_remove, | ||
410 | }; | ||
411 | |||
412 | static int __init imx27_pinctrl_init(void) | ||
413 | { | ||
414 | return platform_driver_register(&imx27_pinctrl_driver); | ||
415 | } | ||
416 | arch_initcall(imx27_pinctrl_init); | ||
417 | |||
418 | static void __exit imx27_pinctrl_exit(void) | ||
419 | { | ||
420 | platform_driver_unregister(&imx27_pinctrl_driver); | ||
421 | } | ||
422 | module_exit(imx27_pinctrl_exit); | ||
423 | MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>"); | ||
424 | MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver"); | ||
425 | MODULE_LICENSE("GPL v2"); | ||