diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-18 07:37:20 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-02-04 09:32:24 -0500 |
commit | 76346a4eabf85a44dc425c0197ba46a8884e6090 (patch) | |
tree | adc6224fe2626cdee005cd7b6589539d2150b2c8 /drivers/pcmcia/sa1100_nanoengine.c | |
parent | 7cf779cb8ddeef797a3a265889c7f088d42a12f7 (diff) |
PCMCIA: sa11x0: nanoengine: convert reset handling to use GPIO subsystem
Rather than accessing GPSR and GPCR directly, use the GPIO subsystem
instead.
Acked-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/pcmcia/sa1100_nanoengine.c')
-rw-r--r-- | drivers/pcmcia/sa1100_nanoengine.c | 38 |
1 files changed, 16 insertions, 22 deletions
diff --git a/drivers/pcmcia/sa1100_nanoengine.c b/drivers/pcmcia/sa1100_nanoengine.c index b19b8161395b..cb43e39aef3f 100644 --- a/drivers/pcmcia/sa1100_nanoengine.c +++ b/drivers/pcmcia/sa1100_nanoengine.c | |||
@@ -19,6 +19,7 @@ | |||
19 | */ | 19 | */ |
20 | #include <linux/device.h> | 20 | #include <linux/device.h> |
21 | #include <linux/errno.h> | 21 | #include <linux/errno.h> |
22 | #include <linux/gpio.h> | ||
22 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
23 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
24 | #include <linux/init.h> | 25 | #include <linux/init.h> |
@@ -37,19 +38,18 @@ | |||
37 | struct nanoengine_pins { | 38 | struct nanoengine_pins { |
38 | unsigned output_pins; | 39 | unsigned output_pins; |
39 | unsigned clear_outputs; | 40 | unsigned clear_outputs; |
41 | int gpio_rst; | ||
40 | int gpio_cd; | 42 | int gpio_cd; |
41 | int gpio_rdy; | 43 | int gpio_rdy; |
42 | }; | 44 | }; |
43 | 45 | ||
44 | static struct nanoengine_pins nano_skts[] = { | 46 | static struct nanoengine_pins nano_skts[] = { |
45 | { | 47 | { |
46 | .output_pins = GPIO_PC_RESET0, | 48 | .gpio_rst = GPIO_PC_RESET0, |
47 | .clear_outputs = GPIO_PC_RESET0, | ||
48 | .gpio_cd = GPIO_PC_CD0, | 49 | .gpio_cd = GPIO_PC_CD0, |
49 | .gpio_rdy = GPIO_PC_READY0, | 50 | .gpio_rdy = GPIO_PC_READY0, |
50 | }, { | 51 | }, { |
51 | .output_pins = GPIO_PC_RESET1, | 52 | .gpio_rst = GPIO_PC_RESET1, |
52 | .clear_outputs = GPIO_PC_RESET1, | ||
53 | .gpio_cd = GPIO_PC_CD1, | 53 | .gpio_cd = GPIO_PC_CD1, |
54 | .gpio_rdy = GPIO_PC_READY1, | 54 | .gpio_rdy = GPIO_PC_READY1, |
55 | } | 55 | } |
@@ -60,12 +60,15 @@ unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts); | |||
60 | static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt) | 60 | static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt) |
61 | { | 61 | { |
62 | unsigned i = skt->nr; | 62 | unsigned i = skt->nr; |
63 | int ret; | ||
63 | 64 | ||
64 | if (i >= num_nano_pcmcia_sockets) | 65 | if (i >= num_nano_pcmcia_sockets) |
65 | return -ENXIO; | 66 | return -ENXIO; |
66 | 67 | ||
67 | GPDR |= nano_skts[i].output_pins; | 68 | ret = gpio_request_one(nano_skts[i].gpio_rst, GPIOF_OUT_INIT_LOW, |
68 | GPCR = nano_skts[i].clear_outputs; | 69 | i ? "PC RST1" : "PC RST0"); |
70 | if (ret) | ||
71 | return ret; | ||
69 | 72 | ||
70 | skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd; | 73 | skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd; |
71 | skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0"; | 74 | skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0"; |
@@ -75,30 +78,20 @@ static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt) | |||
75 | return 0; | 78 | return 0; |
76 | } | 79 | } |
77 | 80 | ||
81 | static void nanoengine_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) | ||
82 | { | ||
83 | gpio_free(nano_skts[skt->nr].gpio_rst); | ||
84 | } | ||
85 | |||
78 | static int nanoengine_pcmcia_configure_socket( | 86 | static int nanoengine_pcmcia_configure_socket( |
79 | struct soc_pcmcia_socket *skt, const socket_state_t *state) | 87 | struct soc_pcmcia_socket *skt, const socket_state_t *state) |
80 | { | 88 | { |
81 | unsigned reset; | ||
82 | unsigned i = skt->nr; | 89 | unsigned i = skt->nr; |
83 | 90 | ||
84 | if (i >= num_nano_pcmcia_sockets) | 91 | if (i >= num_nano_pcmcia_sockets) |
85 | return -ENXIO; | 92 | return -ENXIO; |
86 | 93 | ||
87 | switch (i) { | 94 | gpio_set_value(nano_skts[skt->nr].gpio_rst, !!(state->flags & SS_RESET)); |
88 | case 0: | ||
89 | reset = GPIO_PC_RESET0; | ||
90 | break; | ||
91 | case 1: | ||
92 | reset = GPIO_PC_RESET1; | ||
93 | break; | ||
94 | default: | ||
95 | return -ENXIO; | ||
96 | } | ||
97 | |||
98 | if (state->flags & SS_RESET) | ||
99 | GPSR = reset; | ||
100 | else | ||
101 | GPCR = reset; | ||
102 | 95 | ||
103 | return 0; | 96 | return 0; |
104 | } | 97 | } |
@@ -122,6 +115,7 @@ static struct pcmcia_low_level nanoengine_pcmcia_ops = { | |||
122 | .owner = THIS_MODULE, | 115 | .owner = THIS_MODULE, |
123 | 116 | ||
124 | .hw_init = nanoengine_pcmcia_hw_init, | 117 | .hw_init = nanoengine_pcmcia_hw_init, |
118 | .hw_shutdown = nanoengine_pcmcia_hw_shutdown, | ||
125 | 119 | ||
126 | .configure_socket = nanoengine_pcmcia_configure_socket, | 120 | .configure_socket = nanoengine_pcmcia_configure_socket, |
127 | .socket_state = nanoengine_pcmcia_socket_state, | 121 | .socket_state = nanoengine_pcmcia_socket_state, |