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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-03 19:24:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-03 19:24:35 -0400
commita9238741987386bb549d61572973c7e62b2a4145 (patch)
tree4e49f9c472f86b88cd569a088f7c0ac87ce8b78a /drivers/pci
parent40031da445fb4d269af9c7c445b2adf674f171e7 (diff)
parente89c33168aad32436da842ddda307dcc31c0c4e2 (diff)
Merge tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas: PCI device hotplug: - Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman) - Assign resources on per-host bridge basis (Yinghai Lu) MPS (Max Payload Size): - Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang) - Add warnings about unsafe MPS settings (Yijing Wang) - Simplify interface and messages (Bjorn Helgaas) SR-IOV: - Return -ENOSYS on non-SR-IOV devices (Stefan Assmann) - Update NumVFs register when disabling SR-IOV (Yijing Wang) Virtualization: - Add bus and slot reset support (Alex Williamson) - Fix ACS (Access Control Services) issues (Alex Williamson) Miscellaneous: - Simplify PCIe Capability accessors (Bjorn Helgaas) - Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott) - Disable decoding during BAR sizing only when necessary (Zoltan Kiss) - Delay enabling bridges until they're needed (Yinghai Lu) - Split Designware support into Synopsys and Exynos parts (Jingoo Han) - Convert class code to use dev_groups (Greg Kroah-Hartman) - Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon) - Fix bridge I/O window alignment (Bjorn Helgaas) - Add pci_wait_for_pending_transaction() (Casey Leedom) - Use devm_ioremap_resource() in Marvell driver (Tushar Behera) * tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits) PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available PCI: exynos: Add I/O access wrappers PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc() PCI: Remove pcie_cap_has_devctl() PCI: Support PCIe Capability Slot registers only for ports with slots PCI: Remove PCIe Capability version checks PCI: Allow PCIe Capability link-related register access for switches PCI: Add offsets of PCIe capability registers PCI: Tidy bitmasks and spacing of PCIe capability definitions PCI: Remove obsolete comment reference to pci_pcie_cap2() PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment PCI: Rename PCIe capability definitions to follow convention PCI: Warn if unsafe MPS settings detected PCI: Fix MPS peer-to-peer DMA comment syntax PCI: Disable decoding for BAR sizing only when it was actually enabled PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality PCI: Don't restrict MPS for slots below Root Ports PCI: Simplify MPS test for Downstream Port PCI: Remove unnecessary check for pcie_get_mps() failure ...
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/access.c26
-rw-r--r--drivers/pci/bus.c19
-rw-r--r--drivers/pci/host/Kconfig1
-rw-r--r--drivers/pci/host/Makefile3
-rw-r--r--drivers/pci/host/pci-exynos.c552
-rw-r--r--drivers/pci/host/pci-mvebu.c7
-rw-r--r--drivers/pci/host/pcie-designware.c1044
-rw-r--r--drivers/pci/host/pcie-designware.h65
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c1
-rw-r--r--drivers/pci/hotplug/pciehp.h1
-rw-r--r--drivers/pci/hotplug/pciehp_core.c12
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c31
-rw-r--r--drivers/pci/hotplug/pcihp_slot.c5
-rw-r--r--drivers/pci/iov.c23
-rw-r--r--drivers/pci/pci-driver.c43
-rw-r--r--drivers/pci/pci-sysfs.c32
-rw-r--r--drivers/pci/pci.c573
-rw-r--r--drivers/pci/pci.h2
-rw-r--r--drivers/pci/pcie/Kconfig2
-rw-r--r--drivers/pci/pcie/aer/aerdrv.c2
-rw-r--r--drivers/pci/pcie/aer/aerdrv.h1
-rw-r--r--drivers/pci/pcie/aer/aerdrv_core.c35
-rw-r--r--drivers/pci/probe.c80
-rw-r--r--drivers/pci/quirks.c147
-rw-r--r--drivers/pci/setup-bus.c176
25 files changed, 1806 insertions, 1077 deletions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 1cc23661f79b..0857ca981fae 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -475,37 +475,33 @@ static inline int pcie_cap_version(const struct pci_dev *dev)
475 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; 475 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
476} 476}
477 477
478static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
479{
480 return true;
481}
482
483static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev) 478static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
484{ 479{
485 int type = pci_pcie_type(dev); 480 int type = pci_pcie_type(dev);
486 481
487 return pcie_cap_version(dev) > 1 || 482 return type == PCI_EXP_TYPE_ENDPOINT ||
483 type == PCI_EXP_TYPE_LEG_END ||
488 type == PCI_EXP_TYPE_ROOT_PORT || 484 type == PCI_EXP_TYPE_ROOT_PORT ||
489 type == PCI_EXP_TYPE_ENDPOINT || 485 type == PCI_EXP_TYPE_UPSTREAM ||
490 type == PCI_EXP_TYPE_LEG_END; 486 type == PCI_EXP_TYPE_DOWNSTREAM ||
487 type == PCI_EXP_TYPE_PCI_BRIDGE ||
488 type == PCI_EXP_TYPE_PCIE_BRIDGE;
491} 489}
492 490
493static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) 491static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
494{ 492{
495 int type = pci_pcie_type(dev); 493 int type = pci_pcie_type(dev);
496 494
497 return pcie_cap_version(dev) > 1 || 495 return (type == PCI_EXP_TYPE_ROOT_PORT ||
498 type == PCI_EXP_TYPE_ROOT_PORT || 496 type == PCI_EXP_TYPE_DOWNSTREAM) &&
499 (type == PCI_EXP_TYPE_DOWNSTREAM && 497 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
500 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT);
501} 498}
502 499
503static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) 500static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
504{ 501{
505 int type = pci_pcie_type(dev); 502 int type = pci_pcie_type(dev);
506 503
507 return pcie_cap_version(dev) > 1 || 504 return type == PCI_EXP_TYPE_ROOT_PORT ||
508 type == PCI_EXP_TYPE_ROOT_PORT ||
509 type == PCI_EXP_TYPE_RC_EC; 505 type == PCI_EXP_TYPE_RC_EC;
510} 506}
511 507
@@ -520,7 +516,7 @@ static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
520 case PCI_EXP_DEVCAP: 516 case PCI_EXP_DEVCAP:
521 case PCI_EXP_DEVCTL: 517 case PCI_EXP_DEVCTL:
522 case PCI_EXP_DEVSTA: 518 case PCI_EXP_DEVSTA:
523 return pcie_cap_has_devctl(dev); 519 return true;
524 case PCI_EXP_LNKCAP: 520 case PCI_EXP_LNKCAP:
525 case PCI_EXP_LNKCTL: 521 case PCI_EXP_LNKCTL:
526 case PCI_EXP_LNKSTA: 522 case PCI_EXP_LNKSTA:
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index b1ff02ab4f13..fc1b74013743 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -216,24 +216,6 @@ void pci_bus_add_devices(const struct pci_bus *bus)
216 } 216 }
217} 217}
218 218
219void pci_enable_bridges(struct pci_bus *bus)
220{
221 struct pci_dev *dev;
222 int retval;
223
224 list_for_each_entry(dev, &bus->devices, bus_list) {
225 if (dev->subordinate) {
226 if (!pci_is_enabled(dev)) {
227 retval = pci_enable_device(dev);
228 if (retval)
229 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", retval);
230 pci_set_master(dev);
231 }
232 pci_enable_bridges(dev->subordinate);
233 }
234 }
235}
236
237/** pci_walk_bus - walk devices on/under bus, calling callback. 219/** pci_walk_bus - walk devices on/under bus, calling callback.
238 * @top bus whose devices should be walked 220 * @top bus whose devices should be walked
239 * @cb callback to be called for each device found 221 * @cb callback to be called for each device found
@@ -301,4 +283,3 @@ EXPORT_SYMBOL(pci_bus_put);
301EXPORT_SYMBOL(pci_bus_alloc_resource); 283EXPORT_SYMBOL(pci_bus_alloc_resource);
302EXPORT_SYMBOL_GPL(pci_bus_add_device); 284EXPORT_SYMBOL_GPL(pci_bus_add_device);
303EXPORT_SYMBOL(pci_bus_add_devices); 285EXPORT_SYMBOL(pci_bus_add_devices);
304EXPORT_SYMBOL(pci_enable_bridges);
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 1184ff6fe864..e5ba4eb4e5b3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -4,6 +4,7 @@ menu "PCI host controller drivers"
4config PCI_MVEBU 4config PCI_MVEBU
5 bool "Marvell EBU PCIe controller" 5 bool "Marvell EBU PCIe controller"
6 depends on ARCH_MVEBU || ARCH_KIRKWOOD 6 depends on ARCH_MVEBU || ARCH_KIRKWOOD
7 depends on OF
7 8
8config PCIE_DW 9config PCIE_DW
9 bool 10 bool
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 086d8500e849..ab79ccb5bbff 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,2 +1,3 @@
1obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
2obj-$(CONFIG_PCIE_DW) += pcie-designware.o 1obj-$(CONFIG_PCIE_DW) += pcie-designware.o
2obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
3obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
new file mode 100644
index 000000000000..94e096bb2d0a
--- /dev/null
+++ b/drivers/pci/host/pci-exynos.c
@@ -0,0 +1,552 @@
1/*
2 * PCIe host controller driver for Samsung EXYNOS SoCs
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of_gpio.h>
21#include <linux/pci.h>
22#include <linux/platform_device.h>
23#include <linux/resource.h>
24#include <linux/signal.h>
25#include <linux/types.h>
26
27#include "pcie-designware.h"
28
29#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
30
31struct exynos_pcie {
32 void __iomem *elbi_base;
33 void __iomem *phy_base;
34 void __iomem *block_base;
35 int reset_gpio;
36 struct clk *clk;
37 struct clk *bus_clk;
38 struct pcie_port pp;
39};
40
41/* PCIe ELBI registers */
42#define PCIE_IRQ_PULSE 0x000
43#define IRQ_INTA_ASSERT (0x1 << 0)
44#define IRQ_INTB_ASSERT (0x1 << 2)
45#define IRQ_INTC_ASSERT (0x1 << 4)
46#define IRQ_INTD_ASSERT (0x1 << 6)
47#define PCIE_IRQ_LEVEL 0x004
48#define PCIE_IRQ_SPECIAL 0x008
49#define PCIE_IRQ_EN_PULSE 0x00c
50#define PCIE_IRQ_EN_LEVEL 0x010
51#define PCIE_IRQ_EN_SPECIAL 0x014
52#define PCIE_PWR_RESET 0x018
53#define PCIE_CORE_RESET 0x01c
54#define PCIE_CORE_RESET_ENABLE (0x1 << 0)
55#define PCIE_STICKY_RESET 0x020
56#define PCIE_NONSTICKY_RESET 0x024
57#define PCIE_APP_INIT_RESET 0x028
58#define PCIE_APP_LTSSM_ENABLE 0x02c
59#define PCIE_ELBI_RDLH_LINKUP 0x064
60#define PCIE_ELBI_LTSSM_ENABLE 0x1
61#define PCIE_ELBI_SLV_AWMISC 0x11c
62#define PCIE_ELBI_SLV_ARMISC 0x120
63#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
64
65/* PCIe Purple registers */
66#define PCIE_PHY_GLOBAL_RESET 0x000
67#define PCIE_PHY_COMMON_RESET 0x004
68#define PCIE_PHY_CMN_REG 0x008
69#define PCIE_PHY_MAC_RESET 0x00c
70#define PCIE_PHY_PLL_LOCKED 0x010
71#define PCIE_PHY_TRSVREG_RESET 0x020
72#define PCIE_PHY_TRSV_RESET 0x024
73
74/* PCIe PHY registers */
75#define PCIE_PHY_IMPEDANCE 0x004
76#define PCIE_PHY_PLL_DIV_0 0x008
77#define PCIE_PHY_PLL_BIAS 0x00c
78#define PCIE_PHY_DCC_FEEDBACK 0x014
79#define PCIE_PHY_PLL_DIV_1 0x05c
80#define PCIE_PHY_TRSV0_EMP_LVL 0x084
81#define PCIE_PHY_TRSV0_DRV_LVL 0x088
82#define PCIE_PHY_TRSV0_RXCDR 0x0ac
83#define PCIE_PHY_TRSV0_LVCC 0x0dc
84#define PCIE_PHY_TRSV1_EMP_LVL 0x144
85#define PCIE_PHY_TRSV1_RXCDR 0x16c
86#define PCIE_PHY_TRSV1_LVCC 0x19c
87#define PCIE_PHY_TRSV2_EMP_LVL 0x204
88#define PCIE_PHY_TRSV2_RXCDR 0x22c
89#define PCIE_PHY_TRSV2_LVCC 0x25c
90#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
91#define PCIE_PHY_TRSV3_RXCDR 0x2ec
92#define PCIE_PHY_TRSV3_LVCC 0x31c
93
94static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
95{
96 writel(val, pcie->elbi_base + reg);
97}
98
99static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
100{
101 return readl(pcie->elbi_base + reg);
102}
103
104static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
105{
106 writel(val, pcie->phy_base + reg);
107}
108
109static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
110{
111 return readl(pcie->phy_base + reg);
112}
113
114static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
115{
116 writel(val, pcie->block_base + reg);
117}
118
119static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
120{
121 return readl(pcie->block_base + reg);
122}
123
124static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
125{
126 u32 val;
127 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
128
129 if (on) {
130 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
131 val |= PCIE_ELBI_SLV_DBI_ENABLE;
132 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
133 } else {
134 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
135 val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
136 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
137 }
138}
139
140static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
141{
142 u32 val;
143 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
144
145 if (on) {
146 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
147 val |= PCIE_ELBI_SLV_DBI_ENABLE;
148 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
149 } else {
150 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
151 val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
152 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
153 }
154}
155
156static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
157{
158 u32 val;
159 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
160
161 val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
162 val &= ~PCIE_CORE_RESET_ENABLE;
163 exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
164 exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
165 exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
166 exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
167}
168
169static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
170{
171 u32 val;
172 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
173
174 val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
175 val |= PCIE_CORE_RESET_ENABLE;
176
177 exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
178 exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
179 exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
180 exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
181 exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
182 exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
183}
184
185static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
186{
187 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
188
189 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
190 exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
191}
192
193static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
194{
195 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
196
197 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
198 exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
199 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
200 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
201 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
202 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
203}
204
205static void exynos_pcie_init_phy(struct pcie_port *pp)
206{
207 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
208
209 /* DCC feedback control off */
210 exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
211
212 /* set TX/RX impedance */
213 exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
214
215 /* set 50Mhz PHY clock */
216 exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
217 exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
218
219 /* set TX Differential output for lane 0 */
220 exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
221
222 /* set TX Pre-emphasis Level Control for lane 0 to minimum */
223 exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
224
225 /* set RX clock and data recovery bandwidth */
226 exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
227 exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
228 exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
229 exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
230 exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
231
232 /* change TX Pre-emphasis Level Control for lanes */
233 exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
234 exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
235 exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
236 exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
237
238 /* set LVCC */
239 exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
240 exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
241 exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
242 exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
243}
244
245static void exynos_pcie_assert_reset(struct pcie_port *pp)
246{
247 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
248
249 if (exynos_pcie->reset_gpio >= 0)
250 devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
251 GPIOF_OUT_INIT_HIGH, "RESET");
252 return;
253}
254
255static int exynos_pcie_establish_link(struct pcie_port *pp)
256{
257 u32 val;
258 int count = 0;
259 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
260
261 if (dw_pcie_link_up(pp)) {
262 dev_err(pp->dev, "Link already up\n");
263 return 0;
264 }
265
266 /* assert reset signals */
267 exynos_pcie_assert_core_reset(pp);
268 exynos_pcie_assert_phy_reset(pp);
269
270 /* de-assert phy reset */
271 exynos_pcie_deassert_phy_reset(pp);
272
273 /* initialize phy */
274 exynos_pcie_init_phy(pp);
275
276 /* pulse for common reset */
277 exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
278 udelay(500);
279 exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
280
281 /* de-assert core reset */
282 exynos_pcie_deassert_core_reset(pp);
283
284 /* setup root complex */
285 dw_pcie_setup_rc(pp);
286
287 /* assert reset signal */
288 exynos_pcie_assert_reset(pp);
289
290 /* assert LTSSM enable */
291 exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
292 PCIE_APP_LTSSM_ENABLE);
293
294 /* check if the link is up or not */
295 while (!dw_pcie_link_up(pp)) {
296 mdelay(100);
297 count++;
298 if (count == 10) {
299 while (exynos_phy_readl(exynos_pcie,
300 PCIE_PHY_PLL_LOCKED) == 0) {
301 val = exynos_blk_readl(exynos_pcie,
302 PCIE_PHY_PLL_LOCKED);
303 dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
304 }
305 dev_err(pp->dev, "PCIe Link Fail\n");
306 return -EINVAL;
307 }
308 }
309
310 dev_info(pp->dev, "Link up\n");
311
312 return 0;
313}
314
315static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
316{
317 u32 val;
318 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
319
320 val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
321 exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
322 return;
323}
324
325static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
326{
327 u32 val;
328 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
329
330 /* enable INTX interrupt */
331 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
332 IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
333 exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
334 return;
335}
336
337static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
338{
339 struct pcie_port *pp = arg;
340
341 exynos_pcie_clear_irq_pulse(pp);
342 return IRQ_HANDLED;
343}
344
345static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
346{
347 exynos_pcie_enable_irq_pulse(pp);
348 return;
349}
350
351static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
352 void __iomem *dbi_base, u32 *val)
353{
354 exynos_pcie_sideband_dbi_r_mode(pp, true);
355 *val = readl(dbi_base);
356 exynos_pcie_sideband_dbi_r_mode(pp, false);
357 return;
358}
359
360static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
361 u32 val, void __iomem *dbi_base)
362{
363 exynos_pcie_sideband_dbi_w_mode(pp, true);
364 writel(val, dbi_base);
365 exynos_pcie_sideband_dbi_w_mode(pp, false);
366 return;
367}
368
369static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
370 u32 *val)
371{
372 int ret;
373
374 exynos_pcie_sideband_dbi_r_mode(pp, true);
375 ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
376 exynos_pcie_sideband_dbi_r_mode(pp, false);
377 return ret;
378}
379
380static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
381 u32 val)
382{
383 int ret;
384
385 exynos_pcie_sideband_dbi_w_mode(pp, true);
386 ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
387 exynos_pcie_sideband_dbi_w_mode(pp, false);
388 return ret;
389}
390
391static int exynos_pcie_link_up(struct pcie_port *pp)
392{
393 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
394 u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
395
396 if (val == PCIE_ELBI_LTSSM_ENABLE)
397 return 1;
398
399 return 0;
400}
401
402static void exynos_pcie_host_init(struct pcie_port *pp)
403{
404 exynos_pcie_establish_link(pp);
405 exynos_pcie_enable_interrupts(pp);
406}
407
408static struct pcie_host_ops exynos_pcie_host_ops = {
409 .readl_rc = exynos_pcie_readl_rc,
410 .writel_rc = exynos_pcie_writel_rc,
411 .rd_own_conf = exynos_pcie_rd_own_conf,
412 .wr_own_conf = exynos_pcie_wr_own_conf,
413 .link_up = exynos_pcie_link_up,
414 .host_init = exynos_pcie_host_init,
415};
416
417static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
418{
419 int ret;
420
421 pp->irq = platform_get_irq(pdev, 1);
422 if (!pp->irq) {
423 dev_err(&pdev->dev, "failed to get irq\n");
424 return -ENODEV;
425 }
426 ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,
427 IRQF_SHARED, "exynos-pcie", pp);
428 if (ret) {
429 dev_err(&pdev->dev, "failed to request irq\n");
430 return ret;
431 }
432
433 pp->root_bus_nr = -1;
434 pp->ops = &exynos_pcie_host_ops;
435
436 spin_lock_init(&pp->conf_lock);
437 ret = dw_pcie_host_init(pp);
438 if (ret) {
439 dev_err(&pdev->dev, "failed to initialize host\n");
440 return ret;
441 }
442
443 return 0;
444}
445
446static int __init exynos_pcie_probe(struct platform_device *pdev)
447{
448 struct exynos_pcie *exynos_pcie;
449 struct pcie_port *pp;
450 struct device_node *np = pdev->dev.of_node;
451 struct resource *elbi_base;
452 struct resource *phy_base;
453 struct resource *block_base;
454 int ret;
455
456 exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
457 GFP_KERNEL);
458 if (!exynos_pcie) {
459 dev_err(&pdev->dev, "no memory for exynos pcie\n");
460 return -ENOMEM;
461 }
462
463 pp = &exynos_pcie->pp;
464
465 pp->dev = &pdev->dev;
466
467 exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
468
469 exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
470 if (IS_ERR(exynos_pcie->clk)) {
471 dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
472 return PTR_ERR(exynos_pcie->clk);
473 }
474 ret = clk_prepare_enable(exynos_pcie->clk);
475 if (ret)
476 return ret;
477
478 exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
479 if (IS_ERR(exynos_pcie->bus_clk)) {
480 dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
481 ret = PTR_ERR(exynos_pcie->bus_clk);
482 goto fail_clk;
483 }
484 ret = clk_prepare_enable(exynos_pcie->bus_clk);
485 if (ret)
486 goto fail_clk;
487
488 elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
490 if (IS_ERR(exynos_pcie->elbi_base))
491 return PTR_ERR(exynos_pcie->elbi_base);
492
493 phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
494 exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
495 if (IS_ERR(exynos_pcie->phy_base))
496 return PTR_ERR(exynos_pcie->phy_base);
497
498 block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
499 exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
500 if (IS_ERR(exynos_pcie->block_base))
501 return PTR_ERR(exynos_pcie->block_base);
502
503 ret = add_pcie_port(pp, pdev);
504 if (ret < 0)
505 goto fail_bus_clk;
506
507 platform_set_drvdata(pdev, exynos_pcie);
508 return 0;
509
510fail_bus_clk:
511 clk_disable_unprepare(exynos_pcie->bus_clk);
512fail_clk:
513 clk_disable_unprepare(exynos_pcie->clk);
514 return ret;
515}
516
517static int __exit exynos_pcie_remove(struct platform_device *pdev)
518{
519 struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
520
521 clk_disable_unprepare(exynos_pcie->bus_clk);
522 clk_disable_unprepare(exynos_pcie->clk);
523
524 return 0;
525}
526
527static const struct of_device_id exynos_pcie_of_match[] = {
528 { .compatible = "samsung,exynos5440-pcie", },
529 {},
530};
531MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);
532
533static struct platform_driver exynos_pcie_driver = {
534 .remove = __exit_p(exynos_pcie_remove),
535 .driver = {
536 .name = "exynos-pcie",
537 .owner = THIS_MODULE,
538 .of_match_table = of_match_ptr(exynos_pcie_of_match),
539 },
540};
541
542/* Exynos PCIe driver does not allow module unload */
543
544static int __init pcie_init(void)
545{
546 return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
547}
548subsys_initcall(pcie_init);
549
550MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
551MODULE_DESCRIPTION("Samsung PCIe host controller driver");
552MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 7bf3926aecc0..ce1543a584a3 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -725,9 +725,9 @@ mvebu_pcie_map_registers(struct platform_device *pdev,
725 725
726 ret = of_address_to_resource(np, 0, &regs); 726 ret = of_address_to_resource(np, 0, &regs);
727 if (ret) 727 if (ret)
728 return NULL; 728 return ERR_PTR(ret);
729 729
730 return devm_request_and_ioremap(&pdev->dev, &regs); 730 return devm_ioremap_resource(&pdev->dev, &regs);
731} 731}
732 732
733static int __init mvebu_pcie_probe(struct platform_device *pdev) 733static int __init mvebu_pcie_probe(struct platform_device *pdev)
@@ -817,9 +817,10 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
817 continue; 817 continue;
818 818
819 port->base = mvebu_pcie_map_registers(pdev, child, port); 819 port->base = mvebu_pcie_map_registers(pdev, child, port);
820 if (!port->base) { 820 if (IS_ERR(port->base)) {
821 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", 821 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
822 port->port, port->lane); 822 port->port, port->lane);
823 port->base = NULL;
823 continue; 824 continue;
824 } 825 }
825 826
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 26bdbda8ff90..c10e9ac9bbbc 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * PCIe host controller driver for Samsung EXYNOS SoCs 2 * Synopsys Designware PCIe host controller driver
3 * 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 5 * http://www.samsung.com
@@ -11,74 +11,28 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h> 14#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/module.h> 15#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_address.h> 16#include <linux/of_address.h>
23#include <linux/of_gpio.h>
24#include <linux/of_pci.h>
25#include <linux/pci.h> 17#include <linux/pci.h>
26#include <linux/pci_regs.h> 18#include <linux/pci_regs.h>
27#include <linux/platform_device.h>
28#include <linux/resource.h>
29#include <linux/signal.h>
30#include <linux/slab.h>
31#include <linux/types.h> 19#include <linux/types.h>
32 20
33struct pcie_port_info { 21#include "pcie-designware.h"
34 u32 cfg0_size;
35 u32 cfg1_size;
36 u32 io_size;
37 u32 mem_size;
38 phys_addr_t io_bus_addr;
39 phys_addr_t mem_bus_addr;
40};
41
42struct pcie_port {
43 struct device *dev;
44 u8 controller;
45 u8 root_bus_nr;
46 void __iomem *dbi_base;
47 void __iomem *elbi_base;
48 void __iomem *phy_base;
49 void __iomem *purple_base;
50 u64 cfg0_base;
51 void __iomem *va_cfg0_base;
52 u64 cfg1_base;
53 void __iomem *va_cfg1_base;
54 u64 io_base;
55 u64 mem_base;
56 spinlock_t conf_lock;
57 struct resource cfg;
58 struct resource io;
59 struct resource mem;
60 struct pcie_port_info config;
61 struct clk *clk;
62 struct clk *bus_clk;
63 int irq;
64 int reset_gpio;
65};
66
67/*
68 * Exynos PCIe IP consists of Synopsys specific part and Exynos
69 * specific part. Only core block is a Synopsys designware part;
70 * other parts are Exynos specific.
71 */
72 22
73/* Synopsis specific PCIE configuration registers */ 23/* Synopsis specific PCIE configuration registers */
74#define PCIE_PORT_LINK_CONTROL 0x710 24#define PCIE_PORT_LINK_CONTROL 0x710
75#define PORT_LINK_MODE_MASK (0x3f << 16) 25#define PORT_LINK_MODE_MASK (0x3f << 16)
26#define PORT_LINK_MODE_1_LANES (0x1 << 16)
27#define PORT_LINK_MODE_2_LANES (0x3 << 16)
76#define PORT_LINK_MODE_4_LANES (0x7 << 16) 28#define PORT_LINK_MODE_4_LANES (0x7 << 16)
77 29
78#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 30#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
79#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 31#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
80#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) 32#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
81#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x7 << 8) 33#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
34#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
35#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
82 36
83#define PCIE_MSI_ADDR_LO 0x820 37#define PCIE_MSI_ADDR_LO 0x820
84#define PCIE_MSI_ADDR_HI 0x824 38#define PCIE_MSI_ADDR_HI 0x824
@@ -108,69 +62,16 @@ struct pcie_port {
108#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 62#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
109#define PCIE_ATU_UPPER_TARGET 0x91C 63#define PCIE_ATU_UPPER_TARGET 0x91C
110 64
111/* Exynos specific PCIE configuration registers */ 65static struct hw_pci dw_pci;
112 66
113/* PCIe ELBI registers */ 67unsigned long global_io_offset;
114#define PCIE_IRQ_PULSE 0x000
115#define IRQ_INTA_ASSERT (0x1 << 0)
116#define IRQ_INTB_ASSERT (0x1 << 2)
117#define IRQ_INTC_ASSERT (0x1 << 4)
118#define IRQ_INTD_ASSERT (0x1 << 6)
119#define PCIE_IRQ_LEVEL 0x004
120#define PCIE_IRQ_SPECIAL 0x008
121#define PCIE_IRQ_EN_PULSE 0x00c
122#define PCIE_IRQ_EN_LEVEL 0x010
123#define PCIE_IRQ_EN_SPECIAL 0x014
124#define PCIE_PWR_RESET 0x018
125#define PCIE_CORE_RESET 0x01c
126#define PCIE_CORE_RESET_ENABLE (0x1 << 0)
127#define PCIE_STICKY_RESET 0x020
128#define PCIE_NONSTICKY_RESET 0x024
129#define PCIE_APP_INIT_RESET 0x028
130#define PCIE_APP_LTSSM_ENABLE 0x02c
131#define PCIE_ELBI_RDLH_LINKUP 0x064
132#define PCIE_ELBI_LTSSM_ENABLE 0x1
133#define PCIE_ELBI_SLV_AWMISC 0x11c
134#define PCIE_ELBI_SLV_ARMISC 0x120
135#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
136
137/* PCIe Purple registers */
138#define PCIE_PHY_GLOBAL_RESET 0x000
139#define PCIE_PHY_COMMON_RESET 0x004
140#define PCIE_PHY_CMN_REG 0x008
141#define PCIE_PHY_MAC_RESET 0x00c
142#define PCIE_PHY_PLL_LOCKED 0x010
143#define PCIE_PHY_TRSVREG_RESET 0x020
144#define PCIE_PHY_TRSV_RESET 0x024
145
146/* PCIe PHY registers */
147#define PCIE_PHY_IMPEDANCE 0x004
148#define PCIE_PHY_PLL_DIV_0 0x008
149#define PCIE_PHY_PLL_BIAS 0x00c
150#define PCIE_PHY_DCC_FEEDBACK 0x014
151#define PCIE_PHY_PLL_DIV_1 0x05c
152#define PCIE_PHY_TRSV0_EMP_LVL 0x084
153#define PCIE_PHY_TRSV0_DRV_LVL 0x088
154#define PCIE_PHY_TRSV0_RXCDR 0x0ac
155#define PCIE_PHY_TRSV0_LVCC 0x0dc
156#define PCIE_PHY_TRSV1_EMP_LVL 0x144
157#define PCIE_PHY_TRSV1_RXCDR 0x16c
158#define PCIE_PHY_TRSV1_LVCC 0x19c
159#define PCIE_PHY_TRSV2_EMP_LVL 0x204
160#define PCIE_PHY_TRSV2_RXCDR 0x22c
161#define PCIE_PHY_TRSV2_LVCC 0x25c
162#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
163#define PCIE_PHY_TRSV3_RXCDR 0x2ec
164#define PCIE_PHY_TRSV3_LVCC 0x31c
165
166static struct hw_pci exynos_pci;
167 68
168static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) 69static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
169{ 70{
170 return sys->private_data; 71 return sys->private_data;
171} 72}
172 73
173static inline int cfg_read(void *addr, int where, int size, u32 *val) 74int cfg_read(void __iomem *addr, int where, int size, u32 *val)
174{ 75{
175 *val = readl(addr); 76 *val = readl(addr);
176 77
@@ -184,7 +85,7 @@ static inline int cfg_read(void *addr, int where, int size, u32 *val)
184 return PCIBIOS_SUCCESSFUL; 85 return PCIBIOS_SUCCESSFUL;
185} 86}
186 87
187static inline int cfg_write(void *addr, int where, int size, u32 val) 88int cfg_write(void __iomem *addr, int where, int size, u32 val)
188{ 89{
189 if (size == 4) 90 if (size == 4)
190 writel(val, addr); 91 writel(val, addr);
@@ -198,155 +99,217 @@ static inline int cfg_write(void *addr, int where, int size, u32 val)
198 return PCIBIOS_SUCCESSFUL; 99 return PCIBIOS_SUCCESSFUL;
199} 100}
200 101
201static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) 102static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
202{ 103{
203 u32 val; 104 if (pp->ops->readl_rc)
204 105 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
205 if (on) { 106 else
206 val = readl(pp->elbi_base + PCIE_ELBI_SLV_AWMISC); 107 *val = readl(pp->dbi_base + reg);
207 val |= PCIE_ELBI_SLV_DBI_ENABLE;
208 writel(val, pp->elbi_base + PCIE_ELBI_SLV_AWMISC);
209 } else {
210 val = readl(pp->elbi_base + PCIE_ELBI_SLV_AWMISC);
211 val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
212 writel(val, pp->elbi_base + PCIE_ELBI_SLV_AWMISC);
213 }
214}
215
216static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
217{
218 u32 val;
219
220 if (on) {
221 val = readl(pp->elbi_base + PCIE_ELBI_SLV_ARMISC);
222 val |= PCIE_ELBI_SLV_DBI_ENABLE;
223 writel(val, pp->elbi_base + PCIE_ELBI_SLV_ARMISC);
224 } else {
225 val = readl(pp->elbi_base + PCIE_ELBI_SLV_ARMISC);
226 val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
227 writel(val, pp->elbi_base + PCIE_ELBI_SLV_ARMISC);
228 }
229}
230
231static inline void readl_rc(struct pcie_port *pp, void *dbi_base, u32 *val)
232{
233 exynos_pcie_sideband_dbi_r_mode(pp, true);
234 *val = readl(dbi_base);
235 exynos_pcie_sideband_dbi_r_mode(pp, false);
236 return;
237} 108}
238 109
239static inline void writel_rc(struct pcie_port *pp, u32 val, void *dbi_base) 110static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
240{ 111{
241 exynos_pcie_sideband_dbi_w_mode(pp, true); 112 if (pp->ops->writel_rc)
242 writel(val, dbi_base); 113 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
243 exynos_pcie_sideband_dbi_w_mode(pp, false); 114 else
244 return; 115 writel(val, pp->dbi_base + reg);
245} 116}
246 117
247static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 118int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
248 u32 *val) 119 u32 *val)
249{ 120{
250 int ret; 121 int ret;
251 122
252 exynos_pcie_sideband_dbi_r_mode(pp, true); 123 if (pp->ops->rd_own_conf)
253 ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val); 124 ret = pp->ops->rd_own_conf(pp, where, size, val);
254 exynos_pcie_sideband_dbi_r_mode(pp, false); 125 else
126 ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
127
255 return ret; 128 return ret;
256} 129}
257 130
258static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 131int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
259 u32 val) 132 u32 val)
260{ 133{
261 int ret; 134 int ret;
262 135
263 exynos_pcie_sideband_dbi_w_mode(pp, true); 136 if (pp->ops->wr_own_conf)
264 ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val); 137 ret = pp->ops->wr_own_conf(pp, where, size, val);
265 exynos_pcie_sideband_dbi_w_mode(pp, false); 138 else
139 ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
140 val);
141
266 return ret; 142 return ret;
267} 143}
268 144
269static void exynos_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) 145int dw_pcie_link_up(struct pcie_port *pp)
146{
147 if (pp->ops->link_up)
148 return pp->ops->link_up(pp);
149 else
150 return 0;
151}
152
153int __init dw_pcie_host_init(struct pcie_port *pp)
270{ 154{
155 struct device_node *np = pp->dev->of_node;
156 struct of_pci_range range;
157 struct of_pci_range_parser parser;
271 u32 val; 158 u32 val;
272 void __iomem *dbi_base = pp->dbi_base;
273 159
274 /* Program viewport 0 : OUTBOUND : CFG0 */ 160 if (of_pci_range_parser_init(&parser, np)) {
275 val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0; 161 dev_err(pp->dev, "missing ranges property\n");
276 writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); 162 return -EINVAL;
277 writel_rc(pp, pp->cfg0_base, dbi_base + PCIE_ATU_LOWER_BASE); 163 }
278 writel_rc(pp, (pp->cfg0_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); 164
279 writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1, 165 /* Get the I/O and memory ranges from DT */
280 dbi_base + PCIE_ATU_LIMIT); 166 for_each_of_pci_range(&parser, &range) {
281 writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET); 167 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
282 writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET); 168 if (restype == IORESOURCE_IO) {
283 writel_rc(pp, PCIE_ATU_TYPE_CFG0, dbi_base + PCIE_ATU_CR1); 169 of_pci_range_to_resource(&range, np, &pp->io);
284 val = PCIE_ATU_ENABLE; 170 pp->io.name = "I/O";
285 writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); 171 pp->io.start = max_t(resource_size_t,
172 PCIBIOS_MIN_IO,
173 range.pci_addr + global_io_offset);
174 pp->io.end = min_t(resource_size_t,
175 IO_SPACE_LIMIT,
176 range.pci_addr + range.size
177 + global_io_offset);
178 pp->config.io_size = resource_size(&pp->io);
179 pp->config.io_bus_addr = range.pci_addr;
180 }
181 if (restype == IORESOURCE_MEM) {
182 of_pci_range_to_resource(&range, np, &pp->mem);
183 pp->mem.name = "MEM";
184 pp->config.mem_size = resource_size(&pp->mem);
185 pp->config.mem_bus_addr = range.pci_addr;
186 }
187 if (restype == 0) {
188 of_pci_range_to_resource(&range, np, &pp->cfg);
189 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
190 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
191 }
192 }
193
194 if (!pp->dbi_base) {
195 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
196 resource_size(&pp->cfg));
197 if (!pp->dbi_base) {
198 dev_err(pp->dev, "error with ioremap\n");
199 return -ENOMEM;
200 }
201 }
202
203 pp->cfg0_base = pp->cfg.start;
204 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
205 pp->io_base = pp->io.start;
206 pp->mem_base = pp->mem.start;
207
208 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
209 pp->config.cfg0_size);
210 if (!pp->va_cfg0_base) {
211 dev_err(pp->dev, "error with ioremap in function\n");
212 return -ENOMEM;
213 }
214 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
215 pp->config.cfg1_size);
216 if (!pp->va_cfg1_base) {
217 dev_err(pp->dev, "error with ioremap\n");
218 return -ENOMEM;
219 }
220
221 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
222 dev_err(pp->dev, "Failed to parse the number of lanes\n");
223 return -EINVAL;
224 }
225
226 if (pp->ops->host_init)
227 pp->ops->host_init(pp);
228
229 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
230
231 /* program correct class for RC */
232 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
233
234 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
235 val |= PORT_LOGIC_SPEED_CHANGE;
236 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
237
238 dw_pci.nr_controllers = 1;
239 dw_pci.private_data = (void **)&pp;
240
241 pci_common_init(&dw_pci);
242 pci_assign_unassigned_resources();
243#ifdef CONFIG_PCI_DOMAINS
244 dw_pci.domain++;
245#endif
246
247 return 0;
286} 248}
287 249
288static void exynos_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) 250static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
289{ 251{
290 u32 val; 252 /* Program viewport 0 : OUTBOUND : CFG0 */
291 void __iomem *dbi_base = pp->dbi_base; 253 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
254 PCIE_ATU_VIEWPORT);
255 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
256 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
257 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
258 PCIE_ATU_LIMIT);
259 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
260 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
261 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
262 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
263}
292 264
265static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
266{
293 /* Program viewport 1 : OUTBOUND : CFG1 */ 267 /* Program viewport 1 : OUTBOUND : CFG1 */
294 val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1; 268 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
295 writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); 269 PCIE_ATU_VIEWPORT);
296 writel_rc(pp, PCIE_ATU_TYPE_CFG1, dbi_base + PCIE_ATU_CR1); 270 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
297 val = PCIE_ATU_ENABLE; 271 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
298 writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); 272 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
299 writel_rc(pp, pp->cfg1_base, dbi_base + PCIE_ATU_LOWER_BASE); 273 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
300 writel_rc(pp, (pp->cfg1_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); 274 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
301 writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, 275 PCIE_ATU_LIMIT);
302 dbi_base + PCIE_ATU_LIMIT); 276 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
303 writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET); 277 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
304 writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET);
305} 278}
306 279
307static void exynos_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) 280static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
308{ 281{
309 u32 val;
310 void __iomem *dbi_base = pp->dbi_base;
311
312 /* Program viewport 0 : OUTBOUND : MEM */ 282 /* Program viewport 0 : OUTBOUND : MEM */
313 val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0; 283 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
314 writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); 284 PCIE_ATU_VIEWPORT);
315 writel_rc(pp, PCIE_ATU_TYPE_MEM, dbi_base + PCIE_ATU_CR1); 285 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
316 val = PCIE_ATU_ENABLE; 286 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
317 writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); 287 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
318 writel_rc(pp, pp->mem_base, dbi_base + PCIE_ATU_LOWER_BASE); 288 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
319 writel_rc(pp, (pp->mem_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); 289 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
320 writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, 290 PCIE_ATU_LIMIT);
321 dbi_base + PCIE_ATU_LIMIT); 291 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
322 writel_rc(pp, pp->config.mem_bus_addr, 292 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
323 dbi_base + PCIE_ATU_LOWER_TARGET); 293 PCIE_ATU_UPPER_TARGET);
324 writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
325 dbi_base + PCIE_ATU_UPPER_TARGET);
326} 294}
327 295
328static void exynos_pcie_prog_viewport_io_outbound(struct pcie_port *pp) 296static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
329{ 297{
330 u32 val;
331 void __iomem *dbi_base = pp->dbi_base;
332
333 /* Program viewport 1 : OUTBOUND : IO */ 298 /* Program viewport 1 : OUTBOUND : IO */
334 val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1; 299 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
335 writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); 300 PCIE_ATU_VIEWPORT);
336 writel_rc(pp, PCIE_ATU_TYPE_IO, dbi_base + PCIE_ATU_CR1); 301 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
337 val = PCIE_ATU_ENABLE; 302 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
338 writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); 303 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
339 writel_rc(pp, pp->io_base, dbi_base + PCIE_ATU_LOWER_BASE); 304 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
340 writel_rc(pp, (pp->io_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); 305 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
341 writel_rc(pp, pp->io_base + pp->config.io_size - 1, 306 PCIE_ATU_LIMIT);
342 dbi_base + PCIE_ATU_LIMIT); 307 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
343 writel_rc(pp, pp->config.io_bus_addr, 308 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
344 dbi_base + PCIE_ATU_LOWER_TARGET); 309 PCIE_ATU_UPPER_TARGET);
345 writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), 310}
346 dbi_base + PCIE_ATU_UPPER_TARGET); 311
347} 312static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
348
349static int exynos_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
350 u32 devfn, int where, int size, u32 *val) 313 u32 devfn, int where, int size, u32 *val)
351{ 314{
352 int ret = PCIBIOS_SUCCESSFUL; 315 int ret = PCIBIOS_SUCCESSFUL;
@@ -357,19 +320,19 @@ static int exynos_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
357 address = where & ~0x3; 320 address = where & ~0x3;
358 321
359 if (bus->parent->number == pp->root_bus_nr) { 322 if (bus->parent->number == pp->root_bus_nr) {
360 exynos_pcie_prog_viewport_cfg0(pp, busdev); 323 dw_pcie_prog_viewport_cfg0(pp, busdev);
361 ret = cfg_read(pp->va_cfg0_base + address, where, size, val); 324 ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
362 exynos_pcie_prog_viewport_mem_outbound(pp); 325 dw_pcie_prog_viewport_mem_outbound(pp);
363 } else { 326 } else {
364 exynos_pcie_prog_viewport_cfg1(pp, busdev); 327 dw_pcie_prog_viewport_cfg1(pp, busdev);
365 ret = cfg_read(pp->va_cfg1_base + address, where, size, val); 328 ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
366 exynos_pcie_prog_viewport_io_outbound(pp); 329 dw_pcie_prog_viewport_io_outbound(pp);
367 } 330 }
368 331
369 return ret; 332 return ret;
370} 333}
371 334
372static int exynos_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 335static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
373 u32 devfn, int where, int size, u32 val) 336 u32 devfn, int where, int size, u32 val)
374{ 337{
375 int ret = PCIBIOS_SUCCESSFUL; 338 int ret = PCIBIOS_SUCCESSFUL;
@@ -380,59 +343,25 @@ static int exynos_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
380 address = where & ~0x3; 343 address = where & ~0x3;
381 344
382 if (bus->parent->number == pp->root_bus_nr) { 345 if (bus->parent->number == pp->root_bus_nr) {
383 exynos_pcie_prog_viewport_cfg0(pp, busdev); 346 dw_pcie_prog_viewport_cfg0(pp, busdev);
384 ret = cfg_write(pp->va_cfg0_base + address, where, size, val); 347 ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
385 exynos_pcie_prog_viewport_mem_outbound(pp); 348 dw_pcie_prog_viewport_mem_outbound(pp);
386 } else { 349 } else {
387 exynos_pcie_prog_viewport_cfg1(pp, busdev); 350 dw_pcie_prog_viewport_cfg1(pp, busdev);
388 ret = cfg_write(pp->va_cfg1_base + address, where, size, val); 351 ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
389 exynos_pcie_prog_viewport_io_outbound(pp); 352 dw_pcie_prog_viewport_io_outbound(pp);
390 } 353 }
391 354
392 return ret; 355 return ret;
393} 356}
394 357
395static unsigned long global_io_offset;
396
397static int exynos_pcie_setup(int nr, struct pci_sys_data *sys)
398{
399 struct pcie_port *pp;
400
401 pp = sys_to_pcie(sys);
402
403 if (!pp)
404 return 0;
405
406 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
407 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
408 pci_ioremap_io(sys->io_offset, pp->io.start);
409 global_io_offset += SZ_64K;
410 pci_add_resource_offset(&sys->resources, &pp->io,
411 sys->io_offset);
412 }
413
414 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
415 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
416
417 return 1;
418}
419
420static int exynos_pcie_link_up(struct pcie_port *pp)
421{
422 u32 val = readl(pp->elbi_base + PCIE_ELBI_RDLH_LINKUP);
423
424 if (val == PCIE_ELBI_LTSSM_ENABLE)
425 return 1;
426 358
427 return 0; 359static int dw_pcie_valid_config(struct pcie_port *pp,
428}
429
430static int exynos_pcie_valid_config(struct pcie_port *pp,
431 struct pci_bus *bus, int dev) 360 struct pci_bus *bus, int dev)
432{ 361{
433 /* If there is no link, then there is no device */ 362 /* If there is no link, then there is no device */
434 if (bus->number != pp->root_bus_nr) { 363 if (bus->number != pp->root_bus_nr) {
435 if (!exynos_pcie_link_up(pp)) 364 if (!dw_pcie_link_up(pp))
436 return 0; 365 return 0;
437 } 366 }
438 367
@@ -450,7 +379,7 @@ static int exynos_pcie_valid_config(struct pcie_port *pp,
450 return 1; 379 return 1;
451} 380}
452 381
453static int exynos_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 382static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
454 int size, u32 *val) 383 int size, u32 *val)
455{ 384{
456 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 385 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
@@ -462,23 +391,23 @@ static int exynos_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
462 return -EINVAL; 391 return -EINVAL;
463 } 392 }
464 393
465 if (exynos_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { 394 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
466 *val = 0xffffffff; 395 *val = 0xffffffff;
467 return PCIBIOS_DEVICE_NOT_FOUND; 396 return PCIBIOS_DEVICE_NOT_FOUND;
468 } 397 }
469 398
470 spin_lock_irqsave(&pp->conf_lock, flags); 399 spin_lock_irqsave(&pp->conf_lock, flags);
471 if (bus->number != pp->root_bus_nr) 400 if (bus->number != pp->root_bus_nr)
472 ret = exynos_pcie_rd_other_conf(pp, bus, devfn, 401 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
473 where, size, val); 402 where, size, val);
474 else 403 else
475 ret = exynos_pcie_rd_own_conf(pp, where, size, val); 404 ret = dw_pcie_rd_own_conf(pp, where, size, val);
476 spin_unlock_irqrestore(&pp->conf_lock, flags); 405 spin_unlock_irqrestore(&pp->conf_lock, flags);
477 406
478 return ret; 407 return ret;
479} 408}
480 409
481static int exynos_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 410static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
482 int where, int size, u32 val) 411 int where, int size, u32 val)
483{ 412{
484 struct pcie_port *pp = sys_to_pcie(bus->sysdata); 413 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
@@ -490,34 +419,56 @@ static int exynos_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
490 return -EINVAL; 419 return -EINVAL;
491 } 420 }
492 421
493 if (exynos_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) 422 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
494 return PCIBIOS_DEVICE_NOT_FOUND; 423 return PCIBIOS_DEVICE_NOT_FOUND;
495 424
496 spin_lock_irqsave(&pp->conf_lock, flags); 425 spin_lock_irqsave(&pp->conf_lock, flags);
497 if (bus->number != pp->root_bus_nr) 426 if (bus->number != pp->root_bus_nr)
498 ret = exynos_pcie_wr_other_conf(pp, bus, devfn, 427 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
499 where, size, val); 428 where, size, val);
500 else 429 else
501 ret = exynos_pcie_wr_own_conf(pp, where, size, val); 430 ret = dw_pcie_wr_own_conf(pp, where, size, val);
502 spin_unlock_irqrestore(&pp->conf_lock, flags); 431 spin_unlock_irqrestore(&pp->conf_lock, flags);
503 432
504 return ret; 433 return ret;
505} 434}
506 435
507static struct pci_ops exynos_pcie_ops = { 436static struct pci_ops dw_pcie_ops = {
508 .read = exynos_pcie_rd_conf, 437 .read = dw_pcie_rd_conf,
509 .write = exynos_pcie_wr_conf, 438 .write = dw_pcie_wr_conf,
510}; 439};
511 440
512static struct pci_bus *exynos_pcie_scan_bus(int nr, 441int dw_pcie_setup(int nr, struct pci_sys_data *sys)
513 struct pci_sys_data *sys) 442{
443 struct pcie_port *pp;
444
445 pp = sys_to_pcie(sys);
446
447 if (!pp)
448 return 0;
449
450 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
451 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
452 pci_ioremap_io(sys->io_offset, pp->io.start);
453 global_io_offset += SZ_64K;
454 pci_add_resource_offset(&sys->resources, &pp->io,
455 sys->io_offset);
456 }
457
458 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
459 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
460
461 return 1;
462}
463
464struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
514{ 465{
515 struct pci_bus *bus; 466 struct pci_bus *bus;
516 struct pcie_port *pp = sys_to_pcie(sys); 467 struct pcie_port *pp = sys_to_pcie(sys);
517 468
518 if (pp) { 469 if (pp) {
519 pp->root_bus_nr = sys->busnr; 470 pp->root_bus_nr = sys->busnr;
520 bus = pci_scan_root_bus(NULL, sys->busnr, &exynos_pcie_ops, 471 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
521 sys, &sys->resources); 472 sys, &sys->resources);
522 } else { 473 } else {
523 bus = NULL; 474 bus = NULL;
@@ -527,531 +478,88 @@ static struct pci_bus *exynos_pcie_scan_bus(int nr,
527 return bus; 478 return bus;
528} 479}
529 480
530static int exynos_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 481int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
531{ 482{
532 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); 483 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
533 484
534 return pp->irq; 485 return pp->irq;
535} 486}
536 487
537static struct hw_pci exynos_pci = { 488static struct hw_pci dw_pci = {
538 .setup = exynos_pcie_setup, 489 .setup = dw_pcie_setup,
539 .scan = exynos_pcie_scan_bus, 490 .scan = dw_pcie_scan_bus,
540 .map_irq = exynos_pcie_map_irq, 491 .map_irq = dw_pcie_map_irq,
541}; 492};
542 493
543static void exynos_pcie_setup_rc(struct pcie_port *pp) 494void dw_pcie_setup_rc(struct pcie_port *pp)
544{ 495{
545 struct pcie_port_info *config = &pp->config; 496 struct pcie_port_info *config = &pp->config;
546 void __iomem *dbi_base = pp->dbi_base;
547 u32 val; 497 u32 val;
548 u32 membase; 498 u32 membase;
549 u32 memlimit; 499 u32 memlimit;
550 500
551 /* set the number of lines as 4 */ 501 /* set the number of lines as 4 */
552 readl_rc(pp, dbi_base + PCIE_PORT_LINK_CONTROL, &val); 502 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
553 val &= ~PORT_LINK_MODE_MASK; 503 val &= ~PORT_LINK_MODE_MASK;
554 val |= PORT_LINK_MODE_4_LANES; 504 switch (pp->lanes) {
555 writel_rc(pp, val, dbi_base + PCIE_PORT_LINK_CONTROL); 505 case 1:
506 val |= PORT_LINK_MODE_1_LANES;
507 break;
508 case 2:
509 val |= PORT_LINK_MODE_2_LANES;
510 break;
511 case 4:
512 val |= PORT_LINK_MODE_4_LANES;
513 break;
514 }
515 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
556 516
557 /* set link width speed control register */ 517 /* set link width speed control register */
558 readl_rc(pp, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, &val); 518 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
559 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 519 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
560 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 520 switch (pp->lanes) {
561 writel_rc(pp, val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 521 case 1:
522 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
523 break;
524 case 2:
525 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
526 break;
527 case 4:
528 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
529 break;
530 }
531 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
562 532
563 /* setup RC BARs */ 533 /* setup RC BARs */
564 writel_rc(pp, 0x00000004, dbi_base + PCI_BASE_ADDRESS_0); 534 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
565 writel_rc(pp, 0x00000004, dbi_base + PCI_BASE_ADDRESS_1); 535 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
566 536
567 /* setup interrupt pins */ 537 /* setup interrupt pins */
568 readl_rc(pp, dbi_base + PCI_INTERRUPT_LINE, &val); 538 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
569 val &= 0xffff00ff; 539 val &= 0xffff00ff;
570 val |= 0x00000100; 540 val |= 0x00000100;
571 writel_rc(pp, val, dbi_base + PCI_INTERRUPT_LINE); 541 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
572 542
573 /* setup bus numbers */ 543 /* setup bus numbers */
574 readl_rc(pp, dbi_base + PCI_PRIMARY_BUS, &val); 544 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
575 val &= 0xff000000; 545 val &= 0xff000000;
576 val |= 0x00010100; 546 val |= 0x00010100;
577 writel_rc(pp, val, dbi_base + PCI_PRIMARY_BUS); 547 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
578 548
579 /* setup memory base, memory limit */ 549 /* setup memory base, memory limit */
580 membase = ((u32)pp->mem_base & 0xfff00000) >> 16; 550 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
581 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000; 551 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
582 val = memlimit | membase; 552 val = memlimit | membase;
583 writel_rc(pp, val, dbi_base + PCI_MEMORY_BASE); 553 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
584 554
585 /* setup command register */ 555 /* setup command register */
586 readl_rc(pp, dbi_base + PCI_COMMAND, &val); 556 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
587 val &= 0xffff0000; 557 val &= 0xffff0000;
588 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 558 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
589 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 559 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
590 writel_rc(pp, val, dbi_base + PCI_COMMAND); 560 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
591}
592
593static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
594{
595 u32 val;
596 void __iomem *elbi_base = pp->elbi_base;
597
598 val = readl(elbi_base + PCIE_CORE_RESET);
599 val &= ~PCIE_CORE_RESET_ENABLE;
600 writel(val, elbi_base + PCIE_CORE_RESET);
601 writel(0, elbi_base + PCIE_PWR_RESET);
602 writel(0, elbi_base + PCIE_STICKY_RESET);
603 writel(0, elbi_base + PCIE_NONSTICKY_RESET);
604}
605
606static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
607{
608 u32 val;
609 void __iomem *elbi_base = pp->elbi_base;
610 void __iomem *purple_base = pp->purple_base;
611
612 val = readl(elbi_base + PCIE_CORE_RESET);
613 val |= PCIE_CORE_RESET_ENABLE;
614 writel(val, elbi_base + PCIE_CORE_RESET);
615 writel(1, elbi_base + PCIE_STICKY_RESET);
616 writel(1, elbi_base + PCIE_NONSTICKY_RESET);
617 writel(1, elbi_base + PCIE_APP_INIT_RESET);
618 writel(0, elbi_base + PCIE_APP_INIT_RESET);
619 writel(1, purple_base + PCIE_PHY_MAC_RESET);
620}
621
622static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
623{
624 void __iomem *purple_base = pp->purple_base;
625
626 writel(0, purple_base + PCIE_PHY_MAC_RESET);
627 writel(1, purple_base + PCIE_PHY_GLOBAL_RESET);
628}
629
630static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
631{
632 void __iomem *elbi_base = pp->elbi_base;
633 void __iomem *purple_base = pp->purple_base;
634
635 writel(0, purple_base + PCIE_PHY_GLOBAL_RESET);
636 writel(1, elbi_base + PCIE_PWR_RESET);
637 writel(0, purple_base + PCIE_PHY_COMMON_RESET);
638 writel(0, purple_base + PCIE_PHY_CMN_REG);
639 writel(0, purple_base + PCIE_PHY_TRSVREG_RESET);
640 writel(0, purple_base + PCIE_PHY_TRSV_RESET);
641}
642
643static void exynos_pcie_init_phy(struct pcie_port *pp)
644{
645 void __iomem *phy_base = pp->phy_base;
646
647 /* DCC feedback control off */
648 writel(0x29, phy_base + PCIE_PHY_DCC_FEEDBACK);
649
650 /* set TX/RX impedance */
651 writel(0xd5, phy_base + PCIE_PHY_IMPEDANCE);
652
653 /* set 50Mhz PHY clock */
654 writel(0x14, phy_base + PCIE_PHY_PLL_DIV_0);
655 writel(0x12, phy_base + PCIE_PHY_PLL_DIV_1);
656
657 /* set TX Differential output for lane 0 */
658 writel(0x7f, phy_base + PCIE_PHY_TRSV0_DRV_LVL);
659
660 /* set TX Pre-emphasis Level Control for lane 0 to minimum */
661 writel(0x0, phy_base + PCIE_PHY_TRSV0_EMP_LVL);
662
663 /* set RX clock and data recovery bandwidth */
664 writel(0xe7, phy_base + PCIE_PHY_PLL_BIAS);
665 writel(0x82, phy_base + PCIE_PHY_TRSV0_RXCDR);
666 writel(0x82, phy_base + PCIE_PHY_TRSV1_RXCDR);
667 writel(0x82, phy_base + PCIE_PHY_TRSV2_RXCDR);
668 writel(0x82, phy_base + PCIE_PHY_TRSV3_RXCDR);
669
670 /* change TX Pre-emphasis Level Control for lanes */
671 writel(0x39, phy_base + PCIE_PHY_TRSV0_EMP_LVL);
672 writel(0x39, phy_base + PCIE_PHY_TRSV1_EMP_LVL);
673 writel(0x39, phy_base + PCIE_PHY_TRSV2_EMP_LVL);
674 writel(0x39, phy_base + PCIE_PHY_TRSV3_EMP_LVL);
675
676 /* set LVCC */
677 writel(0x20, phy_base + PCIE_PHY_TRSV0_LVCC);
678 writel(0xa0, phy_base + PCIE_PHY_TRSV1_LVCC);
679 writel(0xa0, phy_base + PCIE_PHY_TRSV2_LVCC);
680 writel(0xa0, phy_base + PCIE_PHY_TRSV3_LVCC);
681}
682
683static void exynos_pcie_assert_reset(struct pcie_port *pp)
684{
685 if (pp->reset_gpio >= 0)
686 devm_gpio_request_one(pp->dev, pp->reset_gpio,
687 GPIOF_OUT_INIT_HIGH, "RESET");
688 return;
689}
690
691static int exynos_pcie_establish_link(struct pcie_port *pp)
692{
693 u32 val;
694 int count = 0;
695 void __iomem *elbi_base = pp->elbi_base;
696 void __iomem *purple_base = pp->purple_base;
697 void __iomem *phy_base = pp->phy_base;
698
699 if (exynos_pcie_link_up(pp)) {
700 dev_err(pp->dev, "Link already up\n");
701 return 0;
702 }
703
704 /* assert reset signals */
705 exynos_pcie_assert_core_reset(pp);
706 exynos_pcie_assert_phy_reset(pp);
707
708 /* de-assert phy reset */
709 exynos_pcie_deassert_phy_reset(pp);
710
711 /* initialize phy */
712 exynos_pcie_init_phy(pp);
713
714 /* pulse for common reset */
715 writel(1, purple_base + PCIE_PHY_COMMON_RESET);
716 udelay(500);
717 writel(0, purple_base + PCIE_PHY_COMMON_RESET);
718
719 /* de-assert core reset */
720 exynos_pcie_deassert_core_reset(pp);
721
722 /* setup root complex */
723 exynos_pcie_setup_rc(pp);
724
725 /* assert reset signal */
726 exynos_pcie_assert_reset(pp);
727
728 /* assert LTSSM enable */
729 writel(PCIE_ELBI_LTSSM_ENABLE, elbi_base + PCIE_APP_LTSSM_ENABLE);
730
731 /* check if the link is up or not */
732 while (!exynos_pcie_link_up(pp)) {
733 mdelay(100);
734 count++;
735 if (count == 10) {
736 while (readl(phy_base + PCIE_PHY_PLL_LOCKED) == 0) {
737 val = readl(purple_base + PCIE_PHY_PLL_LOCKED);
738 dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
739 }
740 dev_err(pp->dev, "PCIe Link Fail\n");
741 return -EINVAL;
742 }
743 }
744
745 dev_info(pp->dev, "Link up\n");
746
747 return 0;
748}
749
750static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
751{
752 u32 val;
753 void __iomem *elbi_base = pp->elbi_base;
754
755 val = readl(elbi_base + PCIE_IRQ_PULSE);
756 writel(val, elbi_base + PCIE_IRQ_PULSE);
757 return;
758}
759
760static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
761{
762 u32 val;
763 void __iomem *elbi_base = pp->elbi_base;
764
765 /* enable INTX interrupt */
766 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
767 IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
768 writel(val, elbi_base + PCIE_IRQ_EN_PULSE);
769 return;
770}
771
772static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
773{
774 struct pcie_port *pp = arg;
775
776 exynos_pcie_clear_irq_pulse(pp);
777 return IRQ_HANDLED;
778}
779
780static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
781{
782 exynos_pcie_enable_irq_pulse(pp);
783 return;
784}
785
786static void exynos_pcie_host_init(struct pcie_port *pp)
787{
788 struct pcie_port_info *config = &pp->config;
789 u32 val;
790
791 /* Keep first 64K for IO */
792 pp->cfg0_base = pp->cfg.start;
793 pp->cfg1_base = pp->cfg.start + config->cfg0_size;
794 pp->io_base = pp->io.start;
795 pp->mem_base = pp->mem.start;
796
797 /* enable link */
798 exynos_pcie_establish_link(pp);
799
800 exynos_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
801
802 /* program correct class for RC */
803 exynos_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
804
805 exynos_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
806 val |= PORT_LOGIC_SPEED_CHANGE;
807 exynos_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
808
809 exynos_pcie_enable_interrupts(pp);
810}
811
812static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
813{
814 struct resource *elbi_base;
815 struct resource *phy_base;
816 struct resource *purple_base;
817 int ret;
818
819 elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
820 if (!elbi_base) {
821 dev_err(&pdev->dev, "couldn't get elbi base resource\n");
822 return -EINVAL;
823 }
824 pp->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
825 if (IS_ERR(pp->elbi_base))
826 return PTR_ERR(pp->elbi_base);
827
828 phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
829 if (!phy_base) {
830 dev_err(&pdev->dev, "couldn't get phy base resource\n");
831 return -EINVAL;
832 }
833 pp->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
834 if (IS_ERR(pp->phy_base))
835 return PTR_ERR(pp->phy_base);
836
837 purple_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
838 if (!purple_base) {
839 dev_err(&pdev->dev, "couldn't get purple base resource\n");
840 return -EINVAL;
841 }
842 pp->purple_base = devm_ioremap_resource(&pdev->dev, purple_base);
843 if (IS_ERR(pp->purple_base))
844 return PTR_ERR(pp->purple_base);
845
846 pp->irq = platform_get_irq(pdev, 1);
847 if (!pp->irq) {
848 dev_err(&pdev->dev, "failed to get irq\n");
849 return -ENODEV;
850 }
851 ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,
852 IRQF_SHARED, "exynos-pcie", pp);
853 if (ret) {
854 dev_err(&pdev->dev, "failed to request irq\n");
855 return ret;
856 }
857
858 pp->dbi_base = devm_ioremap(&pdev->dev, pp->cfg.start,
859 resource_size(&pp->cfg));
860 if (!pp->dbi_base) {
861 dev_err(&pdev->dev, "error with ioremap\n");
862 return -ENOMEM;
863 }
864
865 pp->root_bus_nr = -1;
866
867 spin_lock_init(&pp->conf_lock);
868 exynos_pcie_host_init(pp);
869 pp->va_cfg0_base = devm_ioremap(&pdev->dev, pp->cfg0_base,
870 pp->config.cfg0_size);
871 if (!pp->va_cfg0_base) {
872 dev_err(pp->dev, "error with ioremap in function\n");
873 return -ENOMEM;
874 }
875 pp->va_cfg1_base = devm_ioremap(&pdev->dev, pp->cfg1_base,
876 pp->config.cfg1_size);
877 if (!pp->va_cfg1_base) {
878 dev_err(pp->dev, "error with ioremap\n");
879 return -ENOMEM;
880 }
881
882 return 0;
883}
884
885static int __init exynos_pcie_probe(struct platform_device *pdev)
886{
887 struct pcie_port *pp;
888 struct device_node *np = pdev->dev.of_node;
889 struct of_pci_range range;
890 struct of_pci_range_parser parser;
891 int ret;
892
893 pp = devm_kzalloc(&pdev->dev, sizeof(*pp), GFP_KERNEL);
894 if (!pp) {
895 dev_err(&pdev->dev, "no memory for pcie port\n");
896 return -ENOMEM;
897 }
898
899 pp->dev = &pdev->dev;
900
901 if (of_pci_range_parser_init(&parser, np)) {
902 dev_err(&pdev->dev, "missing ranges property\n");
903 return -EINVAL;
904 }
905
906 /* Get the I/O and memory ranges from DT */
907 for_each_of_pci_range(&parser, &range) {
908 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
909 if (restype == IORESOURCE_IO) {
910 of_pci_range_to_resource(&range, np, &pp->io);
911 pp->io.name = "I/O";
912 pp->io.start = max_t(resource_size_t,
913 PCIBIOS_MIN_IO,
914 range.pci_addr + global_io_offset);
915 pp->io.end = min_t(resource_size_t,
916 IO_SPACE_LIMIT,
917 range.pci_addr + range.size
918 + global_io_offset);
919 pp->config.io_size = resource_size(&pp->io);
920 pp->config.io_bus_addr = range.pci_addr;
921 }
922 if (restype == IORESOURCE_MEM) {
923 of_pci_range_to_resource(&range, np, &pp->mem);
924 pp->mem.name = "MEM";
925 pp->config.mem_size = resource_size(&pp->mem);
926 pp->config.mem_bus_addr = range.pci_addr;
927 }
928 if (restype == 0) {
929 of_pci_range_to_resource(&range, np, &pp->cfg);
930 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
931 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
932 }
933 }
934
935 pp->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
936
937 pp->clk = devm_clk_get(&pdev->dev, "pcie");
938 if (IS_ERR(pp->clk)) {
939 dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
940 return PTR_ERR(pp->clk);
941 }
942 ret = clk_prepare_enable(pp->clk);
943 if (ret)
944 return ret;
945
946 pp->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
947 if (IS_ERR(pp->bus_clk)) {
948 dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
949 ret = PTR_ERR(pp->bus_clk);
950 goto fail_clk;
951 }
952 ret = clk_prepare_enable(pp->bus_clk);
953 if (ret)
954 goto fail_clk;
955
956 ret = add_pcie_port(pp, pdev);
957 if (ret < 0)
958 goto fail_bus_clk;
959
960 pp->controller = exynos_pci.nr_controllers;
961 exynos_pci.nr_controllers = 1;
962 exynos_pci.private_data = (void **)&pp;
963
964 pci_common_init(&exynos_pci);
965 pci_assign_unassigned_resources();
966#ifdef CONFIG_PCI_DOMAINS
967 exynos_pci.domain++;
968#endif
969
970 platform_set_drvdata(pdev, pp);
971 return 0;
972
973fail_bus_clk:
974 clk_disable_unprepare(pp->bus_clk);
975fail_clk:
976 clk_disable_unprepare(pp->clk);
977 return ret;
978}
979
980static int __exit exynos_pcie_remove(struct platform_device *pdev)
981{
982 struct pcie_port *pp = platform_get_drvdata(pdev);
983
984 clk_disable_unprepare(pp->bus_clk);
985 clk_disable_unprepare(pp->clk);
986
987 return 0;
988}
989
990static const struct of_device_id exynos_pcie_of_match[] = {
991 { .compatible = "samsung,exynos5440-pcie", },
992 {},
993};
994MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);
995
996static struct platform_driver exynos_pcie_driver = {
997 .remove = __exit_p(exynos_pcie_remove),
998 .driver = {
999 .name = "exynos-pcie",
1000 .owner = THIS_MODULE,
1001 .of_match_table = of_match_ptr(exynos_pcie_of_match),
1002 },
1003};
1004
1005static int exynos_pcie_abort(unsigned long addr, unsigned int fsr,
1006 struct pt_regs *regs)
1007{
1008 unsigned long pc = instruction_pointer(regs);
1009 unsigned long instr = *(unsigned long *)pc;
1010
1011 WARN_ONCE(1, "pcie abort\n");
1012
1013 /*
1014 * If the instruction being executed was a read,
1015 * make it look like it read all-ones.
1016 */
1017 if ((instr & 0x0c100000) == 0x04100000) {
1018 int reg = (instr >> 12) & 15;
1019 unsigned long val;
1020
1021 if (instr & 0x00400000)
1022 val = 255;
1023 else
1024 val = -1;
1025
1026 regs->uregs[reg] = val;
1027 regs->ARM_pc += 4;
1028 return 0;
1029 }
1030
1031 if ((instr & 0x0e100090) == 0x00100090) {
1032 int reg = (instr >> 12) & 15;
1033
1034 regs->uregs[reg] = -1;
1035 regs->ARM_pc += 4;
1036 return 0;
1037 }
1038
1039 return 1;
1040}
1041
1042/* Exynos PCIe driver does not allow module unload */
1043
1044static int __init pcie_init(void)
1045{
1046 hook_fault_code(16 + 6, exynos_pcie_abort, SIGBUS, 0,
1047 "imprecise external abort");
1048
1049 platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
1050
1051 return 0;
1052} 561}
1053subsys_initcall(pcie_init);
1054 562
1055MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 563MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1056MODULE_DESCRIPTION("Samsung PCIe host controller driver"); 564MODULE_DESCRIPTION("Designware PCIe host controller driver");
1057MODULE_LICENSE("GPL v2"); 565MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
new file mode 100644
index 000000000000..133820f1da97
--- /dev/null
+++ b/drivers/pci/host/pcie-designware.h
@@ -0,0 +1,65 @@
1/*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14struct pcie_port_info {
15 u32 cfg0_size;
16 u32 cfg1_size;
17 u32 io_size;
18 u32 mem_size;
19 phys_addr_t io_bus_addr;
20 phys_addr_t mem_bus_addr;
21};
22
23struct pcie_port {
24 struct device *dev;
25 u8 root_bus_nr;
26 void __iomem *dbi_base;
27 u64 cfg0_base;
28 void __iomem *va_cfg0_base;
29 u64 cfg1_base;
30 void __iomem *va_cfg1_base;
31 u64 io_base;
32 u64 mem_base;
33 spinlock_t conf_lock;
34 struct resource cfg;
35 struct resource io;
36 struct resource mem;
37 struct pcie_port_info config;
38 int irq;
39 u32 lanes;
40 struct pcie_host_ops *ops;
41};
42
43struct pcie_host_ops {
44 void (*readl_rc)(struct pcie_port *pp,
45 void __iomem *dbi_base, u32 *val);
46 void (*writel_rc)(struct pcie_port *pp,
47 u32 val, void __iomem *dbi_base);
48 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
49 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
50 int (*link_up)(struct pcie_port *pp);
51 void (*host_init)(struct pcie_port *pp);
52};
53
54extern unsigned long global_io_offset;
55
56int cfg_read(void __iomem *addr, int where, int size, u32 *val);
57int cfg_write(void __iomem *addr, int where, int size, u32 val);
58int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
59int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
60int dw_pcie_link_up(struct pcie_port *pp);
61void dw_pcie_setup_rc(struct pcie_port *pp);
62int dw_pcie_host_init(struct pcie_port *pp);
63int dw_pcie_setup(int nr, struct pci_sys_data *sys);
64struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
65int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 8054ddcdaed0..f6488adf3af1 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -572,7 +572,6 @@ static void __ref enable_slot(struct acpiphp_slot *slot)
572 acpiphp_sanitize_bus(bus); 572 acpiphp_sanitize_bus(bus);
573 acpiphp_set_hpp_values(bus); 573 acpiphp_set_hpp_values(bus);
574 acpiphp_set_acpi_region(slot); 574 acpiphp_set_acpi_region(slot);
575 pci_enable_bridges(bus);
576 575
577 list_for_each_entry(dev, &bus->devices, bus_list) { 576 list_for_each_entry(dev, &bus->devices, bus_list) {
578 /* Assume that newly added devices are powered on already. */ 577 /* Assume that newly added devices are powered on already. */
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 7fb326983ed6..541bbe6d5343 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -155,6 +155,7 @@ void pciehp_green_led_off(struct slot *slot);
155void pciehp_green_led_blink(struct slot *slot); 155void pciehp_green_led_blink(struct slot *slot);
156int pciehp_check_link_status(struct controller *ctrl); 156int pciehp_check_link_status(struct controller *ctrl);
157void pciehp_release_ctrl(struct controller *ctrl); 157void pciehp_release_ctrl(struct controller *ctrl);
158int pciehp_reset_slot(struct slot *slot, int probe);
158 159
159static inline const char *slot_name(struct slot *slot) 160static inline const char *slot_name(struct slot *slot)
160{ 161{
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 7d72c5e2eba9..f4a18f51a29c 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -69,6 +69,7 @@ static int get_power_status (struct hotplug_slot *slot, u8 *value);
69static int get_attention_status (struct hotplug_slot *slot, u8 *value); 69static int get_attention_status (struct hotplug_slot *slot, u8 *value);
70static int get_latch_status (struct hotplug_slot *slot, u8 *value); 70static int get_latch_status (struct hotplug_slot *slot, u8 *value);
71static int get_adapter_status (struct hotplug_slot *slot, u8 *value); 71static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
72static int reset_slot (struct hotplug_slot *slot, int probe);
72 73
73/** 74/**
74 * release_slot - free up the memory used by a slot 75 * release_slot - free up the memory used by a slot
@@ -111,6 +112,7 @@ static int init_slot(struct controller *ctrl)
111 ops->disable_slot = disable_slot; 112 ops->disable_slot = disable_slot;
112 ops->get_power_status = get_power_status; 113 ops->get_power_status = get_power_status;
113 ops->get_adapter_status = get_adapter_status; 114 ops->get_adapter_status = get_adapter_status;
115 ops->reset_slot = reset_slot;
114 if (MRL_SENS(ctrl)) 116 if (MRL_SENS(ctrl))
115 ops->get_latch_status = get_latch_status; 117 ops->get_latch_status = get_latch_status;
116 if (ATTN_LED(ctrl)) { 118 if (ATTN_LED(ctrl)) {
@@ -223,6 +225,16 @@ static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value)
223 return pciehp_get_adapter_status(slot, value); 225 return pciehp_get_adapter_status(slot, value);
224} 226}
225 227
228static int reset_slot(struct hotplug_slot *hotplug_slot, int probe)
229{
230 struct slot *slot = hotplug_slot->private;
231
232 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
233 __func__, slot_name(slot));
234
235 return pciehp_reset_slot(slot, probe);
236}
237
226static int pciehp_probe(struct pcie_device *dev) 238static int pciehp_probe(struct pcie_device *dev)
227{ 239{
228 int rc; 240 int rc;
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index b2255736ac81..51f56ef4ab6f 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -749,6 +749,37 @@ static void pcie_disable_notification(struct controller *ctrl)
749 ctrl_warn(ctrl, "Cannot disable software notification\n"); 749 ctrl_warn(ctrl, "Cannot disable software notification\n");
750} 750}
751 751
752/*
753 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
754 * bus reset of the bridge, but if the slot supports surprise removal we need
755 * to disable presence detection around the bus reset and clear any spurious
756 * events after.
757 */
758int pciehp_reset_slot(struct slot *slot, int probe)
759{
760 struct controller *ctrl = slot->ctrl;
761
762 if (probe)
763 return 0;
764
765 if (HP_SUPR_RM(ctrl)) {
766 pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE);
767 if (pciehp_poll_mode)
768 del_timer_sync(&ctrl->poll_timer);
769 }
770
771 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
772
773 if (HP_SUPR_RM(ctrl)) {
774 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDC);
775 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);
776 if (pciehp_poll_mode)
777 int_poll_timeout(ctrl->poll_timer.data);
778 }
779
780 return 0;
781}
782
752int pcie_init_notification(struct controller *ctrl) 783int pcie_init_notification(struct controller *ctrl)
753{ 784{
754 if (pciehp_request_irq(ctrl)) 785 if (pciehp_request_irq(ctrl))
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
index fec2d5b75440..16f920352317 100644
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ b/drivers/pci/hotplug/pcihp_slot.c
@@ -160,9 +160,8 @@ void pci_configure_slot(struct pci_dev *dev)
160 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) 160 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
161 return; 161 return;
162 162
163 if (dev->bus && dev->bus->self) 163 if (dev->bus)
164 pcie_bus_configure_settings(dev->bus, 164 pcie_bus_configure_settings(dev->bus);
165 dev->bus->self->pcie_mpss);
166 165
167 memset(&hpp, 0, sizeof(hpp)); 166 memset(&hpp, 0, sizeof(hpp));
168 ret = pci_get_hp_params(dev, &hpp); 167 ret = pci_get_hp_params(dev, &hpp);
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index de8ffacf9c9b..21a7182dccd4 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -286,7 +286,6 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
286 (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial))) 286 (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))
287 return -EINVAL; 287 return -EINVAL;
288 288
289 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
290 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset); 289 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset);
291 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride); 290 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride);
292 if (!offset || (nr_virtfn > 1 && !stride)) 291 if (!offset || (nr_virtfn > 1 && !stride))
@@ -324,7 +323,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
324 323
325 if (!pdev->is_physfn) { 324 if (!pdev->is_physfn) {
326 pci_dev_put(pdev); 325 pci_dev_put(pdev);
327 return -ENODEV; 326 return -ENOSYS;
328 } 327 }
329 328
330 rc = sysfs_create_link(&dev->dev.kobj, 329 rc = sysfs_create_link(&dev->dev.kobj,
@@ -334,6 +333,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
334 return rc; 333 return rc;
335 } 334 }
336 335
336 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
337 iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; 337 iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
338 pci_cfg_access_lock(dev); 338 pci_cfg_access_lock(dev);
339 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); 339 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
@@ -368,6 +368,7 @@ failed:
368 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE); 368 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
369 pci_cfg_access_lock(dev); 369 pci_cfg_access_lock(dev);
370 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); 370 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
371 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);
371 ssleep(1); 372 ssleep(1);
372 pci_cfg_access_unlock(dev); 373 pci_cfg_access_unlock(dev);
373 374
@@ -401,6 +402,7 @@ static void sriov_disable(struct pci_dev *dev)
401 sysfs_remove_link(&dev->dev.kobj, "dep_link"); 402 sysfs_remove_link(&dev->dev.kobj, "dep_link");
402 403
403 iov->num_VFs = 0; 404 iov->num_VFs = 0;
405 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);
404} 406}
405 407
406static int sriov_init(struct pci_dev *dev, int pos) 408static int sriov_init(struct pci_dev *dev, int pos)
@@ -662,7 +664,7 @@ int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
662 might_sleep(); 664 might_sleep();
663 665
664 if (!dev->is_physfn) 666 if (!dev->is_physfn)
665 return -ENODEV; 667 return -ENOSYS;
666 668
667 return sriov_enable(dev, nr_virtfn); 669 return sriov_enable(dev, nr_virtfn);
668} 670}
@@ -722,7 +724,7 @@ EXPORT_SYMBOL_GPL(pci_num_vf);
722 * @dev: the PCI device 724 * @dev: the PCI device
723 * 725 *
724 * Returns number of VFs belonging to this device that are assigned to a guest. 726 * Returns number of VFs belonging to this device that are assigned to a guest.
725 * If device is not a physical function returns -ENODEV. 727 * If device is not a physical function returns 0.
726 */ 728 */
727int pci_vfs_assigned(struct pci_dev *dev) 729int pci_vfs_assigned(struct pci_dev *dev)
728{ 730{
@@ -767,12 +769,15 @@ EXPORT_SYMBOL_GPL(pci_vfs_assigned);
767 * device's mutex held. 769 * device's mutex held.
768 * 770 *
769 * Returns 0 if PF is an SRIOV-capable device and 771 * Returns 0 if PF is an SRIOV-capable device and
770 * value of numvfs valid. If not a PF with VFS, return -EINVAL; 772 * value of numvfs valid. If not a PF return -ENOSYS;
773 * if numvfs is invalid return -EINVAL;
771 * if VFs already enabled, return -EBUSY. 774 * if VFs already enabled, return -EBUSY.
772 */ 775 */
773int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 776int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
774{ 777{
775 if (!dev->is_physfn || (numvfs > dev->sriov->total_VFs)) 778 if (!dev->is_physfn)
779 return -ENOSYS;
780 if (numvfs > dev->sriov->total_VFs)
776 return -EINVAL; 781 return -EINVAL;
777 782
778 /* Shouldn't change if VFs already enabled */ 783 /* Shouldn't change if VFs already enabled */
@@ -786,17 +791,17 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
786EXPORT_SYMBOL_GPL(pci_sriov_set_totalvfs); 791EXPORT_SYMBOL_GPL(pci_sriov_set_totalvfs);
787 792
788/** 793/**
789 * pci_sriov_get_totalvfs -- get total VFs supported on this devic3 794 * pci_sriov_get_totalvfs -- get total VFs supported on this device
790 * @dev: the PCI PF device 795 * @dev: the PCI PF device
791 * 796 *
792 * For a PCIe device with SRIOV support, return the PCIe 797 * For a PCIe device with SRIOV support, return the PCIe
793 * SRIOV capability value of TotalVFs or the value of driver_max_VFs 798 * SRIOV capability value of TotalVFs or the value of driver_max_VFs
794 * if the driver reduced it. Otherwise, -EINVAL. 799 * if the driver reduced it. Otherwise 0.
795 */ 800 */
796int pci_sriov_get_totalvfs(struct pci_dev *dev) 801int pci_sriov_get_totalvfs(struct pci_dev *dev)
797{ 802{
798 if (!dev->is_physfn) 803 if (!dev->is_physfn)
799 return -EINVAL; 804 return 0;
800 805
801 if (dev->sriov->driver_max_VFs) 806 if (dev->sriov->driver_max_VFs)
802 return dev->sriov->driver_max_VFs; 807 return dev->sriov->driver_max_VFs;
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index e6515e21afa3..98f7b9b89507 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -763,6 +763,13 @@ static int pci_pm_resume(struct device *dev)
763 763
764#ifdef CONFIG_HIBERNATE_CALLBACKS 764#ifdef CONFIG_HIBERNATE_CALLBACKS
765 765
766
767/*
768 * pcibios_pm_ops - provide arch-specific hooks when a PCI device is doing
769 * a hibernate transition
770 */
771struct dev_pm_ops __weak pcibios_pm_ops;
772
766static int pci_pm_freeze(struct device *dev) 773static int pci_pm_freeze(struct device *dev)
767{ 774{
768 struct pci_dev *pci_dev = to_pci_dev(dev); 775 struct pci_dev *pci_dev = to_pci_dev(dev);
@@ -786,6 +793,9 @@ static int pci_pm_freeze(struct device *dev)
786 return error; 793 return error;
787 } 794 }
788 795
796 if (pcibios_pm_ops.freeze)
797 return pcibios_pm_ops.freeze(dev);
798
789 return 0; 799 return 0;
790} 800}
791 801
@@ -811,6 +821,9 @@ static int pci_pm_freeze_noirq(struct device *dev)
811 821
812 pci_pm_set_unknown_state(pci_dev); 822 pci_pm_set_unknown_state(pci_dev);
813 823
824 if (pcibios_pm_ops.freeze_noirq)
825 return pcibios_pm_ops.freeze_noirq(dev);
826
814 return 0; 827 return 0;
815} 828}
816 829
@@ -820,6 +833,12 @@ static int pci_pm_thaw_noirq(struct device *dev)
820 struct device_driver *drv = dev->driver; 833 struct device_driver *drv = dev->driver;
821 int error = 0; 834 int error = 0;
822 835
836 if (pcibios_pm_ops.thaw_noirq) {
837 error = pcibios_pm_ops.thaw_noirq(dev);
838 if (error)
839 return error;
840 }
841
823 if (pci_has_legacy_pm_support(pci_dev)) 842 if (pci_has_legacy_pm_support(pci_dev))
824 return pci_legacy_resume_early(dev); 843 return pci_legacy_resume_early(dev);
825 844
@@ -837,6 +856,12 @@ static int pci_pm_thaw(struct device *dev)
837 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 856 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
838 int error = 0; 857 int error = 0;
839 858
859 if (pcibios_pm_ops.thaw) {
860 error = pcibios_pm_ops.thaw(dev);
861 if (error)
862 return error;
863 }
864
840 if (pci_has_legacy_pm_support(pci_dev)) 865 if (pci_has_legacy_pm_support(pci_dev))
841 return pci_legacy_resume(dev); 866 return pci_legacy_resume(dev);
842 867
@@ -878,6 +903,9 @@ static int pci_pm_poweroff(struct device *dev)
878 Fixup: 903 Fixup:
879 pci_fixup_device(pci_fixup_suspend, pci_dev); 904 pci_fixup_device(pci_fixup_suspend, pci_dev);
880 905
906 if (pcibios_pm_ops.poweroff)
907 return pcibios_pm_ops.poweroff(dev);
908
881 return 0; 909 return 0;
882} 910}
883 911
@@ -911,6 +939,9 @@ static int pci_pm_poweroff_noirq(struct device *dev)
911 if (pci_dev->class == PCI_CLASS_SERIAL_USB_EHCI) 939 if (pci_dev->class == PCI_CLASS_SERIAL_USB_EHCI)
912 pci_write_config_word(pci_dev, PCI_COMMAND, 0); 940 pci_write_config_word(pci_dev, PCI_COMMAND, 0);
913 941
942 if (pcibios_pm_ops.poweroff_noirq)
943 return pcibios_pm_ops.poweroff_noirq(dev);
944
914 return 0; 945 return 0;
915} 946}
916 947
@@ -920,6 +951,12 @@ static int pci_pm_restore_noirq(struct device *dev)
920 struct device_driver *drv = dev->driver; 951 struct device_driver *drv = dev->driver;
921 int error = 0; 952 int error = 0;
922 953
954 if (pcibios_pm_ops.restore_noirq) {
955 error = pcibios_pm_ops.restore_noirq(dev);
956 if (error)
957 return error;
958 }
959
923 pci_pm_default_resume_early(pci_dev); 960 pci_pm_default_resume_early(pci_dev);
924 961
925 if (pci_has_legacy_pm_support(pci_dev)) 962 if (pci_has_legacy_pm_support(pci_dev))
@@ -937,6 +974,12 @@ static int pci_pm_restore(struct device *dev)
937 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 974 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
938 int error = 0; 975 int error = 0;
939 976
977 if (pcibios_pm_ops.restore) {
978 error = pcibios_pm_ops.restore(dev);
979 if (error)
980 return error;
981 }
982
940 /* 983 /*
941 * This is necessary for the hibernation error path in which restore is 984 * This is necessary for the hibernation error path in which restore is
942 * called without restoring the standard config registers of the device. 985 * called without restoring the standard config registers of the device.
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index c0dbe1f61362..7128cfdd64aa 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -131,19 +131,19 @@ static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
131 return ret; 131 return ret;
132} 132}
133 133
134static inline ssize_t pci_bus_show_cpumaskaffinity(struct device *dev, 134static ssize_t cpuaffinity_show(struct device *dev,
135 struct device_attribute *attr, 135 struct device_attribute *attr, char *buf)
136 char *buf)
137{ 136{
138 return pci_bus_show_cpuaffinity(dev, 0, attr, buf); 137 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
139} 138}
139static DEVICE_ATTR_RO(cpuaffinity);
140 140
141static inline ssize_t pci_bus_show_cpulistaffinity(struct device *dev, 141static ssize_t cpulistaffinity_show(struct device *dev,
142 struct device_attribute *attr, 142 struct device_attribute *attr, char *buf)
143 char *buf)
144{ 143{
145 return pci_bus_show_cpuaffinity(dev, 1, attr, buf); 144 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
146} 145}
146static DEVICE_ATTR_RO(cpulistaffinity);
147 147
148/* show resources */ 148/* show resources */
149static ssize_t 149static ssize_t
@@ -379,6 +379,7 @@ dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
379 } 379 }
380 return count; 380 return count;
381} 381}
382static DEVICE_ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store);
382 383
383#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI) 384#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
384static ssize_t d3cold_allowed_store(struct device *dev, 385static ssize_t d3cold_allowed_store(struct device *dev,
@@ -514,11 +515,20 @@ struct device_attribute pci_dev_attrs[] = {
514 __ATTR_NULL, 515 __ATTR_NULL,
515}; 516};
516 517
517struct device_attribute pcibus_dev_attrs[] = { 518static struct attribute *pcibus_attrs[] = {
518 __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store), 519 &dev_attr_rescan.attr,
519 __ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL), 520 &dev_attr_cpuaffinity.attr,
520 __ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL), 521 &dev_attr_cpulistaffinity.attr,
521 __ATTR_NULL, 522 NULL,
523};
524
525static const struct attribute_group pcibus_group = {
526 .attrs = pcibus_attrs,
527};
528
529const struct attribute_group *pcibus_groups[] = {
530 &pcibus_group,
531 NULL,
522}; 532};
523 533
524static ssize_t 534static ssize_t
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e37fea6e178d..b821a62958fd 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/device.h> 23#include <linux/device.h>
24#include <linux/pm_runtime.h> 24#include <linux/pm_runtime.h>
25#include <linux/pci_hotplug.h>
25#include <asm-generic/pci-bridge.h> 26#include <asm-generic/pci-bridge.h>
26#include <asm/setup.h> 27#include <asm/setup.h>
27#include "pci.h" 28#include "pci.h"
@@ -1145,6 +1146,24 @@ int pci_reenable_device(struct pci_dev *dev)
1145 return 0; 1146 return 0;
1146} 1147}
1147 1148
1149static void pci_enable_bridge(struct pci_dev *dev)
1150{
1151 int retval;
1152
1153 if (!dev)
1154 return;
1155
1156 pci_enable_bridge(dev->bus->self);
1157
1158 if (pci_is_enabled(dev))
1159 return;
1160 retval = pci_enable_device(dev);
1161 if (retval)
1162 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1163 retval);
1164 pci_set_master(dev);
1165}
1166
1148static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) 1167static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1149{ 1168{
1150 int err; 1169 int err;
@@ -1165,6 +1184,8 @@ static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1165 if (atomic_inc_return(&dev->enable_cnt) > 1) 1184 if (atomic_inc_return(&dev->enable_cnt) > 1)
1166 return 0; /* already enabled */ 1185 return 0; /* already enabled */
1167 1186
1187 pci_enable_bridge(dev->bus->self);
1188
1168 /* only skip sriov related */ 1189 /* only skip sriov related */
1169 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1190 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1170 if (dev->resource[i].flags & flags) 1191 if (dev->resource[i].flags & flags)
@@ -1992,7 +2013,7 @@ static void pci_add_saved_cap(struct pci_dev *pci_dev,
1992} 2013}
1993 2014
1994/** 2015/**
1995 * pci_add_save_buffer - allocate buffer for saving given capability registers 2016 * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
1996 * @dev: the PCI device 2017 * @dev: the PCI device
1997 * @cap: the capability to allocate the buffer for 2018 * @cap: the capability to allocate the buffer for
1998 * @size: requested size of the buffer 2019 * @size: requested size of the buffer
@@ -2095,9 +2116,9 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2095 u16 ctrl = 0; 2116 u16 ctrl = 0;
2096 2117
2097 if (type & PCI_EXP_IDO_REQUEST) 2118 if (type & PCI_EXP_IDO_REQUEST)
2098 ctrl |= PCI_EXP_IDO_REQ_EN; 2119 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
2099 if (type & PCI_EXP_IDO_COMPLETION) 2120 if (type & PCI_EXP_IDO_COMPLETION)
2100 ctrl |= PCI_EXP_IDO_CMP_EN; 2121 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
2101 if (ctrl) 2122 if (ctrl)
2102 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl); 2123 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2103} 2124}
@@ -2113,9 +2134,9 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2113 u16 ctrl = 0; 2134 u16 ctrl = 0;
2114 2135
2115 if (type & PCI_EXP_IDO_REQUEST) 2136 if (type & PCI_EXP_IDO_REQUEST)
2116 ctrl |= PCI_EXP_IDO_REQ_EN; 2137 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
2117 if (type & PCI_EXP_IDO_COMPLETION) 2138 if (type & PCI_EXP_IDO_COMPLETION)
2118 ctrl |= PCI_EXP_IDO_CMP_EN; 2139 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
2119 if (ctrl) 2140 if (ctrl)
2120 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl); 2141 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2121} 2142}
@@ -2147,7 +2168,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2147 int ret; 2168 int ret;
2148 2169
2149 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2170 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2150 if (!(cap & PCI_EXP_OBFF_MASK)) 2171 if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
2151 return -ENOTSUPP; /* no OBFF support at all */ 2172 return -ENOTSUPP; /* no OBFF support at all */
2152 2173
2153 /* Make sure the topology supports OBFF as well */ 2174 /* Make sure the topology supports OBFF as well */
@@ -2158,17 +2179,17 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2158 } 2179 }
2159 2180
2160 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl); 2181 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2161 if (cap & PCI_EXP_OBFF_WAKE) 2182 if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
2162 ctrl |= PCI_EXP_OBFF_WAKE_EN; 2183 ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2163 else { 2184 else {
2164 switch (type) { 2185 switch (type) {
2165 case PCI_EXP_OBFF_SIGNAL_L0: 2186 case PCI_EXP_OBFF_SIGNAL_L0:
2166 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN)) 2187 if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
2167 ctrl |= PCI_EXP_OBFF_MSGA_EN; 2188 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
2168 break; 2189 break;
2169 case PCI_EXP_OBFF_SIGNAL_ALWAYS: 2190 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2170 ctrl &= ~PCI_EXP_OBFF_WAKE_EN; 2191 ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2171 ctrl |= PCI_EXP_OBFF_MSGB_EN; 2192 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
2172 break; 2193 break;
2173 default: 2194 default:
2174 WARN(1, "bad OBFF signal type\n"); 2195 WARN(1, "bad OBFF signal type\n");
@@ -2189,7 +2210,8 @@ EXPORT_SYMBOL(pci_enable_obff);
2189 */ 2210 */
2190void pci_disable_obff(struct pci_dev *dev) 2211void pci_disable_obff(struct pci_dev *dev)
2191{ 2212{
2192 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN); 2213 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2214 PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
2193} 2215}
2194EXPORT_SYMBOL(pci_disable_obff); 2216EXPORT_SYMBOL(pci_disable_obff);
2195 2217
@@ -2237,7 +2259,8 @@ int pci_enable_ltr(struct pci_dev *dev)
2237 return ret; 2259 return ret;
2238 } 2260 }
2239 2261
2240 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN); 2262 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2263 PCI_EXP_DEVCTL2_LTR_EN);
2241} 2264}
2242EXPORT_SYMBOL(pci_enable_ltr); 2265EXPORT_SYMBOL(pci_enable_ltr);
2243 2266
@@ -2254,7 +2277,8 @@ void pci_disable_ltr(struct pci_dev *dev)
2254 if (!pci_ltr_supported(dev)) 2277 if (!pci_ltr_supported(dev))
2255 return; 2278 return;
2256 2279
2257 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN); 2280 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2281 PCI_EXP_DEVCTL2_LTR_EN);
2258} 2282}
2259EXPORT_SYMBOL(pci_disable_ltr); 2283EXPORT_SYMBOL(pci_disable_ltr);
2260 2284
@@ -2359,6 +2383,27 @@ void pci_enable_acs(struct pci_dev *dev)
2359 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2383 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2360} 2384}
2361 2385
2386static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2387{
2388 int pos;
2389 u16 cap, ctrl;
2390
2391 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2392 if (!pos)
2393 return false;
2394
2395 /*
2396 * Except for egress control, capabilities are either required
2397 * or only required if controllable. Features missing from the
2398 * capability field can therefore be assumed as hard-wired enabled.
2399 */
2400 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2401 acs_flags &= (cap | PCI_ACS_EC);
2402
2403 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2404 return (ctrl & acs_flags) == acs_flags;
2405}
2406
2362/** 2407/**
2363 * pci_acs_enabled - test ACS against required flags for a given device 2408 * pci_acs_enabled - test ACS against required flags for a given device
2364 * @pdev: device to test 2409 * @pdev: device to test
@@ -2366,36 +2411,76 @@ void pci_enable_acs(struct pci_dev *dev)
2366 * 2411 *
2367 * Return true if the device supports the provided flags. Automatically 2412 * Return true if the device supports the provided flags. Automatically
2368 * filters out flags that are not implemented on multifunction devices. 2413 * filters out flags that are not implemented on multifunction devices.
2414 *
2415 * Note that this interface checks the effective ACS capabilities of the
2416 * device rather than the actual capabilities. For instance, most single
2417 * function endpoints are not required to support ACS because they have no
2418 * opportunity for peer-to-peer access. We therefore return 'true'
2419 * regardless of whether the device exposes an ACS capability. This makes
2420 * it much easier for callers of this function to ignore the actual type
2421 * or topology of the device when testing ACS support.
2369 */ 2422 */
2370bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2423bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2371{ 2424{
2372 int pos, ret; 2425 int ret;
2373 u16 ctrl;
2374 2426
2375 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2427 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2376 if (ret >= 0) 2428 if (ret >= 0)
2377 return ret > 0; 2429 return ret > 0;
2378 2430
2431 /*
2432 * Conventional PCI and PCI-X devices never support ACS, either
2433 * effectively or actually. The shared bus topology implies that
2434 * any device on the bus can receive or snoop DMA.
2435 */
2379 if (!pci_is_pcie(pdev)) 2436 if (!pci_is_pcie(pdev))
2380 return false; 2437 return false;
2381 2438
2382 /* Filter out flags not applicable to multifunction */ 2439 switch (pci_pcie_type(pdev)) {
2383 if (pdev->multifunction) 2440 /*
2384 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | 2441 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2385 PCI_ACS_EC | PCI_ACS_DT); 2442 * but since their primary inteface is PCI/X, we conservatively
2386 2443 * handle them as we would a non-PCIe device.
2387 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM || 2444 */
2388 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || 2445 case PCI_EXP_TYPE_PCIE_BRIDGE:
2389 pdev->multifunction) { 2446 /*
2390 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2447 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2391 if (!pos) 2448 * applicable... must never implement an ACS Extended Capability...".
2392 return false; 2449 * This seems arbitrary, but we take a conservative interpretation
2450 * of this statement.
2451 */
2452 case PCI_EXP_TYPE_PCI_BRIDGE:
2453 case PCI_EXP_TYPE_RC_EC:
2454 return false;
2455 /*
2456 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2457 * implement ACS in order to indicate their peer-to-peer capabilities,
2458 * regardless of whether they are single- or multi-function devices.
2459 */
2460 case PCI_EXP_TYPE_DOWNSTREAM:
2461 case PCI_EXP_TYPE_ROOT_PORT:
2462 return pci_acs_flags_enabled(pdev, acs_flags);
2463 /*
2464 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2465 * implemented by the remaining PCIe types to indicate peer-to-peer
2466 * capabilities, but only when they are part of a multifunciton
2467 * device. The footnote for section 6.12 indicates the specific
2468 * PCIe types included here.
2469 */
2470 case PCI_EXP_TYPE_ENDPOINT:
2471 case PCI_EXP_TYPE_UPSTREAM:
2472 case PCI_EXP_TYPE_LEG_END:
2473 case PCI_EXP_TYPE_RC_END:
2474 if (!pdev->multifunction)
2475 break;
2393 2476
2394 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2477 return pci_acs_flags_enabled(pdev, acs_flags);
2395 if ((ctrl & acs_flags) != acs_flags)
2396 return false;
2397 } 2478 }
2398 2479
2480 /*
2481 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable
2482 * to single function devices with the exception of downstream ports.
2483 */
2399 return true; 2484 return true;
2400} 2485}
2401 2486
@@ -3059,18 +3144,23 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev)
3059EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 3144EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3060 3145
3061/** 3146/**
3062 * pci_msi_off - disables any msi or msix capabilities 3147 * pci_msi_off - disables any MSI or MSI-X capabilities
3063 * @dev: the PCI device to operate on 3148 * @dev: the PCI device to operate on
3064 * 3149 *
3065 * If you want to use msi see pci_enable_msi and friends. 3150 * If you want to use MSI, see pci_enable_msi() and friends.
3066 * This is a lower level primitive that allows us to disable 3151 * This is a lower-level primitive that allows us to disable
3067 * msi operation at the device level. 3152 * MSI operation at the device level.
3068 */ 3153 */
3069void pci_msi_off(struct pci_dev *dev) 3154void pci_msi_off(struct pci_dev *dev)
3070{ 3155{
3071 int pos; 3156 int pos;
3072 u16 control; 3157 u16 control;
3073 3158
3159 /*
3160 * This looks like it could go in msi.c, but we need it even when
3161 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3162 * dev->msi_cap or dev->msix_cap here.
3163 */
3074 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 3164 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3075 if (pos) { 3165 if (pos) {
3076 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 3166 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
@@ -3098,19 +3188,17 @@ int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3098} 3188}
3099EXPORT_SYMBOL(pci_set_dma_seg_boundary); 3189EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3100 3190
3101static int pcie_flr(struct pci_dev *dev, int probe) 3191/**
3192 * pci_wait_for_pending_transaction - waits for pending transaction
3193 * @dev: the PCI device to operate on
3194 *
3195 * Return 0 if transaction is pending 1 otherwise.
3196 */
3197int pci_wait_for_pending_transaction(struct pci_dev *dev)
3102{ 3198{
3103 int i; 3199 int i;
3104 u32 cap;
3105 u16 status; 3200 u16 status;
3106 3201
3107 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3108 if (!(cap & PCI_EXP_DEVCAP_FLR))
3109 return -ENOTTY;
3110
3111 if (probe)
3112 return 0;
3113
3114 /* Wait for Transaction Pending bit clean */ 3202 /* Wait for Transaction Pending bit clean */
3115 for (i = 0; i < 4; i++) { 3203 for (i = 0; i < 4; i++) {
3116 if (i) 3204 if (i)
@@ -3118,13 +3206,27 @@ static int pcie_flr(struct pci_dev *dev, int probe)
3118 3206
3119 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 3207 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3120 if (!(status & PCI_EXP_DEVSTA_TRPND)) 3208 if (!(status & PCI_EXP_DEVSTA_TRPND))
3121 goto clear; 3209 return 1;
3122 } 3210 }
3123 3211
3124 dev_err(&dev->dev, "transaction is not cleared; " 3212 return 0;
3125 "proceeding with reset anyway\n"); 3213}
3214EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3215
3216static int pcie_flr(struct pci_dev *dev, int probe)
3217{
3218 u32 cap;
3219
3220 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3221 if (!(cap & PCI_EXP_DEVCAP_FLR))
3222 return -ENOTTY;
3223
3224 if (probe)
3225 return 0;
3226
3227 if (!pci_wait_for_pending_transaction(dev))
3228 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3126 3229
3127clear:
3128 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3230 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3129 3231
3130 msleep(100); 3232 msleep(100);
@@ -3215,9 +3317,42 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
3215 return 0; 3317 return 0;
3216} 3318}
3217 3319
3218static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3320/**
3321 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3322 * @dev: Bridge device
3323 *
3324 * Use the bridge control register to assert reset on the secondary bus.
3325 * Devices on the secondary bus are left in power-on state.
3326 */
3327void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3219{ 3328{
3220 u16 ctrl; 3329 u16 ctrl;
3330
3331 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3332 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3333 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3334 /*
3335 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3336 * this to 2ms to ensure that we meet the minium requirement.
3337 */
3338 msleep(2);
3339
3340 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3341 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3342
3343 /*
3344 * Trhfa for conventional PCI is 2^25 clock cycles.
3345 * Assuming a minimum 33MHz clock this results in a 1s
3346 * delay before we can consider subordinate devices to
3347 * be re-initialized. PCIe has some ways to shorten this,
3348 * but we don't make use of them yet.
3349 */
3350 ssleep(1);
3351}
3352EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3353
3354static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3355{
3221 struct pci_dev *pdev; 3356 struct pci_dev *pdev;
3222 3357
3223 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 3358 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
@@ -3230,18 +3365,40 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3230 if (probe) 3365 if (probe)
3231 return 0; 3366 return 0;
3232 3367
3233 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); 3368 pci_reset_bridge_secondary_bus(dev->bus->self);
3234 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3235 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3236 msleep(100);
3237
3238 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3239 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3240 msleep(100);
3241 3369
3242 return 0; 3370 return 0;
3243} 3371}
3244 3372
3373static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3374{
3375 int rc = -ENOTTY;
3376
3377 if (!hotplug || !try_module_get(hotplug->ops->owner))
3378 return rc;
3379
3380 if (hotplug->ops->reset_slot)
3381 rc = hotplug->ops->reset_slot(hotplug, probe);
3382
3383 module_put(hotplug->ops->owner);
3384
3385 return rc;
3386}
3387
3388static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3389{
3390 struct pci_dev *pdev;
3391
3392 if (dev->subordinate || !dev->slot)
3393 return -ENOTTY;
3394
3395 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3396 if (pdev != dev && pdev->slot == dev->slot)
3397 return -ENOTTY;
3398
3399 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3400}
3401
3245static int __pci_dev_reset(struct pci_dev *dev, int probe) 3402static int __pci_dev_reset(struct pci_dev *dev, int probe)
3246{ 3403{
3247 int rc; 3404 int rc;
@@ -3264,27 +3421,65 @@ static int __pci_dev_reset(struct pci_dev *dev, int probe)
3264 if (rc != -ENOTTY) 3421 if (rc != -ENOTTY)
3265 goto done; 3422 goto done;
3266 3423
3424 rc = pci_dev_reset_slot_function(dev, probe);
3425 if (rc != -ENOTTY)
3426 goto done;
3427
3267 rc = pci_parent_bus_reset(dev, probe); 3428 rc = pci_parent_bus_reset(dev, probe);
3268done: 3429done:
3269 return rc; 3430 return rc;
3270} 3431}
3271 3432
3433static void pci_dev_lock(struct pci_dev *dev)
3434{
3435 pci_cfg_access_lock(dev);
3436 /* block PM suspend, driver probe, etc. */
3437 device_lock(&dev->dev);
3438}
3439
3440static void pci_dev_unlock(struct pci_dev *dev)
3441{
3442 device_unlock(&dev->dev);
3443 pci_cfg_access_unlock(dev);
3444}
3445
3446static void pci_dev_save_and_disable(struct pci_dev *dev)
3447{
3448 /*
3449 * Wake-up device prior to save. PM registers default to D0 after
3450 * reset and a simple register restore doesn't reliably return
3451 * to a non-D0 state anyway.
3452 */
3453 pci_set_power_state(dev, PCI_D0);
3454
3455 pci_save_state(dev);
3456 /*
3457 * Disable the device by clearing the Command register, except for
3458 * INTx-disable which is set. This not only disables MMIO and I/O port
3459 * BARs, but also prevents the device from being Bus Master, preventing
3460 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3461 * compliant devices, INTx-disable prevents legacy interrupts.
3462 */
3463 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3464}
3465
3466static void pci_dev_restore(struct pci_dev *dev)
3467{
3468 pci_restore_state(dev);
3469}
3470
3272static int pci_dev_reset(struct pci_dev *dev, int probe) 3471static int pci_dev_reset(struct pci_dev *dev, int probe)
3273{ 3472{
3274 int rc; 3473 int rc;
3275 3474
3276 if (!probe) { 3475 if (!probe)
3277 pci_cfg_access_lock(dev); 3476 pci_dev_lock(dev);
3278 /* block PM suspend, driver probe, etc. */
3279 device_lock(&dev->dev);
3280 }
3281 3477
3282 rc = __pci_dev_reset(dev, probe); 3478 rc = __pci_dev_reset(dev, probe);
3283 3479
3284 if (!probe) { 3480 if (!probe)
3285 device_unlock(&dev->dev); 3481 pci_dev_unlock(dev);
3286 pci_cfg_access_unlock(dev); 3482
3287 }
3288 return rc; 3483 return rc;
3289} 3484}
3290/** 3485/**
@@ -3375,22 +3570,249 @@ int pci_reset_function(struct pci_dev *dev)
3375 if (rc) 3570 if (rc)
3376 return rc; 3571 return rc;
3377 3572
3378 pci_save_state(dev); 3573 pci_dev_save_and_disable(dev);
3379
3380 /*
3381 * both INTx and MSI are disabled after the Interrupt Disable bit
3382 * is set and the Bus Master bit is cleared.
3383 */
3384 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3385 3574
3386 rc = pci_dev_reset(dev, 0); 3575 rc = pci_dev_reset(dev, 0);
3387 3576
3388 pci_restore_state(dev); 3577 pci_dev_restore(dev);
3389 3578
3390 return rc; 3579 return rc;
3391} 3580}
3392EXPORT_SYMBOL_GPL(pci_reset_function); 3581EXPORT_SYMBOL_GPL(pci_reset_function);
3393 3582
3583/* Lock devices from the top of the tree down */
3584static void pci_bus_lock(struct pci_bus *bus)
3585{
3586 struct pci_dev *dev;
3587
3588 list_for_each_entry(dev, &bus->devices, bus_list) {
3589 pci_dev_lock(dev);
3590 if (dev->subordinate)
3591 pci_bus_lock(dev->subordinate);
3592 }
3593}
3594
3595/* Unlock devices from the bottom of the tree up */
3596static void pci_bus_unlock(struct pci_bus *bus)
3597{
3598 struct pci_dev *dev;
3599
3600 list_for_each_entry(dev, &bus->devices, bus_list) {
3601 if (dev->subordinate)
3602 pci_bus_unlock(dev->subordinate);
3603 pci_dev_unlock(dev);
3604 }
3605}
3606
3607/* Lock devices from the top of the tree down */
3608static void pci_slot_lock(struct pci_slot *slot)
3609{
3610 struct pci_dev *dev;
3611
3612 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3613 if (!dev->slot || dev->slot != slot)
3614 continue;
3615 pci_dev_lock(dev);
3616 if (dev->subordinate)
3617 pci_bus_lock(dev->subordinate);
3618 }
3619}
3620
3621/* Unlock devices from the bottom of the tree up */
3622static void pci_slot_unlock(struct pci_slot *slot)
3623{
3624 struct pci_dev *dev;
3625
3626 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3627 if (!dev->slot || dev->slot != slot)
3628 continue;
3629 if (dev->subordinate)
3630 pci_bus_unlock(dev->subordinate);
3631 pci_dev_unlock(dev);
3632 }
3633}
3634
3635/* Save and disable devices from the top of the tree down */
3636static void pci_bus_save_and_disable(struct pci_bus *bus)
3637{
3638 struct pci_dev *dev;
3639
3640 list_for_each_entry(dev, &bus->devices, bus_list) {
3641 pci_dev_save_and_disable(dev);
3642 if (dev->subordinate)
3643 pci_bus_save_and_disable(dev->subordinate);
3644 }
3645}
3646
3647/*
3648 * Restore devices from top of the tree down - parent bridges need to be
3649 * restored before we can get to subordinate devices.
3650 */
3651static void pci_bus_restore(struct pci_bus *bus)
3652{
3653 struct pci_dev *dev;
3654
3655 list_for_each_entry(dev, &bus->devices, bus_list) {
3656 pci_dev_restore(dev);
3657 if (dev->subordinate)
3658 pci_bus_restore(dev->subordinate);
3659 }
3660}
3661
3662/* Save and disable devices from the top of the tree down */
3663static void pci_slot_save_and_disable(struct pci_slot *slot)
3664{
3665 struct pci_dev *dev;
3666
3667 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3668 if (!dev->slot || dev->slot != slot)
3669 continue;
3670 pci_dev_save_and_disable(dev);
3671 if (dev->subordinate)
3672 pci_bus_save_and_disable(dev->subordinate);
3673 }
3674}
3675
3676/*
3677 * Restore devices from top of the tree down - parent bridges need to be
3678 * restored before we can get to subordinate devices.
3679 */
3680static void pci_slot_restore(struct pci_slot *slot)
3681{
3682 struct pci_dev *dev;
3683
3684 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3685 if (!dev->slot || dev->slot != slot)
3686 continue;
3687 pci_dev_restore(dev);
3688 if (dev->subordinate)
3689 pci_bus_restore(dev->subordinate);
3690 }
3691}
3692
3693static int pci_slot_reset(struct pci_slot *slot, int probe)
3694{
3695 int rc;
3696
3697 if (!slot)
3698 return -ENOTTY;
3699
3700 if (!probe)
3701 pci_slot_lock(slot);
3702
3703 might_sleep();
3704
3705 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3706
3707 if (!probe)
3708 pci_slot_unlock(slot);
3709
3710 return rc;
3711}
3712
3713/**
3714 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3715 * @slot: PCI slot to probe
3716 *
3717 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3718 */
3719int pci_probe_reset_slot(struct pci_slot *slot)
3720{
3721 return pci_slot_reset(slot, 1);
3722}
3723EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3724
3725/**
3726 * pci_reset_slot - reset a PCI slot
3727 * @slot: PCI slot to reset
3728 *
3729 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3730 * independent of other slots. For instance, some slots may support slot power
3731 * control. In the case of a 1:1 bus to slot architecture, this function may
3732 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3733 * Generally a slot reset should be attempted before a bus reset. All of the
3734 * function of the slot and any subordinate buses behind the slot are reset
3735 * through this function. PCI config space of all devices in the slot and
3736 * behind the slot is saved before and restored after reset.
3737 *
3738 * Return 0 on success, non-zero on error.
3739 */
3740int pci_reset_slot(struct pci_slot *slot)
3741{
3742 int rc;
3743
3744 rc = pci_slot_reset(slot, 1);
3745 if (rc)
3746 return rc;
3747
3748 pci_slot_save_and_disable(slot);
3749
3750 rc = pci_slot_reset(slot, 0);
3751
3752 pci_slot_restore(slot);
3753
3754 return rc;
3755}
3756EXPORT_SYMBOL_GPL(pci_reset_slot);
3757
3758static int pci_bus_reset(struct pci_bus *bus, int probe)
3759{
3760 if (!bus->self)
3761 return -ENOTTY;
3762
3763 if (probe)
3764 return 0;
3765
3766 pci_bus_lock(bus);
3767
3768 might_sleep();
3769
3770 pci_reset_bridge_secondary_bus(bus->self);
3771
3772 pci_bus_unlock(bus);
3773
3774 return 0;
3775}
3776
3777/**
3778 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3779 * @bus: PCI bus to probe
3780 *
3781 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3782 */
3783int pci_probe_reset_bus(struct pci_bus *bus)
3784{
3785 return pci_bus_reset(bus, 1);
3786}
3787EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3788
3789/**
3790 * pci_reset_bus - reset a PCI bus
3791 * @bus: top level PCI bus to reset
3792 *
3793 * Do a bus reset on the given bus and any subordinate buses, saving
3794 * and restoring state of all devices.
3795 *
3796 * Return 0 on success, non-zero on error.
3797 */
3798int pci_reset_bus(struct pci_bus *bus)
3799{
3800 int rc;
3801
3802 rc = pci_bus_reset(bus, 1);
3803 if (rc)
3804 return rc;
3805
3806 pci_bus_save_and_disable(bus);
3807
3808 rc = pci_bus_reset(bus, 0);
3809
3810 pci_bus_restore(bus);
3811
3812 return rc;
3813}
3814EXPORT_SYMBOL_GPL(pci_reset_bus);
3815
3394/** 3816/**
3395 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 3817 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3396 * @dev: PCI device to query 3818 * @dev: PCI device to query
@@ -3525,8 +3947,6 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
3525 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 3947 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3526 int mps = pcie_get_mps(dev); 3948 int mps = pcie_get_mps(dev);
3527 3949
3528 if (mps < 0)
3529 return mps;
3530 if (mps < rq) 3950 if (mps < rq)
3531 rq = mps; 3951 rq = mps;
3532 } 3952 }
@@ -3543,7 +3963,6 @@ EXPORT_SYMBOL(pcie_set_readrq);
3543 * @dev: PCI device to query 3963 * @dev: PCI device to query
3544 * 3964 *
3545 * Returns maximum payload size in bytes 3965 * Returns maximum payload size in bytes
3546 * or appropriate error value.
3547 */ 3966 */
3548int pcie_get_mps(struct pci_dev *dev) 3967int pcie_get_mps(struct pci_dev *dev)
3549{ 3968{
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d1182c4a754e..816c297f170c 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -151,7 +151,7 @@ static inline int pci_no_d1d2(struct pci_dev *dev)
151 151
152} 152}
153extern struct device_attribute pci_dev_attrs[]; 153extern struct device_attribute pci_dev_attrs[];
154extern struct device_attribute pcibus_dev_attrs[]; 154extern const struct attribute_group *pcibus_groups[];
155extern struct device_type pci_dev_type; 155extern struct device_type pci_dev_type;
156extern struct bus_attribute pci_bus_attrs[]; 156extern struct bus_attribute pci_bus_attrs[];
157 157
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 3b94cfcfa03b..7958e59d6077 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -2,7 +2,7 @@
2# PCI Express Port Bus Configuration 2# PCI Express Port Bus Configuration
3# 3#
4config PCIEPORTBUS 4config PCIEPORTBUS
5 bool "PCI Express support" 5 bool "PCI Express Port Bus support"
6 depends on PCI 6 depends on PCI
7 help 7 help
8 This automatically enables PCI Express Port Bus support. Users can 8 This automatically enables PCI Express Port Bus support. Users can
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 76ef634caf6f..0bf82a20a0fb 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -352,7 +352,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
352 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 352 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
353 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); 353 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
354 354
355 aer_do_secondary_bus_reset(dev); 355 pci_reset_bridge_secondary_bus(dev);
356 dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n"); 356 dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");
357 357
358 /* Clear Root Error Status */ 358 /* Clear Root Error Status */
diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h
index 90ea3e88041f..84420b7c9456 100644
--- a/drivers/pci/pcie/aer/aerdrv.h
+++ b/drivers/pci/pcie/aer/aerdrv.h
@@ -106,7 +106,6 @@ static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
106} 106}
107 107
108extern struct bus_type pcie_port_bus_type; 108extern struct bus_type pcie_port_bus_type;
109void aer_do_secondary_bus_reset(struct pci_dev *dev);
110int aer_init(struct pcie_device *dev); 109int aer_init(struct pcie_device *dev);
111void aer_isr(struct work_struct *work); 110void aer_isr(struct work_struct *work);
112void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 111void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 8b68ae59b7b6..85ca36f2136d 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -367,39 +367,6 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
367} 367}
368 368
369/** 369/**
370 * aer_do_secondary_bus_reset - perform secondary bus reset
371 * @dev: pointer to bridge's pci_dev data structure
372 *
373 * Invoked when performing link reset at Root Port or Downstream Port.
374 */
375void aer_do_secondary_bus_reset(struct pci_dev *dev)
376{
377 u16 p2p_ctrl;
378
379 /* Assert Secondary Bus Reset */
380 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);
381 p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
382 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);
383
384 /*
385 * we should send hot reset message for 2ms to allow it time to
386 * propagate to all downstream ports
387 */
388 msleep(2);
389
390 /* De-assert Secondary Bus Reset */
391 p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
392 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);
393
394 /*
395 * System software must wait for at least 100ms from the end
396 * of a reset of one or more device before it is permitted
397 * to issue Configuration Requests to those devices.
398 */
399 msleep(200);
400}
401
402/**
403 * default_reset_link - default reset function 370 * default_reset_link - default reset function
404 * @dev: pointer to pci_dev data structure 371 * @dev: pointer to pci_dev data structure
405 * 372 *
@@ -408,7 +375,7 @@ void aer_do_secondary_bus_reset(struct pci_dev *dev)
408 */ 375 */
409static pci_ers_result_t default_reset_link(struct pci_dev *dev) 376static pci_ers_result_t default_reset_link(struct pci_dev *dev)
410{ 377{
411 aer_do_secondary_bus_reset(dev); 378 pci_reset_bridge_secondary_bus(dev);
412 dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n"); 379 dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");
413 return PCI_ERS_RESULT_RECOVERED; 380 return PCI_ERS_RESULT_RECOVERED;
414} 381}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 46ada5c098eb..eeb50bd62402 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -96,7 +96,7 @@ static void release_pcibus_dev(struct device *dev)
96static struct class pcibus_class = { 96static struct class pcibus_class = {
97 .name = "pci_bus", 97 .name = "pci_bus",
98 .dev_release = &release_pcibus_dev, 98 .dev_release = &release_pcibus_dev,
99 .dev_attrs = pcibus_dev_attrs, 99 .dev_groups = pcibus_groups,
100}; 100};
101 101
102static int __init pcibus_class_init(void) 102static int __init pcibus_class_init(void)
@@ -156,6 +156,8 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
156 return flags; 156 return flags;
157} 157}
158 158
159#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
160
159/** 161/**
160 * pci_read_base - read a PCI BAR 162 * pci_read_base - read a PCI BAR
161 * @dev: the PCI device 163 * @dev: the PCI device
@@ -178,8 +180,10 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 /* No printks while decoding is disabled! */ 180 /* No printks while decoding is disabled! */
179 if (!dev->mmio_always_on) { 181 if (!dev->mmio_always_on) {
180 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 182 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
181 pci_write_config_word(dev, PCI_COMMAND, 183 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
182 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 184 pci_write_config_word(dev, PCI_COMMAND,
185 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
186 }
183 } 187 }
184 188
185 res->name = pci_name(dev); 189 res->name = pci_name(dev);
@@ -293,7 +297,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
293fail: 297fail:
294 res->flags = 0; 298 res->flags = 0;
295out: 299out:
296 if (!dev->mmio_always_on) 300 if (!dev->mmio_always_on &&
301 (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
297 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 302 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
298 303
299 if (bar_too_big) 304 if (bar_too_big)
@@ -1491,24 +1496,23 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data)
1491 if (!pci_is_pcie(dev)) 1496 if (!pci_is_pcie(dev))
1492 return 0; 1497 return 0;
1493 1498
1494 /* For PCIE hotplug enabled slots not connected directly to a 1499 /*
1495 * PCI-E root port, there can be problems when hotplugging 1500 * We don't have a way to change MPS settings on devices that have
1496 * devices. This is due to the possibility of hotplugging a 1501 * drivers attached. A hot-added device might support only the minimum
1497 * device into the fabric with a smaller MPS that the devices 1502 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1498 * currently running have configured. Modifying the MPS on the 1503 * where devices may be hot-added, we limit the fabric MPS to 128 so
1499 * running devices could cause a fatal bus error due to an 1504 * hot-added devices will work correctly.
1500 * incoming frame being larger than the newly configured MPS. 1505 *
1501 * To work around this, the MPS for the entire fabric must be 1506 * However, if we hot-add a device to a slot directly below a Root
1502 * set to the minimum size. Any devices hotplugged into this 1507 * Port, it's impossible for there to be other existing devices below
1503 * fabric will have the minimum MPS set. If the PCI hotplug 1508 * the port. We don't limit the MPS in this case because we can
1504 * slot is directly connected to the root port and there are not 1509 * reconfigure MPS on both the Root Port and the hot-added device,
1505 * other devices on the fabric (which seems to be the most 1510 * and there are no other devices involved.
1506 * common case), then this is not an issue and MPS discovery 1511 *
1507 * will occur as normal. 1512 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1508 */ 1513 */
1509 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) || 1514 if (dev->is_hotplug_bridge &&
1510 (dev->bus->self && 1515 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1511 pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
1512 *smpss = 0; 1516 *smpss = 0;
1513 1517
1514 if (*smpss > dev->pcie_mpss) 1518 if (*smpss > dev->pcie_mpss)
@@ -1583,6 +1587,22 @@ static void pcie_write_mrrs(struct pci_dev *dev)
1583 "with pci=pcie_bus_safe.\n"); 1587 "with pci=pcie_bus_safe.\n");
1584} 1588}
1585 1589
1590static void pcie_bus_detect_mps(struct pci_dev *dev)
1591{
1592 struct pci_dev *bridge = dev->bus->self;
1593 int mps, p_mps;
1594
1595 if (!bridge)
1596 return;
1597
1598 mps = pcie_get_mps(dev);
1599 p_mps = pcie_get_mps(bridge);
1600
1601 if (mps != p_mps)
1602 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1603 mps, pci_name(bridge), p_mps);
1604}
1605
1586static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 1606static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1587{ 1607{
1588 int mps, orig_mps; 1608 int mps, orig_mps;
@@ -1590,13 +1610,18 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1590 if (!pci_is_pcie(dev)) 1610 if (!pci_is_pcie(dev))
1591 return 0; 1611 return 0;
1592 1612
1613 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1614 pcie_bus_detect_mps(dev);
1615 return 0;
1616 }
1617
1593 mps = 128 << *(u8 *)data; 1618 mps = 128 << *(u8 *)data;
1594 orig_mps = pcie_get_mps(dev); 1619 orig_mps = pcie_get_mps(dev);
1595 1620
1596 pcie_write_mps(dev, mps); 1621 pcie_write_mps(dev, mps);
1597 pcie_write_mrrs(dev); 1622 pcie_write_mrrs(dev);
1598 1623
1599 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), " 1624 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), "
1600 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss, 1625 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1601 orig_mps, pcie_get_readrq(dev)); 1626 orig_mps, pcie_get_readrq(dev));
1602 1627
@@ -1607,25 +1632,25 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1607 * parents then children fashion. If this changes, then this code will not 1632 * parents then children fashion. If this changes, then this code will not
1608 * work as designed. 1633 * work as designed.
1609 */ 1634 */
1610void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss) 1635void pcie_bus_configure_settings(struct pci_bus *bus)
1611{ 1636{
1612 u8 smpss; 1637 u8 smpss;
1613 1638
1614 if (!pci_is_pcie(bus->self)) 1639 if (!bus->self)
1615 return; 1640 return;
1616 1641
1617 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 1642 if (!pci_is_pcie(bus->self))
1618 return; 1643 return;
1619 1644
1620 /* FIXME - Peer to peer DMA is possible, though the endpoint would need 1645 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1621 * to be aware to the MPS of the destination. To work around this, 1646 * to be aware of the MPS of the destination. To work around this,
1622 * simply force the MPS of the entire system to the smallest possible. 1647 * simply force the MPS of the entire system to the smallest possible.
1623 */ 1648 */
1624 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 1649 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1625 smpss = 0; 1650 smpss = 0;
1626 1651
1627 if (pcie_bus_config == PCIE_BUS_SAFE) { 1652 if (pcie_bus_config == PCIE_BUS_SAFE) {
1628 smpss = mpss; 1653 smpss = bus->self->pcie_mpss;
1629 1654
1630 pcie_find_smpss(bus->self, &smpss); 1655 pcie_find_smpss(bus->self, &smpss);
1631 pci_walk_bus(bus, pcie_find_smpss, &smpss); 1656 pci_walk_bus(bus, pcie_find_smpss, &smpss);
@@ -1979,7 +2004,6 @@ unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1979 2004
1980 max = pci_scan_child_bus(bus); 2005 max = pci_scan_child_bus(bus);
1981 pci_assign_unassigned_bus_resources(bus); 2006 pci_assign_unassigned_bus_resources(bus);
1982 pci_enable_bridges(bus);
1983 pci_bus_add_devices(bus); 2007 pci_bus_add_devices(bus);
1984 2008
1985 return max; 2009 return max;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index e85d23044ae0..f6c31fabf3af 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3126,9 +3126,6 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3126 3126
3127static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3127static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3128{ 3128{
3129 int i;
3130 u16 status;
3131
3132 /* 3129 /*
3133 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3130 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3134 * 3131 *
@@ -3140,20 +3137,9 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3140 if (probe) 3137 if (probe)
3141 return 0; 3138 return 0;
3142 3139
3143 /* Wait for Transaction Pending bit clean */ 3140 if (!pci_wait_for_pending_transaction(dev))
3144 for (i = 0; i < 4; i++) { 3141 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3145 if (i)
3146 msleep((1 << (i - 1)) * 100);
3147
3148 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3149 if (!(status & PCI_EXP_DEVSTA_TRPND))
3150 goto clear;
3151 }
3152
3153 dev_err(&dev->dev, "transaction is not cleared; "
3154 "proceeding with reset anyway\n");
3155 3142
3156clear:
3157 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3143 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3158 3144
3159 msleep(100); 3145 msleep(100);
@@ -3208,6 +3194,83 @@ reset_complete:
3208 return 0; 3194 return 0;
3209} 3195}
3210 3196
3197/*
3198 * Device-specific reset method for Chelsio T4-based adapters.
3199 */
3200static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3201{
3202 u16 old_command;
3203 u16 msix_flags;
3204
3205 /*
3206 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3207 * that we have no device-specific reset method.
3208 */
3209 if ((dev->device & 0xf000) != 0x4000)
3210 return -ENOTTY;
3211
3212 /*
3213 * If this is the "probe" phase, return 0 indicating that we can
3214 * reset this device.
3215 */
3216 if (probe)
3217 return 0;
3218
3219 /*
3220 * T4 can wedge if there are DMAs in flight within the chip and Bus
3221 * Master has been disabled. We need to have it on till the Function
3222 * Level Reset completes. (BUS_MASTER is disabled in
3223 * pci_reset_function()).
3224 */
3225 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3226 pci_write_config_word(dev, PCI_COMMAND,
3227 old_command | PCI_COMMAND_MASTER);
3228
3229 /*
3230 * Perform the actual device function reset, saving and restoring
3231 * configuration information around the reset.
3232 */
3233 pci_save_state(dev);
3234
3235 /*
3236 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3237 * are disabled when an MSI-X interrupt message needs to be delivered.
3238 * So we briefly re-enable MSI-X interrupts for the duration of the
3239 * FLR. The pci_restore_state() below will restore the original
3240 * MSI-X state.
3241 */
3242 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3243 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3244 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3245 msix_flags |
3246 PCI_MSIX_FLAGS_ENABLE |
3247 PCI_MSIX_FLAGS_MASKALL);
3248
3249 /*
3250 * Start of pcie_flr() code sequence. This reset code is a copy of
3251 * the guts of pcie_flr() because that's not an exported function.
3252 */
3253
3254 if (!pci_wait_for_pending_transaction(dev))
3255 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3256
3257 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3258 msleep(100);
3259
3260 /*
3261 * End of pcie_flr() code sequence.
3262 */
3263
3264 /*
3265 * Restore the configuration information (BAR values, etc.) including
3266 * the original PCI Configuration Space Command word, and return
3267 * success.
3268 */
3269 pci_restore_state(dev);
3270 pci_write_config_word(dev, PCI_COMMAND, old_command);
3271 return 0;
3272}
3273
3211#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3274#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3212#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3275#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3213#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3276#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
@@ -3221,6 +3284,8 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3221 reset_ivb_igd }, 3284 reset_ivb_igd },
3222 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3285 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3223 reset_intel_generic_dev }, 3286 reset_intel_generic_dev },
3287 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3288 reset_chelsio_generic_dev },
3224 { 0 } 3289 { 0 }
3225}; 3290};
3226 3291
@@ -3295,11 +3360,61 @@ struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3295 return pci_dev_get(dev); 3360 return pci_dev_get(dev);
3296} 3361}
3297 3362
3363/*
3364 * AMD has indicated that the devices below do not support peer-to-peer
3365 * in any system where they are found in the southbridge with an AMD
3366 * IOMMU in the system. Multifunction devices that do not support
3367 * peer-to-peer between functions can claim to support a subset of ACS.
3368 * Such devices effectively enable request redirect (RR) and completion
3369 * redirect (CR) since all transactions are redirected to the upstream
3370 * root complex.
3371 *
3372 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3373 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3374 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3375 *
3376 * 1002:4385 SBx00 SMBus Controller
3377 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3378 * 1002:4383 SBx00 Azalia (Intel HDA)
3379 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3380 * 1002:4384 SBx00 PCI to PCI Bridge
3381 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3382 */
3383static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3384{
3385#ifdef CONFIG_ACPI
3386 struct acpi_table_header *header = NULL;
3387 acpi_status status;
3388
3389 /* Targeting multifunction devices on the SB (appears on root bus) */
3390 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3391 return -ENODEV;
3392
3393 /* The IVRS table describes the AMD IOMMU */
3394 status = acpi_get_table("IVRS", 0, &header);
3395 if (ACPI_FAILURE(status))
3396 return -ENODEV;
3397
3398 /* Filter out flags not applicable to multifunction */
3399 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3400
3401 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3402#else
3403 return -ENODEV;
3404#endif
3405}
3406
3298static const struct pci_dev_acs_enabled { 3407static const struct pci_dev_acs_enabled {
3299 u16 vendor; 3408 u16 vendor;
3300 u16 device; 3409 u16 device;
3301 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 3410 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3302} pci_dev_acs_enabled[] = { 3411} pci_dev_acs_enabled[] = {
3412 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3413 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3414 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3415 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3416 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3417 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3303 { 0 } 3418 { 0 }
3304}; 3419};
3305 3420
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 64a7de22d9af..bc26d7990cc3 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -814,14 +814,14 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
814{ 814{
815 struct pci_dev *dev; 815 struct pci_dev *dev;
816 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 816 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
817 unsigned long size = 0, size0 = 0, size1 = 0; 817 resource_size_t size = 0, size0 = 0, size1 = 0;
818 resource_size_t children_add_size = 0; 818 resource_size_t children_add_size = 0;
819 resource_size_t min_align, io_align, align; 819 resource_size_t min_align, align;
820 820
821 if (!b_res) 821 if (!b_res)
822 return; 822 return;
823 823
824 io_align = min_align = window_alignment(bus, IORESOURCE_IO); 824 min_align = window_alignment(bus, IORESOURCE_IO);
825 list_for_each_entry(dev, &bus->devices, bus_list) { 825 list_for_each_entry(dev, &bus->devices, bus_list) {
826 int i; 826 int i;
827 827
@@ -848,9 +848,6 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
848 } 848 }
849 } 849 }
850 850
851 if (min_align > io_align)
852 min_align = io_align;
853
854 size0 = calculate_iosize(size, min_size, size1, 851 size0 = calculate_iosize(size, min_size, size1,
855 resource_size(b_res), min_align); 852 resource_size(b_res), min_align);
856 if (children_add_size > add_size) 853 if (children_add_size > add_size)
@@ -874,8 +871,9 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
874 add_to_list(realloc_head, bus->self, b_res, size1-size0, 871 add_to_list(realloc_head, bus->self, b_res, size1-size0,
875 min_align); 872 min_align);
876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " 873 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877 "%pR to %pR add_size %lx\n", b_res, 874 "%pR to %pR add_size %llx\n", b_res,
878 &bus->busn_res, size1-size0); 875 &bus->busn_res,
876 (unsigned long long)size1-size0);
879 } 877 }
880} 878}
881 879
@@ -905,6 +903,8 @@ static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
905 * pbus_size_mem() - size the memory window of a given bus 903 * pbus_size_mem() - size the memory window of a given bus
906 * 904 *
907 * @bus : the bus 905 * @bus : the bus
906 * @mask: mask the resource flag, then compare it with type
907 * @type: the type of free resource from bridge
908 * @min_size : the minimum memory window that must to be allocated 908 * @min_size : the minimum memory window that must to be allocated
909 * @add_size : additional optional memory window 909 * @add_size : additional optional memory window
910 * @realloc_head : track the additional memory window on this list 910 * @realloc_head : track the additional memory window on this list
@@ -1364,39 +1364,21 @@ static void pci_bus_dump_resources(struct pci_bus *bus)
1364 } 1364 }
1365} 1365}
1366 1366
1367static int __init pci_bus_get_depth(struct pci_bus *bus) 1367static int pci_bus_get_depth(struct pci_bus *bus)
1368{ 1368{
1369 int depth = 0; 1369 int depth = 0;
1370 struct pci_dev *dev; 1370 struct pci_bus *child_bus;
1371 1371
1372 list_for_each_entry(dev, &bus->devices, bus_list) { 1372 list_for_each_entry(child_bus, &bus->children, node){
1373 int ret; 1373 int ret;
1374 struct pci_bus *b = dev->subordinate;
1375 if (!b)
1376 continue;
1377 1374
1378 ret = pci_bus_get_depth(b); 1375 ret = pci_bus_get_depth(child_bus);
1379 if (ret + 1 > depth) 1376 if (ret + 1 > depth)
1380 depth = ret + 1; 1377 depth = ret + 1;
1381 } 1378 }
1382 1379
1383 return depth; 1380 return depth;
1384} 1381}
1385static int __init pci_get_max_depth(void)
1386{
1387 int depth = 0;
1388 struct pci_bus *bus;
1389
1390 list_for_each_entry(bus, &pci_root_buses, node) {
1391 int ret;
1392
1393 ret = pci_bus_get_depth(bus);
1394 if (ret > depth)
1395 depth = ret;
1396 }
1397
1398 return depth;
1399}
1400 1382
1401/* 1383/*
1402 * -1: undefined, will auto detect later 1384 * -1: undefined, will auto detect later
@@ -1413,7 +1395,7 @@ enum enable_type {
1413 auto_enabled, 1395 auto_enabled,
1414}; 1396};
1415 1397
1416static enum enable_type pci_realloc_enable __initdata = undefined; 1398static enum enable_type pci_realloc_enable = undefined;
1417void __init pci_realloc_get_opt(char *str) 1399void __init pci_realloc_get_opt(char *str)
1418{ 1400{
1419 if (!strncmp(str, "off", 3)) 1401 if (!strncmp(str, "off", 3))
@@ -1421,45 +1403,64 @@ void __init pci_realloc_get_opt(char *str)
1421 else if (!strncmp(str, "on", 2)) 1403 else if (!strncmp(str, "on", 2))
1422 pci_realloc_enable = user_enabled; 1404 pci_realloc_enable = user_enabled;
1423} 1405}
1424static bool __init pci_realloc_enabled(void) 1406static bool pci_realloc_enabled(enum enable_type enable)
1425{ 1407{
1426 return pci_realloc_enable >= user_enabled; 1408 return enable >= user_enabled;
1427} 1409}
1428 1410
1429static void __init pci_realloc_detect(void)
1430{
1431#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) 1411#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1432 struct pci_dev *dev = NULL; 1412static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1433 1413{
1434 if (pci_realloc_enable != undefined) 1414 int i;
1435 return; 1415 bool *unassigned = data;
1436
1437 for_each_pci_dev(dev) {
1438 int i;
1439 1416
1440 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { 1417 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1441 struct resource *r = &dev->resource[i]; 1418 struct resource *r = &dev->resource[i];
1419 struct pci_bus_region region;
1442 1420
1443 /* Not assigned, or rejected by kernel ? */ 1421 /* Not assigned or rejected by kernel? */
1444 if (r->flags && !r->start) { 1422 if (!r->flags)
1445 pci_realloc_enable = auto_enabled; 1423 continue;
1446 1424
1447 return; 1425 pcibios_resource_to_bus(dev, &region, r);
1448 } 1426 if (!region.start) {
1427 *unassigned = true;
1428 return 1; /* return early from pci_walk_bus() */
1449 } 1429 }
1450 } 1430 }
1451#endif 1431
1432 return 0;
1452} 1433}
1453 1434
1435static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1436 enum enable_type enable_local)
1437{
1438 bool unassigned = false;
1439
1440 if (enable_local != undefined)
1441 return enable_local;
1442
1443 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1444 if (unassigned)
1445 return auto_enabled;
1446
1447 return enable_local;
1448}
1449#else
1450static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1451 enum enable_type enable_local)
1452{
1453 return enable_local;
1454}
1455#endif
1456
1454/* 1457/*
1455 * first try will not touch pci bridge res 1458 * first try will not touch pci bridge res
1456 * second and later try will clear small leaf bridge res 1459 * second and later try will clear small leaf bridge res
1457 * will stop till to the max deepth if can not find good one 1460 * will stop till to the max deepth if can not find good one
1458 */ 1461 */
1459void __init 1462void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1460pci_assign_unassigned_resources(void)
1461{ 1463{
1462 struct pci_bus *bus;
1463 LIST_HEAD(realloc_head); /* list of resources that 1464 LIST_HEAD(realloc_head); /* list of resources that
1464 want additional resources */ 1465 want additional resources */
1465 struct list_head *add_list = NULL; 1466 struct list_head *add_list = NULL;
@@ -1470,15 +1471,17 @@ pci_assign_unassigned_resources(void)
1470 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 1471 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1471 IORESOURCE_PREFETCH; 1472 IORESOURCE_PREFETCH;
1472 int pci_try_num = 1; 1473 int pci_try_num = 1;
1474 enum enable_type enable_local;
1473 1475
1474 /* don't realloc if asked to do so */ 1476 /* don't realloc if asked to do so */
1475 pci_realloc_detect(); 1477 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1476 if (pci_realloc_enabled()) { 1478 if (pci_realloc_enabled(enable_local)) {
1477 int max_depth = pci_get_max_depth(); 1479 int max_depth = pci_bus_get_depth(bus);
1478 1480
1479 pci_try_num = max_depth + 1; 1481 pci_try_num = max_depth + 1;
1480 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", 1482 dev_printk(KERN_DEBUG, &bus->dev,
1481 max_depth, pci_try_num); 1483 "max bus depth: %d pci_try_num: %d\n",
1484 max_depth, pci_try_num);
1482 } 1485 }
1483 1486
1484again: 1487again:
@@ -1490,32 +1493,30 @@ again:
1490 add_list = &realloc_head; 1493 add_list = &realloc_head;
1491 /* Depth first, calculate sizes and alignments of all 1494 /* Depth first, calculate sizes and alignments of all
1492 subordinate buses. */ 1495 subordinate buses. */
1493 list_for_each_entry(bus, &pci_root_buses, node) 1496 __pci_bus_size_bridges(bus, add_list);
1494 __pci_bus_size_bridges(bus, add_list);
1495 1497
1496 /* Depth last, allocate resources and update the hardware. */ 1498 /* Depth last, allocate resources and update the hardware. */
1497 list_for_each_entry(bus, &pci_root_buses, node) 1499 __pci_bus_assign_resources(bus, add_list, &fail_head);
1498 __pci_bus_assign_resources(bus, add_list, &fail_head);
1499 if (add_list) 1500 if (add_list)
1500 BUG_ON(!list_empty(add_list)); 1501 BUG_ON(!list_empty(add_list));
1501 tried_times++; 1502 tried_times++;
1502 1503
1503 /* any device complain? */ 1504 /* any device complain? */
1504 if (list_empty(&fail_head)) 1505 if (list_empty(&fail_head))
1505 goto enable_and_dump; 1506 goto dump;
1506 1507
1507 if (tried_times >= pci_try_num) { 1508 if (tried_times >= pci_try_num) {
1508 if (pci_realloc_enable == undefined) 1509 if (enable_local == undefined)
1509 printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n"); 1510 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1510 else if (pci_realloc_enable == auto_enabled) 1511 else if (enable_local == auto_enabled)
1511 printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); 1512 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1512 1513
1513 free_list(&fail_head); 1514 free_list(&fail_head);
1514 goto enable_and_dump; 1515 goto dump;
1515 } 1516 }
1516 1517
1517 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", 1518 dev_printk(KERN_DEBUG, &bus->dev,
1518 tried_times + 1); 1519 "No. %d try to assign unassigned res\n", tried_times + 1);
1519 1520
1520 /* third times and later will not check if it is leaf */ 1521 /* third times and later will not check if it is leaf */
1521 if ((tried_times + 1) > 2) 1522 if ((tried_times + 1) > 2)
@@ -1525,12 +1526,11 @@ again:
1525 * Try to release leaf bridge's resources that doesn't fit resource of 1526 * Try to release leaf bridge's resources that doesn't fit resource of
1526 * child device under that bridge 1527 * child device under that bridge
1527 */ 1528 */
1528 list_for_each_entry(fail_res, &fail_head, list) { 1529 list_for_each_entry(fail_res, &fail_head, list)
1529 bus = fail_res->dev->bus; 1530 pci_bus_release_bridge_resources(fail_res->dev->bus,
1530 pci_bus_release_bridge_resources(bus,
1531 fail_res->flags & type_mask, 1531 fail_res->flags & type_mask,
1532 rel_type); 1532 rel_type);
1533 } 1533
1534 /* restore size and flags */ 1534 /* restore size and flags */
1535 list_for_each_entry(fail_res, &fail_head, list) { 1535 list_for_each_entry(fail_res, &fail_head, list) {
1536 struct resource *res = fail_res->res; 1536 struct resource *res = fail_res->res;
@@ -1545,14 +1545,17 @@ again:
1545 1545
1546 goto again; 1546 goto again;
1547 1547
1548enable_and_dump: 1548dump:
1549 /* Depth last, update the hardware. */
1550 list_for_each_entry(bus, &pci_root_buses, node)
1551 pci_enable_bridges(bus);
1552
1553 /* dump the resource on buses */ 1549 /* dump the resource on buses */
1554 list_for_each_entry(bus, &pci_root_buses, node) 1550 pci_bus_dump_resources(bus);
1555 pci_bus_dump_resources(bus); 1551}
1552
1553void __init pci_assign_unassigned_resources(void)
1554{
1555 struct pci_bus *root_bus;
1556
1557 list_for_each_entry(root_bus, &pci_root_buses, node)
1558 pci_assign_unassigned_root_bus_resources(root_bus);
1556} 1559}
1557 1560
1558void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 1561void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
@@ -1589,13 +1592,11 @@ again:
1589 * Try to release leaf bridge's resources that doesn't fit resource of 1592 * Try to release leaf bridge's resources that doesn't fit resource of
1590 * child device under that bridge 1593 * child device under that bridge
1591 */ 1594 */
1592 list_for_each_entry(fail_res, &fail_head, list) { 1595 list_for_each_entry(fail_res, &fail_head, list)
1593 struct pci_bus *bus = fail_res->dev->bus; 1596 pci_bus_release_bridge_resources(fail_res->dev->bus,
1594 unsigned long flags = fail_res->flags; 1597 fail_res->flags & type_mask,
1595
1596 pci_bus_release_bridge_resources(bus, flags & type_mask,
1597 whole_subtree); 1598 whole_subtree);
1598 } 1599
1599 /* restore size and flags */ 1600 /* restore size and flags */
1600 list_for_each_entry(fail_res, &fail_head, list) { 1601 list_for_each_entry(fail_res, &fail_head, list) {
1601 struct resource *res = fail_res->res; 1602 struct resource *res = fail_res->res;
@@ -1615,7 +1616,6 @@ enable_all:
1615 if (retval) 1616 if (retval)
1616 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); 1617 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1617 pci_set_master(bridge); 1618 pci_set_master(bridge);
1618 pci_enable_bridges(parent);
1619} 1619}
1620EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); 1620EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1621 1621
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 23:27:54 -0500