diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-09-21 03:48:33 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-09-21 03:48:33 -0400 |
commit | f70cac8d9c7125f83048f8b3d1c60f5a041a165c (patch) | |
tree | 0d0efd72c1a41f973a919b16aac1d8210ed1ee30 /drivers/pci | |
parent | 4722cd7741c6404f967f7a7b8b666540b6c1663e (diff) | |
parent | 08aab447c56a5388cf0c768da476ad022f00fef8 (diff) |
Merge branch 'kprobes-test' of git://git.yxit.co.uk/linux into devel-stable
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/hotplug/pcihp_slot.c | 4 | ||||
-rw-r--r-- | drivers/pci/pci.c | 2 | ||||
-rw-r--r-- | drivers/pci/probe.c | 44 |
3 files changed, 26 insertions, 24 deletions
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c index 753b21aaea61..3ffd9c1acc0a 100644 --- a/drivers/pci/hotplug/pcihp_slot.c +++ b/drivers/pci/hotplug/pcihp_slot.c | |||
@@ -169,7 +169,9 @@ void pci_configure_slot(struct pci_dev *dev) | |||
169 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) | 169 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) |
170 | return; | 170 | return; |
171 | 171 | ||
172 | pcie_bus_configure_settings(dev->bus, dev->bus->self->pcie_mpss); | 172 | if (dev->bus && dev->bus->self) |
173 | pcie_bus_configure_settings(dev->bus, | ||
174 | dev->bus->self->pcie_mpss); | ||
173 | 175 | ||
174 | memset(&hpp, 0, sizeof(hpp)); | 176 | memset(&hpp, 0, sizeof(hpp)); |
175 | ret = pci_get_hp_params(dev, &hpp); | 177 | ret = pci_get_hp_params(dev, &hpp); |
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 0ce67423a0a3..4e84fd4a4312 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c | |||
@@ -77,7 +77,7 @@ unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |||
77 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | 77 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; |
78 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | 78 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; |
79 | 79 | ||
80 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; | 80 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE; |
81 | 81 | ||
82 | /* | 82 | /* |
83 | * The default CLS is used if arch didn't set CLS explicitly and not | 83 | * The default CLS is used if arch didn't set CLS explicitly and not |
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 8473727b29fa..b1187ff31d89 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c | |||
@@ -1396,34 +1396,37 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) | |||
1396 | 1396 | ||
1397 | static void pcie_write_mrrs(struct pci_dev *dev, int mps) | 1397 | static void pcie_write_mrrs(struct pci_dev *dev, int mps) |
1398 | { | 1398 | { |
1399 | int rc, mrrs; | 1399 | int rc, mrrs, dev_mpss; |
1400 | 1400 | ||
1401 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | 1401 | /* In the "safe" case, do not configure the MRRS. There appear to be |
1402 | int dev_mpss = 128 << dev->pcie_mpss; | 1402 | * issues with setting MRRS to 0 on a number of devices. |
1403 | */ | ||
1403 | 1404 | ||
1404 | /* For Max performance, the MRRS must be set to the largest | 1405 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
1405 | * supported value. However, it cannot be configured larger | 1406 | return; |
1406 | * than the MPS the device or the bus can support. This assumes | ||
1407 | * that the largest MRRS available on the device cannot be | ||
1408 | * smaller than the device MPSS. | ||
1409 | */ | ||
1410 | mrrs = mps < dev_mpss ? mps : dev_mpss; | ||
1411 | } else | ||
1412 | /* In the "safe" case, configure the MRRS for fairness on the | ||
1413 | * bus by making all devices have the same size | ||
1414 | */ | ||
1415 | mrrs = mps; | ||
1416 | 1407 | ||
1408 | dev_mpss = 128 << dev->pcie_mpss; | ||
1409 | |||
1410 | /* For Max performance, the MRRS must be set to the largest supported | ||
1411 | * value. However, it cannot be configured larger than the MPS the | ||
1412 | * device or the bus can support. This assumes that the largest MRRS | ||
1413 | * available on the device cannot be smaller than the device MPSS. | ||
1414 | */ | ||
1415 | mrrs = min(mps, dev_mpss); | ||
1417 | 1416 | ||
1418 | /* MRRS is a R/W register. Invalid values can be written, but a | 1417 | /* MRRS is a R/W register. Invalid values can be written, but a |
1419 | * subsiquent read will verify if the value is acceptable or not. | 1418 | * subsequent read will verify if the value is acceptable or not. |
1420 | * If the MRRS value provided is not acceptable (e.g., too large), | 1419 | * If the MRRS value provided is not acceptable (e.g., too large), |
1421 | * shrink the value until it is acceptable to the HW. | 1420 | * shrink the value until it is acceptable to the HW. |
1422 | */ | 1421 | */ |
1423 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { | 1422 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
1423 | dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value" | ||
1424 | " to %d. If any issues are encountered, please try " | ||
1425 | "running with pci=pcie_bus_safe\n", mrrs); | ||
1424 | rc = pcie_set_readrq(dev, mrrs); | 1426 | rc = pcie_set_readrq(dev, mrrs); |
1425 | if (rc) | 1427 | if (rc) |
1426 | dev_err(&dev->dev, "Failed attempting to set the MRRS\n"); | 1428 | dev_err(&dev->dev, |
1429 | "Failed attempting to set the MRRS\n"); | ||
1427 | 1430 | ||
1428 | mrrs /= 2; | 1431 | mrrs /= 2; |
1429 | } | 1432 | } |
@@ -1436,13 +1439,13 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |||
1436 | if (!pci_is_pcie(dev)) | 1439 | if (!pci_is_pcie(dev)) |
1437 | return 0; | 1440 | return 0; |
1438 | 1441 | ||
1439 | dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", | 1442 | dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", |
1440 | pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); | 1443 | pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); |
1441 | 1444 | ||
1442 | pcie_write_mps(dev, mps); | 1445 | pcie_write_mps(dev, mps); |
1443 | pcie_write_mrrs(dev, mps); | 1446 | pcie_write_mrrs(dev, mps); |
1444 | 1447 | ||
1445 | dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", | 1448 | dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", |
1446 | pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); | 1449 | pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); |
1447 | 1450 | ||
1448 | return 0; | 1451 | return 0; |
@@ -1456,9 +1459,6 @@ void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss) | |||
1456 | { | 1459 | { |
1457 | u8 smpss = mpss; | 1460 | u8 smpss = mpss; |
1458 | 1461 | ||
1459 | if (!bus->self) | ||
1460 | return; | ||
1461 | |||
1462 | if (!pci_is_pcie(bus->self)) | 1462 | if (!pci_is_pcie(bus->self)) |
1463 | return; | 1463 | return; |
1464 | 1464 | ||