aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci
diff options
context:
space:
mode:
authorKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>2012-09-12 11:14:33 -0400
committerKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>2012-09-12 11:14:33 -0400
commit25a765b7f05cb8460fa01b54568894b20e184862 (patch)
tree0b56db57b4d9f912393ab303c269e0fe6cdf8635 /drivers/pci
parent9d2be9287107695708e6aae5105a8a518a6cb4d0 (diff)
parent64282278989d5b0398dcb3ba7904cb00c621dc35 (diff)
Merge branch 'x86/platform' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into stable/for-linus-3.7
* 'x86/platform' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (9690 commits) x86: Document x86_init.paging.pagetable_init() x86: xen: Cleanup and remove x86_init.paging.pagetable_setup_done() x86: Move paging_init() call to x86_init.paging.pagetable_init() x86: Rename pagetable_setup_start() to pagetable_init() x86: Remove base argument from x86_init.paging.pagetable_setup_start Linux 3.6-rc5 HID: tpkbd: work even if the new Lenovo Keyboard driver is not configured Remove user-triggerable BUG from mpol_to_str xen/pciback: Fix proper FLR steps. uml: fix compile error in deliver_alarm() dj: memory scribble in logi_dj Fix order of arguments to compat_put_time[spec|val] xen: Use correct masking in xen_swiotlb_alloc_coherent. xen: fix logical error in tlb flushing xen/p2m: Fix one-off error in checking the P2M tree directory. powerpc: Don't use __put_user() in patch_instruction powerpc: Make sure IPI handlers see data written by IPI senders powerpc: Restore correct DSCR in context switch powerpc: Fix DSCR inheritance in copy_thread() powerpc: Keep thread.dscr and thread.dscr_inherit in sync ...
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/access.c6
-rw-r--r--drivers/pci/bus.c2
-rw-r--r--drivers/pci/hotplug-pci.c30
-rw-r--r--drivers/pci/hotplug/acpiphp.h4
-rw-r--r--drivers/pci/hotplug/acpiphp_core.c7
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c67
-rw-r--r--drivers/pci/hotplug/cpci_hotplug_core.c14
-rw-r--r--drivers/pci/hotplug/cpci_hotplug_pci.c35
-rw-r--r--drivers/pci/hotplug/cpqphp_core.c14
-rw-r--r--drivers/pci/hotplug/cpqphp_pci.c8
-rw-r--r--drivers/pci/hotplug/ibmphp_core.c10
-rw-r--r--drivers/pci/hotplug/ibmphp_ebda.c2
-rw-r--r--drivers/pci/hotplug/ibmphp_pci.c2
-rw-r--r--drivers/pci/hotplug/pciehp.h4
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c101
-rw-r--r--drivers/pci/hotplug/pciehp_pci.c28
-rw-r--r--drivers/pci/hotplug/pcihp_skeleton.c14
-rw-r--r--drivers/pci/hotplug/sgi_hotplug.c12
-rw-r--r--drivers/pci/hotplug/shpchp_core.c14
-rw-r--r--drivers/pci/hotplug/shpchp_ctrl.c3
-rw-r--r--drivers/pci/hotplug/shpchp_pci.c45
-rw-r--r--drivers/pci/hotplug/shpchp_sysfs.c6
-rw-r--r--drivers/pci/iov.c4
-rw-r--r--drivers/pci/pci-acpi.c40
-rw-r--r--drivers/pci/pci-driver.c37
-rw-r--r--drivers/pci/pci-sysfs.c73
-rw-r--r--drivers/pci/pci.c425
-rw-r--r--drivers/pci/pci.h11
-rw-r--r--drivers/pci/pcie/aer/aerdrv_acpi.c2
-rw-r--r--drivers/pci/pcie/portdrv_pci.c74
-rw-r--r--drivers/pci/probe.c275
-rw-r--r--drivers/pci/quirks.c248
-rw-r--r--drivers/pci/remove.c1
-rw-r--r--drivers/pci/search.c2
-rw-r--r--drivers/pci/setup-bus.c67
-rw-r--r--drivers/pci/setup-res.c125
37 files changed, 1159 insertions, 654 deletions
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 01c001f3b766..8d688b260e28 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MN10300) += setup-bus.o
49obj-$(CONFIG_MICROBLAZE) += setup-bus.o 49obj-$(CONFIG_MICROBLAZE) += setup-bus.o
50obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o 50obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o
51obj-$(CONFIG_SPARC_LEON) += setup-bus.o setup-irq.o 51obj-$(CONFIG_SPARC_LEON) += setup-bus.o setup-irq.o
52obj-$(CONFIG_M68K) += setup-bus.o setup-irq.o
52 53
53# 54#
54# ACPI Related PCI FW Functions 55# ACPI Related PCI FW Functions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 2a581642c237..ba91a7e17519 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -162,7 +162,8 @@ int pci_user_read_config_##size \
162 if (ret > 0) \ 162 if (ret > 0) \
163 ret = -EINVAL; \ 163 ret = -EINVAL; \
164 return ret; \ 164 return ret; \
165} 165} \
166EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
166 167
167/* Returns 0 on success, negative values indicate error. */ 168/* Returns 0 on success, negative values indicate error. */
168#define PCI_USER_WRITE_CONFIG(size,type) \ 169#define PCI_USER_WRITE_CONFIG(size,type) \
@@ -181,7 +182,8 @@ int pci_user_write_config_##size \
181 if (ret > 0) \ 182 if (ret > 0) \
182 ret = -EINVAL; \ 183 ret = -EINVAL; \
183 return ret; \ 184 return ret; \
184} 185} \
186EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
185 187
186PCI_USER_READ_CONFIG(byte, u8) 188PCI_USER_READ_CONFIG(byte, u8)
187PCI_USER_READ_CONFIG(word, u16) 189PCI_USER_READ_CONFIG(word, u16)
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 4ce5ef2f2826..4b0970b46e0b 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -164,6 +164,8 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
164int pci_bus_add_device(struct pci_dev *dev) 164int pci_bus_add_device(struct pci_dev *dev)
165{ 165{
166 int retval; 166 int retval;
167
168 pci_fixup_device(pci_fixup_final, dev);
167 retval = device_add(&dev->dev); 169 retval = device_add(&dev->dev);
168 if (retval) 170 if (retval)
169 return retval; 171 return retval;
diff --git a/drivers/pci/hotplug-pci.c b/drivers/pci/hotplug-pci.c
index d3509cdeb554..6258dc260d9f 100644
--- a/drivers/pci/hotplug-pci.c
+++ b/drivers/pci/hotplug-pci.c
@@ -4,18 +4,26 @@
4#include <linux/export.h> 4#include <linux/export.h>
5#include "pci.h" 5#include "pci.h"
6 6
7 7int __ref pci_hp_add_bridge(struct pci_dev *dev)
8unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
9{ 8{
10 unsigned int max; 9 struct pci_bus *parent = dev->bus;
11 10 int pass, busnr, start = parent->busn_res.start;
12 max = pci_scan_child_bus(bus); 11 int end = parent->busn_res.end;
13 12
14 /* 13 for (busnr = start; busnr <= end; busnr++) {
15 * Make the discovered devices available. 14 if (!pci_find_bus(pci_domain_nr(parent), busnr))
16 */ 15 break;
17 pci_bus_add_devices(bus); 16 }
17 if (busnr-- > end) {
18 printk(KERN_ERR "No bus number available for hot-added bridge %s\n",
19 pci_name(dev));
20 return -1;
21 }
22 for (pass = 0; pass < 2; pass++)
23 busnr = pci_scan_bridge(parent, dev, busnr, pass);
24 if (!dev->subordinate)
25 return -1;
18 26
19 return max; 27 return 0;
20} 28}
21EXPORT_SYMBOL(pci_do_scan_bus); 29EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h
index 7722108e78df..a1afb5b39ad4 100644
--- a/drivers/pci/hotplug/acpiphp.h
+++ b/drivers/pci/hotplug/acpiphp.h
@@ -89,8 +89,6 @@ struct acpiphp_bridge {
89 89
90 /* PCI-to-PCI bridge device */ 90 /* PCI-to-PCI bridge device */
91 struct pci_dev *pci_dev; 91 struct pci_dev *pci_dev;
92
93 spinlock_t res_lock;
94}; 92};
95 93
96 94
@@ -207,6 +205,6 @@ extern u8 acpiphp_get_latch_status (struct acpiphp_slot *slot);
207extern u8 acpiphp_get_adapter_status (struct acpiphp_slot *slot); 205extern u8 acpiphp_get_adapter_status (struct acpiphp_slot *slot);
208 206
209/* variables */ 207/* variables */
210extern int acpiphp_debug; 208extern bool acpiphp_debug;
211 209
212#endif /* _ACPIPHP_H */ 210#endif /* _ACPIPHP_H */
diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c
index aa41631e9e02..96316b74969f 100644
--- a/drivers/pci/hotplug/acpiphp_core.c
+++ b/drivers/pci/hotplug/acpiphp_core.c
@@ -47,8 +47,7 @@
47/* name size which is used for entries in pcihpfs */ 47/* name size which is used for entries in pcihpfs */
48#define SLOT_NAME_SIZE 21 /* {_SUN} */ 48#define SLOT_NAME_SIZE 21 /* {_SUN} */
49 49
50static bool debug; 50bool acpiphp_debug;
51int acpiphp_debug;
52 51
53/* local variables */ 52/* local variables */
54static int num_slots; 53static int num_slots;
@@ -62,7 +61,7 @@ MODULE_AUTHOR(DRIVER_AUTHOR);
62MODULE_DESCRIPTION(DRIVER_DESC); 61MODULE_DESCRIPTION(DRIVER_DESC);
63MODULE_LICENSE("GPL"); 62MODULE_LICENSE("GPL");
64MODULE_PARM_DESC(debug, "Debugging mode enabled or not"); 63MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
65module_param(debug, bool, 0644); 64module_param_named(debug, acpiphp_debug, bool, 0644);
66 65
67/* export the attention callback registration methods */ 66/* export the attention callback registration methods */
68EXPORT_SYMBOL_GPL(acpiphp_register_attention); 67EXPORT_SYMBOL_GPL(acpiphp_register_attention);
@@ -379,8 +378,6 @@ static int __init acpiphp_init(void)
379 if (acpi_pci_disabled) 378 if (acpi_pci_disabled)
380 return 0; 379 return 0;
381 380
382 acpiphp_debug = debug;
383
384 /* read all the ACPI info from the system */ 381 /* read all the ACPI info from the system */
385 return init_acpi(); 382 return init_acpi();
386} 383}
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 806c44fa645a..ad6fd6695495 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -100,11 +100,11 @@ static int post_dock_fixups(struct notifier_block *nb, unsigned long val,
100 PCI_PRIMARY_BUS, 100 PCI_PRIMARY_BUS,
101 &buses); 101 &buses);
102 102
103 if (((buses >> 8) & 0xff) != bus->secondary) { 103 if (((buses >> 8) & 0xff) != bus->busn_res.start) {
104 buses = (buses & 0xff000000) 104 buses = (buses & 0xff000000)
105 | ((unsigned int)(bus->primary) << 0) 105 | ((unsigned int)(bus->primary) << 0)
106 | ((unsigned int)(bus->secondary) << 8) 106 | ((unsigned int)(bus->busn_res.start) << 8)
107 | ((unsigned int)(bus->subordinate) << 16); 107 | ((unsigned int)(bus->busn_res.end) << 16);
108 pci_write_config_dword(bus->self, PCI_PRIMARY_BUS, buses); 108 pci_write_config_dword(bus->self, PCI_PRIMARY_BUS, buses);
109 } 109 }
110 return NOTIFY_OK; 110 return NOTIFY_OK;
@@ -132,6 +132,15 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
132 if (!acpi_pci_check_ejectable(pbus, handle) && !is_dock_device(handle)) 132 if (!acpi_pci_check_ejectable(pbus, handle) && !is_dock_device(handle))
133 return AE_OK; 133 return AE_OK;
134 134
135 status = acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
136 if (ACPI_FAILURE(status)) {
137 warn("can't evaluate _ADR (%#x)\n", status);
138 return AE_OK;
139 }
140
141 device = (adr >> 16) & 0xffff;
142 function = adr & 0xffff;
143
135 pdev = pbus->self; 144 pdev = pbus->self;
136 if (pdev && pci_is_pcie(pdev)) { 145 if (pdev && pci_is_pcie(pdev)) {
137 tmp = acpi_find_root_bridge_handle(pdev); 146 tmp = acpi_find_root_bridge_handle(pdev);
@@ -144,10 +153,6 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
144 } 153 }
145 } 154 }
146 155
147 acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
148 device = (adr >> 16) & 0xffff;
149 function = adr & 0xffff;
150
151 newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL); 156 newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL);
152 if (!newfunc) 157 if (!newfunc)
153 return AE_NO_MEMORY; 158 return AE_NO_MEMORY;
@@ -391,8 +396,6 @@ static void add_host_bridge(acpi_handle *handle)
391 396
392 bridge->pci_bus = root->bus; 397 bridge->pci_bus = root->bus;
393 398
394 spin_lock_init(&bridge->res_lock);
395
396 init_bridge_misc(bridge); 399 init_bridge_misc(bridge);
397} 400}
398 401
@@ -425,7 +428,6 @@ static void add_p2p_bridge(acpi_handle *handle)
425 * (which we access during module unload). 428 * (which we access during module unload).
426 */ 429 */
427 get_device(&bridge->pci_bus->dev); 430 get_device(&bridge->pci_bus->dev);
428 spin_lock_init(&bridge->res_lock);
429 431
430 init_bridge_misc(bridge); 432 init_bridge_misc(bridge);
431 return; 433 return;
@@ -692,7 +694,7 @@ static unsigned char acpiphp_max_busnr(struct pci_bus *bus)
692 * bus->subordinate value because it could have 694 * bus->subordinate value because it could have
693 * padding in it. 695 * padding in it.
694 */ 696 */
695 max = bus->secondary; 697 max = bus->busn_res.start;
696 698
697 list_for_each(tmp, &bus->children) { 699 list_for_each(tmp, &bus->children) {
698 n = pci_bus_max_busnr(pci_bus_b(tmp)); 700 n = pci_bus_max_busnr(pci_bus_b(tmp));
@@ -878,6 +880,24 @@ static void disable_bridges(struct pci_bus *bus)
878 } 880 }
879} 881}
880 882
883/* return first device in slot, acquiring a reference on it */
884static struct pci_dev *dev_in_slot(struct acpiphp_slot *slot)
885{
886 struct pci_bus *bus = slot->bridge->pci_bus;
887 struct pci_dev *dev;
888 struct pci_dev *ret = NULL;
889
890 down_read(&pci_bus_sem);
891 list_for_each_entry(dev, &bus->devices, bus_list)
892 if (PCI_SLOT(dev->devfn) == slot->device) {
893 ret = pci_dev_get(dev);
894 break;
895 }
896 up_read(&pci_bus_sem);
897
898 return ret;
899}
900
881/** 901/**
882 * disable_device - disable a slot 902 * disable_device - disable a slot
883 * @slot: ACPI PHP slot 903 * @slot: ACPI PHP slot
@@ -893,6 +913,7 @@ static int disable_device(struct acpiphp_slot *slot)
893 pdev = pci_get_slot(bus, PCI_DEVFN(slot->device, 0)); 913 pdev = pci_get_slot(bus, PCI_DEVFN(slot->device, 0));
894 if (!pdev) 914 if (!pdev)
895 goto err_exit; 915 goto err_exit;
916 pci_dev_put(pdev);
896 917
897 list_for_each_entry(func, &slot->funcs, sibling) { 918 list_for_each_entry(func, &slot->funcs, sibling) {
898 if (func->bridge) { 919 if (func->bridge) {
@@ -901,18 +922,22 @@ static int disable_device(struct acpiphp_slot *slot)
901 (u32)1, NULL, NULL); 922 (u32)1, NULL, NULL);
902 func->bridge = NULL; 923 func->bridge = NULL;
903 } 924 }
925 }
904 926
905 pdev = pci_get_slot(slot->bridge->pci_bus, 927 /*
906 PCI_DEVFN(slot->device, func->function)); 928 * enable_device() enumerates all functions in this device via
907 if (pdev) { 929 * pci_scan_slot(), whether they have associated ACPI hotplug
908 pci_stop_bus_device(pdev); 930 * methods (_EJ0, etc.) or not. Therefore, we remove all functions
909 if (pdev->subordinate) { 931 * here.
910 disable_bridges(pdev->subordinate); 932 */
911 pci_disable_device(pdev); 933 while ((pdev = dev_in_slot(slot))) {
912 } 934 pci_stop_bus_device(pdev);
913 __pci_remove_bus_device(pdev); 935 if (pdev->subordinate) {
914 pci_dev_put(pdev); 936 disable_bridges(pdev->subordinate);
937 pci_disable_device(pdev);
915 } 938 }
939 __pci_remove_bus_device(pdev);
940 pci_dev_put(pdev);
916 } 941 }
917 942
918 list_for_each_entry(func, &slot->funcs, sibling) { 943 list_for_each_entry(func, &slot->funcs, sibling) {
diff --git a/drivers/pci/hotplug/cpci_hotplug_core.c b/drivers/pci/hotplug/cpci_hotplug_core.c
index 3fadf2f135e8..2b4c412f94c3 100644
--- a/drivers/pci/hotplug/cpci_hotplug_core.c
+++ b/drivers/pci/hotplug/cpci_hotplug_core.c
@@ -225,7 +225,7 @@ cpci_hp_register_bus(struct pci_bus *bus, u8 first, u8 last)
225 struct hotplug_slot *hotplug_slot; 225 struct hotplug_slot *hotplug_slot;
226 struct hotplug_slot_info *info; 226 struct hotplug_slot_info *info;
227 char name[SLOT_NAME_SIZE]; 227 char name[SLOT_NAME_SIZE];
228 int status = -ENOMEM; 228 int status;
229 int i; 229 int i;
230 230
231 if (!(controller && bus)) 231 if (!(controller && bus))
@@ -237,18 +237,24 @@ cpci_hp_register_bus(struct pci_bus *bus, u8 first, u8 last)
237 */ 237 */
238 for (i = first; i <= last; ++i) { 238 for (i = first; i <= last; ++i) {
239 slot = kzalloc(sizeof (struct slot), GFP_KERNEL); 239 slot = kzalloc(sizeof (struct slot), GFP_KERNEL);
240 if (!slot) 240 if (!slot) {
241 status = -ENOMEM;
241 goto error; 242 goto error;
243 }
242 244
243 hotplug_slot = 245 hotplug_slot =
244 kzalloc(sizeof (struct hotplug_slot), GFP_KERNEL); 246 kzalloc(sizeof (struct hotplug_slot), GFP_KERNEL);
245 if (!hotplug_slot) 247 if (!hotplug_slot) {
248 status = -ENOMEM;
246 goto error_slot; 249 goto error_slot;
250 }
247 slot->hotplug_slot = hotplug_slot; 251 slot->hotplug_slot = hotplug_slot;
248 252
249 info = kzalloc(sizeof (struct hotplug_slot_info), GFP_KERNEL); 253 info = kzalloc(sizeof (struct hotplug_slot_info), GFP_KERNEL);
250 if (!info) 254 if (!info) {
255 status = -ENOMEM;
251 goto error_hpslot; 256 goto error_hpslot;
257 }
252 hotplug_slot->info = info; 258 hotplug_slot->info = info;
253 259
254 slot->bus = bus; 260 slot->bus = bus;
diff --git a/drivers/pci/hotplug/cpci_hotplug_pci.c b/drivers/pci/hotplug/cpci_hotplug_pci.c
index ae853ccd0cd5..dcc75c785443 100644
--- a/drivers/pci/hotplug/cpci_hotplug_pci.c
+++ b/drivers/pci/hotplug/cpci_hotplug_pci.c
@@ -285,42 +285,19 @@ int __ref cpci_configure_slot(struct slot *slot)
285 for (fn = 0; fn < 8; fn++) { 285 for (fn = 0; fn < 8; fn++) {
286 struct pci_dev *dev; 286 struct pci_dev *dev;
287 287
288 dev = pci_get_slot(parent, PCI_DEVFN(PCI_SLOT(slot->devfn), fn)); 288 dev = pci_get_slot(parent,
289 PCI_DEVFN(PCI_SLOT(slot->devfn), fn));
289 if (!dev) 290 if (!dev)
290 continue; 291 continue;
291 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 292 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
292 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { 293 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
293 /* Find an unused bus number for the new bridge */ 294 pci_hp_add_bridge(dev);
294 struct pci_bus *child;
295 unsigned char busnr, start = parent->secondary;
296 unsigned char end = parent->subordinate;
297
298 for (busnr = start; busnr <= end; busnr++) {
299 if (!pci_find_bus(pci_domain_nr(parent),
300 busnr))
301 break;
302 }
303 if (busnr >= end) {
304 err("No free bus for hot-added bridge\n");
305 pci_dev_put(dev);
306 continue;
307 }
308 child = pci_add_new_bus(parent, dev, busnr);
309 if (!child) {
310 err("Cannot add new bus for %s\n",
311 pci_name(dev));
312 pci_dev_put(dev);
313 continue;
314 }
315 child->subordinate = pci_do_scan_bus(child);
316 pci_bus_size_bridges(child);
317 }
318 pci_dev_put(dev); 295 pci_dev_put(dev);
319 } 296 }
320 297
321 pci_bus_assign_resources(parent); 298 pci_assign_unassigned_bridge_resources(parent->self);
299
322 pci_bus_add_devices(parent); 300 pci_bus_add_devices(parent);
323 pci_enable_bridges(parent);
324 301
325 dbg("%s - exit", __func__); 302 dbg("%s - exit", __func__);
326 return 0; 303 return 0;
diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c
index 187a199da93c..c8eaeb43fa5d 100644
--- a/drivers/pci/hotplug/cpqphp_core.c
+++ b/drivers/pci/hotplug/cpqphp_core.c
@@ -611,7 +611,7 @@ static int ctrl_slot_setup(struct controller *ctrl,
611 u32 tempdword; 611 u32 tempdword;
612 char name[SLOT_NAME_SIZE]; 612 char name[SLOT_NAME_SIZE];
613 void __iomem *slot_entry= NULL; 613 void __iomem *slot_entry= NULL;
614 int result = -ENOMEM; 614 int result;
615 615
616 dbg("%s\n", __func__); 616 dbg("%s\n", __func__);
617 617
@@ -623,19 +623,25 @@ static int ctrl_slot_setup(struct controller *ctrl,
623 623
624 while (number_of_slots) { 624 while (number_of_slots) {
625 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 625 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
626 if (!slot) 626 if (!slot) {
627 result = -ENOMEM;
627 goto error; 628 goto error;
629 }
628 630
629 slot->hotplug_slot = kzalloc(sizeof(*(slot->hotplug_slot)), 631 slot->hotplug_slot = kzalloc(sizeof(*(slot->hotplug_slot)),
630 GFP_KERNEL); 632 GFP_KERNEL);
631 if (!slot->hotplug_slot) 633 if (!slot->hotplug_slot) {
634 result = -ENOMEM;
632 goto error_slot; 635 goto error_slot;
636 }
633 hotplug_slot = slot->hotplug_slot; 637 hotplug_slot = slot->hotplug_slot;
634 638
635 hotplug_slot->info = kzalloc(sizeof(*(hotplug_slot->info)), 639 hotplug_slot->info = kzalloc(sizeof(*(hotplug_slot->info)),
636 GFP_KERNEL); 640 GFP_KERNEL);
637 if (!hotplug_slot->info) 641 if (!hotplug_slot->info) {
642 result = -ENOMEM;
638 goto error_hpslot; 643 goto error_hpslot;
644 }
639 hotplug_slot_info = hotplug_slot->info; 645 hotplug_slot_info = hotplug_slot->info;
640 646
641 slot->ctrl = ctrl; 647 slot->ctrl = ctrl;
diff --git a/drivers/pci/hotplug/cpqphp_pci.c b/drivers/pci/hotplug/cpqphp_pci.c
index 1c8494021a42..09801c6945ce 100644
--- a/drivers/pci/hotplug/cpqphp_pci.c
+++ b/drivers/pci/hotplug/cpqphp_pci.c
@@ -83,7 +83,6 @@ static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iom
83 83
84int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func) 84int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
85{ 85{
86 unsigned char bus;
87 struct pci_bus *child; 86 struct pci_bus *child;
88 int num; 87 int num;
89 88
@@ -106,9 +105,10 @@ int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
106 } 105 }
107 106
108 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 107 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
109 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus); 108 pci_hp_add_bridge(func->pci_dev);
110 child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus); 109 child = func->pci_dev->subordinate;
111 pci_do_scan_bus(child); 110 if (child)
111 pci_bus_add_devices(child);
112 } 112 }
113 113
114 pci_dev_put(func->pci_dev); 114 pci_dev_put(func->pci_dev);
diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c
index 4fda7e6a86a7..cbd72d81d253 100644
--- a/drivers/pci/hotplug/ibmphp_core.c
+++ b/drivers/pci/hotplug/ibmphp_core.c
@@ -760,7 +760,7 @@ static u8 bus_structure_fixup(u8 busno)
760 for (dev->devfn = 0; dev->devfn < 256; dev->devfn += 8) { 760 for (dev->devfn = 0; dev->devfn < 256; dev->devfn += 8) {
761 if (!pci_read_config_word(dev, PCI_VENDOR_ID, &l) && 761 if (!pci_read_config_word(dev, PCI_VENDOR_ID, &l) &&
762 (l != 0x0000) && (l != 0xffff)) { 762 (l != 0x0000) && (l != 0xffff)) {
763 debug("%s - Inside bus_struture_fixup()\n", 763 debug("%s - Inside bus_structure_fixup()\n",
764 __func__); 764 __func__);
765 pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL); 765 pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL);
766 break; 766 break;
@@ -775,7 +775,6 @@ static u8 bus_structure_fixup(u8 busno)
775 775
776static int ibm_configure_device(struct pci_func *func) 776static int ibm_configure_device(struct pci_func *func)
777{ 777{
778 unsigned char bus;
779 struct pci_bus *child; 778 struct pci_bus *child;
780 int num; 779 int num;
781 int flag = 0; /* this is to make sure we don't double scan the bus, 780 int flag = 0; /* this is to make sure we don't double scan the bus,
@@ -805,9 +804,10 @@ static int ibm_configure_device(struct pci_func *func)
805 } 804 }
806 } 805 }
807 if (!(flag) && (func->dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)) { 806 if (!(flag) && (func->dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
808 pci_read_config_byte(func->dev, PCI_SECONDARY_BUS, &bus); 807 pci_hp_add_bridge(func->dev);
809 child = pci_add_new_bus(func->dev->bus, func->dev, bus); 808 child = func->dev->subordinate;
810 pci_do_scan_bus(child); 809 if (child)
810 pci_bus_add_devices(child);
811 } 811 }
812 812
813 return 0; 813 return 0;
diff --git a/drivers/pci/hotplug/ibmphp_ebda.c b/drivers/pci/hotplug/ibmphp_ebda.c
index 714ca5c4ed50..9df78bc14541 100644
--- a/drivers/pci/hotplug/ibmphp_ebda.c
+++ b/drivers/pci/hotplug/ibmphp_ebda.c
@@ -784,7 +784,7 @@ static int __init ebda_rsrc_controller (void)
784 hpc_ptr->ctlr_relative_id = ctlr; 784 hpc_ptr->ctlr_relative_id = ctlr;
785 hpc_ptr->slot_count = slot_num; 785 hpc_ptr->slot_count = slot_num;
786 hpc_ptr->bus_count = bus_num; 786 hpc_ptr->bus_count = bus_num;
787 debug ("now enter ctlr data struture ---\n"); 787 debug ("now enter ctlr data structure ---\n");
788 debug ("ctlr id: %x\n", ctlr_id); 788 debug ("ctlr id: %x\n", ctlr_id);
789 debug ("ctlr_relative_id: %x\n", hpc_ptr->ctlr_relative_id); 789 debug ("ctlr_relative_id: %x\n", hpc_ptr->ctlr_relative_id);
790 debug ("count of slots controlled by this ctlr: %x\n", slot_num); 790 debug ("count of slots controlled by this ctlr: %x\n", slot_num);
diff --git a/drivers/pci/hotplug/ibmphp_pci.c b/drivers/pci/hotplug/ibmphp_pci.c
index 7b09e16173ad..c60f5f3e838d 100644
--- a/drivers/pci/hotplug/ibmphp_pci.c
+++ b/drivers/pci/hotplug/ibmphp_pci.c
@@ -109,7 +109,7 @@ int ibmphp_configure_card (struct pci_func *func, u8 slotno)
109 109
110 cur_func->function = function; 110 cur_func->function = function;
111 111
112 debug ("inside the loop, cur_func->busno = %x, cur_func->device = %x, cur_func->funcion = %x\n", 112 debug ("inside the loop, cur_func->busno = %x, cur_func->device = %x, cur_func->function = %x\n",
113 cur_func->busno, cur_func->device, cur_func->function); 113 cur_func->busno, cur_func->device, cur_func->function);
114 114
115 pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id); 115 pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 4b7cce1de6ec..26ffd3e3fb74 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -149,10 +149,6 @@ int pciehp_get_attention_status(struct slot *slot, u8 *status);
149int pciehp_set_attention_status(struct slot *slot, u8 status); 149int pciehp_set_attention_status(struct slot *slot, u8 status);
150int pciehp_get_latch_status(struct slot *slot, u8 *status); 150int pciehp_get_latch_status(struct slot *slot, u8 *status);
151int pciehp_get_adapter_status(struct slot *slot, u8 *status); 151int pciehp_get_adapter_status(struct slot *slot, u8 *status);
152int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *speed);
153int pciehp_get_max_link_width(struct slot *slot, enum pcie_link_width *val);
154int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *speed);
155int pciehp_get_cur_link_width(struct slot *slot, enum pcie_link_width *val);
156int pciehp_query_power_fault(struct slot *slot); 152int pciehp_query_power_fault(struct slot *slot);
157void pciehp_green_led_on(struct slot *slot); 153void pciehp_green_led_on(struct slot *slot);
158void pciehp_green_led_off(struct slot *slot); 154void pciehp_green_led_off(struct slot *slot);
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index a960faec1021..302451e8289d 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -705,107 +705,6 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
705 return IRQ_HANDLED; 705 return IRQ_HANDLED;
706} 706}
707 707
708int pciehp_get_max_lnk_width(struct slot *slot,
709 enum pcie_link_width *value)
710{
711 struct controller *ctrl = slot->ctrl;
712 enum pcie_link_width lnk_wdth;
713 u32 lnk_cap;
714 int retval = 0;
715
716 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
717 if (retval) {
718 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
719 return retval;
720 }
721
722 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
723 case 0:
724 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
725 break;
726 case 1:
727 lnk_wdth = PCIE_LNK_X1;
728 break;
729 case 2:
730 lnk_wdth = PCIE_LNK_X2;
731 break;
732 case 4:
733 lnk_wdth = PCIE_LNK_X4;
734 break;
735 case 8:
736 lnk_wdth = PCIE_LNK_X8;
737 break;
738 case 12:
739 lnk_wdth = PCIE_LNK_X12;
740 break;
741 case 16:
742 lnk_wdth = PCIE_LNK_X16;
743 break;
744 case 32:
745 lnk_wdth = PCIE_LNK_X32;
746 break;
747 default:
748 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
749 break;
750 }
751
752 *value = lnk_wdth;
753 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
754
755 return retval;
756}
757
758int pciehp_get_cur_lnk_width(struct slot *slot,
759 enum pcie_link_width *value)
760{
761 struct controller *ctrl = slot->ctrl;
762 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
763 int retval = 0;
764 u16 lnk_status;
765
766 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
767 if (retval) {
768 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
769 __func__);
770 return retval;
771 }
772
773 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
774 case 0:
775 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
776 break;
777 case 1:
778 lnk_wdth = PCIE_LNK_X1;
779 break;
780 case 2:
781 lnk_wdth = PCIE_LNK_X2;
782 break;
783 case 4:
784 lnk_wdth = PCIE_LNK_X4;
785 break;
786 case 8:
787 lnk_wdth = PCIE_LNK_X8;
788 break;
789 case 12:
790 lnk_wdth = PCIE_LNK_X12;
791 break;
792 case 16:
793 lnk_wdth = PCIE_LNK_X16;
794 break;
795 case 32:
796 lnk_wdth = PCIE_LNK_X32;
797 break;
798 default:
799 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
800 break;
801 }
802
803 *value = lnk_wdth;
804 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
805
806 return retval;
807}
808
809int pcie_enable_notification(struct controller *ctrl) 708int pcie_enable_notification(struct controller *ctrl)
810{ 709{
811 u16 cmd, mask; 710 u16 cmd, mask;
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index 47d9dc06b109..09cecaf450c5 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -34,29 +34,6 @@
34#include "../pci.h" 34#include "../pci.h"
35#include "pciehp.h" 35#include "pciehp.h"
36 36
37static int __ref pciehp_add_bridge(struct pci_dev *dev)
38{
39 struct pci_bus *parent = dev->bus;
40 int pass, busnr, start = parent->secondary;
41 int end = parent->subordinate;
42
43 for (busnr = start; busnr <= end; busnr++) {
44 if (!pci_find_bus(pci_domain_nr(parent), busnr))
45 break;
46 }
47 if (busnr-- > end) {
48 err("No bus number available for hot-added bridge %s\n",
49 pci_name(dev));
50 return -1;
51 }
52 for (pass = 0; pass < 2; pass++)
53 busnr = pci_scan_bridge(parent, dev, busnr, pass);
54 if (!dev->subordinate)
55 return -1;
56
57 return 0;
58}
59
60int pciehp_configure_device(struct slot *p_slot) 37int pciehp_configure_device(struct slot *p_slot)
61{ 38{
62 struct pci_dev *dev; 39 struct pci_dev *dev;
@@ -85,9 +62,8 @@ int pciehp_configure_device(struct slot *p_slot)
85 if (!dev) 62 if (!dev)
86 continue; 63 continue;
87 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 64 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
88 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { 65 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
89 pciehp_add_bridge(dev); 66 pci_hp_add_bridge(dev);
90 }
91 pci_dev_put(dev); 67 pci_dev_put(dev);
92 } 68 }
93 69
diff --git a/drivers/pci/hotplug/pcihp_skeleton.c b/drivers/pci/hotplug/pcihp_skeleton.c
index b20ceaaa31f4..1f00b937f721 100644
--- a/drivers/pci/hotplug/pcihp_skeleton.c
+++ b/drivers/pci/hotplug/pcihp_skeleton.c
@@ -252,7 +252,7 @@ static int __init init_slots(void)
252 struct slot *slot; 252 struct slot *slot;
253 struct hotplug_slot *hotplug_slot; 253 struct hotplug_slot *hotplug_slot;
254 struct hotplug_slot_info *info; 254 struct hotplug_slot_info *info;
255 int retval = -ENOMEM; 255 int retval;
256 int i; 256 int i;
257 257
258 /* 258 /*
@@ -261,17 +261,23 @@ static int __init init_slots(void)
261 */ 261 */
262 for (i = 0; i < num_slots; ++i) { 262 for (i = 0; i < num_slots; ++i) {
263 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 263 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
264 if (!slot) 264 if (!slot) {
265 retval = -ENOMEM;
265 goto error; 266 goto error;
267 }
266 268
267 hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL); 269 hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL);
268 if (!hotplug_slot) 270 if (!hotplug_slot) {
271 retval = -ENOMEM;
269 goto error_slot; 272 goto error_slot;
273 }
270 slot->hotplug_slot = hotplug_slot; 274 slot->hotplug_slot = hotplug_slot;
271 275
272 info = kzalloc(sizeof(*info), GFP_KERNEL); 276 info = kzalloc(sizeof(*info), GFP_KERNEL);
273 if (!info) 277 if (!info) {
278 retval = -ENOMEM;
274 goto error_hpslot; 279 goto error_hpslot;
280 }
275 hotplug_slot->info = info; 281 hotplug_slot->info = info;
276 282
277 slot->number = i; 283 slot->number = i;
diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c
index de573113c102..f64ca92253da 100644
--- a/drivers/pci/hotplug/sgi_hotplug.c
+++ b/drivers/pci/hotplug/sgi_hotplug.c
@@ -397,13 +397,11 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
397 else 397 else
398 sn_io_slot_fixup(dev); 398 sn_io_slot_fixup(dev);
399 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 399 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
400 unsigned char sec_bus; 400 pci_hp_add_bridge(dev);
401 pci_read_config_byte(dev, PCI_SECONDARY_BUS, 401 if (dev->subordinate) {
402 &sec_bus); 402 new_bus = dev->subordinate;
403 new_bus = pci_add_new_bus(dev->bus, dev, 403 new_ppb = 1;
404 sec_bus); 404 }
405 pci_scan_child_bus(new_bus);
406 new_ppb = 1;
407 } 405 }
408 pci_dev_put(dev); 406 pci_dev_put(dev);
409 } 407 }
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 7414fd9ad1d2..b6de307248e4 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -99,22 +99,28 @@ static int init_slots(struct controller *ctrl)
99 struct hotplug_slot *hotplug_slot; 99 struct hotplug_slot *hotplug_slot;
100 struct hotplug_slot_info *info; 100 struct hotplug_slot_info *info;
101 char name[SLOT_NAME_SIZE]; 101 char name[SLOT_NAME_SIZE];
102 int retval = -ENOMEM; 102 int retval;
103 int i; 103 int i;
104 104
105 for (i = 0; i < ctrl->num_slots; i++) { 105 for (i = 0; i < ctrl->num_slots; i++) {
106 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 106 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
107 if (!slot) 107 if (!slot) {
108 retval = -ENOMEM;
108 goto error; 109 goto error;
110 }
109 111
110 hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL); 112 hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL);
111 if (!hotplug_slot) 113 if (!hotplug_slot) {
114 retval = -ENOMEM;
112 goto error_slot; 115 goto error_slot;
116 }
113 slot->hotplug_slot = hotplug_slot; 117 slot->hotplug_slot = hotplug_slot;
114 118
115 info = kzalloc(sizeof(*info), GFP_KERNEL); 119 info = kzalloc(sizeof(*info), GFP_KERNEL);
116 if (!info) 120 if (!info) {
121 retval = -ENOMEM;
117 goto error_hpslot; 122 goto error_hpslot;
123 }
118 hotplug_slot->info = info; 124 hotplug_slot->info = info;
119 125
120 slot->hp_slot = i; 126 slot->hp_slot = i;
diff --git a/drivers/pci/hotplug/shpchp_ctrl.c b/drivers/pci/hotplug/shpchp_ctrl.c
index b00b09bdd38a..f9b5a52e4115 100644
--- a/drivers/pci/hotplug/shpchp_ctrl.c
+++ b/drivers/pci/hotplug/shpchp_ctrl.c
@@ -262,9 +262,6 @@ static int board_added(struct slot *p_slot)
262 } 262 }
263 263
264 if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) { 264 if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) {
265 if (slots_not_empty)
266 return WRONG_BUS_FREQUENCY;
267
268 if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) { 265 if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) {
269 ctrl_err(ctrl, "%s: Issue of set bus speed mode command" 266 ctrl_err(ctrl, "%s: Issue of set bus speed mode command"
270 " failed\n", __func__); 267 " failed\n", __func__);
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index df7e4bfadae3..c627ed9957d1 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -37,9 +37,10 @@
37int __ref shpchp_configure_device(struct slot *p_slot) 37int __ref shpchp_configure_device(struct slot *p_slot)
38{ 38{
39 struct pci_dev *dev; 39 struct pci_dev *dev;
40 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
41 int num, fn;
42 struct controller *ctrl = p_slot->ctrl; 40 struct controller *ctrl = p_slot->ctrl;
41 struct pci_dev *bridge = ctrl->pci_dev;
42 struct pci_bus *parent = bridge->subordinate;
43 int num, fn;
43 44
44 dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0)); 45 dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
45 if (dev) { 46 if (dev) {
@@ -61,39 +62,23 @@ int __ref shpchp_configure_device(struct slot *p_slot)
61 if (!dev) 62 if (!dev)
62 continue; 63 continue;
63 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 64 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
64 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { 65 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
65 /* Find an unused bus number for the new bridge */ 66 pci_hp_add_bridge(dev);
66 struct pci_bus *child; 67 pci_dev_put(dev);
67 unsigned char busnr, start = parent->secondary; 68 }
68 unsigned char end = parent->subordinate; 69
69 for (busnr = start; busnr <= end; busnr++) { 70 pci_assign_unassigned_bridge_resources(bridge);
70 if (!pci_find_bus(pci_domain_nr(parent), 71
71 busnr)) 72 for (fn = 0; fn < 8; fn++) {
72 break; 73 dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn));
73 } 74 if (!dev)
74 if (busnr > end) { 75 continue;
75 ctrl_err(ctrl,
76 "No free bus for hot-added bridge\n");
77 pci_dev_put(dev);
78 continue;
79 }
80 child = pci_add_new_bus(parent, dev, busnr);
81 if (!child) {
82 ctrl_err(ctrl, "Cannot add new bus for %s\n",
83 pci_name(dev));
84 pci_dev_put(dev);
85 continue;
86 }
87 child->subordinate = pci_do_scan_bus(child);
88 pci_bus_size_bridges(child);
89 }
90 pci_configure_slot(dev); 76 pci_configure_slot(dev);
91 pci_dev_put(dev); 77 pci_dev_put(dev);
92 } 78 }
93 79
94 pci_bus_assign_resources(parent);
95 pci_bus_add_devices(parent); 80 pci_bus_add_devices(parent);
96 pci_enable_bridges(parent); 81
97 return 0; 82 return 0;
98} 83}
99 84
diff --git a/drivers/pci/hotplug/shpchp_sysfs.c b/drivers/pci/hotplug/shpchp_sysfs.c
index efa30da1ae8f..eeb23ceae4a8 100644
--- a/drivers/pci/hotplug/shpchp_sysfs.c
+++ b/drivers/pci/hotplug/shpchp_sysfs.c
@@ -73,13 +73,13 @@ static ssize_t show_ctrl (struct device *dev, struct device_attribute *attr, cha
73 } 73 }
74 } 74 }
75 out += sprintf(out, "Free resources: bus numbers\n"); 75 out += sprintf(out, "Free resources: bus numbers\n");
76 for (busnr = bus->secondary; busnr <= bus->subordinate; busnr++) { 76 for (busnr = bus->busn_res.start; busnr <= bus->busn_res.end; busnr++) {
77 if (!pci_find_bus(pci_domain_nr(bus), busnr)) 77 if (!pci_find_bus(pci_domain_nr(bus), busnr))
78 break; 78 break;
79 } 79 }
80 if (busnr < bus->subordinate) 80 if (busnr < bus->busn_res.end)
81 out += sprintf(out, "start = %8.8x, length = %8.8x\n", 81 out += sprintf(out, "start = %8.8x, length = %8.8x\n",
82 busnr, (bus->subordinate - busnr)); 82 busnr, (int)(bus->busn_res.end - busnr));
83 83
84 return out - buf; 84 return out - buf;
85} 85}
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 6554e1a0f634..74bbaf82638d 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -47,7 +47,7 @@ static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
47 if (!child) 47 if (!child)
48 return NULL; 48 return NULL;
49 49
50 child->subordinate = busnr; 50 pci_bus_insert_busn_res(child, busnr, busnr);
51 child->dev.parent = bus->bridge; 51 child->dev.parent = bus->bridge;
52 rc = pci_bus_add_child(child); 52 rc = pci_bus_add_child(child);
53 if (rc) { 53 if (rc) {
@@ -327,7 +327,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
327 iov->offset = offset; 327 iov->offset = offset;
328 iov->stride = stride; 328 iov->stride = stride;
329 329
330 if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->subordinate) { 330 if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->busn_res.end) {
331 dev_err(&dev->dev, "SR-IOV: bus number out of range\n"); 331 dev_err(&dev->dev, "SR-IOV: bus number out of range\n");
332 return -ENOMEM; 332 return -ENOMEM;
333 } 333 }
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 61e2fefeedab..c5792d622dc4 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -48,6 +48,12 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context)
48 if (event != ACPI_NOTIFY_DEVICE_WAKE || !pci_dev) 48 if (event != ACPI_NOTIFY_DEVICE_WAKE || !pci_dev)
49 return; 49 return;
50 50
51 if (pci_dev->current_state == PCI_D3cold) {
52 pci_wakeup_event(pci_dev);
53 pm_runtime_resume(&pci_dev->dev);
54 return;
55 }
56
51 if (!pci_dev->pm_cap || !pci_dev->pme_support 57 if (!pci_dev->pm_cap || !pci_dev->pme_support
52 || pci_check_pme_status(pci_dev)) { 58 || pci_check_pme_status(pci_dev)) {
53 if (pci_dev->pme_poll) 59 if (pci_dev->pme_poll)
@@ -162,6 +168,20 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
162 return remove_pm_notifier(dev, pci_acpi_wake_dev); 168 return remove_pm_notifier(dev, pci_acpi_wake_dev);
163} 169}
164 170
171phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
172{
173 acpi_status status = AE_NOT_EXIST;
174 unsigned long long mcfg_addr;
175
176 if (handle)
177 status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
178 NULL, &mcfg_addr);
179 if (ACPI_FAILURE(status))
180 return 0;
181
182 return (phys_addr_t)mcfg_addr;
183}
184
165/* 185/*
166 * _SxD returns the D-state with the highest power 186 * _SxD returns the D-state with the highest power
167 * (lowest D-state number) supported in the S-state "x". 187 * (lowest D-state number) supported in the S-state "x".
@@ -187,9 +207,13 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
187 207
188static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 208static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
189{ 209{
190 int acpi_state; 210 int acpi_state, d_max;
191 211
192 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL); 212 if (pdev->no_d3cold)
213 d_max = ACPI_STATE_D3_HOT;
214 else
215 d_max = ACPI_STATE_D3_COLD;
216 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
193 if (acpi_state < 0) 217 if (acpi_state < 0)
194 return PCI_POWER_ERROR; 218 return PCI_POWER_ERROR;
195 219
@@ -242,8 +266,8 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
242 } 266 }
243 267
244 if (!error) 268 if (!error)
245 dev_printk(KERN_INFO, &dev->dev, 269 dev_info(&dev->dev, "power state changed by ACPI to %s\n",
246 "power state changed by ACPI to D%d\n", state); 270 pci_power_name(state));
247 271
248 return error; 272 return error;
249} 273}
@@ -296,7 +320,13 @@ static void acpi_pci_propagate_run_wake(struct pci_bus *bus, bool enable)
296 320
297static int acpi_pci_run_wake(struct pci_dev *dev, bool enable) 321static int acpi_pci_run_wake(struct pci_dev *dev, bool enable)
298{ 322{
299 if (dev->pme_interrupt) 323 /*
324 * Per PCI Express Base Specification Revision 2.0 section
325 * 5.3.3.2 Link Wakeup, platform support is needed for D3cold
326 * waking up to power on the main link even if there is PME
327 * support for D3cold
328 */
329 if (dev->pme_interrupt && !dev->runtime_d3cold)
300 return 0; 330 return 0;
301 331
302 if (!acpi_pm_device_run_wake(&dev->dev, enable)) 332 if (!acpi_pm_device_run_wake(&dev->dev, enable))
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 099f46cd8e87..d6fd6b6d9d4b 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -280,8 +280,12 @@ static long local_pci_probe(void *_ddi)
280{ 280{
281 struct drv_dev_and_id *ddi = _ddi; 281 struct drv_dev_and_id *ddi = _ddi;
282 struct device *dev = &ddi->dev->dev; 282 struct device *dev = &ddi->dev->dev;
283 struct device *parent = dev->parent;
283 int rc; 284 int rc;
284 285
286 /* The parent bridge must be in active state when probing */
287 if (parent)
288 pm_runtime_get_sync(parent);
285 /* Unbound PCI devices are always set to disabled and suspended. 289 /* Unbound PCI devices are always set to disabled and suspended.
286 * During probe, the device is set to enabled and active and the 290 * During probe, the device is set to enabled and active and the
287 * usage count is incremented. If the driver supports runtime PM, 291 * usage count is incremented. If the driver supports runtime PM,
@@ -298,6 +302,8 @@ static long local_pci_probe(void *_ddi)
298 pm_runtime_set_suspended(dev); 302 pm_runtime_set_suspended(dev);
299 pm_runtime_put_noidle(dev); 303 pm_runtime_put_noidle(dev);
300 } 304 }
305 if (parent)
306 pm_runtime_put(parent);
301 return rc; 307 return rc;
302} 308}
303 309
@@ -459,16 +465,17 @@ static int pci_restore_standard_config(struct pci_dev *pci_dev)
459 return 0; 465 return 0;
460} 466}
461 467
468#endif
469
470#ifdef CONFIG_PM_SLEEP
471
462static void pci_pm_default_resume_early(struct pci_dev *pci_dev) 472static void pci_pm_default_resume_early(struct pci_dev *pci_dev)
463{ 473{
464 pci_restore_standard_config(pci_dev); 474 pci_power_up(pci_dev);
475 pci_restore_state(pci_dev);
465 pci_fixup_device(pci_fixup_resume_early, pci_dev); 476 pci_fixup_device(pci_fixup_resume_early, pci_dev);
466} 477}
467 478
468#endif
469
470#ifdef CONFIG_PM_SLEEP
471
472/* 479/*
473 * Default "suspend" method for devices that have no driver provided suspend, 480 * Default "suspend" method for devices that have no driver provided suspend,
474 * or not even a driver at all (second part). 481 * or not even a driver at all (second part).
@@ -958,6 +965,13 @@ static int pci_pm_poweroff_noirq(struct device *dev)
958 if (!pci_dev->state_saved && !pci_is_bridge(pci_dev)) 965 if (!pci_dev->state_saved && !pci_is_bridge(pci_dev))
959 pci_prepare_to_sleep(pci_dev); 966 pci_prepare_to_sleep(pci_dev);
960 967
968 /*
969 * The reason for doing this here is the same as for the analogous code
970 * in pci_pm_suspend_noirq().
971 */
972 if (pci_dev->class == PCI_CLASS_SERIAL_USB_EHCI)
973 pci_write_config_word(pci_dev, PCI_COMMAND, 0);
974
961 return 0; 975 return 0;
962} 976}
963 977
@@ -1031,10 +1045,13 @@ static int pci_pm_runtime_suspend(struct device *dev)
1031 if (!pm || !pm->runtime_suspend) 1045 if (!pm || !pm->runtime_suspend)
1032 return -ENOSYS; 1046 return -ENOSYS;
1033 1047
1048 pci_dev->no_d3cold = false;
1034 error = pm->runtime_suspend(dev); 1049 error = pm->runtime_suspend(dev);
1035 suspend_report_result(pm->runtime_suspend, error); 1050 suspend_report_result(pm->runtime_suspend, error);
1036 if (error) 1051 if (error)
1037 return error; 1052 return error;
1053 if (!pci_dev->d3cold_allowed)
1054 pci_dev->no_d3cold = true;
1038 1055
1039 pci_fixup_device(pci_fixup_suspend, pci_dev); 1056 pci_fixup_device(pci_fixup_suspend, pci_dev);
1040 1057
@@ -1056,17 +1073,23 @@ static int pci_pm_runtime_suspend(struct device *dev)
1056 1073
1057static int pci_pm_runtime_resume(struct device *dev) 1074static int pci_pm_runtime_resume(struct device *dev)
1058{ 1075{
1076 int rc;
1059 struct pci_dev *pci_dev = to_pci_dev(dev); 1077 struct pci_dev *pci_dev = to_pci_dev(dev);
1060 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 1078 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
1061 1079
1062 if (!pm || !pm->runtime_resume) 1080 if (!pm || !pm->runtime_resume)
1063 return -ENOSYS; 1081 return -ENOSYS;
1064 1082
1065 pci_pm_default_resume_early(pci_dev); 1083 pci_restore_standard_config(pci_dev);
1084 pci_fixup_device(pci_fixup_resume_early, pci_dev);
1066 __pci_enable_wake(pci_dev, PCI_D0, true, false); 1085 __pci_enable_wake(pci_dev, PCI_D0, true, false);
1067 pci_fixup_device(pci_fixup_resume, pci_dev); 1086 pci_fixup_device(pci_fixup_resume, pci_dev);
1068 1087
1069 return pm->runtime_resume(dev); 1088 rc = pm->runtime_resume(dev);
1089
1090 pci_dev->runtime_d3cold = false;
1091
1092 return rc;
1070} 1093}
1071 1094
1072static int pci_pm_runtime_idle(struct device *dev) 1095static int pci_pm_runtime_idle(struct device *dev)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 86c63fe45d11..02d107b15281 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -28,6 +28,7 @@
28#include <linux/pci-aspm.h> 28#include <linux/pci-aspm.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/vgaarb.h> 30#include <linux/vgaarb.h>
31#include <linux/pm_runtime.h>
31#include "pci.h" 32#include "pci.h"
32 33
33static int sysfs_initialized; /* = 0 */ 34static int sysfs_initialized; /* = 0 */
@@ -378,6 +379,31 @@ dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
378 379
379#endif 380#endif
380 381
382#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
383static ssize_t d3cold_allowed_store(struct device *dev,
384 struct device_attribute *attr,
385 const char *buf, size_t count)
386{
387 struct pci_dev *pdev = to_pci_dev(dev);
388 unsigned long val;
389
390 if (strict_strtoul(buf, 0, &val) < 0)
391 return -EINVAL;
392
393 pdev->d3cold_allowed = !!val;
394 pm_runtime_resume(dev);
395
396 return count;
397}
398
399static ssize_t d3cold_allowed_show(struct device *dev,
400 struct device_attribute *attr, char *buf)
401{
402 struct pci_dev *pdev = to_pci_dev(dev);
403 return sprintf (buf, "%u\n", pdev->d3cold_allowed);
404}
405#endif
406
381struct device_attribute pci_dev_attrs[] = { 407struct device_attribute pci_dev_attrs[] = {
382 __ATTR_RO(resource), 408 __ATTR_RO(resource),
383 __ATTR_RO(vendor), 409 __ATTR_RO(vendor),
@@ -402,6 +428,9 @@ struct device_attribute pci_dev_attrs[] = {
402 __ATTR(remove, (S_IWUSR|S_IWGRP), NULL, remove_store), 428 __ATTR(remove, (S_IWUSR|S_IWGRP), NULL, remove_store),
403 __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_rescan_store), 429 __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_rescan_store),
404#endif 430#endif
431#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
432 __ATTR(d3cold_allowed, 0644, d3cold_allowed_show, d3cold_allowed_store),
433#endif
405 __ATTR_NULL, 434 __ATTR_NULL,
406}; 435};
407 436
@@ -429,6 +458,40 @@ boot_vga_show(struct device *dev, struct device_attribute *attr, char *buf)
429} 458}
430struct device_attribute vga_attr = __ATTR_RO(boot_vga); 459struct device_attribute vga_attr = __ATTR_RO(boot_vga);
431 460
461static void
462pci_config_pm_runtime_get(struct pci_dev *pdev)
463{
464 struct device *dev = &pdev->dev;
465 struct device *parent = dev->parent;
466
467 if (parent)
468 pm_runtime_get_sync(parent);
469 pm_runtime_get_noresume(dev);
470 /*
471 * pdev->current_state is set to PCI_D3cold during suspending,
472 * so wait until suspending completes
473 */
474 pm_runtime_barrier(dev);
475 /*
476 * Only need to resume devices in D3cold, because config
477 * registers are still accessible for devices suspended but
478 * not in D3cold.
479 */
480 if (pdev->current_state == PCI_D3cold)
481 pm_runtime_resume(dev);
482}
483
484static void
485pci_config_pm_runtime_put(struct pci_dev *pdev)
486{
487 struct device *dev = &pdev->dev;
488 struct device *parent = dev->parent;
489
490 pm_runtime_put(dev);
491 if (parent)
492 pm_runtime_put_sync(parent);
493}
494
432static ssize_t 495static ssize_t
433pci_read_config(struct file *filp, struct kobject *kobj, 496pci_read_config(struct file *filp, struct kobject *kobj,
434 struct bin_attribute *bin_attr, 497 struct bin_attribute *bin_attr,
@@ -455,6 +518,8 @@ pci_read_config(struct file *filp, struct kobject *kobj,
455 size = count; 518 size = count;
456 } 519 }
457 520
521 pci_config_pm_runtime_get(dev);
522
458 if ((off & 1) && size) { 523 if ((off & 1) && size) {
459 u8 val; 524 u8 val;
460 pci_user_read_config_byte(dev, off, &val); 525 pci_user_read_config_byte(dev, off, &val);
@@ -500,6 +565,8 @@ pci_read_config(struct file *filp, struct kobject *kobj,
500 --size; 565 --size;
501 } 566 }
502 567
568 pci_config_pm_runtime_put(dev);
569
503 return count; 570 return count;
504} 571}
505 572
@@ -520,6 +587,8 @@ pci_write_config(struct file* filp, struct kobject *kobj,
520 count = size; 587 count = size;
521 } 588 }
522 589
590 pci_config_pm_runtime_get(dev);
591
523 if ((off & 1) && size) { 592 if ((off & 1) && size) {
524 pci_user_write_config_byte(dev, off, data[off - init_off]); 593 pci_user_write_config_byte(dev, off, data[off - init_off]);
525 off++; 594 off++;
@@ -558,6 +627,8 @@ pci_write_config(struct file* filp, struct kobject *kobj,
558 --size; 627 --size;
559 } 628 }
560 629
630 pci_config_pm_runtime_put(dev);
631
561 return count; 632 return count;
562} 633}
563 634
@@ -1112,7 +1183,7 @@ static struct bin_attribute pcie_config_attr = {
1112 .write = pci_write_config, 1183 .write = pci_write_config,
1113}; 1184};
1114 1185
1115int __attribute__ ((weak)) pcibios_add_platform_entries(struct pci_dev *dev) 1186int __weak pcibios_add_platform_entries(struct pci_dev *dev)
1116{ 1187{
1117 return 0; 1188 return 0;
1118} 1189}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 447e83472c01..ab4bf5a4c2f1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -110,7 +110,7 @@ unsigned char pci_bus_max_busnr(struct pci_bus* bus)
110 struct list_head *tmp; 110 struct list_head *tmp;
111 unsigned char max, n; 111 unsigned char max, n;
112 112
113 max = bus->subordinate; 113 max = bus->busn_res.end;
114 list_for_each(tmp, &bus->children) { 114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp)); 115 n = pci_bus_max_busnr(pci_bus_b(tmp));
116 if(n > max) 116 if(n > max)
@@ -136,30 +136,6 @@ void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
136EXPORT_SYMBOL_GPL(pci_ioremap_bar); 136EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137#endif 137#endif
138 138
139#if 0
140/**
141 * pci_max_busnr - returns maximum PCI bus number
142 *
143 * Returns the highest PCI bus number present in the system global list of
144 * PCI buses.
145 */
146unsigned char __devinit
147pci_max_busnr(void)
148{
149 struct pci_bus *bus = NULL;
150 unsigned char max, n;
151
152 max = 0;
153 while ((bus = pci_find_next_bus(bus)) != NULL) {
154 n = pci_bus_max_busnr(bus);
155 if(n > max)
156 max = n;
157 }
158 return max;
159}
160
161#endif /* 0 */
162
163#define PCI_FIND_CAP_TTL 48 139#define PCI_FIND_CAP_TTL 48
164 140
165static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 141static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
@@ -278,6 +254,38 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
278} 254}
279 255
280/** 256/**
257 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
258 * @dev: PCI device to check
259 *
260 * Like pci_pcie_cap() but also checks that the PCIe capability version is
261 * >= 2. Note that v1 capability structures could be sparse in that not
262 * all register fields were required. v2 requires the entire structure to
263 * be present size wise, while still allowing for non-implemented registers
264 * to exist but they must be hardwired to 0.
265 *
266 * Due to the differences in the versions of capability structures, one
267 * must be careful not to try and access non-existant registers that may
268 * exist in early versions - v1 - of Express devices.
269 *
270 * Returns the offset of the PCIe capability structure as long as the
271 * capability version is >= 2; otherwise 0 is returned.
272 */
273static int pci_pcie_cap2(struct pci_dev *dev)
274{
275 u16 flags;
276 int pos;
277
278 pos = pci_pcie_cap(dev);
279 if (pos) {
280 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
281 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
282 pos = 0;
283 }
284
285 return pos;
286}
287
288/**
281 * pci_find_ext_capability - Find an extended capability 289 * pci_find_ext_capability - Find an extended capability
282 * @dev: PCI device to query 290 * @dev: PCI device to query
283 * @cap: capability code 291 * @cap: capability code
@@ -329,49 +337,6 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
329} 337}
330EXPORT_SYMBOL_GPL(pci_find_ext_capability); 338EXPORT_SYMBOL_GPL(pci_find_ext_capability);
331 339
332/**
333 * pci_bus_find_ext_capability - find an extended capability
334 * @bus: the PCI bus to query
335 * @devfn: PCI device to query
336 * @cap: capability code
337 *
338 * Like pci_find_ext_capability() but works for pci devices that do not have a
339 * pci_dev structure set up yet.
340 *
341 * Returns the address of the requested capability structure within the
342 * device's PCI configuration space or 0 in case the device does not
343 * support it.
344 */
345int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
346 int cap)
347{
348 u32 header;
349 int ttl;
350 int pos = PCI_CFG_SPACE_SIZE;
351
352 /* minimum 8 bytes per capability */
353 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
354
355 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
356 return 0;
357 if (header == 0xffffffff || header == 0)
358 return 0;
359
360 while (ttl-- > 0) {
361 if (PCI_EXT_CAP_ID(header) == cap)
362 return pos;
363
364 pos = PCI_EXT_CAP_NEXT(header);
365 if (pos < PCI_CFG_SPACE_SIZE)
366 break;
367
368 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
369 break;
370 }
371
372 return 0;
373}
374
375static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 340static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
376{ 341{
377 int rc, ttl = PCI_FIND_CAP_TTL; 342 int rc, ttl = PCI_FIND_CAP_TTL;
@@ -622,7 +587,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
622 dev_info(&dev->dev, "Refused to change power state, " 587 dev_info(&dev->dev, "Refused to change power state, "
623 "currently in D%d\n", dev->current_state); 588 "currently in D%d\n", dev->current_state);
624 589
625 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 590 /*
591 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
626 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 592 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
627 * from D3hot to D0 _may_ perform an internal reset, thereby 593 * from D3hot to D0 _may_ perform an internal reset, thereby
628 * going to "D0 Uninitialized" rather than "D0 Initialized". 594 * going to "D0 Uninitialized" rather than "D0 Initialized".
@@ -654,6 +620,16 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
654 if (dev->pm_cap) { 620 if (dev->pm_cap) {
655 u16 pmcsr; 621 u16 pmcsr;
656 622
623 /*
624 * Configuration space is not accessible for device in
625 * D3cold, so just keep or set D3cold for safety
626 */
627 if (dev->current_state == PCI_D3cold)
628 return;
629 if (state == PCI_D3cold) {
630 dev->current_state = PCI_D3cold;
631 return;
632 }
657 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 633 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
658 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 634 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
659 } else { 635 } else {
@@ -662,6 +638,19 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
662} 638}
663 639
664/** 640/**
641 * pci_power_up - Put the given device into D0 forcibly
642 * @dev: PCI device to power up
643 */
644void pci_power_up(struct pci_dev *dev)
645{
646 if (platform_pci_power_manageable(dev))
647 platform_pci_set_power_state(dev, PCI_D0);
648
649 pci_raw_set_power_state(dev, PCI_D0);
650 pci_update_current_state(dev, PCI_D0);
651}
652
653/**
665 * pci_platform_power_transition - Use platform to change device power state 654 * pci_platform_power_transition - Use platform to change device power state
666 * @dev: PCI device to handle. 655 * @dev: PCI device to handle.
667 * @state: State to put the device into. 656 * @state: State to put the device into.
@@ -694,8 +683,50 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
694 */ 683 */
695static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 684static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
696{ 685{
697 if (state == PCI_D0) 686 if (state == PCI_D0) {
698 pci_platform_power_transition(dev, PCI_D0); 687 pci_platform_power_transition(dev, PCI_D0);
688 /*
689 * Mandatory power management transition delays, see
690 * PCI Express Base Specification Revision 2.0 Section
691 * 6.6.1: Conventional Reset. Do not delay for
692 * devices powered on/off by corresponding bridge,
693 * because have already delayed for the bridge.
694 */
695 if (dev->runtime_d3cold) {
696 msleep(dev->d3cold_delay);
697 /*
698 * When powering on a bridge from D3cold, the
699 * whole hierarchy may be powered on into
700 * D0uninitialized state, resume them to give
701 * them a chance to suspend again
702 */
703 pci_wakeup_bus(dev->subordinate);
704 }
705 }
706}
707
708/**
709 * __pci_dev_set_current_state - Set current state of a PCI device
710 * @dev: Device to handle
711 * @data: pointer to state to be set
712 */
713static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
714{
715 pci_power_t state = *(pci_power_t *)data;
716
717 dev->current_state = state;
718 return 0;
719}
720
721/**
722 * __pci_bus_set_current_state - Walk given bus and set current state of devices
723 * @bus: Top bus of the subtree to walk.
724 * @state: state to be set
725 */
726static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
727{
728 if (bus)
729 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
699} 730}
700 731
701/** 732/**
@@ -707,8 +738,15 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
707 */ 738 */
708int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 739int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
709{ 740{
710 return state >= PCI_D0 ? 741 int ret;
711 pci_platform_power_transition(dev, state) : -EINVAL; 742
743 if (state <= PCI_D0)
744 return -EINVAL;
745 ret = pci_platform_power_transition(dev, state);
746 /* Power off the bridge may power off the whole hierarchy */
747 if (!ret && state == PCI_D3cold)
748 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
749 return ret;
712} 750}
713EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 751EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
714 752
@@ -732,8 +770,8 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
732 int error; 770 int error;
733 771
734 /* bound the state we're entering */ 772 /* bound the state we're entering */
735 if (state > PCI_D3hot) 773 if (state > PCI_D3cold)
736 state = PCI_D3hot; 774 state = PCI_D3cold;
737 else if (state < PCI_D0) 775 else if (state < PCI_D0)
738 state = PCI_D0; 776 state = PCI_D0;
739 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 777 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
@@ -744,14 +782,23 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
744 */ 782 */
745 return 0; 783 return 0;
746 784
785 /* Check if we're already there */
786 if (dev->current_state == state)
787 return 0;
788
747 __pci_start_power_transition(dev, state); 789 __pci_start_power_transition(dev, state);
748 790
749 /* This device is quirked not to be put into D3, so 791 /* This device is quirked not to be put into D3, so
750 don't put it in D3 */ 792 don't put it in D3 */
751 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 793 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
752 return 0; 794 return 0;
753 795
754 error = pci_raw_set_power_state(dev, state); 796 /*
797 * To put device in D3cold, we put device into D3hot in native
798 * way, then put device into D3cold with platform ops
799 */
800 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
801 PCI_D3hot : state);
755 802
756 if (!__pci_complete_power_transition(dev, state)) 803 if (!__pci_complete_power_transition(dev, state))
757 error = 0; 804 error = 0;
@@ -822,12 +869,6 @@ EXPORT_SYMBOL(pci_choose_state);
822 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 869 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
823 (type == PCI_EXP_TYPE_ROOT_PORT || \ 870 (type == PCI_EXP_TYPE_ROOT_PORT || \
824 type == PCI_EXP_TYPE_RC_EC)) 871 type == PCI_EXP_TYPE_RC_EC))
825#define pcie_cap_has_devctl2(type, flags) \
826 ((flags & PCI_EXP_FLAGS_VERS) > 1)
827#define pcie_cap_has_lnkctl2(type, flags) \
828 ((flags & PCI_EXP_FLAGS_VERS) > 1)
829#define pcie_cap_has_sltctl2(type, flags) \
830 ((flags & PCI_EXP_FLAGS_VERS) > 1)
831 872
832static struct pci_cap_saved_state *pci_find_saved_cap( 873static struct pci_cap_saved_state *pci_find_saved_cap(
833 struct pci_dev *pci_dev, char cap) 874 struct pci_dev *pci_dev, char cap)
@@ -870,13 +911,14 @@ static int pci_save_pcie_state(struct pci_dev *dev)
870 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 911 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
871 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 912 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
872 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 913 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
873 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
874 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
875 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
876 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
877 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
878 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
879 914
915 pos = pci_pcie_cap2(dev);
916 if (!pos)
917 return 0;
918
919 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
920 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
921 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
880 return 0; 922 return 0;
881} 923}
882 924
@@ -903,12 +945,14 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
903 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 945 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
904 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 946 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
905 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 947 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
906 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 948
907 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 949 pos = pci_pcie_cap2(dev);
908 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 950 if (!pos)
909 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 951 return;
910 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 952
911 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 953 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
954 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
955 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
912} 956}
913 957
914 958
@@ -1349,7 +1393,7 @@ void pcim_pin_device(struct pci_dev *pdev)
1349 * is the default implementation. Architecture implementations can 1393 * is the default implementation. Architecture implementations can
1350 * override this. 1394 * override this.
1351 */ 1395 */
1352void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 1396void __weak pcibios_disable_device (struct pci_dev *dev) {}
1353 1397
1354static void do_pci_disable_device(struct pci_dev *dev) 1398static void do_pci_disable_device(struct pci_dev *dev)
1355{ 1399{
@@ -1413,8 +1457,8 @@ pci_disable_device(struct pci_dev *dev)
1413 * Sets the PCIe reset state for the device. This is the default 1457 * Sets the PCIe reset state for the device. This is the default
1414 * implementation. Architecture implementations can override this. 1458 * implementation. Architecture implementations can override this.
1415 */ 1459 */
1416int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, 1460int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1417 enum pcie_reset_state state) 1461 enum pcie_reset_state state)
1418{ 1462{
1419 return -EINVAL; 1463 return -EINVAL;
1420} 1464}
@@ -1498,6 +1542,28 @@ void pci_pme_wakeup_bus(struct pci_bus *bus)
1498} 1542}
1499 1543
1500/** 1544/**
1545 * pci_wakeup - Wake up a PCI device
1546 * @dev: Device to handle.
1547 * @ign: ignored parameter
1548 */
1549static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1550{
1551 pci_wakeup_event(pci_dev);
1552 pm_request_resume(&pci_dev->dev);
1553 return 0;
1554}
1555
1556/**
1557 * pci_wakeup_bus - Walk given bus and wake up devices on it
1558 * @bus: Top bus of the subtree to walk.
1559 */
1560void pci_wakeup_bus(struct pci_bus *bus)
1561{
1562 if (bus)
1563 pci_walk_bus(bus, pci_wakeup, NULL);
1564}
1565
1566/**
1501 * pci_pme_capable - check the capability of PCI device to generate PME# 1567 * pci_pme_capable - check the capability of PCI device to generate PME#
1502 * @dev: PCI device to handle. 1568 * @dev: PCI device to handle.
1503 * @state: PCI state from which device will issue PME#. 1569 * @state: PCI state from which device will issue PME#.
@@ -1518,6 +1584,16 @@ static void pci_pme_list_scan(struct work_struct *work)
1518 if (!list_empty(&pci_pme_list)) { 1584 if (!list_empty(&pci_pme_list)) {
1519 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1585 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1520 if (pme_dev->dev->pme_poll) { 1586 if (pme_dev->dev->pme_poll) {
1587 struct pci_dev *bridge;
1588
1589 bridge = pme_dev->dev->bus->self;
1590 /*
1591 * If bridge is in low power state, the
1592 * configuration space of subordinate devices
1593 * may be not accessible
1594 */
1595 if (bridge && bridge->current_state != PCI_D0)
1596 continue;
1521 pci_pme_wakeup(pme_dev->dev, NULL); 1597 pci_pme_wakeup(pme_dev->dev, NULL);
1522 } else { 1598 } else {
1523 list_del(&pme_dev->list); 1599 list_del(&pme_dev->list);
@@ -1744,6 +1820,10 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
1744 if (target_state == PCI_POWER_ERROR) 1820 if (target_state == PCI_POWER_ERROR)
1745 return -EIO; 1821 return -EIO;
1746 1822
1823 /* D3cold during system suspend/hibernate is not supported */
1824 if (target_state > PCI_D3hot)
1825 target_state = PCI_D3hot;
1826
1747 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1827 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1748 1828
1749 error = pci_set_power_state(dev, target_state); 1829 error = pci_set_power_state(dev, target_state);
@@ -1781,12 +1861,16 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
1781 if (target_state == PCI_POWER_ERROR) 1861 if (target_state == PCI_POWER_ERROR)
1782 return -EIO; 1862 return -EIO;
1783 1863
1864 dev->runtime_d3cold = target_state == PCI_D3cold;
1865
1784 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 1866 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1785 1867
1786 error = pci_set_power_state(dev, target_state); 1868 error = pci_set_power_state(dev, target_state);
1787 1869
1788 if (error) 1870 if (error) {
1789 __pci_enable_wake(dev, target_state, true, false); 1871 __pci_enable_wake(dev, target_state, true, false);
1872 dev->runtime_d3cold = false;
1873 }
1790 1874
1791 return error; 1875 return error;
1792} 1876}
@@ -1856,6 +1940,8 @@ void pci_pm_init(struct pci_dev *dev)
1856 1940
1857 dev->pm_cap = pm; 1941 dev->pm_cap = pm;
1858 dev->d3_delay = PCI_PM_D3_WAIT; 1942 dev->d3_delay = PCI_PM_D3_WAIT;
1943 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1944 dev->d3cold_allowed = true;
1859 1945
1860 dev->d1_support = false; 1946 dev->d1_support = false;
1861 dev->d2_support = false; 1947 dev->d2_support = false;
@@ -1983,7 +2069,7 @@ void pci_enable_ari(struct pci_dev *dev)
1983{ 2069{
1984 int pos; 2070 int pos;
1985 u32 cap; 2071 u32 cap;
1986 u16 flags, ctrl; 2072 u16 ctrl;
1987 struct pci_dev *bridge; 2073 struct pci_dev *bridge;
1988 2074
1989 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2075 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
@@ -1994,18 +2080,14 @@ void pci_enable_ari(struct pci_dev *dev)
1994 return; 2080 return;
1995 2081
1996 bridge = dev->bus->self; 2082 bridge = dev->bus->self;
1997 if (!bridge || !pci_is_pcie(bridge)) 2083 if (!bridge)
1998 return; 2084 return;
1999 2085
2000 pos = pci_pcie_cap(bridge); 2086 /* ARI is a PCIe cap v2 feature */
2087 pos = pci_pcie_cap2(bridge);
2001 if (!pos) 2088 if (!pos)
2002 return; 2089 return;
2003 2090
2004 /* ARI is a PCIe v2 feature */
2005 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
2006 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
2007 return;
2008
2009 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); 2091 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2010 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2092 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2011 return; 2093 return;
@@ -2018,7 +2100,7 @@ void pci_enable_ari(struct pci_dev *dev)
2018} 2100}
2019 2101
2020/** 2102/**
2021 * pci_enable_ido - enable ID-based ordering on a device 2103 * pci_enable_ido - enable ID-based Ordering on a device
2022 * @dev: the PCI device 2104 * @dev: the PCI device
2023 * @type: which types of IDO to enable 2105 * @type: which types of IDO to enable
2024 * 2106 *
@@ -2031,7 +2113,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2031 int pos; 2113 int pos;
2032 u16 ctrl; 2114 u16 ctrl;
2033 2115
2034 pos = pci_pcie_cap(dev); 2116 /* ID-based Ordering is a PCIe cap v2 feature */
2117 pos = pci_pcie_cap2(dev);
2035 if (!pos) 2118 if (!pos)
2036 return; 2119 return;
2037 2120
@@ -2054,10 +2137,8 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2054 int pos; 2137 int pos;
2055 u16 ctrl; 2138 u16 ctrl;
2056 2139
2057 if (!pci_is_pcie(dev)) 2140 /* ID-based Ordering is a PCIe cap v2 feature */
2058 return; 2141 pos = pci_pcie_cap2(dev);
2059
2060 pos = pci_pcie_cap(dev);
2061 if (!pos) 2142 if (!pos)
2062 return; 2143 return;
2063 2144
@@ -2096,10 +2177,8 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2096 u16 ctrl; 2177 u16 ctrl;
2097 int ret; 2178 int ret;
2098 2179
2099 if (!pci_is_pcie(dev)) 2180 /* OBFF is a PCIe cap v2 feature */
2100 return -ENOTSUPP; 2181 pos = pci_pcie_cap2(dev);
2101
2102 pos = pci_pcie_cap(dev);
2103 if (!pos) 2182 if (!pos)
2104 return -ENOTSUPP; 2183 return -ENOTSUPP;
2105 2184
@@ -2108,7 +2187,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2108 return -ENOTSUPP; /* no OBFF support at all */ 2187 return -ENOTSUPP; /* no OBFF support at all */
2109 2188
2110 /* Make sure the topology supports OBFF as well */ 2189 /* Make sure the topology supports OBFF as well */
2111 if (dev->bus) { 2190 if (dev->bus->self) {
2112 ret = pci_enable_obff(dev->bus->self, type); 2191 ret = pci_enable_obff(dev->bus->self, type);
2113 if (ret) 2192 if (ret)
2114 return ret; 2193 return ret;
@@ -2149,10 +2228,8 @@ void pci_disable_obff(struct pci_dev *dev)
2149 int pos; 2228 int pos;
2150 u16 ctrl; 2229 u16 ctrl;
2151 2230
2152 if (!pci_is_pcie(dev)) 2231 /* OBFF is a PCIe cap v2 feature */
2153 return; 2232 pos = pci_pcie_cap2(dev);
2154
2155 pos = pci_pcie_cap(dev);
2156 if (!pos) 2233 if (!pos)
2157 return; 2234 return;
2158 2235
@@ -2169,15 +2246,13 @@ EXPORT_SYMBOL(pci_disable_obff);
2169 * RETURNS: 2246 * RETURNS:
2170 * True if @dev supports latency tolerance reporting, false otherwise. 2247 * True if @dev supports latency tolerance reporting, false otherwise.
2171 */ 2248 */
2172bool pci_ltr_supported(struct pci_dev *dev) 2249static bool pci_ltr_supported(struct pci_dev *dev)
2173{ 2250{
2174 int pos; 2251 int pos;
2175 u32 cap; 2252 u32 cap;
2176 2253
2177 if (!pci_is_pcie(dev)) 2254 /* LTR is a PCIe cap v2 feature */
2178 return false; 2255 pos = pci_pcie_cap2(dev);
2179
2180 pos = pci_pcie_cap(dev);
2181 if (!pos) 2256 if (!pos)
2182 return false; 2257 return false;
2183 2258
@@ -2185,7 +2260,6 @@ bool pci_ltr_supported(struct pci_dev *dev)
2185 2260
2186 return cap & PCI_EXP_DEVCAP2_LTR; 2261 return cap & PCI_EXP_DEVCAP2_LTR;
2187} 2262}
2188EXPORT_SYMBOL(pci_ltr_supported);
2189 2263
2190/** 2264/**
2191 * pci_enable_ltr - enable latency tolerance reporting 2265 * pci_enable_ltr - enable latency tolerance reporting
@@ -2206,7 +2280,8 @@ int pci_enable_ltr(struct pci_dev *dev)
2206 if (!pci_ltr_supported(dev)) 2280 if (!pci_ltr_supported(dev))
2207 return -ENOTSUPP; 2281 return -ENOTSUPP;
2208 2282
2209 pos = pci_pcie_cap(dev); 2283 /* LTR is a PCIe cap v2 feature */
2284 pos = pci_pcie_cap2(dev);
2210 if (!pos) 2285 if (!pos)
2211 return -ENOTSUPP; 2286 return -ENOTSUPP;
2212 2287
@@ -2215,7 +2290,7 @@ int pci_enable_ltr(struct pci_dev *dev)
2215 return -EINVAL; 2290 return -EINVAL;
2216 2291
2217 /* Enable upstream ports first */ 2292 /* Enable upstream ports first */
2218 if (dev->bus) { 2293 if (dev->bus->self) {
2219 ret = pci_enable_ltr(dev->bus->self); 2294 ret = pci_enable_ltr(dev->bus->self);
2220 if (ret) 2295 if (ret)
2221 return ret; 2296 return ret;
@@ -2241,7 +2316,8 @@ void pci_disable_ltr(struct pci_dev *dev)
2241 if (!pci_ltr_supported(dev)) 2316 if (!pci_ltr_supported(dev))
2242 return; 2317 return;
2243 2318
2244 pos = pci_pcie_cap(dev); 2319 /* LTR is a PCIe cap v2 feature */
2320 pos = pci_pcie_cap2(dev);
2245 if (!pos) 2321 if (!pos)
2246 return; 2322 return;
2247 2323
@@ -2360,6 +2436,75 @@ void pci_enable_acs(struct pci_dev *dev)
2360} 2436}
2361 2437
2362/** 2438/**
2439 * pci_acs_enabled - test ACS against required flags for a given device
2440 * @pdev: device to test
2441 * @acs_flags: required PCI ACS flags
2442 *
2443 * Return true if the device supports the provided flags. Automatically
2444 * filters out flags that are not implemented on multifunction devices.
2445 */
2446bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2447{
2448 int pos, ret;
2449 u16 ctrl;
2450
2451 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2452 if (ret >= 0)
2453 return ret > 0;
2454
2455 if (!pci_is_pcie(pdev))
2456 return false;
2457
2458 /* Filter out flags not applicable to multifunction */
2459 if (pdev->multifunction)
2460 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2461 PCI_ACS_EC | PCI_ACS_DT);
2462
2463 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM ||
2464 pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2465 pdev->multifunction) {
2466 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2467 if (!pos)
2468 return false;
2469
2470 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2471 if ((ctrl & acs_flags) != acs_flags)
2472 return false;
2473 }
2474
2475 return true;
2476}
2477
2478/**
2479 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2480 * @start: starting downstream device
2481 * @end: ending upstream device or NULL to search to the root bus
2482 * @acs_flags: required flags
2483 *
2484 * Walk up a device tree from start to end testing PCI ACS support. If
2485 * any step along the way does not support the required flags, return false.
2486 */
2487bool pci_acs_path_enabled(struct pci_dev *start,
2488 struct pci_dev *end, u16 acs_flags)
2489{
2490 struct pci_dev *pdev, *parent = start;
2491
2492 do {
2493 pdev = parent;
2494
2495 if (!pci_acs_enabled(pdev, acs_flags))
2496 return false;
2497
2498 if (pci_is_root_bus(pdev->bus))
2499 return (end == NULL);
2500
2501 parent = pdev->bus->self;
2502 } while (pdev != end);
2503
2504 return true;
2505}
2506
2507/**
2363 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2508 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2364 * @dev: the PCI device 2509 * @dev: the PCI device
2365 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2510 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
@@ -2666,6 +2811,18 @@ static void __pci_set_master(struct pci_dev *dev, bool enable)
2666} 2811}
2667 2812
2668/** 2813/**
2814 * pcibios_setup - process "pci=" kernel boot arguments
2815 * @str: string used to pass in "pci=" kernel boot arguments
2816 *
2817 * Process kernel boot arguments. This is the default implementation.
2818 * Architecture specific implementations can override this as necessary.
2819 */
2820char * __weak __init pcibios_setup(char *str)
2821{
2822 return str;
2823}
2824
2825/**
2669 * pcibios_set_master - enable PCI bus-mastering for device dev 2826 * pcibios_set_master - enable PCI bus-mastering for device dev
2670 * @dev: the PCI device to enable 2827 * @dev: the PCI device to enable
2671 * 2828 *
@@ -2876,6 +3033,9 @@ bool pci_intx_mask_supported(struct pci_dev *dev)
2876 bool mask_supported = false; 3033 bool mask_supported = false;
2877 u16 orig, new; 3034 u16 orig, new;
2878 3035
3036 if (dev->broken_intx_masking)
3037 return false;
3038
2879 pci_cfg_access_lock(dev); 3039 pci_cfg_access_lock(dev);
2880 3040
2881 pci_read_config_word(dev, PCI_COMMAND, &orig); 3041 pci_read_config_word(dev, PCI_COMMAND, &orig);
@@ -3395,8 +3555,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3395 3555
3396 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 3556 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3397 if (o != v) { 3557 if (o != v) {
3398 if (v > o && dev->bus && 3558 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3399 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3400 return -EIO; 3559 return -EIO;
3401 3560
3402 cmd &= ~PCI_X_CMD_MAX_READ; 3561 cmd &= ~PCI_X_CMD_MAX_READ;
@@ -3851,7 +4010,7 @@ static void __devinit pci_no_domains(void)
3851 * greater than 0xff). This is the default implementation. Architecture 4010 * greater than 0xff). This is the default implementation. Architecture
3852 * implementations can override this. 4011 * implementations can override this.
3853 */ 4012 */
3854int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) 4013int __weak pci_ext_cfg_avail(struct pci_dev *dev)
3855{ 4014{
3856 return 1; 4015 return 1;
3857} 4016}
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index e4943479b234..bacbcba69cf3 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -67,9 +67,11 @@ struct pci_platform_pm_ops {
67 67
68extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops); 68extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
69extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 69extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
70extern void pci_power_up(struct pci_dev *dev);
70extern void pci_disable_enabled_device(struct pci_dev *dev); 71extern void pci_disable_enabled_device(struct pci_dev *dev);
71extern int pci_finish_runtime_suspend(struct pci_dev *dev); 72extern int pci_finish_runtime_suspend(struct pci_dev *dev);
72extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 73extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
74extern void pci_wakeup_bus(struct pci_bus *bus);
73extern void pci_pm_init(struct pci_dev *dev); 75extern void pci_pm_init(struct pci_dev *dev);
74extern void platform_pci_wakeup_init(struct pci_dev *dev); 76extern void platform_pci_wakeup_init(struct pci_dev *dev);
75extern void pci_allocate_cap_save_buffers(struct pci_dev *dev); 77extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
@@ -86,13 +88,6 @@ static inline bool pci_is_bridge(struct pci_dev *pci_dev)
86 return !!(pci_dev->subordinate); 88 return !!(pci_dev->subordinate);
87} 89}
88 90
89extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
90extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
91extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
92extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
93extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
94extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
95
96struct pci_vpd_ops { 91struct pci_vpd_ops {
97 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 92 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
98 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 93 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
@@ -124,7 +119,7 @@ static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
124#endif 119#endif
125 120
126/* Functions for PCI Hotplug drivers to use */ 121/* Functions for PCI Hotplug drivers to use */
127extern unsigned int pci_do_scan_bus(struct pci_bus *bus); 122int pci_hp_add_bridge(struct pci_dev *dev);
128 123
129#ifdef HAVE_PCI_LEGACY 124#ifdef HAVE_PCI_LEGACY
130extern void pci_create_legacy_files(struct pci_bus *bus); 125extern void pci_create_legacy_files(struct pci_bus *bus);
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c
index 275bf158ffa7..124f20ff11b2 100644
--- a/drivers/pci/pcie/aer/aerdrv_acpi.c
+++ b/drivers/pci/pcie/aer/aerdrv_acpi.c
@@ -59,7 +59,7 @@ static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
59 59
60 p = (struct acpi_hest_aer_common *)(hest_hdr + 1); 60 p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
61 if (p->flags & ACPI_HEST_GLOBAL) { 61 if (p->flags & ACPI_HEST_GLOBAL) {
62 if ((info->pci_dev->is_pcie && 62 if ((pci_is_pcie(info->pci_dev) &&
63 info->pci_dev->pcie_type == pcie_type) || bridge) 63 info->pci_dev->pcie_type == pcie_type) || bridge)
64 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST); 64 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
65 } else 65 } else
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index e0610bda1dea..e76b44777dbf 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -11,6 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/pm.h> 13#include <linux/pm.h>
14#include <linux/pm_runtime.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/pcieport_if.h> 16#include <linux/pcieport_if.h>
16#include <linux/aer.h> 17#include <linux/aer.h>
@@ -99,6 +100,59 @@ static int pcie_port_resume_noirq(struct device *dev)
99 return 0; 100 return 0;
100} 101}
101 102
103#ifdef CONFIG_PM_RUNTIME
104struct d3cold_info {
105 bool no_d3cold;
106 unsigned int d3cold_delay;
107};
108
109static int pci_dev_d3cold_info(struct pci_dev *pdev, void *data)
110{
111 struct d3cold_info *info = data;
112
113 info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
114 info->d3cold_delay);
115 if (pdev->no_d3cold)
116 info->no_d3cold = true;
117 return 0;
118}
119
120static int pcie_port_runtime_suspend(struct device *dev)
121{
122 struct pci_dev *pdev = to_pci_dev(dev);
123 struct d3cold_info d3cold_info = {
124 .no_d3cold = false,
125 .d3cold_delay = PCI_PM_D3_WAIT,
126 };
127
128 /*
129 * If any subordinate device disable D3cold, we should not put
130 * the port into D3cold. The D3cold delay of port should be
131 * the max of that of all subordinate devices.
132 */
133 pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
134 pdev->no_d3cold = d3cold_info.no_d3cold;
135 pdev->d3cold_delay = d3cold_info.d3cold_delay;
136 return 0;
137}
138
139static int pcie_port_runtime_resume(struct device *dev)
140{
141 return 0;
142}
143
144static int pcie_port_runtime_idle(struct device *dev)
145{
146 /* Delay for a short while to prevent too frequent suspend/resume */
147 pm_schedule_suspend(dev, 10);
148 return -EBUSY;
149}
150#else
151#define pcie_port_runtime_suspend NULL
152#define pcie_port_runtime_resume NULL
153#define pcie_port_runtime_idle NULL
154#endif
155
102static const struct dev_pm_ops pcie_portdrv_pm_ops = { 156static const struct dev_pm_ops pcie_portdrv_pm_ops = {
103 .suspend = pcie_port_device_suspend, 157 .suspend = pcie_port_device_suspend,
104 .resume = pcie_port_device_resume, 158 .resume = pcie_port_device_resume,
@@ -107,6 +161,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
107 .poweroff = pcie_port_device_suspend, 161 .poweroff = pcie_port_device_suspend,
108 .restore = pcie_port_device_resume, 162 .restore = pcie_port_device_resume,
109 .resume_noirq = pcie_port_resume_noirq, 163 .resume_noirq = pcie_port_resume_noirq,
164 .runtime_suspend = pcie_port_runtime_suspend,
165 .runtime_resume = pcie_port_runtime_resume,
166 .runtime_idle = pcie_port_runtime_idle,
110}; 167};
111 168
112#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops) 169#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
@@ -117,6 +174,14 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
117#endif /* !PM */ 174#endif /* !PM */
118 175
119/* 176/*
177 * PCIe port runtime suspend is broken for some chipsets, so use a
178 * black list to disable runtime PM for these chipsets.
179 */
180static const struct pci_device_id port_runtime_pm_black_list[] = {
181 { /* end: all zeroes */ }
182};
183
184/*
120 * pcie_portdrv_probe - Probe PCI-Express port devices 185 * pcie_portdrv_probe - Probe PCI-Express port devices
121 * @dev: PCI-Express port device being probed 186 * @dev: PCI-Express port device being probed
122 * 187 *
@@ -144,12 +209,21 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
144 return status; 209 return status;
145 210
146 pci_save_state(dev); 211 pci_save_state(dev);
212 /*
213 * D3cold may not work properly on some PCIe port, so disable
214 * it by default.
215 */
216 dev->d3cold_allowed = false;
217 if (!pci_match_id(port_runtime_pm_black_list, dev))
218 pm_runtime_put_noidle(&dev->dev);
147 219
148 return 0; 220 return 0;
149} 221}
150 222
151static void pcie_portdrv_remove(struct pci_dev *dev) 223static void pcie_portdrv_remove(struct pci_dev *dev)
152{ 224{
225 if (!pci_match_id(port_runtime_pm_black_list, dev))
226 pm_runtime_get_noresume(&dev->dev);
153 pcie_port_device_remove(dev); 227 pcie_port_device_remove(dev);
154 pci_disable_device(dev); 228 pci_disable_device(dev);
155} 229}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 658ac977cb56..9f8a6b79a8ec 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -16,10 +16,47 @@
16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17#define CARDBUS_RESERVE_BUSNR 3 17#define CARDBUS_RESERVE_BUSNR 3
18 18
19struct resource busn_resource = {
20 .name = "PCI busn",
21 .start = 0,
22 .end = 255,
23 .flags = IORESOURCE_BUS,
24};
25
19/* Ugh. Need to stop exporting this to modules. */ 26/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses); 27LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses); 28EXPORT_SYMBOL(pci_root_buses);
22 29
30static LIST_HEAD(pci_domain_busn_res_list);
31
32struct pci_domain_busn_res {
33 struct list_head list;
34 struct resource res;
35 int domain_nr;
36};
37
38static struct resource *get_pci_domain_busn_res(int domain_nr)
39{
40 struct pci_domain_busn_res *r;
41
42 list_for_each_entry(r, &pci_domain_busn_res_list, list)
43 if (r->domain_nr == domain_nr)
44 return &r->res;
45
46 r = kzalloc(sizeof(*r), GFP_KERNEL);
47 if (!r)
48 return NULL;
49
50 r->domain_nr = domain_nr;
51 r->res.start = 0;
52 r->res.end = 0xff;
53 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
54
55 list_add_tail(&r->list, &pci_domain_busn_res_list);
56
57 return &r->res;
58}
59
23static int find_anything(struct device *dev, void *data) 60static int find_anything(struct device *dev, void *data)
24{ 61{
25 return 1; 62 return 1;
@@ -107,15 +144,13 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
107 case PCI_BASE_ADDRESS_MEM_TYPE_32: 144 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break; 145 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 146 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); 147 /* 1M mem BAR treated as 32-bit BAR */
111 break; 148 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64: 149 case PCI_BASE_ADDRESS_MEM_TYPE_64:
113 flags |= IORESOURCE_MEM_64; 150 flags |= IORESOURCE_MEM_64;
114 break; 151 break;
115 default: 152 default:
116 dev_warn(&dev->dev, 153 /* mem unknown type treated as 32-bit BAR */
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break; 154 break;
120 } 155 }
121 return flags; 156 return flags;
@@ -136,9 +171,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
136 u32 l, sz, mask; 171 u32 l, sz, mask;
137 u16 orig_cmd; 172 u16 orig_cmd;
138 struct pci_bus_region region; 173 struct pci_bus_region region;
174 bool bar_too_big = false, bar_disabled = false;
139 175
140 mask = type ? PCI_ROM_ADDRESS_MASK : ~0; 176 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
141 177
178 /* No printks while decoding is disabled! */
142 if (!dev->mmio_always_on) { 179 if (!dev->mmio_always_on) {
143 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 180 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
144 pci_write_config_word(dev, PCI_COMMAND, 181 pci_write_config_word(dev, PCI_COMMAND,
@@ -152,9 +189,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
152 pci_read_config_dword(dev, pos, &sz); 189 pci_read_config_dword(dev, pos, &sz);
153 pci_write_config_dword(dev, pos, l); 190 pci_write_config_dword(dev, pos, l);
154 191
155 if (!dev->mmio_always_on)
156 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
157
158 /* 192 /*
159 * All bits set in sz means the device isn't working properly. 193 * All bits set in sz means the device isn't working properly.
160 * If the BAR isn't implemented, all bits must be 0. If it's a 194 * If the BAR isn't implemented, all bits must be 0. If it's a
@@ -206,8 +240,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
206 goto fail; 240 goto fail;
207 241
208 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 242 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
209 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", 243 bar_too_big = true;
210 pos);
211 goto fail; 244 goto fail;
212 } 245 }
213 246
@@ -218,12 +251,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
218 region.start = 0; 251 region.start = 0;
219 region.end = sz64; 252 region.end = sz64;
220 pcibios_bus_to_resource(dev, res, &region); 253 pcibios_bus_to_resource(dev, res, &region);
254 bar_disabled = true;
221 } else { 255 } else {
222 region.start = l64; 256 region.start = l64;
223 region.end = l64 + sz64; 257 region.end = l64 + sz64;
224 pcibios_bus_to_resource(dev, res, &region); 258 pcibios_bus_to_resource(dev, res, &region);
225 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
226 pos, res);
227 } 259 }
228 } else { 260 } else {
229 sz = pci_size(l, sz, mask); 261 sz = pci_size(l, sz, mask);
@@ -234,15 +266,23 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
234 region.start = l; 266 region.start = l;
235 region.end = l + sz; 267 region.end = l + sz;
236 pcibios_bus_to_resource(dev, res, &region); 268 pcibios_bus_to_resource(dev, res, &region);
269 }
270
271 goto out;
272
273
274fail:
275 res->flags = 0;
276out:
277 if (!dev->mmio_always_on)
278 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
237 279
280 if (bar_too_big)
281 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", pos);
282 if (res->flags && !bar_disabled)
238 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); 283 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
239 }
240 284
241 out:
242 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 285 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
243 fail:
244 res->flags = 0;
245 goto out;
246} 286}
247 287
248static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 288static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
@@ -269,34 +309,38 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child)
269{ 309{
270 struct pci_dev *dev = child->self; 310 struct pci_dev *dev = child->self;
271 u8 io_base_lo, io_limit_lo; 311 u8 io_base_lo, io_limit_lo;
272 unsigned long base, limit; 312 unsigned long io_mask, io_granularity, base, limit;
273 struct pci_bus_region region; 313 struct pci_bus_region region;
274 struct resource *res, res2; 314 struct resource *res;
315
316 io_mask = PCI_IO_RANGE_MASK;
317 io_granularity = 0x1000;
318 if (dev->io_window_1k) {
319 /* Support 1K I/O space granularity */
320 io_mask = PCI_IO_1K_RANGE_MASK;
321 io_granularity = 0x400;
322 }
275 323
276 res = child->resource[0]; 324 res = child->resource[0];
277 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 325 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
278 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 326 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
279 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 327 base = (io_base_lo & io_mask) << 8;
280 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 328 limit = (io_limit_lo & io_mask) << 8;
281 329
282 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 330 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
283 u16 io_base_hi, io_limit_hi; 331 u16 io_base_hi, io_limit_hi;
332
284 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 333 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
285 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 334 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
286 base |= (io_base_hi << 16); 335 base |= ((unsigned long) io_base_hi << 16);
287 limit |= (io_limit_hi << 16); 336 limit |= ((unsigned long) io_limit_hi << 16);
288 } 337 }
289 338
290 if (base && base <= limit) { 339 if (base <= limit) {
291 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 340 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
292 res2.flags = res->flags;
293 region.start = base; 341 region.start = base;
294 region.end = limit + 0xfff; 342 region.end = limit + io_granularity - 1;
295 pcibios_bus_to_resource(dev, &res2, &region); 343 pcibios_bus_to_resource(dev, res, &region);
296 if (!res->start)
297 res->start = res2.start;
298 if (!res->end)
299 res->end = res2.end;
300 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 344 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
301 } 345 }
302} 346}
@@ -312,9 +356,9 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
312 res = child->resource[1]; 356 res = child->resource[1];
313 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 357 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
314 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 358 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
315 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 359 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
316 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 360 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
317 if (base && base <= limit) { 361 if (base <= limit) {
318 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 362 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
319 region.start = base; 363 region.start = base;
320 region.end = limit + 0xfffff; 364 region.end = limit + 0xfffff;
@@ -334,11 +378,12 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
334 res = child->resource[2]; 378 res = child->resource[2];
335 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 379 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
336 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 380 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
337 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 381 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
338 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 382 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
339 383
340 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 384 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
341 u32 mem_base_hi, mem_limit_hi; 385 u32 mem_base_hi, mem_limit_hi;
386
342 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 387 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
343 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 388 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
344 389
@@ -349,8 +394,8 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
349 */ 394 */
350 if (mem_base_hi <= mem_limit_hi) { 395 if (mem_base_hi <= mem_limit_hi) {
351#if BITS_PER_LONG == 64 396#if BITS_PER_LONG == 64
352 base |= ((long) mem_base_hi) << 32; 397 base |= ((unsigned long) mem_base_hi) << 32;
353 limit |= ((long) mem_limit_hi) << 32; 398 limit |= ((unsigned long) mem_limit_hi) << 32;
354#else 399#else
355 if (mem_base_hi || mem_limit_hi) { 400 if (mem_base_hi || mem_limit_hi) {
356 dev_err(&dev->dev, "can't handle 64-bit " 401 dev_err(&dev->dev, "can't handle 64-bit "
@@ -360,7 +405,7 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
360#endif 405#endif
361 } 406 }
362 } 407 }
363 if (base && base <= limit) { 408 if (base <= limit) {
364 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 409 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
365 IORESOURCE_MEM | IORESOURCE_PREFETCH; 410 IORESOURCE_MEM | IORESOURCE_PREFETCH;
366 if (res->flags & PCI_PREF_RANGE_TYPE_64) 411 if (res->flags & PCI_PREF_RANGE_TYPE_64)
@@ -381,8 +426,8 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
381 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 426 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
382 return; 427 return;
383 428
384 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 429 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
385 child->secondary, child->subordinate, 430 &child->busn_res,
386 dev->transparent ? " (subtractive decode)" : ""); 431 dev->transparent ? " (subtractive decode)" : "");
387 432
388 pci_bus_remove_resources(child); 433 pci_bus_remove_resources(child);
@@ -599,9 +644,9 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
599 * Set up the primary, secondary and subordinate 644 * Set up the primary, secondary and subordinate
600 * bus numbers. 645 * bus numbers.
601 */ 646 */
602 child->number = child->secondary = busnr; 647 child->number = child->busn_res.start = busnr;
603 child->primary = parent->secondary; 648 child->primary = parent->busn_res.start;
604 child->subordinate = 0xff; 649 child->busn_res.end = 0xff;
605 650
606 if (!bridge) 651 if (!bridge)
607 return child; 652 return child;
@@ -643,8 +688,8 @@ static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
643 if (!pcibios_assign_all_busses()) 688 if (!pcibios_assign_all_busses())
644 return; 689 return;
645 690
646 while (parent->parent && parent->subordinate < max) { 691 while (parent->parent && parent->busn_res.end < max) {
647 parent->subordinate = max; 692 parent->busn_res.end = max;
648 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 693 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
649 parent = parent->parent; 694 parent = parent->parent;
650 } 695 }
@@ -718,15 +763,15 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
718 if (!child) 763 if (!child)
719 goto out; 764 goto out;
720 child->primary = primary; 765 child->primary = primary;
721 child->subordinate = subordinate; 766 pci_bus_insert_busn_res(child, secondary, subordinate);
722 child->bridge_ctl = bctl; 767 child->bridge_ctl = bctl;
723 } 768 }
724 769
725 cmax = pci_scan_child_bus(child); 770 cmax = pci_scan_child_bus(child);
726 if (cmax > max) 771 if (cmax > max)
727 max = cmax; 772 max = cmax;
728 if (child->subordinate > max) 773 if (child->busn_res.end > max)
729 max = child->subordinate; 774 max = child->busn_res.end;
730 } else { 775 } else {
731 /* 776 /*
732 * We need to assign a number to this bus which we always 777 * We need to assign a number to this bus which we always
@@ -756,11 +801,12 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
756 child = pci_add_new_bus(bus, dev, ++max); 801 child = pci_add_new_bus(bus, dev, ++max);
757 if (!child) 802 if (!child)
758 goto out; 803 goto out;
804 pci_bus_insert_busn_res(child, max, 0xff);
759 } 805 }
760 buses = (buses & 0xff000000) 806 buses = (buses & 0xff000000)
761 | ((unsigned int)(child->primary) << 0) 807 | ((unsigned int)(child->primary) << 0)
762 | ((unsigned int)(child->secondary) << 8) 808 | ((unsigned int)(child->busn_res.start) << 8)
763 | ((unsigned int)(child->subordinate) << 16); 809 | ((unsigned int)(child->busn_res.end) << 16);
764 810
765 /* 811 /*
766 * yenta.c forces a secondary latency timer of 176. 812 * yenta.c forces a secondary latency timer of 176.
@@ -805,8 +851,8 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
805 break; 851 break;
806 while (parent->parent) { 852 while (parent->parent) {
807 if ((!pcibios_assign_all_busses()) && 853 if ((!pcibios_assign_all_busses()) &&
808 (parent->subordinate > max) && 854 (parent->busn_res.end > max) &&
809 (parent->subordinate <= max+i)) { 855 (parent->busn_res.end <= max+i)) {
810 j = 1; 856 j = 1;
811 } 857 }
812 parent = parent->parent; 858 parent = parent->parent;
@@ -827,7 +873,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
827 /* 873 /*
828 * Set the subordinate bus number to its real value. 874 * Set the subordinate bus number to its real value.
829 */ 875 */
830 child->subordinate = max; 876 pci_bus_update_busn_res_end(child, max);
831 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 877 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
832 } 878 }
833 879
@@ -837,19 +883,19 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
837 883
838 /* Has only triggered on CardBus, fixup is in yenta_socket */ 884 /* Has only triggered on CardBus, fixup is in yenta_socket */
839 while (bus->parent) { 885 while (bus->parent) {
840 if ((child->subordinate > bus->subordinate) || 886 if ((child->busn_res.end > bus->busn_res.end) ||
841 (child->number > bus->subordinate) || 887 (child->number > bus->busn_res.end) ||
842 (child->number < bus->number) || 888 (child->number < bus->number) ||
843 (child->subordinate < bus->number)) { 889 (child->busn_res.end < bus->number)) {
844 dev_info(&child->dev, "[bus %02x-%02x] %s " 890 dev_info(&child->dev, "%pR %s "
845 "hidden behind%s bridge %s [bus %02x-%02x]\n", 891 "hidden behind%s bridge %s %pR\n",
846 child->number, child->subordinate, 892 &child->busn_res,
847 (bus->number > child->subordinate && 893 (bus->number > child->busn_res.end &&
848 bus->subordinate < child->number) ? 894 bus->busn_res.end < child->number) ?
849 "wholly" : "partially", 895 "wholly" : "partially",
850 bus->self->transparent ? " transparent" : "", 896 bus->self->transparent ? " transparent" : "",
851 dev_name(&bus->dev), 897 dev_name(&bus->dev),
852 bus->number, bus->subordinate); 898 &bus->busn_res);
853 } 899 }
854 bus = bus->parent; 900 bus = bus->parent;
855 } 901 }
@@ -1548,7 +1594,7 @@ EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1548 1594
1549unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1595unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1550{ 1596{
1551 unsigned int devfn, pass, max = bus->secondary; 1597 unsigned int devfn, pass, max = bus->busn_res.start;
1552 struct pci_dev *dev; 1598 struct pci_dev *dev;
1553 1599
1554 dev_dbg(&bus->dev, "scanning bus\n"); 1600 dev_dbg(&bus->dev, "scanning bus\n");
@@ -1642,7 +1688,7 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1642 /* Create legacy_io and legacy_mem files for this bus */ 1688 /* Create legacy_io and legacy_mem files for this bus */
1643 pci_create_legacy_files(b); 1689 pci_create_legacy_files(b);
1644 1690
1645 b->number = b->secondary = bus; 1691 b->number = b->busn_res.start = bus;
1646 1692
1647 if (parent) 1693 if (parent)
1648 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); 1694 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
@@ -1654,7 +1700,10 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1654 list_move_tail(&window->list, &bridge->windows); 1700 list_move_tail(&window->list, &bridge->windows);
1655 res = window->res; 1701 res = window->res;
1656 offset = window->offset; 1702 offset = window->offset;
1657 pci_bus_add_resource(b, res, 0); 1703 if (res->flags & IORESOURCE_BUS)
1704 pci_bus_insert_busn_res(b, bus, res->end);
1705 else
1706 pci_bus_add_resource(b, res, 0);
1658 if (offset) { 1707 if (offset) {
1659 if (resource_type(res) == IORESOURCE_IO) 1708 if (resource_type(res) == IORESOURCE_IO)
1660 fmt = " (bus address [%#06llx-%#06llx])"; 1709 fmt = " (bus address [%#06llx-%#06llx])";
@@ -1684,16 +1733,104 @@ err_out:
1684 return NULL; 1733 return NULL;
1685} 1734}
1686 1735
1736int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1737{
1738 struct resource *res = &b->busn_res;
1739 struct resource *parent_res, *conflict;
1740
1741 res->start = bus;
1742 res->end = bus_max;
1743 res->flags = IORESOURCE_BUS;
1744
1745 if (!pci_is_root_bus(b))
1746 parent_res = &b->parent->busn_res;
1747 else {
1748 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
1749 res->flags |= IORESOURCE_PCI_FIXED;
1750 }
1751
1752 conflict = insert_resource_conflict(parent_res, res);
1753
1754 if (conflict)
1755 dev_printk(KERN_DEBUG, &b->dev,
1756 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1757 res, pci_is_root_bus(b) ? "domain " : "",
1758 parent_res, conflict->name, conflict);
1759 else
1760 dev_printk(KERN_DEBUG, &b->dev,
1761 "busn_res: %pR is inserted under %s%pR\n",
1762 res, pci_is_root_bus(b) ? "domain " : "",
1763 parent_res);
1764
1765 return conflict == NULL;
1766}
1767
1768int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
1769{
1770 struct resource *res = &b->busn_res;
1771 struct resource old_res = *res;
1772 resource_size_t size;
1773 int ret;
1774
1775 if (res->start > bus_max)
1776 return -EINVAL;
1777
1778 size = bus_max - res->start + 1;
1779 ret = adjust_resource(res, res->start, size);
1780 dev_printk(KERN_DEBUG, &b->dev,
1781 "busn_res: %pR end %s updated to %02x\n",
1782 &old_res, ret ? "can not be" : "is", bus_max);
1783
1784 if (!ret && !res->parent)
1785 pci_bus_insert_busn_res(b, res->start, res->end);
1786
1787 return ret;
1788}
1789
1790void pci_bus_release_busn_res(struct pci_bus *b)
1791{
1792 struct resource *res = &b->busn_res;
1793 int ret;
1794
1795 if (!res->flags || !res->parent)
1796 return;
1797
1798 ret = release_resource(res);
1799 dev_printk(KERN_DEBUG, &b->dev,
1800 "busn_res: %pR %s released\n",
1801 res, ret ? "can not be" : "is");
1802}
1803
1687struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, 1804struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1688 struct pci_ops *ops, void *sysdata, struct list_head *resources) 1805 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1689{ 1806{
1807 struct pci_host_bridge_window *window;
1808 bool found = false;
1690 struct pci_bus *b; 1809 struct pci_bus *b;
1810 int max;
1811
1812 list_for_each_entry(window, resources, list)
1813 if (window->res->flags & IORESOURCE_BUS) {
1814 found = true;
1815 break;
1816 }
1691 1817
1692 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 1818 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1693 if (!b) 1819 if (!b)
1694 return NULL; 1820 return NULL;
1695 1821
1696 b->subordinate = pci_scan_child_bus(b); 1822 if (!found) {
1823 dev_info(&b->dev,
1824 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1825 bus);
1826 pci_bus_insert_busn_res(b, bus, 255);
1827 }
1828
1829 max = pci_scan_child_bus(b);
1830
1831 if (!found)
1832 pci_bus_update_busn_res_end(b, max);
1833
1697 pci_bus_add_devices(b); 1834 pci_bus_add_devices(b);
1698 return b; 1835 return b;
1699} 1836}
@@ -1708,9 +1845,10 @@ struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1708 1845
1709 pci_add_resource(&resources, &ioport_resource); 1846 pci_add_resource(&resources, &ioport_resource);
1710 pci_add_resource(&resources, &iomem_resource); 1847 pci_add_resource(&resources, &iomem_resource);
1848 pci_add_resource(&resources, &busn_resource);
1711 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); 1849 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1712 if (b) 1850 if (b)
1713 b->subordinate = pci_scan_child_bus(b); 1851 pci_scan_child_bus(b);
1714 else 1852 else
1715 pci_free_resource_list(&resources); 1853 pci_free_resource_list(&resources);
1716 return b; 1854 return b;
@@ -1725,9 +1863,10 @@ struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1725 1863
1726 pci_add_resource(&resources, &ioport_resource); 1864 pci_add_resource(&resources, &ioport_resource);
1727 pci_add_resource(&resources, &iomem_resource); 1865 pci_add_resource(&resources, &iomem_resource);
1866 pci_add_resource(&resources, &busn_resource);
1728 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 1867 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1729 if (b) { 1868 if (b) {
1730 b->subordinate = pci_scan_child_bus(b); 1869 pci_scan_child_bus(b);
1731 pci_bus_add_devices(b); 1870 pci_bus_add_devices(b);
1732 } else { 1871 } else {
1733 pci_free_resource_list(&resources); 1872 pci_free_resource_list(&resources);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2a7521677541..51553179e967 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -253,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx)
253 * workaround applied too 253 * workaround applied too
254 * [Info kindly provided by ALi] 254 * [Info kindly provided by ALi]
255 */ 255 */
256static void __init quirk_alimagik(struct pci_dev *dev) 256static void __devinit quirk_alimagik(struct pci_dev *dev)
257{ 257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -789,7 +789,7 @@ static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
789} 789}
790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791 791
792static void __init quirk_ioapic_rmw(struct pci_dev *dev) 792static void __devinit quirk_ioapic_rmw(struct pci_dev *dev)
793{ 793{
794 if (dev->devfn == 0 && dev->bus->number == 0) 794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1; 795 sis_apic_bug = 1;
@@ -801,7 +801,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
801 * Some settings of MMRBC can lead to data corruption so block changes. 801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */ 803 */
804static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 804static void __devinit quirk_amd_8131_mmrbc(struct pci_dev *dev)
805{ 805{
806 if (dev->subordinate && dev->revision <= 0x12) { 806 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; " 807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
@@ -1039,7 +1039,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041 1041
1042static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 1042static void quirk_amd_ide_mode(struct pci_dev *pdev)
1043{ 1043{
1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045 u8 tmp; 1045 u8 tmp;
@@ -1082,7 +1082,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB
1082/* 1082/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */ 1084 */
1085static void __init quirk_ide_samemode(struct pci_dev *pdev) 1085static void __devinit quirk_ide_samemode(struct pci_dev *pdev)
1086{ 1086{
1087 u8 prog; 1087 u8 prog;
1088 1088
@@ -1121,7 +1121,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1121/* This was originally an Alpha specific thing, but it really fits here. 1121/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */ 1123 */
1124static void __init quirk_eisa_bridge(struct pci_dev *dev) 1124static void __devinit quirk_eisa_bridge(struct pci_dev *dev)
1125{ 1125{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127} 1127}
@@ -1155,7 +1155,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_e
1155 */ 1155 */
1156static int asus_hides_smbus; 1156static int asus_hides_smbus;
1157 1157
1158static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1158static void __devinit asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159{ 1159{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
@@ -1538,7 +1538,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB3
1538#endif 1538#endif
1539 1539
1540#ifdef CONFIG_X86_IO_APIC 1540#ifdef CONFIG_X86_IO_APIC
1541static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1541static void __devinit quirk_alder_ioapic(struct pci_dev *pdev)
1542{ 1542{
1543 int i; 1543 int i;
1544 1544
@@ -1777,7 +1777,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, qui
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed... 1778 * Re-allocate the region if needed...
1779 */ 1779 */
1780static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1780static void __devinit quirk_tc86c001_ide(struct pci_dev *dev)
1781{ 1781{
1782 struct resource *r = &dev->resource[0]; 1782 struct resource *r = &dev->resource[0];
1783 1783
@@ -1938,53 +1938,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1
1938static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1938static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1939{ 1939{
1940 u16 en1k; 1940 u16 en1k;
1941 u8 io_base_lo, io_limit_lo;
1942 unsigned long base, limit;
1943 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1944 1941
1945 pci_read_config_word(dev, 0x40, &en1k); 1942 pci_read_config_word(dev, 0x40, &en1k);
1946 1943
1947 if (en1k & 0x200) { 1944 if (en1k & 0x200) {
1948 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1945 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1949 1946 dev->io_window_1k = 1;
1950 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1951 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1952 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1953 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1954
1955 if (base <= limit) {
1956 res->start = base;
1957 res->end = limit + 0x3ff;
1958 }
1959 } 1947 }
1960} 1948}
1961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1962 1950
1963/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1964 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1965 * in drivers/pci/setup-bus.c
1966 */
1967static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1968{
1969 u16 en1k, iobl_adr, iobl_adr_1k;
1970 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1971
1972 pci_read_config_word(dev, 0x40, &en1k);
1973
1974 if (en1k & 0x200) {
1975 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1976
1977 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1978
1979 if (iobl_adr != iobl_adr_1k) {
1980 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1981 iobl_adr,iobl_adr_1k);
1982 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1983 }
1984 }
1985}
1986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1987
1988/* Under some circumstances, AER is not linked with extended capabilities. 1951/* Under some circumstances, AER is not linked with extended capabilities.
1989 * Force it to be linked by setting the corresponding control bit in the 1952 * Force it to be linked by setting the corresponding control bit in the
1990 * config space. 1953 * config space.
@@ -2104,7 +2067,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2104 PCI_DEVICE_ID_NX2_5709S, 2067 PCI_DEVICE_ID_NX2_5709S,
2105 quirk_brcm_570x_limit_vpd); 2068 quirk_brcm_570x_limit_vpd);
2106 2069
2107static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2070static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2108{ 2071{
2109 u32 rev; 2072 u32 rev;
2110 2073
@@ -2143,9 +2106,9 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2106DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2144 quirk_unhide_mch_dev6); 2107 quirk_unhide_mch_dev6);
2145 2108
2146#ifdef CONFIG_TILE 2109#ifdef CONFIG_TILEPRO
2147/* 2110/*
2148 * The Tilera TILEmpower platform needs to set the link speed 2111 * The Tilera TILEmpower tilepro platform needs to set the link speed
2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2112 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2113 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2151 * capability register of the PEX8624 PCIe switch. The switch 2114 * capability register of the PEX8624 PCIe switch. The switch
@@ -2160,7 +2123,7 @@ static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2160 } 2123 }
2161} 2124}
2162DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2163#endif /* CONFIG_TILE */ 2126#endif /* CONFIG_TILEPRO */
2164 2127
2165#ifdef CONFIG_PCI_MSI 2128#ifdef CONFIG_PCI_MSI
2166/* Some chipsets do not support MSI. We cannot easily rely on setting 2129/* Some chipsets do not support MSI. We cannot easily rely on setting
@@ -2169,7 +2132,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2169 * aware of it. Instead of setting the flag on all busses in the 2132 * aware of it. Instead of setting the flag on all busses in the
2170 * machine, simply disable MSI globally. 2133 * machine, simply disable MSI globally.
2171 */ 2134 */
2172static void __init quirk_disable_all_msi(struct pci_dev *dev) 2135static void __devinit quirk_disable_all_msi(struct pci_dev *dev)
2173{ 2136{
2174 pci_no_msi(); 2137 pci_no_msi();
2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2138 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
@@ -2217,7 +2180,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2217 2180
2218/* Go through the list of Hypertransport capabilities and 2181/* Go through the list of Hypertransport capabilities and
2219 * return 1 if a HT MSI capability is found and enabled */ 2182 * return 1 if a HT MSI capability is found and enabled */
2220static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 2183static int msi_ht_cap_enabled(struct pci_dev *dev)
2221{ 2184{
2222 int pos, ttl = 48; 2185 int pos, ttl = 48;
2223 2186
@@ -2241,7 +2204,7 @@ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2241} 2204}
2242 2205
2243/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2206/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2244static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 2207static void quirk_msi_ht_cap(struct pci_dev *dev)
2245{ 2208{
2246 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2209 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2247 dev_warn(&dev->dev, "MSI quirk detected; " 2210 dev_warn(&dev->dev, "MSI quirk detected; "
@@ -2255,7 +2218,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2
2255/* The nVidia CK804 chipset may have 2 HT MSI mappings. 2218/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2256 * MSI are supported if the MSI capability set in any of these mappings. 2219 * MSI are supported if the MSI capability set in any of these mappings.
2257 */ 2220 */
2258static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2221static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2259{ 2222{
2260 struct pci_dev *pdev; 2223 struct pci_dev *pdev;
2261 2224
@@ -2279,7 +2242,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2279 quirk_nvidia_ck804_msi_ht_cap); 2242 quirk_nvidia_ck804_msi_ht_cap);
2280 2243
2281/* Force enable MSI mapping capability on HT bridges */ 2244/* Force enable MSI mapping capability on HT bridges */
2282static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 2245static void ht_enable_msi_mapping(struct pci_dev *dev)
2283{ 2246{
2284 int pos, ttl = 48; 2247 int pos, ttl = 48;
2285 2248
@@ -2359,7 +2322,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2359 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2322 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2360 nvbridge_check_legacy_irq_routing); 2323 nvbridge_check_legacy_irq_routing);
2361 2324
2362static int __devinit ht_check_msi_mapping(struct pci_dev *dev) 2325static int ht_check_msi_mapping(struct pci_dev *dev)
2363{ 2326{
2364 int pos, ttl = 48; 2327 int pos, ttl = 48;
2365 int found = 0; 2328 int found = 0;
@@ -2387,7 +2350,7 @@ static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2387 return found; 2350 return found;
2388} 2351}
2389 2352
2390static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) 2353static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2391{ 2354{
2392 struct pci_dev *dev; 2355 struct pci_dev *dev;
2393 int pos; 2356 int pos;
@@ -2421,7 +2384,7 @@ static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2421#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2384#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2422#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2385#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2423 2386
2424static int __devinit is_end_of_ht_chain(struct pci_dev *dev) 2387static int is_end_of_ht_chain(struct pci_dev *dev)
2425{ 2388{
2426 int pos, ctrl_off; 2389 int pos, ctrl_off;
2427 int end = 0; 2390 int end = 0;
@@ -2445,7 +2408,7 @@ out:
2445 return end; 2408 return end;
2446} 2409}
2447 2410
2448static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) 2411static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2449{ 2412{
2450 struct pci_dev *host_bridge; 2413 struct pci_dev *host_bridge;
2451 int pos; 2414 int pos;
@@ -2484,7 +2447,7 @@ out:
2484 pci_dev_put(host_bridge); 2447 pci_dev_put(host_bridge);
2485} 2448}
2486 2449
2487static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) 2450static void ht_disable_msi_mapping(struct pci_dev *dev)
2488{ 2451{
2489 int pos, ttl = 48; 2452 int pos, ttl = 48;
2490 2453
@@ -2504,7 +2467,7 @@ static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2504 } 2467 }
2505} 2468}
2506 2469
2507static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2470static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2508{ 2471{
2509 struct pci_dev *host_bridge; 2472 struct pci_dev *host_bridge;
2510 int pos; 2473 int pos;
@@ -2541,23 +2504,26 @@ static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2541 else 2504 else
2542 nv_ht_enable_msi_mapping(dev); 2505 nv_ht_enable_msi_mapping(dev);
2543 } 2506 }
2544 return; 2507 goto out;
2545 } 2508 }
2546 2509
2547 /* HT MSI is not enabled */ 2510 /* HT MSI is not enabled */
2548 if (found == 1) 2511 if (found == 1)
2549 return; 2512 goto out;
2550 2513
2551 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2514 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2552 ht_disable_msi_mapping(dev); 2515 ht_disable_msi_mapping(dev);
2516
2517out:
2518 pci_dev_put(host_bridge);
2553} 2519}
2554 2520
2555static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2521static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2556{ 2522{
2557 return __nv_msi_ht_cap_quirk(dev, 1); 2523 return __nv_msi_ht_cap_quirk(dev, 1);
2558} 2524}
2559 2525
2560static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2526static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2561{ 2527{
2562 return __nv_msi_ht_cap_quirk(dev, 0); 2528 return __nv_msi_ht_cap_quirk(dev, 0);
2563} 2529}
@@ -2879,20 +2845,34 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2880 2846
2881 2847
2882static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev) 2848static ktime_t fixup_debug_start(struct pci_dev *dev,
2849 void (*fn)(struct pci_dev *dev))
2850{
2851 ktime_t calltime = ktime_set(0, 0);
2852
2853 dev_dbg(&dev->dev, "calling %pF\n", fn);
2854 if (initcall_debug) {
2855 pr_debug("calling %pF @ %i for %s\n",
2856 fn, task_pid_nr(current), dev_name(&dev->dev));
2857 calltime = ktime_get();
2858 }
2859
2860 return calltime;
2861}
2862
2863static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2864 void (*fn)(struct pci_dev *dev))
2883{ 2865{
2884 ktime_t calltime, delta, rettime; 2866 ktime_t delta, rettime;
2885 unsigned long long duration; 2867 unsigned long long duration;
2886 2868
2887 printk(KERN_DEBUG "calling %pF @ %i for %s\n", 2869 if (initcall_debug) {
2888 fn, task_pid_nr(current), dev_name(&dev->dev)); 2870 rettime = ktime_get();
2889 calltime = ktime_get(); 2871 delta = ktime_sub(rettime, calltime);
2890 fn(dev); 2872 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2891 rettime = ktime_get(); 2873 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2892 delta = ktime_sub(rettime, calltime); 2874 fn, duration, dev_name(&dev->dev));
2893 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 2875 }
2894 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs for %s\n",
2895 fn, duration, dev_name(&dev->dev));
2896} 2876}
2897 2877
2898/* 2878/*
@@ -2929,9 +2909,25 @@ static void __devinit disable_igfx_irq(struct pci_dev *dev)
2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 2909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 2910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931 2911
2912/*
2913 * Some devices may pass our check in pci_intx_mask_supported if
2914 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2915 * support this feature.
2916 */
2917static void __devinit quirk_broken_intx_masking(struct pci_dev *dev)
2918{
2919 dev->broken_intx_masking = 1;
2920}
2921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2922 quirk_broken_intx_masking);
2923DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2924 quirk_broken_intx_masking);
2925
2932static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2926static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2933 struct pci_fixup *end) 2927 struct pci_fixup *end)
2934{ 2928{
2929 ktime_t calltime;
2930
2935 for (; f < end; f++) 2931 for (; f < end; f++)
2936 if ((f->class == (u32) (dev->class >> f->class_shift) || 2932 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2937 f->class == (u32) PCI_ANY_ID) && 2933 f->class == (u32) PCI_ANY_ID) &&
@@ -2939,11 +2935,9 @@ static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2939 f->vendor == (u16) PCI_ANY_ID) && 2935 f->vendor == (u16) PCI_ANY_ID) &&
2940 (f->device == dev->device || 2936 (f->device == dev->device ||
2941 f->device == (u16) PCI_ANY_ID)) { 2937 f->device == (u16) PCI_ANY_ID)) {
2942 dev_dbg(&dev->dev, "calling %pF\n", f->hook); 2938 calltime = fixup_debug_start(dev, f->hook);
2943 if (initcall_debug) 2939 f->hook(dev);
2944 do_one_fixup_debug(f->hook, dev); 2940 fixup_debug_report(dev, calltime, f->hook);
2945 else
2946 f->hook(dev);
2947 } 2941 }
2948} 2942}
2949 2943
@@ -2962,6 +2956,7 @@ extern struct pci_fixup __end_pci_fixups_resume_early[];
2962extern struct pci_fixup __start_pci_fixups_suspend[]; 2956extern struct pci_fixup __start_pci_fixups_suspend[];
2963extern struct pci_fixup __end_pci_fixups_suspend[]; 2957extern struct pci_fixup __end_pci_fixups_suspend[];
2964 2958
2959static bool pci_apply_fixup_final_quirks;
2965 2960
2966void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2961void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2967{ 2962{
@@ -2979,6 +2974,8 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2979 break; 2974 break;
2980 2975
2981 case pci_fixup_final: 2976 case pci_fixup_final:
2977 if (!pci_apply_fixup_final_quirks)
2978 return;
2982 start = __start_pci_fixups_final; 2979 start = __start_pci_fixups_final;
2983 end = __end_pci_fixups_final; 2980 end = __end_pci_fixups_final;
2984 break; 2981 break;
@@ -3011,6 +3008,7 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3011} 3008}
3012EXPORT_SYMBOL(pci_fixup_device); 3009EXPORT_SYMBOL(pci_fixup_device);
3013 3010
3011
3014static int __init pci_apply_final_quirks(void) 3012static int __init pci_apply_final_quirks(void)
3015{ 3013{
3016 struct pci_dev *dev = NULL; 3014 struct pci_dev *dev = NULL;
@@ -3021,6 +3019,7 @@ static int __init pci_apply_final_quirks(void)
3021 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3019 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3022 pci_cache_line_size << 2); 3020 pci_cache_line_size << 2);
3023 3021
3022 pci_apply_fixup_final_quirks = true;
3024 for_each_pci_dev(dev) { 3023 for_each_pci_dev(dev) {
3025 pci_fixup_device(pci_fixup_final, dev); 3024 pci_fixup_device(pci_fixup_final, dev);
3026 /* 3025 /*
@@ -3041,6 +3040,7 @@ static int __init pci_apply_final_quirks(void)
3041 pci_cache_line_size = pci_dfl_cache_line_size; 3040 pci_cache_line_size = pci_dfl_cache_line_size;
3042 } 3041 }
3043 } 3042 }
3043
3044 if (!pci_cache_line_size) { 3044 if (!pci_cache_line_size) {
3045 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3045 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3046 cls << 2, pci_dfl_cache_line_size << 2); 3046 cls << 2, pci_dfl_cache_line_size << 2);
@@ -3179,3 +3179,87 @@ int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3179 3179
3180 return -ENOTTY; 3180 return -ENOTTY;
3181} 3181}
3182
3183static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3184{
3185 if (!PCI_FUNC(dev->devfn))
3186 return pci_dev_get(dev);
3187
3188 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3189}
3190
3191static const struct pci_dev_dma_source {
3192 u16 vendor;
3193 u16 device;
3194 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3195} pci_dev_dma_source[] = {
3196 /*
3197 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3198 *
3199 * Some Ricoh devices use the function 0 source ID for DMA on
3200 * other functions of a multifunction device. The DMA devices
3201 * is therefore function 0, which will have implications of the
3202 * iommu grouping of these devices.
3203 */
3204 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3205 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3206 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3207 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3208 { 0 }
3209};
3210
3211/*
3212 * IOMMUs with isolation capabilities need to be programmed with the
3213 * correct source ID of a device. In most cases, the source ID matches
3214 * the device doing the DMA, but sometimes hardware is broken and will
3215 * tag the DMA as being sourced from a different device. This function
3216 * allows that translation. Note that the reference count of the
3217 * returned device is incremented on all paths.
3218 */
3219struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3220{
3221 const struct pci_dev_dma_source *i;
3222
3223 for (i = pci_dev_dma_source; i->dma_source; i++) {
3224 if ((i->vendor == dev->vendor ||
3225 i->vendor == (u16)PCI_ANY_ID) &&
3226 (i->device == dev->device ||
3227 i->device == (u16)PCI_ANY_ID))
3228 return i->dma_source(dev);
3229 }
3230
3231 return pci_dev_get(dev);
3232}
3233
3234static const struct pci_dev_acs_enabled {
3235 u16 vendor;
3236 u16 device;
3237 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3238} pci_dev_acs_enabled[] = {
3239 { 0 }
3240};
3241
3242int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3243{
3244 const struct pci_dev_acs_enabled *i;
3245 int ret;
3246
3247 /*
3248 * Allow devices that do not expose standard PCIe ACS capabilities
3249 * or control to indicate their support here. Multi-function express
3250 * devices which do not allow internal peer-to-peer between functions,
3251 * but do not implement PCIe ACS may wish to return true here.
3252 */
3253 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3254 if ((i->vendor == dev->vendor ||
3255 i->vendor == (u16)PCI_ANY_ID) &&
3256 (i->device == dev->device ||
3257 i->device == (u16)PCI_ANY_ID)) {
3258 ret = i->acs_enabled(dev, acs_flags);
3259 if (ret >= 0)
3260 return ret;
3261 }
3262 }
3263
3264 return -ENOTTY;
3265}
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index fd77e2bde2e8..04a4861b4749 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -68,6 +68,7 @@ void pci_remove_bus(struct pci_bus *pci_bus)
68 68
69 down_write(&pci_bus_sem); 69 down_write(&pci_bus_sem);
70 list_del(&pci_bus->node); 70 list_del(&pci_bus->node);
71 pci_bus_release_busn_res(pci_bus);
71 up_write(&pci_bus_sem); 72 up_write(&pci_bus_sem);
72 if (!pci_bus->is_added) 73 if (!pci_bus->is_added)
73 return; 74 return;
diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index 9d75dc8ca602..993d4a0a2469 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -15,6 +15,8 @@
15#include "pci.h" 15#include "pci.h"
16 16
17DECLARE_RWSEM(pci_bus_sem); 17DECLARE_RWSEM(pci_bus_sem);
18EXPORT_SYMBOL_GPL(pci_bus_sem);
19
18/* 20/*
19 * find the upstream PCIe-to-PCI bridge of a PCI device 21 * find the upstream PCIe-to-PCI bridge of a PCI device
20 * if the device is PCIE, return NULL 22 * if the device is PCIE, return NULL
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 8fa2d4be88de..fb506137aaee 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -265,7 +265,7 @@ out:
265 * assign_requested_resources_sorted() - satisfy resource requests 265 * assign_requested_resources_sorted() - satisfy resource requests
266 * 266 *
267 * @head : head of the list tracking requests for resources 267 * @head : head of the list tracking requests for resources
268 * @failed_list : head of the list tracking requests that could 268 * @fail_head : head of the list tracking requests that could
269 * not be allocated 269 * not be allocated
270 * 270 *
271 * Satisfy resource requests of each element in the list. Add 271 * Satisfy resource requests of each element in the list. Add
@@ -308,7 +308,7 @@ static void __assign_resources_sorted(struct list_head *head,
308 * Should not assign requested resources at first. 308 * Should not assign requested resources at first.
309 * they could be adjacent, so later reassign can not reallocate 309 * they could be adjacent, so later reassign can not reallocate
310 * them one by one in parent resource window. 310 * them one by one in parent resource window.
311 * Try to assign requested + add_size at begining 311 * Try to assign requested + add_size at beginning
312 * if could do that, could get out early. 312 * if could do that, could get out early.
313 * if could not do that, we still try to assign requested at first, 313 * if could not do that, we still try to assign requested at first,
314 * then try to reassign add_size for some resources. 314 * then try to reassign add_size for some resources.
@@ -404,8 +404,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
404 struct resource *res; 404 struct resource *res;
405 struct pci_bus_region region; 405 struct pci_bus_region region;
406 406
407 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", 407 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
408 bus->secondary, bus->subordinate); 408 &bus->busn_res);
409 409
410 res = bus->resource[0]; 410 res = bus->resource[0];
411 pcibios_resource_to_bus(bridge, &region, res); 411 pcibios_resource_to_bus(bridge, &region, res);
@@ -469,16 +469,23 @@ static void pci_setup_bridge_io(struct pci_bus *bus)
469 struct pci_dev *bridge = bus->self; 469 struct pci_dev *bridge = bus->self;
470 struct resource *res; 470 struct resource *res;
471 struct pci_bus_region region; 471 struct pci_bus_region region;
472 unsigned long io_mask;
473 u8 io_base_lo, io_limit_lo;
472 u32 l, io_upper16; 474 u32 l, io_upper16;
473 475
476 io_mask = PCI_IO_RANGE_MASK;
477 if (bridge->io_window_1k)
478 io_mask = PCI_IO_1K_RANGE_MASK;
479
474 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 480 /* Set up the top and bottom of the PCI I/O segment for this bus. */
475 res = bus->resource[0]; 481 res = bus->resource[0];
476 pcibios_resource_to_bus(bridge, &region, res); 482 pcibios_resource_to_bus(bridge, &region, res);
477 if (res->flags & IORESOURCE_IO) { 483 if (res->flags & IORESOURCE_IO) {
478 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 484 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
479 l &= 0xffff0000; 485 l &= 0xffff0000;
480 l |= (region.start >> 8) & 0x00f0; 486 io_base_lo = (region.start >> 8) & io_mask;
481 l |= region.end & 0xf000; 487 io_limit_lo = (region.end >> 8) & io_mask;
488 l |= ((u32) io_limit_lo << 8) | io_base_lo;
482 /* Set up upper 16 bits of I/O base/limit. */ 489 /* Set up upper 16 bits of I/O base/limit. */
483 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 490 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
484 dev_info(&bridge->dev, " bridge window %pR\n", res); 491 dev_info(&bridge->dev, " bridge window %pR\n", res);
@@ -553,8 +560,8 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
553{ 560{
554 struct pci_dev *bridge = bus->self; 561 struct pci_dev *bridge = bus->self;
555 562
556 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", 563 dev_info(&bridge->dev, "PCI bridge to %pR\n",
557 bus->secondary, bus->subordinate); 564 &bus->busn_res);
558 565
559 if (type & IORESOURCE_IO) 566 if (type & IORESOURCE_IO)
560 pci_setup_bridge_io(bus); 567 pci_setup_bridge_io(bus);
@@ -699,7 +706,7 @@ static resource_size_t calculate_memsize(resource_size_t size,
699 * @realloc_head : track the additional io window on this list 706 * @realloc_head : track the additional io window on this list
700 * 707 *
701 * Sizing the IO windows of the PCI-PCI bridge is trivial, 708 * Sizing the IO windows of the PCI-PCI bridge is trivial,
702 * since these windows have 4K granularity and the IO ranges 709 * since these windows have 1K or 4K granularity and the IO ranges
703 * of non-bridge PCI devices are limited to 256 bytes. 710 * of non-bridge PCI devices are limited to 256 bytes.
704 * We must be careful with the ISA aliasing though. 711 * We must be careful with the ISA aliasing though.
705 */ 712 */
@@ -710,10 +717,17 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
710 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 717 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
711 unsigned long size = 0, size0 = 0, size1 = 0; 718 unsigned long size = 0, size0 = 0, size1 = 0;
712 resource_size_t children_add_size = 0; 719 resource_size_t children_add_size = 0;
720 resource_size_t min_align = 4096, align;
713 721
714 if (!b_res) 722 if (!b_res)
715 return; 723 return;
716 724
725 /*
726 * Per spec, I/O windows are 4K-aligned, but some bridges have an
727 * extension to support 1K alignment.
728 */
729 if (bus->self->io_window_1k)
730 min_align = 1024;
717 list_for_each_entry(dev, &bus->devices, bus_list) { 731 list_for_each_entry(dev, &bus->devices, bus_list) {
718 int i; 732 int i;
719 733
@@ -731,34 +745,43 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
731 else 745 else
732 size1 += r_size; 746 size1 += r_size;
733 747
748 align = pci_resource_alignment(dev, r);
749 if (align > min_align)
750 min_align = align;
751
734 if (realloc_head) 752 if (realloc_head)
735 children_add_size += get_res_add_size(realloc_head, r); 753 children_add_size += get_res_add_size(realloc_head, r);
736 } 754 }
737 } 755 }
756
757 if (min_align > 4096)
758 min_align = 4096;
759
738 size0 = calculate_iosize(size, min_size, size1, 760 size0 = calculate_iosize(size, min_size, size1,
739 resource_size(b_res), 4096); 761 resource_size(b_res), min_align);
740 if (children_add_size > add_size) 762 if (children_add_size > add_size)
741 add_size = children_add_size; 763 add_size = children_add_size;
742 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : 764 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
743 calculate_iosize(size, min_size, add_size + size1, 765 calculate_iosize(size, min_size, add_size + size1,
744 resource_size(b_res), 4096); 766 resource_size(b_res), min_align);
745 if (!size0 && !size1) { 767 if (!size0 && !size1) {
746 if (b_res->start || b_res->end) 768 if (b_res->start || b_res->end)
747 dev_info(&bus->self->dev, "disabling bridge window " 769 dev_info(&bus->self->dev, "disabling bridge window "
748 "%pR to [bus %02x-%02x] (unused)\n", b_res, 770 "%pR to %pR (unused)\n", b_res,
749 bus->secondary, bus->subordinate); 771 &bus->busn_res);
750 b_res->flags = 0; 772 b_res->flags = 0;
751 return; 773 return;
752 } 774 }
753 /* Alignment of the IO window is always 4K */ 775
754 b_res->start = 4096; 776 b_res->start = min_align;
755 b_res->end = b_res->start + size0 - 1; 777 b_res->end = b_res->start + size0 - 1;
756 b_res->flags |= IORESOURCE_STARTALIGN; 778 b_res->flags |= IORESOURCE_STARTALIGN;
757 if (size1 > size0 && realloc_head) { 779 if (size1 > size0 && realloc_head) {
758 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); 780 add_to_list(realloc_head, bus->self, b_res, size1-size0,
781 min_align);
759 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " 782 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
760 "%pR to [bus %02x-%02x] add_size %lx\n", b_res, 783 "%pR to %pR add_size %lx\n", b_res,
761 bus->secondary, bus->subordinate, size1-size0); 784 &bus->busn_res, size1-size0);
762 } 785 }
763} 786}
764 787
@@ -863,8 +886,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
863 if (!size0 && !size1) { 886 if (!size0 && !size1) {
864 if (b_res->start || b_res->end) 887 if (b_res->start || b_res->end)
865 dev_info(&bus->self->dev, "disabling bridge window " 888 dev_info(&bus->self->dev, "disabling bridge window "
866 "%pR to [bus %02x-%02x] (unused)\n", b_res, 889 "%pR to %pR (unused)\n", b_res,
867 bus->secondary, bus->subordinate); 890 &bus->busn_res);
868 b_res->flags = 0; 891 b_res->flags = 0;
869 return 1; 892 return 1;
870 } 893 }
@@ -874,8 +897,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
874 if (size1 > size0 && realloc_head) { 897 if (size1 > size0 && realloc_head) {
875 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); 898 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " 899 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877 "%pR to [bus %02x-%02x] add_size %llx\n", b_res, 900 "%pR to %pR add_size %llx\n", b_res,
878 bus->secondary, bus->subordinate, (unsigned long long)size1-size0); 901 &bus->busn_res, (unsigned long long)size1-size0);
879 } 902 }
880 return 1; 903 return 1;
881} 904}
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index eea85dafc763..81b88bda7930 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -30,6 +30,8 @@
30void pci_update_resource(struct pci_dev *dev, int resno) 30void pci_update_resource(struct pci_dev *dev, int resno)
31{ 31{
32 struct pci_bus_region region; 32 struct pci_bus_region region;
33 bool disable;
34 u16 cmd;
33 u32 new, check, mask; 35 u32 new, check, mask;
34 int reg; 36 int reg;
35 enum pci_bar_type type; 37 enum pci_bar_type type;
@@ -67,6 +69,18 @@ void pci_update_resource(struct pci_dev *dev, int resno)
67 new |= PCI_ROM_ADDRESS_ENABLE; 69 new |= PCI_ROM_ADDRESS_ENABLE;
68 } 70 }
69 71
72 /*
73 * We can't update a 64-bit BAR atomically, so when possible,
74 * disable decoding so that a half-updated BAR won't conflict
75 * with another device.
76 */
77 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
78 if (disable) {
79 pci_read_config_word(dev, PCI_COMMAND, &cmd);
80 pci_write_config_word(dev, PCI_COMMAND,
81 cmd & ~PCI_COMMAND_MEMORY);
82 }
83
70 pci_write_config_dword(dev, reg, new); 84 pci_write_config_dword(dev, reg, new);
71 pci_read_config_dword(dev, reg, &check); 85 pci_read_config_dword(dev, reg, &check);
72 86
@@ -84,6 +98,10 @@ void pci_update_resource(struct pci_dev *dev, int resno)
84 "(high %#08x != %#08x)\n", resno, new, check); 98 "(high %#08x != %#08x)\n", resno, new, check);
85 } 99 }
86 } 100 }
101
102 if (disable)
103 pci_write_config_word(dev, PCI_COMMAND, cmd);
104
87 res->flags &= ~IORESOURCE_UNSET; 105 res->flags &= ~IORESOURCE_UNSET;
88 dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n", 106 dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
89 resno, res, (unsigned long long)region.start, 107 resno, res, (unsigned long long)region.start,
@@ -127,33 +145,6 @@ void pci_disable_bridge_window(struct pci_dev *dev)
127 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 145 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
128} 146}
129 147
130static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
131 int resno, resource_size_t size, resource_size_t align)
132{
133 struct resource *res = dev->resource + resno;
134 resource_size_t min;
135 int ret;
136
137 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
138
139 /* First, try exact prefetching match.. */
140 ret = pci_bus_alloc_resource(bus, res, size, align, min,
141 IORESOURCE_PREFETCH,
142 pcibios_align_resource, dev);
143
144 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
145 /*
146 * That failed.
147 *
148 * But a prefetching area can handle a non-prefetching
149 * window (it will just not perform as well).
150 */
151 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
152 pcibios_align_resource, dev);
153 }
154 return ret;
155}
156
157/* 148/*
158 * Generic function that returns a value indicating that the device's 149 * Generic function that returns a value indicating that the device's
159 * original BIOS BAR address was not saved and so is not available for 150 * original BIOS BAR address was not saved and so is not available for
@@ -206,7 +197,35 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
206 return ret; 197 return ret;
207} 198}
208 199
209static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align) 200static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
201 int resno, resource_size_t size, resource_size_t align)
202{
203 struct resource *res = dev->resource + resno;
204 resource_size_t min;
205 int ret;
206
207 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
208
209 /* First, try exact prefetching match.. */
210 ret = pci_bus_alloc_resource(bus, res, size, align, min,
211 IORESOURCE_PREFETCH,
212 pcibios_align_resource, dev);
213
214 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
215 /*
216 * That failed.
217 *
218 * But a prefetching area can handle a non-prefetching
219 * window (it will just not perform as well).
220 */
221 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
222 pcibios_align_resource, dev);
223 }
224 return ret;
225}
226
227static int _pci_assign_resource(struct pci_dev *dev, int resno,
228 resource_size_t size, resource_size_t min_align)
210{ 229{
211 struct resource *res = dev->resource + resno; 230 struct resource *res = dev->resource + resno;
212 struct pci_bus *bus; 231 struct pci_bus *bus;
@@ -238,31 +257,6 @@ static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resour
238 return ret; 257 return ret;
239} 258}
240 259
241int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
242 resource_size_t min_align)
243{
244 struct resource *res = dev->resource + resno;
245 resource_size_t new_size;
246 int ret;
247
248 if (!res->parent) {
249 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
250 "\n", resno, res);
251 return -EINVAL;
252 }
253
254 /* already aligned with min_align */
255 new_size = resource_size(res) + addsize;
256 ret = _pci_assign_resource(dev, resno, new_size, min_align);
257 if (!ret) {
258 res->flags &= ~IORESOURCE_STARTALIGN;
259 dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
260 if (resno < PCI_BRIDGE_RESOURCES)
261 pci_update_resource(dev, resno);
262 }
263 return ret;
264}
265
266int pci_assign_resource(struct pci_dev *dev, int resno) 260int pci_assign_resource(struct pci_dev *dev, int resno)
267{ 261{
268 struct resource *res = dev->resource + resno; 262 struct resource *res = dev->resource + resno;
@@ -298,6 +292,31 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
298 return ret; 292 return ret;
299} 293}
300 294
295int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
296 resource_size_t min_align)
297{
298 struct resource *res = dev->resource + resno;
299 resource_size_t new_size;
300 int ret;
301
302 if (!res->parent) {
303 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
304 "\n", resno, res);
305 return -EINVAL;
306 }
307
308 /* already aligned with min_align */
309 new_size = resource_size(res) + addsize;
310 ret = _pci_assign_resource(dev, resno, new_size, min_align);
311 if (!ret) {
312 res->flags &= ~IORESOURCE_STARTALIGN;
313 dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
314 if (resno < PCI_BRIDGE_RESOURCES)
315 pci_update_resource(dev, resno);
316 }
317 return ret;
318}
319
301int pci_enable_resources(struct pci_dev *dev, int mask) 320int pci_enable_resources(struct pci_dev *dev, int mask)
302{ 321{
303 u16 cmd, old_cmd; 322 u16 cmd, old_cmd;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 03:49:51 -0500