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authorLinus Torvalds <torvalds@linux-foundation.org>2008-04-29 13:17:59 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-29 13:17:59 -0400
commita217656cb26c5b7ebe9900354b2e808c1f74b470 (patch)
tree37679bb7f1cebf927bac353b42e6bda8b4e7c63e /drivers/pci
parent8f45c1a58a25c3a1a2f42521445e1e786c4c0b92 (diff)
parenta53edac131cadee317e7e36a5908bb4c71d874cd (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits) pciehp: fix error message about getting hotplug control pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2 pci/irq: restore mask_bits in msi shutdown -v3 doc: replace yet another dev with pdev for consistency in DMA-mapping.txt PCI: don't expose struct pci_vpd to userspace doc: fix an incorrect suggestion to pass NULL for PCI like buses Consistently use pdev as the variable of type struct pci_dev *. pciehp: Fix command write shpchp: fix slot name make pciehp_acpi_get_hp_hw_control_from_firmware() pciehp: Clean up pcie_init() pciehp: Mask hotplug interrupt at controller release pciehp: Remove useless hotplug interrupt enabling pciehp: Fix wrong slot capability check pciehp: Fix wrong slot control register access pciehp: Add missing memory barrier pciehp: Fix interrupt event handlig pciehp: fix slot name Update MAINTAINERS with location of PCI tree PCI: Add Intel SCH PCI IDs ...
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/hotplug/pciehp.h17
-rw-r--r--drivers/pci/hotplug/pciehp_core.c19
-rw-r--r--drivers/pci/hotplug/pciehp_ctrl.c46
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c565
-rw-r--r--drivers/pci/hotplug/shpchp_core.c11
-rw-r--r--drivers/pci/msi.c56
-rw-r--r--drivers/pci/pci-driver.c2
-rw-r--r--drivers/pci/pcie/Kconfig2
8 files changed, 271 insertions, 447 deletions
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index f14267e197dd..8264a7680435 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -93,11 +93,10 @@ struct controller {
93 u8 slot_device_offset; 93 u8 slot_device_offset;
94 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */ 94 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */
95 u8 slot_bus; /* Bus where the slots handled by this controller sit */ 95 u8 slot_bus; /* Bus where the slots handled by this controller sit */
96 u8 ctrlcap; 96 u32 slot_cap;
97 u8 cap_base; 97 u8 cap_base;
98 struct timer_list poll_timer; 98 struct timer_list poll_timer;
99 volatile int cmd_busy; 99 volatile int cmd_busy;
100 spinlock_t lock;
101}; 100};
102 101
103#define INT_BUTTON_IGNORE 0 102#define INT_BUTTON_IGNORE 0
@@ -137,13 +136,13 @@ struct controller {
137#define HP_SUPR_RM_SUP 0x00000020 136#define HP_SUPR_RM_SUP 0x00000020
138#define EMI_PRSN 0x00020000 137#define EMI_PRSN 0x00020000
139 138
140#define ATTN_BUTTN(cap) (cap & ATTN_BUTTN_PRSN) 139#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & ATTN_BUTTN_PRSN)
141#define POWER_CTRL(cap) (cap & PWR_CTRL_PRSN) 140#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PWR_CTRL_PRSN)
142#define MRL_SENS(cap) (cap & MRL_SENS_PRSN) 141#define MRL_SENS(ctrl) ((ctrl)->slot_cap & MRL_SENS_PRSN)
143#define ATTN_LED(cap) (cap & ATTN_LED_PRSN) 142#define ATTN_LED(ctrl) ((ctrl)->slot_cap & ATTN_LED_PRSN)
144#define PWR_LED(cap) (cap & PWR_LED_PRSN) 143#define PWR_LED(ctrl) ((ctrl)->slot_cap & PWR_LED_PRSN)
145#define HP_SUPR_RM(cap) (cap & HP_SUPR_RM_SUP) 144#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & HP_SUPR_RM_SUP)
146#define EMI(cap) (cap & EMI_PRSN) 145#define EMI(ctrl) ((ctrl)->slot_cap & EMI_PRSN)
147 146
148extern int pciehp_sysfs_enable_slot(struct slot *slot); 147extern int pciehp_sysfs_enable_slot(struct slot *slot);
149extern int pciehp_sysfs_disable_slot(struct slot *slot); 148extern int pciehp_sysfs_disable_slot(struct slot *slot);
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index aee19f013d84..43d8ddb2d679 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -41,6 +41,7 @@ int pciehp_debug;
41int pciehp_poll_mode; 41int pciehp_poll_mode;
42int pciehp_poll_time; 42int pciehp_poll_time;
43int pciehp_force; 43int pciehp_force;
44int pciehp_slot_with_bus;
44struct workqueue_struct *pciehp_wq; 45struct workqueue_struct *pciehp_wq;
45 46
46#define DRIVER_VERSION "0.4" 47#define DRIVER_VERSION "0.4"
@@ -55,10 +56,12 @@ module_param(pciehp_debug, bool, 0644);
55module_param(pciehp_poll_mode, bool, 0644); 56module_param(pciehp_poll_mode, bool, 0644);
56module_param(pciehp_poll_time, int, 0644); 57module_param(pciehp_poll_time, int, 0644);
57module_param(pciehp_force, bool, 0644); 58module_param(pciehp_force, bool, 0644);
59module_param(pciehp_slot_with_bus, bool, 0644);
58MODULE_PARM_DESC(pciehp_debug, "Debugging mode enabled or not"); 60MODULE_PARM_DESC(pciehp_debug, "Debugging mode enabled or not");
59MODULE_PARM_DESC(pciehp_poll_mode, "Using polling mechanism for hot-plug events or not"); 61MODULE_PARM_DESC(pciehp_poll_mode, "Using polling mechanism for hot-plug events or not");
60MODULE_PARM_DESC(pciehp_poll_time, "Polling mechanism frequency, in seconds"); 62MODULE_PARM_DESC(pciehp_poll_time, "Polling mechanism frequency, in seconds");
61MODULE_PARM_DESC(pciehp_force, "Force pciehp, even if _OSC and OSHP are missing"); 63MODULE_PARM_DESC(pciehp_force, "Force pciehp, even if _OSC and OSHP are missing");
64MODULE_PARM_DESC(pciehp_slot_with_bus, "Use bus number in the slot name");
62 65
63#define PCIE_MODULE_NAME "pciehp" 66#define PCIE_MODULE_NAME "pciehp"
64 67
@@ -193,8 +196,12 @@ static void release_slot(struct hotplug_slot *hotplug_slot)
193 196
194static void make_slot_name(struct slot *slot) 197static void make_slot_name(struct slot *slot)
195{ 198{
196 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%04d_%04d", 199 if (pciehp_slot_with_bus)
197 slot->bus, slot->number); 200 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%04d_%04d",
201 slot->bus, slot->number);
202 else
203 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%d",
204 slot->number);
198} 205}
199 206
200static int init_slots(struct controller *ctrl) 207static int init_slots(struct controller *ctrl)
@@ -251,7 +258,7 @@ static int init_slots(struct controller *ctrl)
251 goto error_info; 258 goto error_info;
252 } 259 }
253 /* create additional sysfs entries */ 260 /* create additional sysfs entries */
254 if (EMI(ctrl->ctrlcap)) { 261 if (EMI(ctrl)) {
255 retval = sysfs_create_file(&hotplug_slot->kobj, 262 retval = sysfs_create_file(&hotplug_slot->kobj,
256 &hotplug_slot_attr_lock.attr); 263 &hotplug_slot_attr_lock.attr);
257 if (retval) { 264 if (retval) {
@@ -284,7 +291,7 @@ static void cleanup_slots(struct controller *ctrl)
284 list_for_each_safe(tmp, next, &ctrl->slot_list) { 291 list_for_each_safe(tmp, next, &ctrl->slot_list) {
285 slot = list_entry(tmp, struct slot, slot_list); 292 slot = list_entry(tmp, struct slot, slot_list);
286 list_del(&slot->slot_list); 293 list_del(&slot->slot_list);
287 if (EMI(ctrl->ctrlcap)) 294 if (EMI(ctrl))
288 sysfs_remove_file(&slot->hotplug_slot->kobj, 295 sysfs_remove_file(&slot->hotplug_slot->kobj,
289 &hotplug_slot_attr_lock.attr); 296 &hotplug_slot_attr_lock.attr);
290 cancel_delayed_work(&slot->work); 297 cancel_delayed_work(&slot->work);
@@ -305,7 +312,7 @@ static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status)
305 312
306 hotplug_slot->info->attention_status = status; 313 hotplug_slot->info->attention_status = status;
307 314
308 if (ATTN_LED(slot->ctrl->ctrlcap)) 315 if (ATTN_LED(slot->ctrl))
309 slot->hpc_ops->set_attention_status(slot, status); 316 slot->hpc_ops->set_attention_status(slot, status);
310 317
311 return 0; 318 return 0;
@@ -472,7 +479,7 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
472 if (rc) /* -ENODEV: shouldn't happen, but deal with it */ 479 if (rc) /* -ENODEV: shouldn't happen, but deal with it */
473 value = 0; 480 value = 0;
474 } 481 }
475 if ((POWER_CTRL(ctrl->ctrlcap)) && !value) { 482 if ((POWER_CTRL(ctrl)) && !value) {
476 rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/ 483 rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/
477 if (rc) 484 if (rc)
478 goto err_out_free_ctrl_slot; 485 goto err_out_free_ctrl_slot;
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c
index 0c481f7d2ab3..0a7aa628e955 100644
--- a/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/drivers/pci/hotplug/pciehp_ctrl.c
@@ -178,7 +178,7 @@ u8 pciehp_handle_power_fault(u8 hp_slot, struct controller *ctrl)
178static void set_slot_off(struct controller *ctrl, struct slot * pslot) 178static void set_slot_off(struct controller *ctrl, struct slot * pslot)
179{ 179{
180 /* turn off slot, turn on Amber LED, turn off Green LED if supported*/ 180 /* turn off slot, turn on Amber LED, turn off Green LED if supported*/
181 if (POWER_CTRL(ctrl->ctrlcap)) { 181 if (POWER_CTRL(ctrl)) {
182 if (pslot->hpc_ops->power_off_slot(pslot)) { 182 if (pslot->hpc_ops->power_off_slot(pslot)) {
183 err("%s: Issue of Slot Power Off command failed\n", 183 err("%s: Issue of Slot Power Off command failed\n",
184 __func__); 184 __func__);
@@ -186,10 +186,10 @@ static void set_slot_off(struct controller *ctrl, struct slot * pslot)
186 } 186 }
187 } 187 }
188 188
189 if (PWR_LED(ctrl->ctrlcap)) 189 if (PWR_LED(ctrl))
190 pslot->hpc_ops->green_led_off(pslot); 190 pslot->hpc_ops->green_led_off(pslot);
191 191
192 if (ATTN_LED(ctrl->ctrlcap)) { 192 if (ATTN_LED(ctrl)) {
193 if (pslot->hpc_ops->set_attention_status(pslot, 1)) { 193 if (pslot->hpc_ops->set_attention_status(pslot, 1)) {
194 err("%s: Issue of Set Attention Led command failed\n", 194 err("%s: Issue of Set Attention Led command failed\n",
195 __func__); 195 __func__);
@@ -214,14 +214,14 @@ static int board_added(struct slot *p_slot)
214 __func__, p_slot->device, 214 __func__, p_slot->device,
215 ctrl->slot_device_offset, p_slot->hp_slot); 215 ctrl->slot_device_offset, p_slot->hp_slot);
216 216
217 if (POWER_CTRL(ctrl->ctrlcap)) { 217 if (POWER_CTRL(ctrl)) {
218 /* Power on slot */ 218 /* Power on slot */
219 retval = p_slot->hpc_ops->power_on_slot(p_slot); 219 retval = p_slot->hpc_ops->power_on_slot(p_slot);
220 if (retval) 220 if (retval)
221 return retval; 221 return retval;
222 } 222 }
223 223
224 if (PWR_LED(ctrl->ctrlcap)) 224 if (PWR_LED(ctrl))
225 p_slot->hpc_ops->green_led_blink(p_slot); 225 p_slot->hpc_ops->green_led_blink(p_slot);
226 226
227 /* Wait for ~1 second */ 227 /* Wait for ~1 second */
@@ -254,7 +254,7 @@ static int board_added(struct slot *p_slot)
254 */ 254 */
255 if (pcie_mch_quirk) 255 if (pcie_mch_quirk)
256 pci_fixup_device(pci_fixup_final, ctrl->pci_dev); 256 pci_fixup_device(pci_fixup_final, ctrl->pci_dev);
257 if (PWR_LED(ctrl->ctrlcap)) 257 if (PWR_LED(ctrl))
258 p_slot->hpc_ops->green_led_on(p_slot); 258 p_slot->hpc_ops->green_led_on(p_slot);
259 259
260 return 0; 260 return 0;
@@ -279,7 +279,7 @@ static int remove_board(struct slot *p_slot)
279 279
280 dbg("In %s, hp_slot = %d\n", __func__, p_slot->hp_slot); 280 dbg("In %s, hp_slot = %d\n", __func__, p_slot->hp_slot);
281 281
282 if (POWER_CTRL(ctrl->ctrlcap)) { 282 if (POWER_CTRL(ctrl)) {
283 /* power off slot */ 283 /* power off slot */
284 retval = p_slot->hpc_ops->power_off_slot(p_slot); 284 retval = p_slot->hpc_ops->power_off_slot(p_slot);
285 if (retval) { 285 if (retval) {
@@ -289,7 +289,7 @@ static int remove_board(struct slot *p_slot)
289 } 289 }
290 } 290 }
291 291
292 if (PWR_LED(ctrl->ctrlcap)) 292 if (PWR_LED(ctrl))
293 /* turn off Green LED */ 293 /* turn off Green LED */
294 p_slot->hpc_ops->green_led_off(p_slot); 294 p_slot->hpc_ops->green_led_off(p_slot);
295 295
@@ -327,7 +327,7 @@ static void pciehp_power_thread(struct work_struct *work)
327 case POWERON_STATE: 327 case POWERON_STATE:
328 mutex_unlock(&p_slot->lock); 328 mutex_unlock(&p_slot->lock);
329 if (pciehp_enable_slot(p_slot) && 329 if (pciehp_enable_slot(p_slot) &&
330 PWR_LED(p_slot->ctrl->ctrlcap)) 330 PWR_LED(p_slot->ctrl))
331 p_slot->hpc_ops->green_led_off(p_slot); 331 p_slot->hpc_ops->green_led_off(p_slot);
332 mutex_lock(&p_slot->lock); 332 mutex_lock(&p_slot->lock);
333 p_slot->state = STATIC_STATE; 333 p_slot->state = STATIC_STATE;
@@ -409,9 +409,9 @@ static void handle_button_press_event(struct slot *p_slot)
409 "press.\n", p_slot->name); 409 "press.\n", p_slot->name);
410 } 410 }
411 /* blink green LED and turn off amber */ 411 /* blink green LED and turn off amber */
412 if (PWR_LED(ctrl->ctrlcap)) 412 if (PWR_LED(ctrl))
413 p_slot->hpc_ops->green_led_blink(p_slot); 413 p_slot->hpc_ops->green_led_blink(p_slot);
414 if (ATTN_LED(ctrl->ctrlcap)) 414 if (ATTN_LED(ctrl))
415 p_slot->hpc_ops->set_attention_status(p_slot, 0); 415 p_slot->hpc_ops->set_attention_status(p_slot, 0);
416 416
417 schedule_delayed_work(&p_slot->work, 5*HZ); 417 schedule_delayed_work(&p_slot->work, 5*HZ);
@@ -427,13 +427,13 @@ static void handle_button_press_event(struct slot *p_slot)
427 dbg("%s: button cancel\n", __func__); 427 dbg("%s: button cancel\n", __func__);
428 cancel_delayed_work(&p_slot->work); 428 cancel_delayed_work(&p_slot->work);
429 if (p_slot->state == BLINKINGOFF_STATE) { 429 if (p_slot->state == BLINKINGOFF_STATE) {
430 if (PWR_LED(ctrl->ctrlcap)) 430 if (PWR_LED(ctrl))
431 p_slot->hpc_ops->green_led_on(p_slot); 431 p_slot->hpc_ops->green_led_on(p_slot);
432 } else { 432 } else {
433 if (PWR_LED(ctrl->ctrlcap)) 433 if (PWR_LED(ctrl))
434 p_slot->hpc_ops->green_led_off(p_slot); 434 p_slot->hpc_ops->green_led_off(p_slot);
435 } 435 }
436 if (ATTN_LED(ctrl->ctrlcap)) 436 if (ATTN_LED(ctrl))
437 p_slot->hpc_ops->set_attention_status(p_slot, 0); 437 p_slot->hpc_ops->set_attention_status(p_slot, 0);
438 info("PCI slot #%s - action canceled due to button press\n", 438 info("PCI slot #%s - action canceled due to button press\n",
439 p_slot->name); 439 p_slot->name);
@@ -492,16 +492,16 @@ static void interrupt_event_handler(struct work_struct *work)
492 handle_button_press_event(p_slot); 492 handle_button_press_event(p_slot);
493 break; 493 break;
494 case INT_POWER_FAULT: 494 case INT_POWER_FAULT:
495 if (!POWER_CTRL(ctrl->ctrlcap)) 495 if (!POWER_CTRL(ctrl))
496 break; 496 break;
497 if (ATTN_LED(ctrl->ctrlcap)) 497 if (ATTN_LED(ctrl))
498 p_slot->hpc_ops->set_attention_status(p_slot, 1); 498 p_slot->hpc_ops->set_attention_status(p_slot, 1);
499 if (PWR_LED(ctrl->ctrlcap)) 499 if (PWR_LED(ctrl))
500 p_slot->hpc_ops->green_led_off(p_slot); 500 p_slot->hpc_ops->green_led_off(p_slot);
501 break; 501 break;
502 case INT_PRESENCE_ON: 502 case INT_PRESENCE_ON:
503 case INT_PRESENCE_OFF: 503 case INT_PRESENCE_OFF:
504 if (!HP_SUPR_RM(ctrl->ctrlcap)) 504 if (!HP_SUPR_RM(ctrl))
505 break; 505 break;
506 dbg("Surprise Removal\n"); 506 dbg("Surprise Removal\n");
507 update_slot_info(p_slot); 507 update_slot_info(p_slot);
@@ -531,7 +531,7 @@ int pciehp_enable_slot(struct slot *p_slot)
531 mutex_unlock(&p_slot->ctrl->crit_sect); 531 mutex_unlock(&p_slot->ctrl->crit_sect);
532 return -ENODEV; 532 return -ENODEV;
533 } 533 }
534 if (MRL_SENS(p_slot->ctrl->ctrlcap)) { 534 if (MRL_SENS(p_slot->ctrl)) {
535 rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 535 rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
536 if (rc || getstatus) { 536 if (rc || getstatus) {
537 info("%s: latch open on slot(%s)\n", __func__, 537 info("%s: latch open on slot(%s)\n", __func__,
@@ -541,7 +541,7 @@ int pciehp_enable_slot(struct slot *p_slot)
541 } 541 }
542 } 542 }
543 543
544 if (POWER_CTRL(p_slot->ctrl->ctrlcap)) { 544 if (POWER_CTRL(p_slot->ctrl)) {
545 rc = p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 545 rc = p_slot->hpc_ops->get_power_status(p_slot, &getstatus);
546 if (rc || getstatus) { 546 if (rc || getstatus) {
547 info("%s: already enabled on slot(%s)\n", __func__, 547 info("%s: already enabled on slot(%s)\n", __func__,
@@ -576,7 +576,7 @@ int pciehp_disable_slot(struct slot *p_slot)
576 /* Check to see if (latch closed, card present, power on) */ 576 /* Check to see if (latch closed, card present, power on) */
577 mutex_lock(&p_slot->ctrl->crit_sect); 577 mutex_lock(&p_slot->ctrl->crit_sect);
578 578
579 if (!HP_SUPR_RM(p_slot->ctrl->ctrlcap)) { 579 if (!HP_SUPR_RM(p_slot->ctrl)) {
580 ret = p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus); 580 ret = p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus);
581 if (ret || !getstatus) { 581 if (ret || !getstatus) {
582 info("%s: no adapter on slot(%s)\n", __func__, 582 info("%s: no adapter on slot(%s)\n", __func__,
@@ -586,7 +586,7 @@ int pciehp_disable_slot(struct slot *p_slot)
586 } 586 }
587 } 587 }
588 588
589 if (MRL_SENS(p_slot->ctrl->ctrlcap)) { 589 if (MRL_SENS(p_slot->ctrl)) {
590 ret = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus); 590 ret = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
591 if (ret || getstatus) { 591 if (ret || getstatus) {
592 info("%s: latch open on slot(%s)\n", __func__, 592 info("%s: latch open on slot(%s)\n", __func__,
@@ -596,7 +596,7 @@ int pciehp_disable_slot(struct slot *p_slot)
596 } 596 }
597 } 597 }
598 598
599 if (POWER_CTRL(p_slot->ctrl->ctrlcap)) { 599 if (POWER_CTRL(p_slot->ctrl)) {
600 ret = p_slot->hpc_ops->get_power_status(p_slot, &getstatus); 600 ret = p_slot->hpc_ops->get_power_status(p_slot, &getstatus);
601 if (ret || !getstatus) { 601 if (ret || !getstatus) {
602 info("%s: already disabled slot(%s)\n", __func__, 602 info("%s: already disabled slot(%s)\n", __func__,
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index b4bbd07d1e39..891f81a0400c 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -221,6 +221,32 @@ static void start_int_poll_timer(struct controller *ctrl, int sec)
221 add_timer(&ctrl->poll_timer); 221 add_timer(&ctrl->poll_timer);
222} 222}
223 223
224static inline int pciehp_request_irq(struct controller *ctrl)
225{
226 int retval, irq = ctrl->pci_dev->irq;
227
228 /* Install interrupt polling timer. Start with 10 sec delay */
229 if (pciehp_poll_mode) {
230 init_timer(&ctrl->poll_timer);
231 start_int_poll_timer(ctrl, 10);
232 return 0;
233 }
234
235 /* Installs the interrupt handler */
236 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
237 if (retval)
238 err("Cannot get irq %d for the hotplug controller\n", irq);
239 return retval;
240}
241
242static inline void pciehp_free_irq(struct controller *ctrl)
243{
244 if (pciehp_poll_mode)
245 del_timer_sync(&ctrl->poll_timer);
246 else
247 free_irq(ctrl->pci_dev->irq, ctrl);
248}
249
224static inline int pcie_wait_cmd(struct controller *ctrl) 250static inline int pcie_wait_cmd(struct controller *ctrl)
225{ 251{
226 int retval = 0; 252 int retval = 0;
@@ -242,17 +268,15 @@ static inline int pcie_wait_cmd(struct controller *ctrl)
242 268
243/** 269/**
244 * pcie_write_cmd - Issue controller command 270 * pcie_write_cmd - Issue controller command
245 * @slot: slot to which the command is issued 271 * @ctrl: controller to which the command is issued
246 * @cmd: command value written to slot control register 272 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified 273 * @mask: bitmask of slot control register to be modified
248 */ 274 */
249static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask) 275static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
250{ 276{
251 struct controller *ctrl = slot->ctrl;
252 int retval = 0; 277 int retval = 0;
253 u16 slot_status; 278 u16 slot_status;
254 u16 slot_ctrl; 279 u16 slot_ctrl;
255 unsigned long flags;
256 280
257 mutex_lock(&ctrl->ctrl_lock); 281 mutex_lock(&ctrl->ctrl_lock);
258 282
@@ -270,24 +294,24 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
270 __func__); 294 __func__);
271 } 295 }
272 296
273 spin_lock_irqsave(&ctrl->lock, flags);
274 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 297 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
275 if (retval) { 298 if (retval) {
276 err("%s: Cannot read SLOTCTRL register\n", __func__); 299 err("%s: Cannot read SLOTCTRL register\n", __func__);
277 goto out_spin_unlock; 300 goto out;
278 } 301 }
279 302
280 slot_ctrl &= ~mask; 303 slot_ctrl &= ~mask;
281 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE); 304 slot_ctrl |= (cmd & mask);
305 /* Don't enable command completed if caller is changing it. */
306 if (!(mask & CMD_CMPL_INTR_ENABLE))
307 slot_ctrl |= CMD_CMPL_INTR_ENABLE;
282 308
283 ctrl->cmd_busy = 1; 309 ctrl->cmd_busy = 1;
310 smp_mb();
284 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); 311 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
285 if (retval) 312 if (retval)
286 err("%s: Cannot write to SLOTCTRL register\n", __func__); 313 err("%s: Cannot write to SLOTCTRL register\n", __func__);
287 314
288 out_spin_unlock:
289 spin_unlock_irqrestore(&ctrl->lock, flags);
290
291 /* 315 /*
292 * Wait for command completion. 316 * Wait for command completion.
293 */ 317 */
@@ -467,12 +491,7 @@ static int hpc_toggle_emi(struct slot *slot)
467 491
468 slot_cmd = EMI_CTRL; 492 slot_cmd = EMI_CTRL;
469 cmd_mask = EMI_CTRL; 493 cmd_mask = EMI_CTRL;
470 if (!pciehp_poll_mode) { 494 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
471 slot_cmd = slot_cmd | HP_INTR_ENABLE;
472 cmd_mask = cmd_mask | HP_INTR_ENABLE;
473 }
474
475 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
476 slot->last_emi_toggle = get_seconds(); 495 slot->last_emi_toggle = get_seconds();
477 496
478 return rc; 497 return rc;
@@ -499,12 +518,7 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
499 default: 518 default:
500 return -1; 519 return -1;
501 } 520 }
502 if (!pciehp_poll_mode) { 521 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
503 slot_cmd = slot_cmd | HP_INTR_ENABLE;
504 cmd_mask = cmd_mask | HP_INTR_ENABLE;
505 }
506
507 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
508 dbg("%s: SLOTCTRL %x write cmd %x\n", 522 dbg("%s: SLOTCTRL %x write cmd %x\n",
509 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 523 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
510 524
@@ -519,13 +533,7 @@ static void hpc_set_green_led_on(struct slot *slot)
519 533
520 slot_cmd = 0x0100; 534 slot_cmd = 0x0100;
521 cmd_mask = PWR_LED_CTRL; 535 cmd_mask = PWR_LED_CTRL;
522 if (!pciehp_poll_mode) { 536 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
523 slot_cmd = slot_cmd | HP_INTR_ENABLE;
524 cmd_mask = cmd_mask | HP_INTR_ENABLE;
525 }
526
527 pcie_write_cmd(slot, slot_cmd, cmd_mask);
528
529 dbg("%s: SLOTCTRL %x write cmd %x\n", 537 dbg("%s: SLOTCTRL %x write cmd %x\n",
530 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 538 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
531} 539}
@@ -538,12 +546,7 @@ static void hpc_set_green_led_off(struct slot *slot)
538 546
539 slot_cmd = 0x0300; 547 slot_cmd = 0x0300;
540 cmd_mask = PWR_LED_CTRL; 548 cmd_mask = PWR_LED_CTRL;
541 if (!pciehp_poll_mode) { 549 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
542 slot_cmd = slot_cmd | HP_INTR_ENABLE;
543 cmd_mask = cmd_mask | HP_INTR_ENABLE;
544 }
545
546 pcie_write_cmd(slot, slot_cmd, cmd_mask);
547 dbg("%s: SLOTCTRL %x write cmd %x\n", 550 dbg("%s: SLOTCTRL %x write cmd %x\n",
548 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 551 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
549} 552}
@@ -556,23 +559,19 @@ static void hpc_set_green_led_blink(struct slot *slot)
556 559
557 slot_cmd = 0x0200; 560 slot_cmd = 0x0200;
558 cmd_mask = PWR_LED_CTRL; 561 cmd_mask = PWR_LED_CTRL;
559 if (!pciehp_poll_mode) { 562 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
560 slot_cmd = slot_cmd | HP_INTR_ENABLE;
561 cmd_mask = cmd_mask | HP_INTR_ENABLE;
562 }
563
564 pcie_write_cmd(slot, slot_cmd, cmd_mask);
565
566 dbg("%s: SLOTCTRL %x write cmd %x\n", 563 dbg("%s: SLOTCTRL %x write cmd %x\n",
567 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 564 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
568} 565}
569 566
570static void hpc_release_ctlr(struct controller *ctrl) 567static void hpc_release_ctlr(struct controller *ctrl)
571{ 568{
572 if (pciehp_poll_mode) 569 /* Mask Hot-plug Interrupt Enable */
573 del_timer(&ctrl->poll_timer); 570 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE))
574 else 571 err("%s: Cannot mask hotplut interrupt enable\n", __func__);
575 free_irq(ctrl->pci_dev->irq, ctrl); 572
573 /* Free interrupt handler or interrupt polling timer */
574 pciehp_free_irq(ctrl);
576 575
577 /* 576 /*
578 * If this is the last controller to be released, destroy the 577 * If this is the last controller to be released, destroy the
@@ -612,19 +611,13 @@ static int hpc_power_on_slot(struct slot * slot)
612 cmd_mask = PWR_CTRL; 611 cmd_mask = PWR_CTRL;
613 /* Enable detection that we turned off at slot power-off time */ 612 /* Enable detection that we turned off at slot power-off time */
614 if (!pciehp_poll_mode) { 613 if (!pciehp_poll_mode) {
615 slot_cmd = slot_cmd | 614 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
616 PWR_FAULT_DETECT_ENABLE | 615 PRSN_DETECT_ENABLE);
617 MRL_DETECT_ENABLE | 616 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
618 PRSN_DETECT_ENABLE | 617 PRSN_DETECT_ENABLE);
619 HP_INTR_ENABLE;
620 cmd_mask = cmd_mask |
621 PWR_FAULT_DETECT_ENABLE |
622 MRL_DETECT_ENABLE |
623 PRSN_DETECT_ENABLE |
624 HP_INTR_ENABLE;
625 } 618 }
626 619
627 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask); 620 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
628 621
629 if (retval) { 622 if (retval) {
630 err("%s: Write %x command failed!\n", __func__, slot_cmd); 623 err("%s: Write %x command failed!\n", __func__, slot_cmd);
@@ -697,18 +690,13 @@ static int hpc_power_off_slot(struct slot * slot)
697 * till the slot is powered on again. 690 * till the slot is powered on again.
698 */ 691 */
699 if (!pciehp_poll_mode) { 692 if (!pciehp_poll_mode) {
700 slot_cmd = (slot_cmd & 693 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
701 ~PWR_FAULT_DETECT_ENABLE & 694 PRSN_DETECT_ENABLE);
702 ~MRL_DETECT_ENABLE & 695 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
703 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE; 696 PRSN_DETECT_ENABLE);
704 cmd_mask = cmd_mask |
705 PWR_FAULT_DETECT_ENABLE |
706 MRL_DETECT_ENABLE |
707 PRSN_DETECT_ENABLE |
708 HP_INTR_ENABLE;
709 } 697 }
710 698
711 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask); 699 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
712 if (retval) { 700 if (retval) {
713 err("%s: Write command failed!\n", __func__); 701 err("%s: Write command failed!\n", __func__);
714 retval = -1; 702 retval = -1;
@@ -733,139 +721,56 @@ static int hpc_power_off_slot(struct slot * slot)
733static irqreturn_t pcie_isr(int irq, void *dev_id) 721static irqreturn_t pcie_isr(int irq, void *dev_id)
734{ 722{
735 struct controller *ctrl = (struct controller *)dev_id; 723 struct controller *ctrl = (struct controller *)dev_id;
736 u16 slot_status, intr_detect, intr_loc; 724 u16 detected, intr_loc;
737 u16 temp_word;
738 int hp_slot = 0; /* only 1 slot per PCI Express port */
739 int rc = 0;
740 unsigned long flags;
741
742 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
743 if (rc) {
744 err("%s: Cannot read SLOTSTATUS register\n", __func__);
745 return IRQ_NONE;
746 }
747
748 intr_detect = (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
749 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | CMD_COMPLETED);
750
751 intr_loc = slot_status & intr_detect;
752
753 /* Check to see if it was our interrupt */
754 if ( !intr_loc )
755 return IRQ_NONE;
756 725
757 dbg("%s: intr_loc %x\n", __func__, intr_loc); 726 /*
758 /* Mask Hot-plug Interrupt Enable */ 727 * In order to guarantee that all interrupt events are
759 if (!pciehp_poll_mode) { 728 * serviced, we need to re-inspect Slot Status register after
760 spin_lock_irqsave(&ctrl->lock, flags); 729 * clearing what is presumed to be the last pending interrupt.
761 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 730 */
762 if (rc) { 731 intr_loc = 0;
763 err("%s: Cannot read SLOT_CTRL register\n", 732 do {
764 __func__); 733 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
765 spin_unlock_irqrestore(&ctrl->lock, flags); 734 err("%s: Cannot read SLOTSTATUS\n", __func__);
766 return IRQ_NONE; 735 return IRQ_NONE;
767 } 736 }
768 737
769 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", 738 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
770 __func__, temp_word); 739 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
771 temp_word = (temp_word & ~HP_INTR_ENABLE & 740 CMD_COMPLETED);
772 ~CMD_CMPL_INTR_ENABLE) | 0x00; 741 intr_loc |= detected;
773 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); 742 if (!intr_loc)
774 if (rc) {
775 err("%s: Cannot write to SLOTCTRL register\n",
776 __func__);
777 spin_unlock_irqrestore(&ctrl->lock, flags);
778 return IRQ_NONE; 743 return IRQ_NONE;
779 } 744 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
780 spin_unlock_irqrestore(&ctrl->lock, flags); 745 err("%s: Cannot write to SLOTSTATUS\n", __func__);
781
782 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
783 if (rc) {
784 err("%s: Cannot read SLOT_STATUS register\n",
785 __func__);
786 return IRQ_NONE; 746 return IRQ_NONE;
787 } 747 }
788 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n", 748 } while (detected);
789 __func__, slot_status);
790 749
791 /* Clear command complete interrupt caused by this write */ 750 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
792 temp_word = 0x1f;
793 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
794 if (rc) {
795 err("%s: Cannot write to SLOTSTATUS register\n",
796 __func__);
797 return IRQ_NONE;
798 }
799 }
800 751
752 /* Check Command Complete Interrupt Pending */
801 if (intr_loc & CMD_COMPLETED) { 753 if (intr_loc & CMD_COMPLETED) {
802 /*
803 * Command Complete Interrupt Pending
804 */
805 ctrl->cmd_busy = 0; 754 ctrl->cmd_busy = 0;
755 smp_mb();
806 wake_up_interruptible(&ctrl->queue); 756 wake_up_interruptible(&ctrl->queue);
807 } 757 }
808 758
759 /* Check MRL Sensor Changed */
809 if (intr_loc & MRL_SENS_CHANGED) 760 if (intr_loc & MRL_SENS_CHANGED)
810 pciehp_handle_switch_change(hp_slot, ctrl); 761 pciehp_handle_switch_change(0, ctrl);
811 762
763 /* Check Attention Button Pressed */
812 if (intr_loc & ATTN_BUTTN_PRESSED) 764 if (intr_loc & ATTN_BUTTN_PRESSED)
813 pciehp_handle_attention_button(hp_slot, ctrl); 765 pciehp_handle_attention_button(0, ctrl);
814 766
767 /* Check Presence Detect Changed */
815 if (intr_loc & PRSN_DETECT_CHANGED) 768 if (intr_loc & PRSN_DETECT_CHANGED)
816 pciehp_handle_presence_change(hp_slot, ctrl); 769 pciehp_handle_presence_change(0, ctrl);
817 770
771 /* Check Power Fault Detected */
818 if (intr_loc & PWR_FAULT_DETECTED) 772 if (intr_loc & PWR_FAULT_DETECTED)
819 pciehp_handle_power_fault(hp_slot, ctrl); 773 pciehp_handle_power_fault(0, ctrl);
820
821 /* Clear all events after serving them */
822 temp_word = 0x1F;
823 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
824 if (rc) {
825 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
826 return IRQ_NONE;
827 }
828 /* Unmask Hot-plug Interrupt Enable */
829 if (!pciehp_poll_mode) {
830 spin_lock_irqsave(&ctrl->lock, flags);
831 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
832 if (rc) {
833 err("%s: Cannot read SLOTCTRL register\n",
834 __func__);
835 spin_unlock_irqrestore(&ctrl->lock, flags);
836 return IRQ_NONE;
837 }
838
839 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __func__);
840 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
841
842 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
843 if (rc) {
844 err("%s: Cannot write to SLOTCTRL register\n",
845 __func__);
846 spin_unlock_irqrestore(&ctrl->lock, flags);
847 return IRQ_NONE;
848 }
849 spin_unlock_irqrestore(&ctrl->lock, flags);
850
851 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
852 if (rc) {
853 err("%s: Cannot read SLOT_STATUS register\n",
854 __func__);
855 return IRQ_NONE;
856 }
857
858 /* Clear command complete interrupt caused by this write */
859 temp_word = 0x1F;
860 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
861 if (rc) {
862 err("%s: Cannot write to SLOTSTATUS failed\n",
863 __func__);
864 return IRQ_NONE;
865 }
866 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
867 __func__, temp_word);
868 }
869 774
870 return IRQ_HANDLED; 775 return IRQ_HANDLED;
871} 776}
@@ -1052,7 +957,7 @@ static struct hpc_ops pciehp_hpc_ops = {
1052}; 957};
1053 958
1054#ifdef CONFIG_ACPI 959#ifdef CONFIG_ACPI
1055int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) 960static int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1056{ 961{
1057 acpi_status status; 962 acpi_status status;
1058 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); 963 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
@@ -1112,7 +1017,7 @@ int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1112 break; 1017 break;
1113 } 1018 }
1114 1019
1115 err("Cannot get control of hotplug hardware for pci %s\n", 1020 dbg("Cannot get control of hotplug hardware for pci %s\n",
1116 pci_name(dev)); 1021 pci_name(dev));
1117 1022
1118 kfree(string.pointer); 1023 kfree(string.pointer);
@@ -1123,45 +1028,9 @@ int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1123static int pcie_init_hardware_part1(struct controller *ctrl, 1028static int pcie_init_hardware_part1(struct controller *ctrl,
1124 struct pcie_device *dev) 1029 struct pcie_device *dev)
1125{ 1030{
1126 int rc;
1127 u16 temp_word;
1128 u32 slot_cap;
1129 u16 slot_status;
1130
1131 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1132 if (rc) {
1133 err("%s: Cannot read SLOTCAP register\n", __func__);
1134 return -1;
1135 }
1136
1137 /* Mask Hot-plug Interrupt Enable */ 1031 /* Mask Hot-plug Interrupt Enable */
1138 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1032 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1139 if (rc) { 1033 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1140 err("%s: Cannot read SLOTCTRL register\n", __func__);
1141 return -1;
1142 }
1143
1144 dbg("%s: SLOTCTRL %x value read %x\n",
1145 __func__, ctrl->cap_base + SLOTCTRL, temp_word);
1146 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
1147 0x00;
1148
1149 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1150 if (rc) {
1151 err("%s: Cannot write to SLOTCTRL register\n", __func__);
1152 return -1;
1153 }
1154
1155 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1156 if (rc) {
1157 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1158 return -1;
1159 }
1160
1161 temp_word = 0x1F; /* Clear all events */
1162 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1163 if (rc) {
1164 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1165 return -1; 1034 return -1;
1166 } 1035 }
1167 return 0; 1036 return 0;
@@ -1169,205 +1038,125 @@ static int pcie_init_hardware_part1(struct controller *ctrl,
1169 1038
1170int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev) 1039int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1171{ 1040{
1172 int rc; 1041 u16 cmd, mask;
1173 u16 temp_word;
1174 u16 intr_enable = 0;
1175 u32 slot_cap;
1176 u16 slot_status;
1177 1042
1178 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1043 /*
1179 if (rc) { 1044 * We need to clear all events before enabling hotplug interrupt
1180 err("%s: Cannot read SLOTCTRL register\n", __func__); 1045 * notification mechanism in order for hotplug controler to
1181 goto abort; 1046 * generate interrupts.
1182 } 1047 */
1183 1048 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1184 intr_enable = intr_enable | PRSN_DETECT_ENABLE; 1049 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1185 1050 return -1;
1186 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1187 if (rc) {
1188 err("%s: Cannot read SLOTCAP register\n", __func__);
1189 goto abort;
1190 } 1051 }
1191 1052
1192 if (ATTN_BUTTN(slot_cap)) 1053 cmd = PRSN_DETECT_ENABLE;
1193 intr_enable = intr_enable | ATTN_BUTTN_ENABLE; 1054 if (ATTN_BUTTN(ctrl))
1194 1055 cmd |= ATTN_BUTTN_ENABLE;
1195 if (POWER_CTRL(slot_cap)) 1056 if (POWER_CTRL(ctrl))
1196 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; 1057 cmd |= PWR_FAULT_DETECT_ENABLE;
1197 1058 if (MRL_SENS(ctrl))
1198 if (MRL_SENS(slot_cap)) 1059 cmd |= MRL_DETECT_ENABLE;
1199 intr_enable = intr_enable | MRL_DETECT_ENABLE; 1060 if (!pciehp_poll_mode)
1061 cmd |= HP_INTR_ENABLE;
1200 1062
1201 temp_word = (temp_word & ~intr_enable) | intr_enable; 1063 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1064 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1202 1065
1203 if (pciehp_poll_mode) { 1066 if (pcie_write_cmd(ctrl, cmd, mask)) {
1204 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; 1067 err("%s: Cannot enable software notification\n", __func__);
1205 } else {
1206 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1207 }
1208
1209 /*
1210 * Unmask Hot-plug Interrupt Enable for the interrupt
1211 * notification mechanism case.
1212 */
1213 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1214 if (rc) {
1215 err("%s: Cannot write to SLOTCTRL register\n", __func__);
1216 goto abort; 1068 goto abort;
1217 } 1069 }
1218 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1219 if (rc) {
1220 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1221 goto abort_disable_intr;
1222 }
1223
1224 temp_word = 0x1F; /* Clear all events */
1225 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1226 if (rc) {
1227 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1228 goto abort_disable_intr;
1229 }
1230 1070
1231 if (pciehp_force) { 1071 if (pciehp_force)
1232 dbg("Bypassing BIOS check for pciehp use on %s\n", 1072 dbg("Bypassing BIOS check for pciehp use on %s\n",
1233 pci_name(ctrl->pci_dev)); 1073 pci_name(ctrl->pci_dev));
1234 } else { 1074 else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev))
1235 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); 1075 goto abort_disable_intr;
1236 if (rc)
1237 goto abort_disable_intr;
1238 }
1239 1076
1240 return 0; 1077 return 0;
1241 1078
1242 /* We end up here for the many possible ways to fail this API. */ 1079 /* We end up here for the many possible ways to fail this API. */
1243abort_disable_intr: 1080abort_disable_intr:
1244 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1081 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE))
1245 if (!rc) {
1246 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1247 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1248 }
1249 if (rc)
1250 err("%s : disabling interrupts failed\n", __func__); 1082 err("%s : disabling interrupts failed\n", __func__);
1251abort: 1083abort:
1252 return -1; 1084 return -1;
1253} 1085}
1254 1086
1255int pcie_init(struct controller *ctrl, struct pcie_device *dev) 1087static inline void dbg_ctrl(struct controller *ctrl)
1256{ 1088{
1257 int rc; 1089 int i;
1258 u16 cap_reg; 1090 u16 reg16;
1259 u32 slot_cap; 1091 struct pci_dev *pdev = ctrl->pci_dev;
1260 int cap_base;
1261 u16 slot_status, slot_ctrl;
1262 struct pci_dev *pdev;
1263
1264 pdev = dev->port;
1265 ctrl->pci_dev = pdev; /* save pci_dev in context */
1266
1267 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1268 __func__, pdev->vendor, pdev->device);
1269 1092
1270 cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1093 if (!pciehp_debug)
1271 if (cap_base == 0) { 1094 return;
1272 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
1273 goto abort;
1274 }
1275 1095
1276 ctrl->cap_base = cap_base; 1096 dbg("Hotplug Controller:\n");
1097 dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
1098 dbg(" Vendor ID : 0x%04x\n", pdev->vendor);
1099 dbg(" Device ID : 0x%04x\n", pdev->device);
1100 dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device);
1101 dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor);
1102 dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
1103 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1104 if (!pci_resource_len(pdev, i))
1105 continue;
1106 dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i,
1107 (unsigned long long)pci_resource_len(pdev, i),
1108 (unsigned long long)pci_resource_start(pdev, i));
1109 }
1110 dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1111 dbg(" Physical Slot Number : %d\n", ctrl->first_slot);
1112 dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
1113 dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
1114 dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no");
1115 dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no");
1116 dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no");
1117 dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
1118 dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no");
1119 pciehp_readw(ctrl, SLOTSTATUS, &reg16);
1120 dbg("Slot Status : 0x%04x\n", reg16);
1121 pciehp_readw(ctrl, SLOTSTATUS, &reg16);
1122 dbg("Slot Control : 0x%04x\n", reg16);
1123}
1277 1124
1278 dbg("%s: pcie_cap_base %x\n", __func__, cap_base); 1125int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1126{
1127 u32 slot_cap;
1128 struct pci_dev *pdev = dev->port;
1279 1129
1280 rc = pciehp_readw(ctrl, CAPREG, &cap_reg); 1130 ctrl->pci_dev = pdev;
1281 if (rc) { 1131 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1282 err("%s: Cannot read CAPREG register\n", __func__); 1132 if (!ctrl->cap_base) {
1283 goto abort; 1133 err("%s: Cannot find PCI Express capability\n", __func__);
1284 }
1285 dbg("%s: CAPREG offset %x cap_reg %x\n",
1286 __func__, ctrl->cap_base + CAPREG, cap_reg);
1287
1288 if (((cap_reg & SLOT_IMPL) == 0) ||
1289 (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1290 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1291 dbg("%s : This is not a root port or the port is not "
1292 "connected to a slot\n", __func__);
1293 goto abort; 1134 goto abort;
1294 } 1135 }
1295 1136 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1296 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1297 if (rc) {
1298 err("%s: Cannot read SLOTCAP register\n", __func__); 1137 err("%s: Cannot read SLOTCAP register\n", __func__);
1299 goto abort; 1138 goto abort;
1300 } 1139 }
1301 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1302 __func__, ctrl->cap_base + SLOTCAP, slot_cap);
1303
1304 if (!(slot_cap & HP_CAP)) {
1305 dbg("%s : This slot is not hot-plug capable\n", __func__);
1306 goto abort;
1307 }
1308 /* For debugging purpose */
1309 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1310 if (rc) {
1311 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1312 goto abort;
1313 }
1314 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1315 __func__, ctrl->cap_base + SLOTSTATUS, slot_status);
1316
1317 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1318 if (rc) {
1319 err("%s: Cannot read SLOTCTRL register\n", __func__);
1320 goto abort;
1321 }
1322 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1323 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1324
1325 for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1326 if (pci_resource_len(pdev, rc) > 0)
1327 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1328 (unsigned long long)pci_resource_start(pdev, rc),
1329 (unsigned long long)pci_resource_len(pdev, rc));
1330
1331 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1332 pdev->vendor, pdev->device,
1333 pdev->subsystem_vendor, pdev->subsystem_device);
1334 1140
1141 ctrl->slot_cap = slot_cap;
1142 ctrl->first_slot = slot_cap >> 19;
1143 ctrl->slot_device_offset = 0;
1144 ctrl->num_slots = 1;
1145 ctrl->hpc_ops = &pciehp_hpc_ops;
1335 mutex_init(&ctrl->crit_sect); 1146 mutex_init(&ctrl->crit_sect);
1336 mutex_init(&ctrl->ctrl_lock); 1147 mutex_init(&ctrl->ctrl_lock);
1337 spin_lock_init(&ctrl->lock);
1338
1339 /* setup wait queue */
1340 init_waitqueue_head(&ctrl->queue); 1148 init_waitqueue_head(&ctrl->queue);
1149 dbg_ctrl(ctrl);
1341 1150
1342 /* return PCI Controller Info */ 1151 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1343 ctrl->slot_device_offset = 0; 1152 pdev->vendor, pdev->device,
1344 ctrl->num_slots = 1; 1153 pdev->subsystem_vendor, pdev->subsystem_device);
1345 ctrl->first_slot = slot_cap >> 19;
1346 ctrl->ctrlcap = slot_cap & 0x0000007f;
1347 1154
1348 rc = pcie_init_hardware_part1(ctrl, dev); 1155 if (pcie_init_hardware_part1(ctrl, dev))
1349 if (rc)
1350 goto abort; 1156 goto abort;
1351 1157
1352 if (pciehp_poll_mode) { 1158 if (pciehp_request_irq(ctrl))
1353 /* Install interrupt polling timer. Start with 10 sec delay */ 1159 goto abort;
1354 init_timer(&ctrl->poll_timer);
1355 start_int_poll_timer(ctrl, 10);
1356 } else {
1357 /* Installs the interrupt handler */
1358 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1359 MY_NAME, (void *)ctrl);
1360 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1361 __func__, ctrl->pci_dev->irq,
1362 atomic_read(&pciehp_num_controllers), rc);
1363 if (rc) {
1364 err("Can't get irq %d for the hotplug controller\n",
1365 ctrl->pci_dev->irq);
1366 goto abort;
1367 }
1368 }
1369 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1370 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1371 1160
1372 /* 1161 /*
1373 * If this is the first controller to be initialized, 1162 * If this is the first controller to be initialized,
@@ -1376,21 +1165,17 @@ int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1376 if (atomic_add_return(1, &pciehp_num_controllers) == 1) { 1165 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1377 pciehp_wq = create_singlethread_workqueue("pciehpd"); 1166 pciehp_wq = create_singlethread_workqueue("pciehpd");
1378 if (!pciehp_wq) { 1167 if (!pciehp_wq) {
1379 rc = -ENOMEM;
1380 goto abort_free_irq; 1168 goto abort_free_irq;
1381 } 1169 }
1382 } 1170 }
1383 1171
1384 rc = pcie_init_hardware_part2(ctrl, dev); 1172 if (pcie_init_hardware_part2(ctrl, dev))
1385 if (rc == 0) { 1173 goto abort_free_irq;
1386 ctrl->hpc_ops = &pciehp_hpc_ops; 1174
1387 return 0; 1175 return 0;
1388 } 1176
1389abort_free_irq: 1177abort_free_irq:
1390 if (pciehp_poll_mode) 1178 pciehp_free_irq(ctrl);
1391 del_timer_sync(&ctrl->poll_timer);
1392 else
1393 free_irq(ctrl->pci_dev->irq, ctrl);
1394abort: 1179abort:
1395 return -1; 1180 return -1;
1396} 1181}
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 43816d4b3c43..1648076600fc 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -39,6 +39,7 @@
39int shpchp_debug; 39int shpchp_debug;
40int shpchp_poll_mode; 40int shpchp_poll_mode;
41int shpchp_poll_time; 41int shpchp_poll_time;
42int shpchp_slot_with_bus;
42struct workqueue_struct *shpchp_wq; 43struct workqueue_struct *shpchp_wq;
43 44
44#define DRIVER_VERSION "0.4" 45#define DRIVER_VERSION "0.4"
@@ -52,9 +53,11 @@ MODULE_LICENSE("GPL");
52module_param(shpchp_debug, bool, 0644); 53module_param(shpchp_debug, bool, 0644);
53module_param(shpchp_poll_mode, bool, 0644); 54module_param(shpchp_poll_mode, bool, 0644);
54module_param(shpchp_poll_time, int, 0644); 55module_param(shpchp_poll_time, int, 0644);
56module_param(shpchp_slot_with_bus, bool, 0644);
55MODULE_PARM_DESC(shpchp_debug, "Debugging mode enabled or not"); 57MODULE_PARM_DESC(shpchp_debug, "Debugging mode enabled or not");
56MODULE_PARM_DESC(shpchp_poll_mode, "Using polling mechanism for hot-plug events or not"); 58MODULE_PARM_DESC(shpchp_poll_mode, "Using polling mechanism for hot-plug events or not");
57MODULE_PARM_DESC(shpchp_poll_time, "Polling mechanism frequency, in seconds"); 59MODULE_PARM_DESC(shpchp_poll_time, "Polling mechanism frequency, in seconds");
60MODULE_PARM_DESC(shpchp_slot_with_bus, "Use bus number in the slot name");
58 61
59#define SHPC_MODULE_NAME "shpchp" 62#define SHPC_MODULE_NAME "shpchp"
60 63
@@ -100,8 +103,12 @@ static void release_slot(struct hotplug_slot *hotplug_slot)
100 103
101static void make_slot_name(struct slot *slot) 104static void make_slot_name(struct slot *slot)
102{ 105{
103 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%04d_%04d", 106 if (shpchp_slot_with_bus)
104 slot->bus, slot->number); 107 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%04d_%04d",
108 slot->bus, slot->number);
109 else
110 snprintf(slot->hotplug_slot->name, SLOT_NAME_SIZE, "%d",
111 slot->number);
105} 112}
106 113
107static int init_slots(struct controller *ctrl) 114static int init_slots(struct controller *ctrl)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 26938da8f438..8c61304cbb37 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -123,7 +123,7 @@ static void msix_flush_writes(unsigned int irq)
123 } 123 }
124} 124}
125 125
126static void msi_set_mask_bit(unsigned int irq, int flag) 126static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
127{ 127{
128 struct msi_desc *entry; 128 struct msi_desc *entry;
129 129
@@ -137,8 +137,8 @@ static void msi_set_mask_bit(unsigned int irq, int flag)
137 137
138 pos = (long)entry->mask_base; 138 pos = (long)entry->mask_base;
139 pci_read_config_dword(entry->dev, pos, &mask_bits); 139 pci_read_config_dword(entry->dev, pos, &mask_bits);
140 mask_bits &= ~(1); 140 mask_bits &= ~(mask);
141 mask_bits |= flag; 141 mask_bits |= flag & mask;
142 pci_write_config_dword(entry->dev, pos, mask_bits); 142 pci_write_config_dword(entry->dev, pos, mask_bits);
143 } else { 143 } else {
144 msi_set_enable(entry->dev, !flag); 144 msi_set_enable(entry->dev, !flag);
@@ -241,13 +241,13 @@ void write_msi_msg(unsigned int irq, struct msi_msg *msg)
241 241
242void mask_msi_irq(unsigned int irq) 242void mask_msi_irq(unsigned int irq)
243{ 243{
244 msi_set_mask_bit(irq, 1); 244 msi_set_mask_bits(irq, 1, 1);
245 msix_flush_writes(irq); 245 msix_flush_writes(irq);
246} 246}
247 247
248void unmask_msi_irq(unsigned int irq) 248void unmask_msi_irq(unsigned int irq)
249{ 249{
250 msi_set_mask_bit(irq, 0); 250 msi_set_mask_bits(irq, 1, 0);
251 msix_flush_writes(irq); 251 msix_flush_writes(irq);
252} 252}
253 253
@@ -291,7 +291,8 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
291 msi_set_enable(dev, 0); 291 msi_set_enable(dev, 0);
292 write_msi_msg(dev->irq, &entry->msg); 292 write_msi_msg(dev->irq, &entry->msg);
293 if (entry->msi_attrib.maskbit) 293 if (entry->msi_attrib.maskbit)
294 msi_set_mask_bit(dev->irq, entry->msi_attrib.masked); 294 msi_set_mask_bits(dev->irq, entry->msi_attrib.maskbits_mask,
295 entry->msi_attrib.masked);
295 296
296 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 297 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
297 control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); 298 control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
@@ -315,7 +316,7 @@ static void __pci_restore_msix_state(struct pci_dev *dev)
315 316
316 list_for_each_entry(entry, &dev->msi_list, list) { 317 list_for_each_entry(entry, &dev->msi_list, list) {
317 write_msi_msg(entry->irq, &entry->msg); 318 write_msi_msg(entry->irq, &entry->msg);
318 msi_set_mask_bit(entry->irq, entry->msi_attrib.masked); 319 msi_set_mask_bits(entry->irq, 1, entry->msi_attrib.masked);
319 } 320 }
320 321
321 BUG_ON(list_empty(&dev->msi_list)); 322 BUG_ON(list_empty(&dev->msi_list));
@@ -382,6 +383,7 @@ static int msi_capability_init(struct pci_dev *dev)
382 pci_write_config_dword(dev, 383 pci_write_config_dword(dev,
383 msi_mask_bits_reg(pos, is_64bit_address(control)), 384 msi_mask_bits_reg(pos, is_64bit_address(control)),
384 maskbits); 385 maskbits);
386 entry->msi_attrib.maskbits_mask = temp;
385 } 387 }
386 list_add_tail(&entry->list, &dev->msi_list); 388 list_add_tail(&entry->list, &dev->msi_list);
387 389
@@ -569,10 +571,9 @@ int pci_enable_msi(struct pci_dev* dev)
569} 571}
570EXPORT_SYMBOL(pci_enable_msi); 572EXPORT_SYMBOL(pci_enable_msi);
571 573
572void pci_disable_msi(struct pci_dev* dev) 574void pci_msi_shutdown(struct pci_dev* dev)
573{ 575{
574 struct msi_desc *entry; 576 struct msi_desc *entry;
575 int default_irq;
576 577
577 if (!pci_msi_enable || !dev || !dev->msi_enabled) 578 if (!pci_msi_enable || !dev || !dev->msi_enabled)
578 return; 579 return;
@@ -583,15 +584,31 @@ void pci_disable_msi(struct pci_dev* dev)
583 584
584 BUG_ON(list_empty(&dev->msi_list)); 585 BUG_ON(list_empty(&dev->msi_list));
585 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 586 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
586 if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 587 /* Return the the pci reset with msi irqs unmasked */
587 return; 588 if (entry->msi_attrib.maskbit) {
589 u32 mask = entry->msi_attrib.maskbits_mask;
590 msi_set_mask_bits(dev->irq, mask, ~mask);
588 } 591 }
589 592 if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI)
590 default_irq = entry->msi_attrib.default_irq; 593 return;
591 msi_free_irqs(dev);
592 594
593 /* Restore dev->irq to its default pin-assertion irq */ 595 /* Restore dev->irq to its default pin-assertion irq */
594 dev->irq = default_irq; 596 dev->irq = entry->msi_attrib.default_irq;
597}
598void pci_disable_msi(struct pci_dev* dev)
599{
600 struct msi_desc *entry;
601
602 if (!pci_msi_enable || !dev || !dev->msi_enabled)
603 return;
604
605 pci_msi_shutdown(dev);
606
607 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
608 if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI)
609 return;
610
611 msi_free_irqs(dev);
595} 612}
596EXPORT_SYMBOL(pci_disable_msi); 613EXPORT_SYMBOL(pci_disable_msi);
597 614
@@ -684,7 +701,7 @@ static void msix_free_all_irqs(struct pci_dev *dev)
684 msi_free_irqs(dev); 701 msi_free_irqs(dev);
685} 702}
686 703
687void pci_disable_msix(struct pci_dev* dev) 704void pci_msix_shutdown(struct pci_dev* dev)
688{ 705{
689 if (!pci_msi_enable || !dev || !dev->msix_enabled) 706 if (!pci_msi_enable || !dev || !dev->msix_enabled)
690 return; 707 return;
@@ -692,6 +709,13 @@ void pci_disable_msix(struct pci_dev* dev)
692 msix_set_enable(dev, 0); 709 msix_set_enable(dev, 0);
693 pci_intx_for_msi(dev, 1); 710 pci_intx_for_msi(dev, 1);
694 dev->msix_enabled = 0; 711 dev->msix_enabled = 0;
712}
713void pci_disable_msix(struct pci_dev* dev)
714{
715 if (!pci_msi_enable || !dev || !dev->msix_enabled)
716 return;
717
718 pci_msix_shutdown(dev);
695 719
696 msix_free_all_irqs(dev); 720 msix_free_all_irqs(dev);
697} 721}
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index e8d94fafc280..72cf61ed8f96 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -360,6 +360,8 @@ static void pci_device_shutdown(struct device *dev)
360 360
361 if (drv && drv->shutdown) 361 if (drv && drv->shutdown)
362 drv->shutdown(pci_dev); 362 drv->shutdown(pci_dev);
363 pci_msi_shutdown(pci_dev);
364 pci_msix_shutdown(pci_dev);
363} 365}
364 366
365/** 367/**
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 25b04fb2517d..5a0c6ad53f8e 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -33,7 +33,7 @@ source "drivers/pci/pcie/aer/Kconfig"
33config PCIEASPM 33config PCIEASPM
34 bool "PCI Express ASPM support(Experimental)" 34 bool "PCI Express ASPM support(Experimental)"
35 depends on PCI && EXPERIMENTAL && PCIEPORTBUS 35 depends on PCI && EXPERIMENTAL && PCIEPORTBUS
36 default y 36 default n
37 help 37 help
38 This enables PCI Express ASPM (Active State Power Management) and 38 This enables PCI Express ASPM (Active State Power Management) and
39 Clock Power Management. ASPM supports state L0/L0s/L1. 39 Clock Power Management. ASPM supports state L0/L0s/L1.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 14:47:08 -0500