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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2006-12-21 20:01:08 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2007-02-07 18:50:05 -0500
commit75e13178af33e20b5802885f637af2a82c64ac2c (patch)
tree73af18b3bf9bdfc1d956683fd338c684788b1382 /drivers/pci
parent15232ece5566710d24c81ac3dd629f7556a92818 (diff)
pciehp: remove unused pcie_cap_base
This patch removes unused pcie_cap_base variable. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 98eee63f3ec5..d8f4f1241b56 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -105,7 +105,6 @@ enum ctrl_offsets {
105 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), 105 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
106 ROOTSTATUS = offsetof(struct ctrl_reg, root_status), 106 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
107}; 107};
108static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
109 108
110static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 109static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
111{ 110{
@@ -1072,7 +1071,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1072 u16 cap_reg; 1071 u16 cap_reg;
1073 u16 intr_enable = 0; 1072 u16 intr_enable = 0;
1074 u32 slot_cap; 1073 u32 slot_cap;
1075 int cap_base, saved_cap_base; 1074 int cap_base;
1076 u16 slot_status, slot_ctrl; 1075 u16 slot_status, slot_ctrl;
1077 struct pci_dev *pdev; 1076 struct pci_dev *pdev;
1078 1077
@@ -1084,8 +1083,6 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1084 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", 1083 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1085 __FUNCTION__, pdev->vendor, pdev->device); 1084 __FUNCTION__, pdev->vendor, pdev->device);
1086 1085
1087 saved_cap_base = pcie_cap_base;
1088
1089 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { 1086 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1090 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); 1087 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1091 goto abort_free_ctlr; 1088 goto abort_free_ctlr;
@@ -1093,7 +1090,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1093 1090
1094 ctrl->cap_base = cap_base; 1091 ctrl->cap_base = cap_base;
1095 1092
1096 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base); 1093 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1097 1094
1098 rc = pciehp_readw(ctrl, CAPREG, &cap_reg); 1095 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1099 if (rc) { 1096 if (rc) {
@@ -1289,8 +1286,6 @@ abort_free_irq:
1289 free_irq(ctrl->pci_dev->irq, ctrl); 1286 free_irq(ctrl->pci_dev->irq, ctrl);
1290 1287
1291abort_free_ctlr: 1288abort_free_ctlr:
1292 pcie_cap_base = saved_cap_base;
1293
1294 DBG_LEAVE_ROUTINE 1289 DBG_LEAVE_ROUTINE
1295 return -1; 1290 return -1;
1296} 1291}