diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2006-05-01 22:10:37 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-06-19 17:13:23 -0400 |
commit | 5858759c2098c6792af1afa6d5ded94044740f9c (patch) | |
tree | 673a917583ba1f4e8c16027f0aa712bc04fb4b48 /drivers/pci | |
parent | 2b34da7e61383b4b7773d2d4e776e58725794347 (diff) |
[PATCH] SHPC: Cleanup SHPC Logical Slot Register bits access
This patch cleans up the code to access bits in slot logical
registers. This patch has no functional change.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Cc: Kristen Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/hotplug/shpchp_hpc.c | 151 |
1 files changed, 64 insertions, 87 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index a5337cf1436d..9731ee8224f2 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c | |||
@@ -95,43 +95,40 @@ | |||
95 | */ | 95 | */ |
96 | #define SLOT_REG(i) (SLOT1 + (4 * i)) | 96 | #define SLOT_REG(i) (SLOT1 + (4 * i)) |
97 | 97 | ||
98 | /* Slot Status Field Definitions */ | 98 | #define SLOT_STATE_SHIFT (0) |
99 | /* Slot State */ | 99 | #define SLOT_STATE_MASK (3 << 0) |
100 | #define PWR_ONLY 0x0001 | 100 | #define SLOT_STATE_PWRONLY (1) |
101 | #define ENABLED 0x0002 | 101 | #define SLOT_STATE_ENABLED (2) |
102 | #define DISABLED 0x0003 | 102 | #define SLOT_STATE_DISABLED (3) |
103 | 103 | #define PWR_LED_STATE_SHIFT (2) | |
104 | /* Power Indicator State */ | 104 | #define PWR_LED_STATE_MASK (3 << 2) |
105 | #define PWR_LED_ON 0x0004 | 105 | #define ATN_LED_STATE_SHIFT (4) |
106 | #define PWR_LED_BLINK 0x0008 | 106 | #define ATN_LED_STATE_MASK (3 << 4) |
107 | #define PWR_LED_OFF 0x000c | 107 | #define ATN_LED_STATE_ON (1) |
108 | 108 | #define ATN_LED_STATE_BLINK (2) | |
109 | /* Attention Indicator State */ | 109 | #define ATN_LED_STATE_OFF (3) |
110 | #define ATTEN_LED_ON 0x0010 | 110 | #define POWER_FAULT (1 << 6) |
111 | #define ATTEN_LED_BLINK 0x0020 | 111 | #define ATN_BUTTON (1 << 7) |
112 | #define ATTEN_LED_OFF 0x0030 | 112 | #define MRL_SENSOR (1 << 8) |
113 | 113 | #define MHZ66_CAP (1 << 9) | |
114 | /* Power Fault */ | 114 | #define PRSNT_SHIFT (10) |
115 | #define pwr_fault 0x0040 | 115 | #define PRSNT_MASK (3 << 10) |
116 | 116 | #define PCIX_CAP_SHIFT (12) | |
117 | /* Attention Button */ | 117 | #define PCIX_CAP_MASK_PI1 (3 << 12) |
118 | #define ATTEN_BUTTON 0x0080 | 118 | #define PCIX_CAP_MASK_PI2 (7 << 12) |
119 | 119 | #define PRSNT_CHANGE_DETECTED (1 << 16) | |
120 | /* MRL Sensor */ | 120 | #define ISO_PFAULT_DETECTED (1 << 17) |
121 | #define MRL_SENSOR 0x0100 | 121 | #define BUTTON_PRESS_DETECTED (1 << 18) |
122 | 122 | #define MRL_CHANGE_DETECTED (1 << 19) | |
123 | /* 66 MHz Capable */ | 123 | #define CON_PFAULT_DETECTED (1 << 20) |
124 | #define IS_66MHZ_CAP 0x0200 | 124 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) |
125 | 125 | #define ISO_PFAULT_INTR_MASK (1 << 25) | |
126 | /* PRSNT1#/PRSNT2# */ | 126 | #define BUTTON_PRESS_INTR_MASK (1 << 26) |
127 | #define SLOT_EMP 0x0c00 | 127 | #define MRL_CHANGE_INTR_MASK (1 << 27) |
128 | 128 | #define CON_PFAULT_INTR_MASK (1 << 28) | |
129 | /* PCI-X Capability */ | 129 | #define MRL_CHANGE_SERR_MASK (1 << 29) |
130 | #define NON_PCIX 0x0000 | 130 | #define CON_PFAULT_SERR_MASK (1 << 30) |
131 | #define PCIX_66 0x1000 | 131 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) |
132 | #define PCIX_133 0x3000 | ||
133 | #define PCIX_266 0x4000 /* For PI = 2 only */ | ||
134 | #define PCIX_533 0x5000 /* For PI = 2 only */ | ||
135 | 132 | ||
136 | /* SHPC 'write' operations/commands */ | 133 | /* SHPC 'write' operations/commands */ |
137 | 134 | ||
@@ -428,8 +425,7 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
428 | { | 425 | { |
429 | struct controller *ctrl = slot->ctrl; | 426 | struct controller *ctrl = slot->ctrl; |
430 | u32 slot_reg; | 427 | u32 slot_reg; |
431 | u16 slot_status; | 428 | u8 state; |
432 | u8 atten_led_state; | ||
433 | 429 | ||
434 | DBG_ENTER_ROUTINE | 430 | DBG_ENTER_ROUTINE |
435 | 431 | ||
@@ -439,24 +435,20 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
439 | } | 435 | } |
440 | 436 | ||
441 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | 437 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
442 | slot_status = (u16) slot_reg; | 438 | state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
443 | atten_led_state = (slot_status & 0x0030) >> 4; | ||
444 | 439 | ||
445 | switch (atten_led_state) { | 440 | switch (state) { |
446 | case 0: | 441 | case ATN_LED_STATE_ON: |
447 | *status = 0xFF; /* Reserved */ | ||
448 | break; | ||
449 | case 1: | ||
450 | *status = 1; /* On */ | 442 | *status = 1; /* On */ |
451 | break; | 443 | break; |
452 | case 2: | 444 | case ATN_LED_STATE_BLINK: |
453 | *status = 2; /* Blink */ | 445 | *status = 2; /* Blink */ |
454 | break; | 446 | break; |
455 | case 3: | 447 | case ATN_LED_STATE_OFF: |
456 | *status = 0; /* Off */ | 448 | *status = 0; /* Off */ |
457 | break; | 449 | break; |
458 | default: | 450 | default: |
459 | *status = 0xFF; | 451 | *status = 0xFF; /* Reserved */ |
460 | break; | 452 | break; |
461 | } | 453 | } |
462 | 454 | ||
@@ -468,9 +460,7 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) | |||
468 | { | 460 | { |
469 | struct controller *ctrl = slot->ctrl; | 461 | struct controller *ctrl = slot->ctrl; |
470 | u32 slot_reg; | 462 | u32 slot_reg; |
471 | u16 slot_status; | 463 | u8 state; |
472 | u8 slot_state; | ||
473 | int retval = 0; | ||
474 | 464 | ||
475 | DBG_ENTER_ROUTINE | 465 | DBG_ENTER_ROUTINE |
476 | 466 | ||
@@ -480,29 +470,25 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) | |||
480 | } | 470 | } |
481 | 471 | ||
482 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | 472 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
483 | slot_status = (u16) slot_reg; | 473 | state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
484 | slot_state = (slot_status & 0x0003); | ||
485 | 474 | ||
486 | switch (slot_state) { | 475 | switch (state) { |
487 | case 0: | 476 | case SLOT_STATE_PWRONLY: |
488 | *status = 0xFF; | ||
489 | break; | ||
490 | case 1: | ||
491 | *status = 2; /* Powered only */ | 477 | *status = 2; /* Powered only */ |
492 | break; | 478 | break; |
493 | case 2: | 479 | case SLOT_STATE_ENABLED: |
494 | *status = 1; /* Enabled */ | 480 | *status = 1; /* Enabled */ |
495 | break; | 481 | break; |
496 | case 3: | 482 | case SLOT_STATE_DISABLED: |
497 | *status = 0; /* Disabled */ | 483 | *status = 0; /* Disabled */ |
498 | break; | 484 | break; |
499 | default: | 485 | default: |
500 | *status = 0xFF; | 486 | *status = 0xFF; /* Reserved */ |
501 | break; | 487 | break; |
502 | } | 488 | } |
503 | 489 | ||
504 | DBG_LEAVE_ROUTINE | 490 | DBG_LEAVE_ROUTINE |
505 | return retval; | 491 | return 0; |
506 | } | 492 | } |
507 | 493 | ||
508 | 494 | ||
@@ -510,7 +496,6 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status) | |||
510 | { | 496 | { |
511 | struct controller *ctrl = slot->ctrl; | 497 | struct controller *ctrl = slot->ctrl; |
512 | u32 slot_reg; | 498 | u32 slot_reg; |
513 | u16 slot_status; | ||
514 | 499 | ||
515 | DBG_ENTER_ROUTINE | 500 | DBG_ENTER_ROUTINE |
516 | 501 | ||
@@ -520,10 +505,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status) | |||
520 | } | 505 | } |
521 | 506 | ||
522 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | 507 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
523 | slot_status = (u16)slot_reg; | 508 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
524 | |||
525 | *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */ | ||
526 | |||
527 | 509 | ||
528 | DBG_LEAVE_ROUTINE | 510 | DBG_LEAVE_ROUTINE |
529 | return 0; | 511 | return 0; |
@@ -533,8 +515,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |||
533 | { | 515 | { |
534 | struct controller *ctrl = slot->ctrl; | 516 | struct controller *ctrl = slot->ctrl; |
535 | u32 slot_reg; | 517 | u32 slot_reg; |
536 | u16 slot_status; | 518 | u8 state; |
537 | u8 card_state; | ||
538 | 519 | ||
539 | DBG_ENTER_ROUTINE | 520 | DBG_ENTER_ROUTINE |
540 | 521 | ||
@@ -544,9 +525,8 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |||
544 | } | 525 | } |
545 | 526 | ||
546 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | 527 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
547 | slot_status = (u16)slot_reg; | 528 | state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
548 | card_state = (u8)((slot_status & 0x0C00) >> 10); | 529 | *status = (state != 0x3) ? 1 : 0; |
549 | *status = (card_state != 0x3) ? 1 : 0; | ||
550 | 530 | ||
551 | DBG_LEAVE_ROUTINE | 531 | DBG_LEAVE_ROUTINE |
552 | return 0; | 532 | return 0; |
@@ -574,8 +554,8 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |||
574 | int retval = 0; | 554 | int retval = 0; |
575 | struct controller *ctrl = slot->ctrl; | 555 | struct controller *ctrl = slot->ctrl; |
576 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | 556 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
577 | u8 pcix_cap = (slot_reg >> 12) & 7; | 557 | u8 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; |
578 | u8 m66_cap = (slot_reg >> 9) & 1; | 558 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
579 | 559 | ||
580 | DBG_ENTER_ROUTINE | 560 | DBG_ENTER_ROUTINE |
581 | 561 | ||
@@ -643,8 +623,6 @@ static int hpc_query_power_fault(struct slot * slot) | |||
643 | { | 623 | { |
644 | struct controller *ctrl = slot->ctrl; | 624 | struct controller *ctrl = slot->ctrl; |
645 | u32 slot_reg; | 625 | u32 slot_reg; |
646 | u16 slot_status; | ||
647 | u8 pwr_fault_state, status; | ||
648 | 626 | ||
649 | DBG_ENTER_ROUTINE | 627 | DBG_ENTER_ROUTINE |
650 | 628 | ||
@@ -654,13 +632,10 @@ static int hpc_query_power_fault(struct slot * slot) | |||
654 | } | 632 | } |
655 | 633 | ||
656 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); | 634 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
657 | slot_status = (u16) slot_reg; | ||
658 | pwr_fault_state = (slot_status & 0x0040) >> 7; | ||
659 | status = (pwr_fault_state == 1) ? 0 : 1; | ||
660 | 635 | ||
661 | DBG_LEAVE_ROUTINE | 636 | DBG_LEAVE_ROUTINE |
662 | /* Note: Logic 0 => fault */ | 637 | /* Note: Logic 0 => fault */ |
663 | return status; | 638 | return !(slot_reg & POWER_FAULT); |
664 | } | 639 | } |
665 | 640 | ||
666 | static int hpc_set_attention_status(struct slot *slot, u8 value) | 641 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
@@ -1019,7 +994,6 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1019 | struct controller *ctrl = NULL; | 994 | struct controller *ctrl = NULL; |
1020 | struct php_ctlr_state_s *php_ctlr; | 995 | struct php_ctlr_state_s *php_ctlr; |
1021 | u8 schedule_flag = 0; | 996 | u8 schedule_flag = 0; |
1022 | u8 temp_byte; | ||
1023 | u32 temp_dword, intr_loc, intr_loc2; | 997 | u32 temp_dword, intr_loc, intr_loc2; |
1024 | int hp_slot; | 998 | int hp_slot; |
1025 | 999 | ||
@@ -1080,17 +1054,20 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |||
1080 | temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot)); | 1054 | temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1081 | dbg("%s: Slot %x with intr, slot register = %x\n", | 1055 | dbg("%s: Slot %x with intr, slot register = %x\n", |
1082 | __FUNCTION__, hp_slot, temp_dword); | 1056 | __FUNCTION__, hp_slot, temp_dword); |
1083 | temp_byte = (temp_dword >> 16) & 0xFF; | 1057 | if ((php_ctlr->switch_change_callback) && |
1084 | if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08)) | 1058 | (temp_dword & MRL_CHANGE_DETECTED)) |
1085 | schedule_flag += php_ctlr->switch_change_callback( | 1059 | schedule_flag += php_ctlr->switch_change_callback( |
1086 | hp_slot, php_ctlr->callback_instance_id); | 1060 | hp_slot, php_ctlr->callback_instance_id); |
1087 | if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04)) | 1061 | if ((php_ctlr->attention_button_callback) && |
1062 | (temp_dword & BUTTON_PRESS_DETECTED)) | ||
1088 | schedule_flag += php_ctlr->attention_button_callback( | 1063 | schedule_flag += php_ctlr->attention_button_callback( |
1089 | hp_slot, php_ctlr->callback_instance_id); | 1064 | hp_slot, php_ctlr->callback_instance_id); |
1090 | if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01)) | 1065 | if ((php_ctlr->presence_change_callback) && |
1066 | (temp_dword & PRSNT_CHANGE_DETECTED)) | ||
1091 | schedule_flag += php_ctlr->presence_change_callback( | 1067 | schedule_flag += php_ctlr->presence_change_callback( |
1092 | hp_slot , php_ctlr->callback_instance_id); | 1068 | hp_slot , php_ctlr->callback_instance_id); |
1093 | if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12)) | 1069 | if ((php_ctlr->power_fault_callback) && |
1070 | (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))) | ||
1094 | schedule_flag += php_ctlr->power_fault_callback( | 1071 | schedule_flag += php_ctlr->power_fault_callback( |
1095 | hp_slot, php_ctlr->callback_instance_id); | 1072 | hp_slot, php_ctlr->callback_instance_id); |
1096 | 1073 | ||