diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2009-09-15 04:34:05 -0400 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-09-17 13:06:46 -0400 |
commit | 656927b119a6f2fe0ed453191e13eec6fe041f4c (patch) | |
tree | 33a7468578e2010b761e20eca71c5934d574b9ed /drivers/pci | |
parent | d9fb42a845f8e56d91017462650ba41e854f5552 (diff) |
PCI: pciehp: remove slot capabilities definitions
Use generic PCIe slot capabilities register definitions instead of
internal definitions.
Acked-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/hotplug/pciehp.h | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 13be51dd401e..3070f77eb56a 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h | |||
@@ -117,24 +117,14 @@ struct controller { | |||
117 | #define POWERON_STATE 3 | 117 | #define POWERON_STATE 3 |
118 | #define POWEROFF_STATE 4 | 118 | #define POWEROFF_STATE 4 |
119 | 119 | ||
120 | /* Field definitions in Slot Capabilities Register */ | 120 | #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP) |
121 | #define ATTN_BUTTN_PRSN 0x00000001 | 121 | #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP) |
122 | #define PWR_CTRL_PRSN 0x00000002 | 122 | #define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP) |
123 | #define MRL_SENS_PRSN 0x00000004 | 123 | #define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP) |
124 | #define ATTN_LED_PRSN 0x00000008 | 124 | #define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP) |
125 | #define PWR_LED_PRSN 0x00000010 | 125 | #define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS) |
126 | #define HP_SUPR_RM_SUP 0x00000020 | 126 | #define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP) |
127 | #define EMI_PRSN 0x00020000 | 127 | #define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS) |
128 | #define NO_CMD_CMPL_SUP 0x00040000 | ||
129 | |||
130 | #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & ATTN_BUTTN_PRSN) | ||
131 | #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PWR_CTRL_PRSN) | ||
132 | #define MRL_SENS(ctrl) ((ctrl)->slot_cap & MRL_SENS_PRSN) | ||
133 | #define ATTN_LED(ctrl) ((ctrl)->slot_cap & ATTN_LED_PRSN) | ||
134 | #define PWR_LED(ctrl) ((ctrl)->slot_cap & PWR_LED_PRSN) | ||
135 | #define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & HP_SUPR_RM_SUP) | ||
136 | #define EMI(ctrl) ((ctrl)->slot_cap & EMI_PRSN) | ||
137 | #define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & NO_CMD_CMPL_SUP) | ||
138 | #define PSN(ctrl) ((ctrl)->slot_cap >> 19) | 128 | #define PSN(ctrl) ((ctrl)->slot_cap >> 19) |
139 | 129 | ||
140 | extern int pciehp_sysfs_enable_slot(struct slot *slot); | 130 | extern int pciehp_sysfs_enable_slot(struct slot *slot); |