Merge branch 'master' into for-linus

3 files changed, 25 insertions, 9 deletions

diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index 796828fce34c..c9171be74564 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -340,7 +340,7 @@ int dmar_disabled = 0;
 int dmar_disabled = 1;
 #endif /*CONFIG_DMAR_DEFAULT_ON*/
 
-static int __initdata dmar_map_gfx = 1;
+static int dmar_map_gfx = 1;
 static int dmar_forcedac;
 static int intel_iommu_strict;
 
@@ -1874,14 +1874,15 @@ static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
                         }
                 }
                 if (found) {
+                        spin_unlock_irqrestore(&device_domain_lock, flags);
                         free_devinfo_mem(info);
                         domain_exit(domain);
                         domain = found;
                 } else {
                         list_add(&info->link, &domain->devices);
                         list_add(&info->global, &device_domain_list);
+                        spin_unlock_irqrestore(&device_domain_lock, flags);
                 }
-                spin_unlock_irqrestore(&device_domain_lock, flags);
         }
 
 found_domain:
@@ -3603,7 +3604,8 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
                 pte = dmar_domain->pgd;
                 if (dma_pte_present(pte)) {
                         free_pgtable_page(dmar_domain->pgd);
-                        dmar_domain->pgd = (struct dma_pte *)dma_pte_addr(pte);
+                        dmar_domain->pgd = (struct dma_pte *)
+                                phys_to_virt(dma_pte_addr(pte));
                 }
                 dmar_domain->agaw--;
         }
@@ -3719,6 +3721,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
          */
         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
         rwbf_quirk = 1;
+
+        /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
+        if (dev->revision == 0x07) {
+                printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
+                dmar_map_gfx = 0;
+        }
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 60f30e7f1c8c..740fb4ea9669 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2292,6 +2292,7 @@ void pci_msi_off(struct pci_dev *dev)
                 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
         }
 }
+EXPORT_SYMBOL_GPL(pci_msi_off);
 
 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
diff --git a/drivers/pci/pcie/pme/pcie_pme.c b/drivers/pci/pcie/pme/pcie_pme.c
index aac285a16b62..d672a0a63816 100644
--- a/drivers/pci/pcie/pme/pcie_pme.c
+++ b/drivers/pci/pcie/pme/pcie_pme.c
@@ -34,7 +34,7 @@
  * being registered.  Consequently, the interrupt-based PCIe PME signaling will
  * not be used by any PCIe root ports in that case.
  */
-static bool pcie_pme_disabled;
+static bool pcie_pme_disabled = true;
 
 /*
  * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
@@ -64,12 +64,19 @@ bool pcie_pme_msi_disabled;
 
 static int __init pcie_pme_setup(char *str)
 {
-        if (!strcmp(str, "off"))
-                pcie_pme_disabled = true;
-        else if (!strcmp(str, "force"))
+        if (!strncmp(str, "auto", 4))
+                pcie_pme_disabled = false;
+        else if (!strncmp(str, "force", 5))
                 pcie_pme_force_enable = true;
-        else if (!strcmp(str, "nomsi"))
-                pcie_pme_msi_disabled = true;
+
+        str = strchr(str, ',');
+        if (str) {
+                str++;
+                str += strspn(str, " \t");
+                if (*str && !strcmp(str, "nomsi"))
+                        pcie_pme_msi_disabled = true;
+        }
+
         return 1;
 }
 __setup("pcie_pme=", pcie_pme_setup);