diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2007-08-09 19:09:33 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2007-10-12 18:03:14 -0400 |
commit | c8426483776d913c5bdc3d698a7633496a885b78 (patch) | |
tree | 424aa9e8fca2a518a73c6e641a9e7bd0c891a7d1 /drivers/pci | |
parent | 57d90c027641169b0724f94d355704e28895bcd6 (diff) |
pciehp: remove DBG_XXX_ROUTINE
This patch removes DBG_ENTER_ROUTIN, DBG_LEAVE_ROUTINE and related
code, which seem no longer needed.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 111 |
1 files changed, 5 insertions, 106 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index dbd04660babb..f6143175de71 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c | |||
@@ -39,37 +39,6 @@ | |||
39 | 39 | ||
40 | #include "../pci.h" | 40 | #include "../pci.h" |
41 | #include "pciehp.h" | 41 | #include "pciehp.h" |
42 | #ifdef DEBUG | ||
43 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | ||
44 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | ||
45 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | ||
46 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | ||
47 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | ||
48 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | ||
49 | /* Redefine this flagword to set debug level */ | ||
50 | #define DEBUG_LEVEL DBG_K_STANDARD | ||
51 | |||
52 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | ||
53 | |||
54 | #define DBG_PRINT( dbg_flags, args... ) \ | ||
55 | do { \ | ||
56 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | ||
57 | { \ | ||
58 | int len; \ | ||
59 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | ||
60 | __FILE__, __LINE__, __FUNCTION__ ); \ | ||
61 | sprintf( __dbg_str_buf + len, args ); \ | ||
62 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | ||
63 | } \ | ||
64 | } while (0) | ||
65 | |||
66 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | ||
67 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | ||
68 | #else | ||
69 | #define DEFINE_DBG_BUFFER | ||
70 | #define DBG_ENTER_ROUTINE | ||
71 | #define DBG_LEAVE_ROUTINE | ||
72 | #endif /* DEBUG */ | ||
73 | 42 | ||
74 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); | 43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
75 | 44 | ||
@@ -221,8 +190,6 @@ static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |||
221 | #define EMI_STATE 0x0080 | 190 | #define EMI_STATE 0x0080 |
222 | #define EMI_STATUS_BIT 7 | 191 | #define EMI_STATUS_BIT 7 |
223 | 192 | ||
224 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | ||
225 | |||
226 | static irqreturn_t pcie_isr(int irq, void *dev_id); | 193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
227 | static void start_int_poll_timer(struct controller *ctrl, int sec); | 194 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
228 | 195 | ||
@@ -231,8 +198,6 @@ static void int_poll_timeout(unsigned long data) | |||
231 | { | 198 | { |
232 | struct controller *ctrl = (struct controller *)data; | 199 | struct controller *ctrl = (struct controller *)data; |
233 | 200 | ||
234 | DBG_ENTER_ROUTINE | ||
235 | |||
236 | /* Poll for interrupt events. regs == NULL => polling */ | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
237 | pcie_isr(0, ctrl); | 202 | pcie_isr(0, ctrl); |
238 | 203 | ||
@@ -289,8 +254,6 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask) | |||
289 | u16 slot_ctrl; | 254 | u16 slot_ctrl; |
290 | unsigned long flags; | 255 | unsigned long flags; |
291 | 256 | ||
292 | DBG_ENTER_ROUTINE | ||
293 | |||
294 | mutex_lock(&ctrl->ctrl_lock); | 257 | mutex_lock(&ctrl->ctrl_lock); |
295 | 258 | ||
296 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 259 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
@@ -332,7 +295,6 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask) | |||
332 | retval = pcie_wait_cmd(ctrl); | 295 | retval = pcie_wait_cmd(ctrl); |
333 | out: | 296 | out: |
334 | mutex_unlock(&ctrl->ctrl_lock); | 297 | mutex_unlock(&ctrl->ctrl_lock); |
335 | DBG_LEAVE_ROUTINE | ||
336 | return retval; | 298 | return retval; |
337 | } | 299 | } |
338 | 300 | ||
@@ -341,8 +303,6 @@ static int hpc_check_lnk_status(struct controller *ctrl) | |||
341 | u16 lnk_status; | 303 | u16 lnk_status; |
342 | int retval = 0; | 304 | int retval = 0; |
343 | 305 | ||
344 | DBG_ENTER_ROUTINE | ||
345 | |||
346 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 306 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
347 | if (retval) { | 307 | if (retval) { |
348 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); | 308 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
@@ -357,7 +317,6 @@ static int hpc_check_lnk_status(struct controller *ctrl) | |||
357 | return retval; | 317 | return retval; |
358 | } | 318 | } |
359 | 319 | ||
360 | DBG_LEAVE_ROUTINE | ||
361 | return retval; | 320 | return retval; |
362 | } | 321 | } |
363 | 322 | ||
@@ -368,8 +327,6 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
368 | u16 slot_ctrl; | 327 | u16 slot_ctrl; |
369 | u8 atten_led_state; | 328 | u8 atten_led_state; |
370 | int retval = 0; | 329 | int retval = 0; |
371 | |||
372 | DBG_ENTER_ROUTINE | ||
373 | 330 | ||
374 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | 331 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
375 | if (retval) { | 332 | if (retval) { |
@@ -400,7 +357,6 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
400 | break; | 357 | break; |
401 | } | 358 | } |
402 | 359 | ||
403 | DBG_LEAVE_ROUTINE | ||
404 | return 0; | 360 | return 0; |
405 | } | 361 | } |
406 | 362 | ||
@@ -410,8 +366,6 @@ static int hpc_get_power_status(struct slot *slot, u8 *status) | |||
410 | u16 slot_ctrl; | 366 | u16 slot_ctrl; |
411 | u8 pwr_state; | 367 | u8 pwr_state; |
412 | int retval = 0; | 368 | int retval = 0; |
413 | |||
414 | DBG_ENTER_ROUTINE | ||
415 | 369 | ||
416 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | 370 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
417 | if (retval) { | 371 | if (retval) { |
@@ -435,7 +389,6 @@ static int hpc_get_power_status(struct slot *slot, u8 *status) | |||
435 | break; | 389 | break; |
436 | } | 390 | } |
437 | 391 | ||
438 | DBG_LEAVE_ROUTINE | ||
439 | return retval; | 392 | return retval; |
440 | } | 393 | } |
441 | 394 | ||
@@ -446,8 +399,6 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status) | |||
446 | u16 slot_status; | 399 | u16 slot_status; |
447 | int retval = 0; | 400 | int retval = 0; |
448 | 401 | ||
449 | DBG_ENTER_ROUTINE | ||
450 | |||
451 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 402 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
452 | if (retval) { | 403 | if (retval) { |
453 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); | 404 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
@@ -456,7 +407,6 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status) | |||
456 | 407 | ||
457 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; | 408 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
458 | 409 | ||
459 | DBG_LEAVE_ROUTINE | ||
460 | return 0; | 410 | return 0; |
461 | } | 411 | } |
462 | 412 | ||
@@ -467,8 +417,6 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |||
467 | u8 card_state; | 417 | u8 card_state; |
468 | int retval = 0; | 418 | int retval = 0; |
469 | 419 | ||
470 | DBG_ENTER_ROUTINE | ||
471 | |||
472 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 420 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
473 | if (retval) { | 421 | if (retval) { |
474 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); | 422 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
@@ -477,7 +425,6 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |||
477 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | 425 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); |
478 | *status = (card_state == 1) ? 1 : 0; | 426 | *status = (card_state == 1) ? 1 : 0; |
479 | 427 | ||
480 | DBG_LEAVE_ROUTINE | ||
481 | return 0; | 428 | return 0; |
482 | } | 429 | } |
483 | 430 | ||
@@ -488,8 +435,6 @@ static int hpc_query_power_fault(struct slot *slot) | |||
488 | u8 pwr_fault; | 435 | u8 pwr_fault; |
489 | int retval = 0; | 436 | int retval = 0; |
490 | 437 | ||
491 | DBG_ENTER_ROUTINE | ||
492 | |||
493 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 438 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
494 | if (retval) { | 439 | if (retval) { |
495 | err("%s: Cannot check for power fault\n", __FUNCTION__); | 440 | err("%s: Cannot check for power fault\n", __FUNCTION__); |
@@ -497,7 +442,6 @@ static int hpc_query_power_fault(struct slot *slot) | |||
497 | } | 442 | } |
498 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | 443 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); |
499 | 444 | ||
500 | DBG_LEAVE_ROUTINE | ||
501 | return pwr_fault; | 445 | return pwr_fault; |
502 | } | 446 | } |
503 | 447 | ||
@@ -507,8 +451,6 @@ static int hpc_get_emi_status(struct slot *slot, u8 *status) | |||
507 | u16 slot_status; | 451 | u16 slot_status; |
508 | int retval = 0; | 452 | int retval = 0; |
509 | 453 | ||
510 | DBG_ENTER_ROUTINE | ||
511 | |||
512 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 454 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
513 | if (retval) { | 455 | if (retval) { |
514 | err("%s : Cannot check EMI status\n", __FUNCTION__); | 456 | err("%s : Cannot check EMI status\n", __FUNCTION__); |
@@ -516,7 +458,6 @@ static int hpc_get_emi_status(struct slot *slot, u8 *status) | |||
516 | } | 458 | } |
517 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | 459 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; |
518 | 460 | ||
519 | DBG_LEAVE_ROUTINE | ||
520 | return retval; | 461 | return retval; |
521 | } | 462 | } |
522 | 463 | ||
@@ -526,8 +467,6 @@ static int hpc_toggle_emi(struct slot *slot) | |||
526 | u16 cmd_mask; | 467 | u16 cmd_mask; |
527 | int rc; | 468 | int rc; |
528 | 469 | ||
529 | DBG_ENTER_ROUTINE | ||
530 | |||
531 | slot_cmd = EMI_CTRL; | 470 | slot_cmd = EMI_CTRL; |
532 | cmd_mask = EMI_CTRL; | 471 | cmd_mask = EMI_CTRL; |
533 | if (!pciehp_poll_mode) { | 472 | if (!pciehp_poll_mode) { |
@@ -537,7 +476,7 @@ static int hpc_toggle_emi(struct slot *slot) | |||
537 | 476 | ||
538 | rc = pcie_write_cmd(slot, slot_cmd, cmd_mask); | 477 | rc = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
539 | slot->last_emi_toggle = get_seconds(); | 478 | slot->last_emi_toggle = get_seconds(); |
540 | DBG_LEAVE_ROUTINE | 479 | |
541 | return rc; | 480 | return rc; |
542 | } | 481 | } |
543 | 482 | ||
@@ -548,8 +487,6 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
548 | u16 cmd_mask; | 487 | u16 cmd_mask; |
549 | int rc; | 488 | int rc; |
550 | 489 | ||
551 | DBG_ENTER_ROUTINE | ||
552 | |||
553 | cmd_mask = ATTN_LED_CTRL; | 490 | cmd_mask = ATTN_LED_CTRL; |
554 | switch (value) { | 491 | switch (value) { |
555 | case 0 : /* turn off */ | 492 | case 0 : /* turn off */ |
@@ -573,7 +510,6 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
573 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 510 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
574 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 511 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
575 | 512 | ||
576 | DBG_LEAVE_ROUTINE | ||
577 | return rc; | 513 | return rc; |
578 | } | 514 | } |
579 | 515 | ||
@@ -584,8 +520,6 @@ static void hpc_set_green_led_on(struct slot *slot) | |||
584 | u16 slot_cmd; | 520 | u16 slot_cmd; |
585 | u16 cmd_mask; | 521 | u16 cmd_mask; |
586 | 522 | ||
587 | DBG_ENTER_ROUTINE | ||
588 | |||
589 | slot_cmd = 0x0100; | 523 | slot_cmd = 0x0100; |
590 | cmd_mask = PWR_LED_CTRL; | 524 | cmd_mask = PWR_LED_CTRL; |
591 | if (!pciehp_poll_mode) { | 525 | if (!pciehp_poll_mode) { |
@@ -597,8 +531,6 @@ static void hpc_set_green_led_on(struct slot *slot) | |||
597 | 531 | ||
598 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 532 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
599 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 533 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
600 | DBG_LEAVE_ROUTINE | ||
601 | return; | ||
602 | } | 534 | } |
603 | 535 | ||
604 | static void hpc_set_green_led_off(struct slot *slot) | 536 | static void hpc_set_green_led_off(struct slot *slot) |
@@ -607,8 +539,6 @@ static void hpc_set_green_led_off(struct slot *slot) | |||
607 | u16 slot_cmd; | 539 | u16 slot_cmd; |
608 | u16 cmd_mask; | 540 | u16 cmd_mask; |
609 | 541 | ||
610 | DBG_ENTER_ROUTINE | ||
611 | |||
612 | slot_cmd = 0x0300; | 542 | slot_cmd = 0x0300; |
613 | cmd_mask = PWR_LED_CTRL; | 543 | cmd_mask = PWR_LED_CTRL; |
614 | if (!pciehp_poll_mode) { | 544 | if (!pciehp_poll_mode) { |
@@ -619,9 +549,6 @@ static void hpc_set_green_led_off(struct slot *slot) | |||
619 | pcie_write_cmd(slot, slot_cmd, cmd_mask); | 549 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
620 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 550 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
621 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 551 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
622 | |||
623 | DBG_LEAVE_ROUTINE | ||
624 | return; | ||
625 | } | 552 | } |
626 | 553 | ||
627 | static void hpc_set_green_led_blink(struct slot *slot) | 554 | static void hpc_set_green_led_blink(struct slot *slot) |
@@ -630,8 +557,6 @@ static void hpc_set_green_led_blink(struct slot *slot) | |||
630 | u16 slot_cmd; | 557 | u16 slot_cmd; |
631 | u16 cmd_mask; | 558 | u16 cmd_mask; |
632 | 559 | ||
633 | DBG_ENTER_ROUTINE | ||
634 | |||
635 | slot_cmd = 0x0200; | 560 | slot_cmd = 0x0200; |
636 | cmd_mask = PWR_LED_CTRL; | 561 | cmd_mask = PWR_LED_CTRL; |
637 | if (!pciehp_poll_mode) { | 562 | if (!pciehp_poll_mode) { |
@@ -643,14 +568,10 @@ static void hpc_set_green_led_blink(struct slot *slot) | |||
643 | 568 | ||
644 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 569 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
645 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 570 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
646 | DBG_LEAVE_ROUTINE | ||
647 | return; | ||
648 | } | 571 | } |
649 | 572 | ||
650 | static void hpc_release_ctlr(struct controller *ctrl) | 573 | static void hpc_release_ctlr(struct controller *ctrl) |
651 | { | 574 | { |
652 | DBG_ENTER_ROUTINE | ||
653 | |||
654 | if (pciehp_poll_mode) | 575 | if (pciehp_poll_mode) |
655 | del_timer(&ctrl->poll_timer); | 576 | del_timer(&ctrl->poll_timer); |
656 | else | 577 | else |
@@ -662,8 +583,6 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
662 | */ | 583 | */ |
663 | if (atomic_dec_and_test(&pciehp_num_controllers)) | 584 | if (atomic_dec_and_test(&pciehp_num_controllers)) |
664 | destroy_workqueue(pciehp_wq); | 585 | destroy_workqueue(pciehp_wq); |
665 | |||
666 | DBG_LEAVE_ROUTINE | ||
667 | } | 586 | } |
668 | 587 | ||
669 | static int hpc_power_on_slot(struct slot * slot) | 588 | static int hpc_power_on_slot(struct slot * slot) |
@@ -674,8 +593,6 @@ static int hpc_power_on_slot(struct slot * slot) | |||
674 | u16 slot_status; | 593 | u16 slot_status; |
675 | int retval = 0; | 594 | int retval = 0; |
676 | 595 | ||
677 | DBG_ENTER_ROUTINE | ||
678 | |||
679 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); | 596 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
680 | 597 | ||
681 | /* Clear sticky power-fault bit from previous power failures */ | 598 | /* Clear sticky power-fault bit from previous power failures */ |
@@ -719,8 +636,6 @@ static int hpc_power_on_slot(struct slot * slot) | |||
719 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 636 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
720 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 637 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
721 | 638 | ||
722 | DBG_LEAVE_ROUTINE | ||
723 | |||
724 | return retval; | 639 | return retval; |
725 | } | 640 | } |
726 | 641 | ||
@@ -731,8 +646,6 @@ static int hpc_power_off_slot(struct slot * slot) | |||
731 | u16 cmd_mask; | 646 | u16 cmd_mask; |
732 | int retval = 0; | 647 | int retval = 0; |
733 | 648 | ||
734 | DBG_ENTER_ROUTINE | ||
735 | |||
736 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); | 649 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
737 | 650 | ||
738 | slot_cmd = POWER_OFF; | 651 | slot_cmd = POWER_OFF; |
@@ -764,8 +677,6 @@ static int hpc_power_off_slot(struct slot * slot) | |||
764 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 677 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
765 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 678 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
766 | 679 | ||
767 | DBG_LEAVE_ROUTINE | ||
768 | |||
769 | return retval; | 680 | return retval; |
770 | } | 681 | } |
771 | 682 | ||
@@ -915,8 +826,6 @@ static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |||
915 | u32 lnk_cap; | 826 | u32 lnk_cap; |
916 | int retval = 0; | 827 | int retval = 0; |
917 | 828 | ||
918 | DBG_ENTER_ROUTINE | ||
919 | |||
920 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); | 829 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
921 | if (retval) { | 830 | if (retval) { |
922 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); | 831 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
@@ -934,7 +843,7 @@ static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |||
934 | 843 | ||
935 | *value = lnk_speed; | 844 | *value = lnk_speed; |
936 | dbg("Max link speed = %d\n", lnk_speed); | 845 | dbg("Max link speed = %d\n", lnk_speed); |
937 | DBG_LEAVE_ROUTINE | 846 | |
938 | return retval; | 847 | return retval; |
939 | } | 848 | } |
940 | 849 | ||
@@ -945,8 +854,6 @@ static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value | |||
945 | u32 lnk_cap; | 854 | u32 lnk_cap; |
946 | int retval = 0; | 855 | int retval = 0; |
947 | 856 | ||
948 | DBG_ENTER_ROUTINE | ||
949 | |||
950 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); | 857 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
951 | if (retval) { | 858 | if (retval) { |
952 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); | 859 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
@@ -985,7 +892,7 @@ static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value | |||
985 | 892 | ||
986 | *value = lnk_wdth; | 893 | *value = lnk_wdth; |
987 | dbg("Max link width = %d\n", lnk_wdth); | 894 | dbg("Max link width = %d\n", lnk_wdth); |
988 | DBG_LEAVE_ROUTINE | 895 | |
989 | return retval; | 896 | return retval; |
990 | } | 897 | } |
991 | 898 | ||
@@ -996,8 +903,6 @@ static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |||
996 | int retval = 0; | 903 | int retval = 0; |
997 | u16 lnk_status; | 904 | u16 lnk_status; |
998 | 905 | ||
999 | DBG_ENTER_ROUTINE | ||
1000 | |||
1001 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 906 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1002 | if (retval) { | 907 | if (retval) { |
1003 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); | 908 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
@@ -1015,7 +920,7 @@ static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |||
1015 | 920 | ||
1016 | *value = lnk_speed; | 921 | *value = lnk_speed; |
1017 | dbg("Current link speed = %d\n", lnk_speed); | 922 | dbg("Current link speed = %d\n", lnk_speed); |
1018 | DBG_LEAVE_ROUTINE | 923 | |
1019 | return retval; | 924 | return retval; |
1020 | } | 925 | } |
1021 | 926 | ||
@@ -1026,8 +931,6 @@ static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value | |||
1026 | int retval = 0; | 931 | int retval = 0; |
1027 | u16 lnk_status; | 932 | u16 lnk_status; |
1028 | 933 | ||
1029 | DBG_ENTER_ROUTINE | ||
1030 | |||
1031 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 934 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1032 | if (retval) { | 935 | if (retval) { |
1033 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); | 936 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
@@ -1066,7 +969,7 @@ static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value | |||
1066 | 969 | ||
1067 | *value = lnk_wdth; | 970 | *value = lnk_wdth; |
1068 | dbg("Current link width = %d\n", lnk_wdth); | 971 | dbg("Current link width = %d\n", lnk_wdth); |
1069 | DBG_LEAVE_ROUTINE | 972 | |
1070 | return retval; | 973 | return retval; |
1071 | } | 974 | } |
1072 | 975 | ||
@@ -1177,8 +1080,6 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1177 | u16 slot_status, slot_ctrl; | 1080 | u16 slot_status, slot_ctrl; |
1178 | struct pci_dev *pdev; | 1081 | struct pci_dev *pdev; |
1179 | 1082 | ||
1180 | DBG_ENTER_ROUTINE | ||
1181 | |||
1182 | pdev = dev->port; | 1083 | pdev = dev->port; |
1183 | ctrl->pci_dev = pdev; /* save pci_dev in context */ | 1084 | ctrl->pci_dev = pdev; /* save pci_dev in context */ |
1184 | 1085 | ||
@@ -1376,7 +1277,6 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1376 | 1277 | ||
1377 | ctrl->hpc_ops = &pciehp_hpc_ops; | 1278 | ctrl->hpc_ops = &pciehp_hpc_ops; |
1378 | 1279 | ||
1379 | DBG_LEAVE_ROUTINE | ||
1380 | return 0; | 1280 | return 0; |
1381 | 1281 | ||
1382 | /* We end up here for the many possible ways to fail this API. */ | 1282 | /* We end up here for the many possible ways to fail this API. */ |
@@ -1396,6 +1296,5 @@ abort_free_irq: | |||
1396 | free_irq(ctrl->pci_dev->irq, ctrl); | 1296 | free_irq(ctrl->pci_dev->irq, ctrl); |
1397 | 1297 | ||
1398 | abort_free_ctlr: | 1298 | abort_free_ctlr: |
1399 | DBG_LEAVE_ROUTINE | ||
1400 | return -1; | 1299 | return -1; |
1401 | } | 1300 | } |