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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2008-04-25 17:39:02 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2008-04-25 17:39:02 -0400
commit2d32a9aed2e335d110fbb11985a9545b1f7219ab (patch)
tree46b6cb666c11a3f55b26cd7e73829b6fd130f649 /drivers/pci
parentc6b069e94601aea8887afbbd922afe20a3580a7d (diff)
pciehp: Add missing memory barrier
Fix the possible race condition between pcie_isr() and pciehp_write_cmd() because of the lack of memory barrier. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 51a5055f6965..19eba2a2f746 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -279,6 +279,7 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
279 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE); 279 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
280 280
281 ctrl->cmd_busy = 1; 281 ctrl->cmd_busy = 1;
282 smp_mb();
282 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); 283 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
283 if (retval) 284 if (retval)
284 err("%s: Cannot write to SLOTCTRL register\n", __func__); 285 err("%s: Cannot write to SLOTCTRL register\n", __func__);
@@ -759,6 +760,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
759 /* Check Command Complete Interrupt Pending */ 760 /* Check Command Complete Interrupt Pending */
760 if (intr_loc & CMD_COMPLETED) { 761 if (intr_loc & CMD_COMPLETED) {
761 ctrl->cmd_busy = 0; 762 ctrl->cmd_busy = 0;
763 smp_mb();
762 wake_up_interruptible(&ctrl->queue); 764 wake_up_interruptible(&ctrl->queue);
763 } 765 }
764 766