diff options
author | Jingoo Han <jg1.han@samsung.com> | 2014-11-11 22:25:38 -0500 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-11-13 12:50:31 -0500 |
commit | bc512c5a8c78db6904de7275bce54ce5b1433893 (patch) | |
tree | 479bbc736d4d26cb7a15f500c179f028ab88e909 /drivers/pci | |
parent | 70b3e89aaf421ad642c4ab0fb196e1c19ea838c5 (diff) |
PCI: exynos: Remove unnecessary return statement
This patch fixes the following checkpatch warning:
WARNING: void function return statements are not generally useful
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/host/pci-exynos.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 902d7cd3e760..850c9f951a3f 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c | |||
@@ -312,7 +312,6 @@ static void exynos_pcie_assert_reset(struct pcie_port *pp) | |||
312 | if (exynos_pcie->reset_gpio >= 0) | 312 | if (exynos_pcie->reset_gpio >= 0) |
313 | devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio, | 313 | devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio, |
314 | GPIOF_OUT_INIT_HIGH, "RESET"); | 314 | GPIOF_OUT_INIT_HIGH, "RESET"); |
315 | return; | ||
316 | } | 315 | } |
317 | 316 | ||
318 | static int exynos_pcie_establish_link(struct pcie_port *pp) | 317 | static int exynos_pcie_establish_link(struct pcie_port *pp) |
@@ -388,7 +387,6 @@ static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp) | |||
388 | 387 | ||
389 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); | 388 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); |
390 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); | 389 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); |
391 | return; | ||
392 | } | 390 | } |
393 | 391 | ||
394 | static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) | 392 | static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) |
@@ -400,7 +398,6 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) | |||
400 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | | 398 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | |
401 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT, | 399 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT, |
402 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); | 400 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); |
403 | return; | ||
404 | } | 401 | } |
405 | 402 | ||
406 | static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) | 403 | static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) |
@@ -429,7 +426,6 @@ static void exynos_pcie_msi_init(struct pcie_port *pp) | |||
429 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL); | 426 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL); |
430 | val |= IRQ_MSI_ENABLE; | 427 | val |= IRQ_MSI_ENABLE; |
431 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL); | 428 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL); |
432 | return; | ||
433 | } | 429 | } |
434 | 430 | ||
435 | static void exynos_pcie_enable_interrupts(struct pcie_port *pp) | 431 | static void exynos_pcie_enable_interrupts(struct pcie_port *pp) |
@@ -438,8 +434,6 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp) | |||
438 | 434 | ||
439 | if (IS_ENABLED(CONFIG_PCI_MSI)) | 435 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
440 | exynos_pcie_msi_init(pp); | 436 | exynos_pcie_msi_init(pp); |
441 | |||
442 | return; | ||
443 | } | 437 | } |
444 | 438 | ||
445 | static inline void exynos_pcie_readl_rc(struct pcie_port *pp, | 439 | static inline void exynos_pcie_readl_rc(struct pcie_port *pp, |
@@ -448,7 +442,6 @@ static inline void exynos_pcie_readl_rc(struct pcie_port *pp, | |||
448 | exynos_pcie_sideband_dbi_r_mode(pp, true); | 442 | exynos_pcie_sideband_dbi_r_mode(pp, true); |
449 | *val = readl(dbi_base); | 443 | *val = readl(dbi_base); |
450 | exynos_pcie_sideband_dbi_r_mode(pp, false); | 444 | exynos_pcie_sideband_dbi_r_mode(pp, false); |
451 | return; | ||
452 | } | 445 | } |
453 | 446 | ||
454 | static inline void exynos_pcie_writel_rc(struct pcie_port *pp, | 447 | static inline void exynos_pcie_writel_rc(struct pcie_port *pp, |
@@ -457,7 +450,6 @@ static inline void exynos_pcie_writel_rc(struct pcie_port *pp, | |||
457 | exynos_pcie_sideband_dbi_w_mode(pp, true); | 450 | exynos_pcie_sideband_dbi_w_mode(pp, true); |
458 | writel(val, dbi_base); | 451 | writel(val, dbi_base); |
459 | exynos_pcie_sideband_dbi_w_mode(pp, false); | 452 | exynos_pcie_sideband_dbi_w_mode(pp, false); |
460 | return; | ||
461 | } | 453 | } |
462 | 454 | ||
463 | static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, | 455 | static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |