diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2014-07-31 14:16:05 -0400 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-09-04 09:32:21 -0400 |
| commit | 3e3e406e3807235906ee0b7c697664ea6dfd88de (patch) | |
| tree | de09c4ec9710c207118fac0cd4ab52fde2f1d856 /drivers/pci | |
| parent | 1ba55f558cd3131bc1dedc84c53a8d254b55d9cf (diff) | |
PCI: imx6: Put LTSSM in "Detect" state before disabling it
This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use. The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.
According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do. Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.
As a workaround, force LTSSM into detect state right before hitting the
disable switch. There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.
[bhelgaas: mention race window]
Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-imx6.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index a568efaa331c..35fc73a8d0b3 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c | |||
| @@ -49,6 +49,9 @@ struct imx6_pcie { | |||
| 49 | 49 | ||
| 50 | /* PCIe Port Logic registers (memory-mapped) */ | 50 | /* PCIe Port Logic registers (memory-mapped) */ |
| 51 | #define PL_OFFSET 0x700 | 51 | #define PL_OFFSET 0x700 |
| 52 | #define PCIE_PL_PFLR (PL_OFFSET + 0x08) | ||
| 53 | #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) | ||
| 54 | #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) | ||
| 52 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) | 55 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) |
| 53 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | 56 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) |
| 54 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) | 57 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) |
| @@ -214,6 +217,32 @@ static int imx6q_pcie_abort_handler(unsigned long addr, | |||
| 214 | static int imx6_pcie_assert_core_reset(struct pcie_port *pp) | 217 | static int imx6_pcie_assert_core_reset(struct pcie_port *pp) |
| 215 | { | 218 | { |
| 216 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | 219 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); |
| 220 | u32 val, gpr1, gpr12; | ||
| 221 | |||
| 222 | /* | ||
| 223 | * If the bootloader already enabled the link we need some special | ||
| 224 | * handling to get the core back into a state where it is safe to | ||
| 225 | * touch it for configuration. As there is no dedicated reset signal | ||
| 226 | * wired up for MX6QDL, we need to manually force LTSSM into "detect" | ||
| 227 | * state before completely disabling LTSSM, which is a prerequisite | ||
| 228 | * for core configuration. | ||
| 229 | * | ||
| 230 | * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong | ||
| 231 | * indication that the bootloader activated the link. | ||
| 232 | */ | ||
| 233 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1); | ||
| 234 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12); | ||
| 235 | |||
| 236 | if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && | ||
| 237 | (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { | ||
| 238 | val = readl(pp->dbi_base + PCIE_PL_PFLR); | ||
| 239 | val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; | ||
| 240 | val |= PCIE_PL_PFLR_FORCE_LINK; | ||
| 241 | writel(val, pp->dbi_base + PCIE_PL_PFLR); | ||
| 242 | |||
| 243 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | ||
| 244 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | ||
| 245 | } | ||
| 217 | 246 | ||
| 218 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | 247 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| 219 | IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); | 248 | IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); |
| @@ -589,6 +618,14 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) | |||
| 589 | return 0; | 618 | return 0; |
| 590 | } | 619 | } |
| 591 | 620 | ||
| 621 | static void imx6_pcie_shutdown(struct platform_device *pdev) | ||
| 622 | { | ||
| 623 | struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); | ||
| 624 | |||
| 625 | /* bring down link, so bootloader gets clean state in case of reboot */ | ||
| 626 | imx6_pcie_assert_core_reset(&imx6_pcie->pp); | ||
| 627 | } | ||
| 628 | |||
| 592 | static const struct of_device_id imx6_pcie_of_match[] = { | 629 | static const struct of_device_id imx6_pcie_of_match[] = { |
| 593 | { .compatible = "fsl,imx6q-pcie", }, | 630 | { .compatible = "fsl,imx6q-pcie", }, |
| 594 | {}, | 631 | {}, |
| @@ -601,6 +638,7 @@ static struct platform_driver imx6_pcie_driver = { | |||
| 601 | .owner = THIS_MODULE, | 638 | .owner = THIS_MODULE, |
| 602 | .of_match_table = imx6_pcie_of_match, | 639 | .of_match_table = imx6_pcie_of_match, |
| 603 | }, | 640 | }, |
| 641 | .shutdown = imx6_pcie_shutdown, | ||
| 604 | }; | 642 | }; |
| 605 | 643 | ||
| 606 | /* Freescale PCIe driver does not allow module unload */ | 644 | /* Freescale PCIe driver does not allow module unload */ |