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authorHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>2010-04-15 00:18:26 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2010-05-11 15:01:37 -0400
commite167bfcaa4cd44b4c66206a3c06b2aafb3f1260e (patch)
treecc21ae9a6f9efb3271b130e4e69ade52e71be871 /drivers/pci
parentf647a44f5725b0e6c8211096f4b49900164123ee (diff)
PCI: aerdrv: remove magical ROOT_ERR_STATUS_MASKS
Make it clear that we only interest in 2 *_RCV bits. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pcie/aer/aerdrv.c2
-rw-r--r--drivers/pci/pcie/aer/aerdrv.h3
2 files changed, 1 insertions, 4 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 1a55c16e2f3f..cbc7cc77b2c3 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -204,7 +204,7 @@ irqreturn_t aer_irq(int irq, void *context)
204 204
205 /* Read error status */ 205 /* Read error status */
206 pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, &status); 206 pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, &status);
207 if (!(status & ROOT_ERR_STATUS_MASKS)) { 207 if (!(status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV))) {
208 spin_unlock_irqrestore(&rpc->e_lock, flags); 208 spin_unlock_irqrestore(&rpc->e_lock, flags);
209 return IRQ_NONE; 209 return IRQ_NONE;
210 } 210 }
diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h
index 2f345405e823..d0f8291c5ca0 100644
--- a/drivers/pci/pcie/aer/aerdrv.h
+++ b/drivers/pci/pcie/aer/aerdrv.h
@@ -17,9 +17,6 @@
17#define AER_FATAL 1 17#define AER_FATAL 1
18#define AER_CORRECTABLE 2 18#define AER_CORRECTABLE 2
19 19
20/* Root Error Status Register Bits */
21#define ROOT_ERR_STATUS_MASKS 0x0f
22
23#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ 20#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
24 PCI_EXP_RTCTL_SENFEE| \ 21 PCI_EXP_RTCTL_SENFEE| \
25 PCI_EXP_RTCTL_SEFEE) 22 PCI_EXP_RTCTL_SEFEE)