diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2008-04-25 17:39:08 -0400 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-04-25 17:39:08 -0400 |
commit | 2aeeef11999590d88249fbd086671af8300116f4 (patch) | |
tree | 84e9349e855c1cb2e553258090f3d264fe3d6134 /drivers/pci | |
parent | d84be093a81c29e085144c4d483d9fa0a83a1918 (diff) |
pciehp: Clean up pcie_init()
Clean up pciehp_ini(). This patch is trying to
- Remove redundant capablity checks that were already done in PCIe
port bus driver.
- Separate the code only for debugging and make debug information
easier to read.
- Make the entire code easier to read and understand what it is doing.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 198 |
1 files changed, 88 insertions, 110 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index df1266cd6861..5cadcd0654cb 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c | |||
@@ -221,6 +221,32 @@ static void start_int_poll_timer(struct controller *ctrl, int sec) | |||
221 | add_timer(&ctrl->poll_timer); | 221 | add_timer(&ctrl->poll_timer); |
222 | } | 222 | } |
223 | 223 | ||
224 | static inline int pciehp_request_irq(struct controller *ctrl) | ||
225 | { | ||
226 | int retval, irq = ctrl->pci_dev->irq; | ||
227 | |||
228 | /* Install interrupt polling timer. Start with 10 sec delay */ | ||
229 | if (pciehp_poll_mode) { | ||
230 | init_timer(&ctrl->poll_timer); | ||
231 | start_int_poll_timer(ctrl, 10); | ||
232 | return 0; | ||
233 | } | ||
234 | |||
235 | /* Installs the interrupt handler */ | ||
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | ||
237 | if (retval) | ||
238 | err("Cannot get irq %d for the hotplug controller\n", irq); | ||
239 | return retval; | ||
240 | } | ||
241 | |||
242 | static inline void pciehp_free_irq(struct controller *ctrl) | ||
243 | { | ||
244 | if (pciehp_poll_mode) | ||
245 | del_timer_sync(&ctrl->poll_timer); | ||
246 | else | ||
247 | free_irq(ctrl->pci_dev->irq, ctrl); | ||
248 | } | ||
249 | |||
224 | static inline int pcie_wait_cmd(struct controller *ctrl) | 250 | static inline int pcie_wait_cmd(struct controller *ctrl) |
225 | { | 251 | { |
226 | int retval = 0; | 252 | int retval = 0; |
@@ -541,10 +567,8 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
541 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) | 567 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) |
542 | err("%s: Cannot mask hotplut interrupt enable\n", __func__); | 568 | err("%s: Cannot mask hotplut interrupt enable\n", __func__); |
543 | 569 | ||
544 | if (pciehp_poll_mode) | 570 | /* Free interrupt handler or interrupt polling timer */ |
545 | del_timer(&ctrl->poll_timer); | 571 | pciehp_free_irq(ctrl); |
546 | else | ||
547 | free_irq(ctrl->pci_dev->irq, ctrl); | ||
548 | 572 | ||
549 | /* | 573 | /* |
550 | * If this is the last controller to be released, destroy the | 574 | * If this is the last controller to be released, destroy the |
@@ -1057,121 +1081,79 @@ abort: | |||
1057 | return -1; | 1081 | return -1; |
1058 | } | 1082 | } |
1059 | 1083 | ||
1060 | int pcie_init(struct controller *ctrl, struct pcie_device *dev) | 1084 | static inline void dbg_ctrl(struct controller *ctrl) |
1061 | { | 1085 | { |
1062 | int rc; | 1086 | int i; |
1063 | u16 cap_reg; | 1087 | u16 reg16; |
1064 | u32 slot_cap; | 1088 | struct pci_dev *pdev = ctrl->pci_dev; |
1065 | int cap_base; | ||
1066 | u16 slot_status, slot_ctrl; | ||
1067 | struct pci_dev *pdev; | ||
1068 | |||
1069 | pdev = dev->port; | ||
1070 | ctrl->pci_dev = pdev; /* save pci_dev in context */ | ||
1071 | 1089 | ||
1072 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", | 1090 | if (!pciehp_debug) |
1073 | __func__, pdev->vendor, pdev->device); | 1091 | return; |
1074 | 1092 | ||
1075 | cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | 1093 | dbg("Hotplug Controller:\n"); |
1076 | if (cap_base == 0) { | 1094 | dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); |
1077 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__); | 1095 | dbg(" Vendor ID : 0x%04x\n", pdev->vendor); |
1078 | goto abort; | 1096 | dbg(" Device ID : 0x%04x\n", pdev->device); |
1097 | dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); | ||
1098 | dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); | ||
1099 | dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | ||
1100 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
1101 | if (!pci_resource_len(pdev, i)) | ||
1102 | continue; | ||
1103 | dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, | ||
1104 | (unsigned long long)pci_resource_len(pdev, i), | ||
1105 | (unsigned long long)pci_resource_start(pdev, i)); | ||
1079 | } | 1106 | } |
1107 | dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); | ||
1108 | dbg(" Physical Slot Number : %d\n", ctrl->first_slot); | ||
1109 | dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); | ||
1110 | dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); | ||
1111 | dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); | ||
1112 | dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); | ||
1113 | dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); | ||
1114 | dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); | ||
1115 | dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); | ||
1116 | pciehp_readw(ctrl, SLOTSTATUS, ®16); | ||
1117 | dbg("Slot Status : 0x%04x\n", reg16); | ||
1118 | pciehp_readw(ctrl, SLOTSTATUS, ®16); | ||
1119 | dbg("Slot Control : 0x%04x\n", reg16); | ||
1120 | } | ||
1080 | 1121 | ||
1081 | ctrl->cap_base = cap_base; | 1122 | int pcie_init(struct controller *ctrl, struct pcie_device *dev) |
1082 | 1123 | { | |
1083 | dbg("%s: pcie_cap_base %x\n", __func__, cap_base); | 1124 | u32 slot_cap; |
1125 | struct pci_dev *pdev = dev->port; | ||
1084 | 1126 | ||
1085 | rc = pciehp_readw(ctrl, CAPREG, &cap_reg); | 1127 | ctrl->pci_dev = pdev; |
1086 | if (rc) { | 1128 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
1087 | err("%s: Cannot read CAPREG register\n", __func__); | 1129 | if (!ctrl->cap_base) { |
1088 | goto abort; | 1130 | err("%s: Cannot find PCI Express capability\n", __func__); |
1089 | } | ||
1090 | dbg("%s: CAPREG offset %x cap_reg %x\n", | ||
1091 | __func__, ctrl->cap_base + CAPREG, cap_reg); | ||
1092 | |||
1093 | if (((cap_reg & SLOT_IMPL) == 0) || | ||
1094 | (((cap_reg & DEV_PORT_TYPE) != 0x0040) | ||
1095 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { | ||
1096 | dbg("%s : This is not a root port or the port is not " | ||
1097 | "connected to a slot\n", __func__); | ||
1098 | goto abort; | 1131 | goto abort; |
1099 | } | 1132 | } |
1100 | 1133 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { | |
1101 | rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap); | ||
1102 | if (rc) { | ||
1103 | err("%s: Cannot read SLOTCAP register\n", __func__); | 1134 | err("%s: Cannot read SLOTCAP register\n", __func__); |
1104 | goto abort; | 1135 | goto abort; |
1105 | } | 1136 | } |
1106 | dbg("%s: SLOTCAP offset %x slot_cap %x\n", | ||
1107 | __func__, ctrl->cap_base + SLOTCAP, slot_cap); | ||
1108 | |||
1109 | if (!(slot_cap & HP_CAP)) { | ||
1110 | dbg("%s : This slot is not hot-plug capable\n", __func__); | ||
1111 | goto abort; | ||
1112 | } | ||
1113 | /* For debugging purpose */ | ||
1114 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | ||
1115 | if (rc) { | ||
1116 | err("%s: Cannot read SLOTSTATUS register\n", __func__); | ||
1117 | goto abort; | ||
1118 | } | ||
1119 | dbg("%s: SLOTSTATUS offset %x slot_status %x\n", | ||
1120 | __func__, ctrl->cap_base + SLOTSTATUS, slot_status); | ||
1121 | |||
1122 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | ||
1123 | if (rc) { | ||
1124 | err("%s: Cannot read SLOTCTRL register\n", __func__); | ||
1125 | goto abort; | ||
1126 | } | ||
1127 | dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", | ||
1128 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | ||
1129 | |||
1130 | for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) | ||
1131 | if (pci_resource_len(pdev, rc) > 0) | ||
1132 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, | ||
1133 | (unsigned long long)pci_resource_start(pdev, rc), | ||
1134 | (unsigned long long)pci_resource_len(pdev, rc)); | ||
1135 | |||
1136 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", | ||
1137 | pdev->vendor, pdev->device, | ||
1138 | pdev->subsystem_vendor, pdev->subsystem_device); | ||
1139 | 1137 | ||
1138 | ctrl->slot_cap = slot_cap; | ||
1139 | ctrl->first_slot = slot_cap >> 19; | ||
1140 | ctrl->slot_device_offset = 0; | ||
1141 | ctrl->num_slots = 1; | ||
1142 | ctrl->hpc_ops = &pciehp_hpc_ops; | ||
1140 | mutex_init(&ctrl->crit_sect); | 1143 | mutex_init(&ctrl->crit_sect); |
1141 | mutex_init(&ctrl->ctrl_lock); | 1144 | mutex_init(&ctrl->ctrl_lock); |
1142 | |||
1143 | /* setup wait queue */ | ||
1144 | init_waitqueue_head(&ctrl->queue); | 1145 | init_waitqueue_head(&ctrl->queue); |
1146 | dbg_ctrl(ctrl); | ||
1145 | 1147 | ||
1146 | /* return PCI Controller Info */ | 1148 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1147 | ctrl->slot_device_offset = 0; | 1149 | pdev->vendor, pdev->device, |
1148 | ctrl->num_slots = 1; | 1150 | pdev->subsystem_vendor, pdev->subsystem_device); |
1149 | ctrl->first_slot = slot_cap >> 19; | ||
1150 | ctrl->slot_cap = slot_cap; | ||
1151 | 1151 | ||
1152 | rc = pcie_init_hardware_part1(ctrl, dev); | 1152 | if (pcie_init_hardware_part1(ctrl, dev)) |
1153 | if (rc) | ||
1154 | goto abort; | 1153 | goto abort; |
1155 | 1154 | ||
1156 | if (pciehp_poll_mode) { | 1155 | if (pciehp_request_irq(ctrl)) |
1157 | /* Install interrupt polling timer. Start with 10 sec delay */ | 1156 | goto abort; |
1158 | init_timer(&ctrl->poll_timer); | ||
1159 | start_int_poll_timer(ctrl, 10); | ||
1160 | } else { | ||
1161 | /* Installs the interrupt handler */ | ||
1162 | rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED, | ||
1163 | MY_NAME, (void *)ctrl); | ||
1164 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", | ||
1165 | __func__, ctrl->pci_dev->irq, | ||
1166 | atomic_read(&pciehp_num_controllers), rc); | ||
1167 | if (rc) { | ||
1168 | err("Can't get irq %d for the hotplug controller\n", | ||
1169 | ctrl->pci_dev->irq); | ||
1170 | goto abort; | ||
1171 | } | ||
1172 | } | ||
1173 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, | ||
1174 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); | ||
1175 | 1157 | ||
1176 | /* | 1158 | /* |
1177 | * If this is the first controller to be initialized, | 1159 | * If this is the first controller to be initialized, |
@@ -1180,21 +1162,17 @@ int pcie_init(struct controller *ctrl, struct pcie_device *dev) | |||
1180 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | 1162 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { |
1181 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | 1163 | pciehp_wq = create_singlethread_workqueue("pciehpd"); |
1182 | if (!pciehp_wq) { | 1164 | if (!pciehp_wq) { |
1183 | rc = -ENOMEM; | ||
1184 | goto abort_free_irq; | 1165 | goto abort_free_irq; |
1185 | } | 1166 | } |
1186 | } | 1167 | } |
1187 | 1168 | ||
1188 | rc = pcie_init_hardware_part2(ctrl, dev); | 1169 | if (pcie_init_hardware_part2(ctrl, dev)) |
1189 | if (rc == 0) { | 1170 | goto abort_free_irq; |
1190 | ctrl->hpc_ops = &pciehp_hpc_ops; | 1171 | |
1191 | return 0; | 1172 | return 0; |
1192 | } | 1173 | |
1193 | abort_free_irq: | 1174 | abort_free_irq: |
1194 | if (pciehp_poll_mode) | 1175 | pciehp_free_irq(ctrl); |
1195 | del_timer_sync(&ctrl->poll_timer); | ||
1196 | else | ||
1197 | free_irq(ctrl->pci_dev->irq, ctrl); | ||
1198 | abort: | 1176 | abort: |
1199 | return -1; | 1177 | return -1; |
1200 | } | 1178 | } |